JP2004282101A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure for preventing contamination on the interface in fabrication of an integrated circuit on an insulating substrate, and to enhance the reliability of the obtained integrated circuit while increasing the production yield. <P>SOLUTION: The semiconductor integrated circuit comprises a silicon nitride film touching the surface of a glass substrate, a silicon oxide film touching the silicon nitride film, and a silicon film touching the silicon oxide film. The silicon nitride film, the silicon oxide film, and the silicon film are formed continuously without touching the glass substrate to the atmosphere, and the silicon film has crystallinity. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a semiconductor integrated circuit formed on an insulating substrate, which is excellent in reliability and mass productivity and has high yield, and a method for manufacturing the same. The present invention is intended to constitute a driving circuit such as a liquid crystal display or a thin film image sensor, a three-dimensional integrated circuit, or the like as an application field thereof.

In recent years, attempts have been made to form a semiconductor integrated circuit on an insulating substrate such as glass or sapphire. The reason is that the operating speed is improved by reducing the parasitic capacitance between the substrate and the wiring, and that the glass material such as quartz is inexpensive because there is no size limitation like a silicon wafer, Easy separation between devices, especially CMO
This is because the latch-up phenomenon that causes a problem in the S monolithic integrated circuit does not occur. Apart from the above reasons, in a liquid crystal display or a contact type image sensor, it is necessary to integrate a semiconductor element and a liquid crystal element or a light detecting element, so that a thin film transistor (TFT) is disposed on a transparent substrate. Etc. must be formed.

For this reason, thin-film semiconductor elements have been formed on insulating substrates. However, a conventional semiconductor integrated circuit on an insulating substrate employs the same manufacturing process as a semiconductor integrated circuit (monolithic integrated circuit) on a semiconductor substrate, so that the number of masks required for the production has been extremely large. In a conventional monolithic integrated circuit, a silicon single crystal, which is a substrate, has extremely high reliability and has almost no problems such as deformation due to heat treatment. Therefore, even in the mask alignment process, the mask is shifted for such a reason. It was not so much.

However, generally commercially available insulating substrates are less reliable than silicon substrates, and in particular, substrates made of a glass-based material are deformed randomly by heat treatment, so that the designed mask is not suitable. In some cases, mask alignment becomes extremely difficult.

Further, when the integrated circuit is used for the purpose of a liquid crystal display or the like, it is required to form the integrated circuit in a much larger area than the conventional integrated circuit. Therefore, it has been required to reduce the number of mask alignment steps. The present invention proposes a manufacturing method with a small number of mask alignment steps in manufacturing an integrated circuit on such an insulating substrate.

Another object of the present invention is to improve the reliability of the obtained integrated circuit and improve the yield. In the case where an integrated circuit is formed on an insulating substrate, particularly, electrostatic breakdown of an element becomes a problem. Because it is easy to generate static electricity because it is an insulating substrate, and
This is because it is difficult to remove static electricity. In particular, in the case of an electrostatic breakdown between multilayer wirings, for example, in the case of a liquid crystal display, one row in each of the vertical and horizontal directions becomes unusable due to a breakdown in one place. It cannot be compensated for in parts, and the damage is great.

The present invention seeks to solve the above problems by introducing a completely different process. That is, with respect to the interlayer insulator used in the conventional integrated circuit, in the present invention, the insulator formed by oxidizing the lower wiring layer is used as all or a part of the interlayer insulator, and thereby, the number of times of mask alignment is increased. Or increase the withstand voltage between the multilayer wirings.

FIG. 1 shows an example of the present invention. First, a silicon oxide film 102 having a thickness of 100 to 1000 nm is formed as a passivation film on a substrate 101 having an insulating surface, and a semiconductor film is formed thereover. As a substrate having this insulating surface, a glass substrate, a substrate provided with an insulating film on a silicon wafer, a substrate provided with an insulating film on a monolithic semiconductor integrated circuit using a silicon semiconductor, or the like can be used. The passivation film has a function of preventing mobile ions such as sodium from entering the semiconductor region thereabove from the substrate and deteriorating semiconductor characteristics. The passivation film may be a single-layer film or a multi-layer film of, for example, silicon nitride, silicon oxide, aluminum oxide, or the like. Further, when the substrate is of sufficiently high purity and the number of mobile ions is sufficiently small, it is not necessary to provide the passivation film in this way. As the semiconductor film, for example, amorphous, polycrystalline, or microcrystalline silicon may be used. The semiconductor film is etched to form a semiconductor region 103.

Further, an insulating film is formed thereon. Since this insulating film is used as a gate insulating film, use a film having excellent characteristics at the interface with the underlying semiconductor region and a film having few defects such as a carrier trap center and an interface state. It is desired. For example, a silicon oxide film formed by an ECR-CVD method is preferable. Further, a structure in which a plurality of insulating films are stacked in multiple layers may be employed. The thickness of this insulating coating is
It is determined in consideration of use as a gate insulating film. Typically, 50-5
00 nm. Thus, the structure shown in FIG. 1A is obtained.

Thereafter, a metal coating mainly composed of a metal, for example, aluminum is formed. That is, aluminum containing almost no impurities or pure aluminum has insufficient strength. For example, when the aluminum is weak to a mechanical force such as electromigration, an alloy obtained by adding 1 to 10% of silicon to aluminum is used. To form a coating. Instead of aluminum, titanium or tantalum, or titanium silicide, tantalum silicide, an aluminum compound, a titanium compound, or a tantalum compound may be used. These metals can form an oxide film of the material by an anodization method (anodization method), and this oxide film has excellent pressure resistance. However,
It should be noted that the choice of the metal is that titanium oxide and tantalum oxide have a much higher dielectric constant than aluminum oxide. Therefore, if these materials having a high dielectric constant are used as the interlayer insulator, the dielectric loss may increase. Further, it must be considered in selecting a material that tantalum and titanium have a higher resistivity than aluminum. Therefore, for example, even for the same first wiring, high-speed responsiveness is required, and aluminum is used for the gate wiring, which is required to have a small electrostatic loss with the upper wiring, and so high-speed responsiveness is required. Rather, it is also desirable to use tantalum or titanium separately for the storage capacitor wiring required to function as a capacitor.
Needless to say, in this case, an extra number of masks is required. The metal film thus formed is selectively removed to function as, for example, a gate electrode 106, a wiring (gate wiring) 105 extending therefrom, or a storage capacitor electrode, and used separately from the gate wiring. The wiring (storage capacitor wiring) 107 to be formed is formed. The gate electrode may be a single layer of phosphorus-doped silicon or metal, or a multilayer of phosphorus-doped silicon film and metal film. In the case of a multilayer, the thickness of the phosphorus-doped silicon film is, for example, 20
To 500 °.

Next, a known impurity diffusion method, for example, an ion implantation method or a plasma doping method,
Thus, an impurity is introduced into the semiconductor region to form an impurity region 108. At this time, since the gate electrode 106 functions as a mask at the time of impurity implantation, impurity regions are formed in a self-aligned (self-aligned) manner. In this way, FIG.
) Is obtained.

After forming the impurity region, immerse the entire substrate in an appropriate electrolytic solution, connect the gate wiring and storage capacitor wiring to the power supply, and perform anodic oxidation through DC or AC current, and then perform gate wiring, gate electrode, storage capacitor electrode, etc. Oxide film 109 is formed on the surface of the substrate.
A film of aluminum oxide is formed when aluminum is used as the material of the wiring, a film of titanium oxide is formed when titanium is used, and a film of tantalum oxide is formed when tantalum is used. These oxide films do not consist purely of metal and oxygen, but instead contain elements constituting the electrolyte or become hydrates, so that their physical properties change. For example, when an organic acid is used for the electrolyte, carbon is contained in the oxide film, and when sulfuric acid is used, sulfur is contained. The use of materials containing alkali metal ions for the electrolyte should be avoided. This is because alkali metal ions (sodium or potassium), when penetrating into the semiconductor region, significantly damage the conductive properties of the semiconductor.

The thickness of the oxide film is determined according to the required breakdown voltage, and since the gate electrode recedes by this oxidation step, the thickness is determined in consideration of how the impurity region overlaps the gate electrode. Typically, the thickness of the oxide film is 10 to 1000 nm.

Also, for example, when only the gate wiring is connected to the power supply and the storage capacitor wiring is not connected, an oxide film is formed only on the gate wiring, and the storage capacitor wiring is substantially formed of a material other than the natural oxide film. No oxide film is formed. Alternatively, the time, current, voltage, etc., for energizing each may be changed. Thus, the thickness of the oxide film to be formed can be changed. For example, when used as an interlayer insulator, it is desirable that the film thickness be large in order to reduce the capacitance between wirings, while on the other hand, when it is used as an insulator of a capacitor such as a storage capacitor, it is desirable that the film thickness be thin. When there is a difference in such purposes, it is effective to use the above-described method.

When the wiring and the like are covered with the oxide film in this way, the substrate is taken out of the solution and dried well. If necessary, the oxide film may be modified by exposure to hot water or high-temperature steam. That is, in the anodic oxidation method,
Under conditions intended to obtain a particularly thick oxide film, the obtained film is a porous film. Although such a film is thick, there may be a problem with the withstand voltage.
In a later step, the current may be short-circuited through the hole. In such a case, the oxide film may be reacted with high-temperature water to form a hydrate, and the volume may be expanded to close the roughness. Thus, a dense film having good insulating properties can be obtained. In any case, it is necessary to sufficiently wash and dry the electrolyte so that no electrolyte remains on the coating. Thus, FIG. 1C is obtained.

After that, a metal film is formed and is patterned to form, for example, the drain wiring / electrode 110 and the source electrode 11. In particular, in a multilayer wiring such as a matrix circuit, the wiring formed in this manner may need to intersect with the wiring formed first. Conventionally, after an initial wiring is formed, an interlayer insulating material is formed with an insulating material, and then an upper wiring is formed. In the present invention, an upper wiring is formed directly without forming an interlayer insulating material. It is possible. That is,
This is because the lower wiring is already covered with the oxide film. Therefore, it is possible to reduce the number of masks by one at this stage as compared with the conventional method. Thus, FIG. 1D is obtained.

In the present invention, the mask required to obtain FIG.
And three for forming the second metal wiring. However,
The conventional method requires four wafers for forming a semiconductor region, forming a first metal wiring, forming a source electrode of a transistor (a hole is formed in an interlayer insulator), and forming a second metal wiring.

Thereafter, for example, as shown in FIG. 1E, a film of a transparent conductive material such as indium tin oxide or tin oxide is formed by, for example, a sputtering method, and this is patterned to form a pixel electrode of a liquid crystal display. If formed, the pixels of the liquid crystal display are formed. The number of masks required for the above steps is four. FIG. 2 shows a state in which the pixels of the liquid crystal display thus manufactured are viewed from above. Dashed lines abcd in the figure correspond to abcd in FIG. 1E, and FIG. 1 schematically shows a cross section at each point.

As is clear from FIG. 1E, the impurity region 1 of the thin film transistor (TFT)
08 and the end of the gate electrode do not match. In the figure, the gate electrode and the impurity region are drawn so as not to overlap. An opening L between the gate electrode and the impurity region (this is referred to as an offset) is designed to be, for example, 0.2 to 0.5 μm. This feature is also a feature of the present invention. That is, in the example of FIG. 1, after the impurity is implanted in a self-aligned manner to form the impurity region, the surface of the gate electrode is oxidized, so that the surface of the gate electrode recedes by this oxidation step. Therefore, an offset state is set. With such an offset state, T
It is possible to obtain an effect of increasing the ON / OFF ratio of the drain current of the FT and suppressing an increase in the leak current that is often seen when a gate voltage of an opposite polarity is applied.

FIG. 1 shows an example in which the relationship between the gate electrode and the impurity region is offset,
According to the present invention, the magnitude L of the offset can be set to an arbitrary value, and the gate electrode and the impurity region can be freely overlapped.
That is, for example, if the ion implantation method is used as the impurity implantation method, the degree of secondary scattering of the implanted ions can be adjusted depending on the energy of the ions. Secondary scattering of ions causes impurity ions to go under the gate electrode. That is, if the secondary scattering is large, the overlap between the gate electrode and the impurity region is large, resulting in an overlapping state. Also, if the secondary energy is suppressed by reducing the energy of the ions, the overlap is suppressed.

On the other hand, in the present invention, the gate electrode recedes thereafter by oxidizing the gate electrode. The degree of this regression is determined by the degree of oxidation. Therefore, by controlling the ion implantation energy and the oxidation conditions, the offset state and the overlap state can be realized with an arbitrary size.

In the figure, the storage capacitor electrode / wiring 107 is shown. This electrode / wiring faces the transparent pixel electrode 112 via the oxide film, and is kept at the same potential as the counter electrode formed with the liquid crystal interposed therebetween, thereby providing a capacitance parallel to the capacitance of the liquid crystal pixel. Configuration. This is provided, for example, for the purpose of reducing the fluctuation of the potential of the liquid crystal pixel due to ON / OFF of the gate signal when the parasitic capacitance between the gate and the source of the thin film transistor (TFT) is large. In the example of FIG. 1, oxides such as titanium, aluminum, and tantalum serve as dielectrics, and the relative dielectric constant of these materials is more than twice that of silicon oxide, which is a typical insulating / dielectric material. Area can be reduced. That is, it is possible to increase the area of a portion of the liquid crystal pixel that transmits light (increase the aperture ratio). In addition, such storage capacitors are not necessary in liquid crystal displays.

FIG. 3 shows another example of the present invention. In the example of FIG. 1, the interlayer insulator is only the oxide film of the lower wiring. In this case, however, there is a problem in thickness, and since such an oxide has a large dielectric constant, This causes an increase in the capacitance between wirings. Therefore, FIG.
In the following, an example is shown in which the interlayer insulating material is made into two layers, the thickness thereof is increased, and the average dielectric constant is reduced to reduce the capacitance between wirings.

As in the case of FIG. 1, a passivation film 302 is formed on an insulating substrate 301, a semiconductor region 303 is formed, a gate oxide film 304 is formed, a gate wiring 305, a gate electrode 306, and a storage capacitor wiring 307 are formed. Is formed, an impurity is implanted in a self-aligned manner by an ion implantation method to form an impurity region 308. Before this ion implantation, unlike the case of FIG. 1, it is preferable to leave all the gate oxide films. Thus, FIG. 3A is obtained.

Thereafter, as shown in FIG. 3B, the surfaces of the gate wiring 305, the gate electrode 306, and the storage capacitor wiring 307 are oxidized as necessary as in the case of FIG. Then, an interlayer insulator 313 is formed, and holes 314 and 31 for source and drain electrodes are formed therein.
5 is formed. Further, a drain wiring 310 and a source electrode 311 are formed to obtain FIG.

Finally, a transparent conductive electrode (pixel electrode) 312 is formed as shown in FIG.
The pixels of the liquid crystal display are formed. In this example, the number of masks used in all the steps is five, that is, formation of a semiconductor region, formation of a gate wiring, formation of an interlayer insulating film, formation of a drain wiring, and formation of a pixel electrode. Is the same as the conventional case.

However, in the present invention, for example, the intersection of the gate wiring and the drain wiring
It has a two-layer structure, such as an oxide layer of a gate wiring and a layer of an interlayer insulator. In particular, the oxide formed by anodization is honey and has high pressure resistance, so it is suitable for insulation separation between layers. It is. Conventionally, there was only one interlayer insulating layer,
There is a problem in its pressure resistance, especially since there is a step at the wiring intersection, the interlayer insulator cannot cover this step, and there is a defect such as a crack, which causes a short circuit with the upper wiring. There were many things. However, in the present invention, it is not necessary to consider such a defect due to a step at all, which contributes to a great improvement in yield.

Although the above example describes an example using only one conductive type thin film transistor, it is needless to say that a complementary device combining two or more transistors, that is, a so-called CMOS can also be used. it can. FIG. 4 shows the CM
The example of the pixel of the liquid crystal display using the OS is shown. In the case of CMOS, one or two more photolithography steps are required for one conductivity type transistor. FIG. 4 shows a process that requires five masks to form one pixel.

First, a passivation film 402 is formed on an insulating substrate 401, and semiconductor regions 403a and 403b are selectively formed, as in the examples described above. Thereafter, a gate insulating film is formed, and a metal wiring 409 and gate electrodes 406a and 406b are formed thereon using a material such as aluminum.

Then, the surfaces of the wirings and electrodes are oxidized by an anodic oxidation method to an appropriate thickness. For example, when aluminum is used as the wiring / electrode material, the surface is covered with a coating 409 of aluminum oxide. Next, if the gate insulating film is silicon oxide, for example, if the substrate is lightly etched with a 1/10 HF (hydrogen fluoride) solution, the gate insulating film is selectively etched. At this time, the silicon oxide under the gate wiring and the gate electrode covered with the aluminum oxide is not etched. After that, an impurity is introduced into the semiconductor region by a known method. At this time, the conductivity type of the impurity is, for example, n-type.

Alternatively, the same structure can be obtained by oxidizing the surface of the gate wiring / electrode and then introducing impurities while the gate insulating film remains, and then etching the gate insulating film using aluminum oxide as a mask. Can be Thus, FIG. 4A is obtained.

For example, in the example of FIG. 1 or FIG. 3, the impurity introduction was performed before the oxidation of the surface of the wiring and the electrode, and in the example of FIG. 1, the removal of the gate insulating film was also performed before the surface oxidation. Then, as typically shown in FIG. 1 (C), aluminum oxide remained on the surface of the wiring / electrode like a mushroom umbrella. For example, if the thickness of the aluminum oxide is 500 nm, a protrusion of about 250 nm can be formed, so that in subsequent wiring formation, voids and voids are generated under the umbrella,
It could cause disconnection. However, in the example of FIG. 4, there is little occurrence of such voids and voids, and there is no problem such as disconnection.

Next, the left semiconductor region 403a is covered with a material 407 such as a photomask, and p-type impurities are introduced in that state. Through the above steps, an n-type impurity region 408a and a p-type impurity region 408b are obtained. In this way, FIG.
) Is obtained.

Instead of the above steps, with no impurities added to any of the semiconductor regions,
First, the semiconductor region 403b is covered with a photoresist or the like to form a semiconductor region 403a.
A step of introducing an n-type impurity only into the semiconductor region 403a and then introducing a p-type impurity only into the semiconductor region 403b may be adopted. However, when such a method is adopted, one more mask is required in addition to the method of FIG.

Subsequent steps are the same as in the example of FIG. 1, and the metal wiring / electrodes 410a and 410b, 411
Is formed to obtain a structure as shown in FIG. 4C, and further, a pixel electrode 412 is formed to obtain a structure as shown in FIG.

FIG. 5 shows a top view of one pixel of the liquid crystal display device obtained by the above steps. In this example, a part of the gate wiring 405 (or the adjacent gate wiring 405 ′) is inserted under the pixel electrode 412, thereby forming a capacitor between them, and has the same function as the storage capacitor of FIG. I decided to have it. A, b, and c given in the chain line in FIG. 5 correspond to a, b, and c in FIG. 4D, and FIG. 4 shows a cross section along the chain line.

The above is an example in which a CMOS structure is used as an inverter structure. In addition, Japanese Patent Application Nos. 3-164542, 3-145643, and 3-3-5 filed by the present inventors.
145566, 3-157502, 3-157503, 3-157504
, 157505, 3-157506, 3-157507, and the like, or a modified structure thereof.

The number of masks for obtaining this structure is five for forming a semiconductor region, forming a gate electrode and wiring, forming a p-type impurity region, forming a (second) metal wiring, and forming a pixel electrode.
It is a sheet. Conventionally, there are a total of six sheets for forming a semiconductor region, forming a gate electrode and wiring, forming a p-type impurity region, forming an electrode hole for an interlayer insulator, forming a (second) metal wiring, and forming a pixel electrode. Was needed.

FIG. 6 shows another manufacturing method using the present invention for obtaining a CMOS structure. This will be more easily understood from the fabrication method shown in FIG. 3 and the previous FIG. In this example, when the thickness of the intersection between the first wiring 605 and the second wiring 610a is not sufficient with the anodic oxide film 609 of the metal wiring alone, it is considered that the capacitance between the wirings becomes too large. Then, an interlayer insulator 613 is separately formed in addition to the anodic oxide film. In that case, a semiconductor region (603a, 603b) formation, a gate wiring / electrode (605, 606a, 606b) formation, a resist (607) formation,
Formation of electrode holes (614a, 614b, 615) of interlayer insulating material, second metal wiring,
It is necessary to form six electrodes (610a, 610b, 611) and a pixel electrode (612). This is the same as the minimum number required by the conventional manufacturing method, but the effect obtained by utilizing the present invention is that the effect obtained by the manufacturing method of FIG. And substantially the same, and a high yield could be achieved.

FIG. 7 shows another example using the present invention. FIG. 1 (and FIG. 4) or FIG.
In the example of (and FIG. 6), the thickness of the interlayer insulator between the lower wiring and the upper wiring and the thickness of the insulator between the storage capacitor wiring and the pixel electrode are substantially the same. Is preferred to be thicker, while the latter is preferred to be thinner. A method for solving this contradiction is the method shown in FIG.

As in the case of FIG. 1, a passivation film 702 is formed on an insulating substrate 701, a semiconductor region 703 is formed, a gate oxide film 704 is formed, and a gate wiring 705, a gate electrode 706, and a storage capacitor wiring 707 are formed. After formation, the surfaces of these wirings / electrodes are anodized, and further, using the anodized film 709 as a mask,
The gate insulating film is removed. Then, an impurity is implanted by ion implantation in a self-aligned manner using the gate as a mask to form an impurity region 708. The gate insulating film may be left without being removed. Thus, FIG. 7A is obtained.

After that, a pixel electrode 712 is formed as shown in FIG. Further, FIG.
As shown in C), an interlayer insulator 713 is formed, and holes 714 for source and drain electrodes are formed therein. Further, a drain wiring 710 is formed to obtain FIG.

In the pixel of the liquid crystal display having such a structure, the interlayer insulator at the intersection of the wiring is thick and the dielectric layer of the storage capacitor is thin. The masks required for the above steps are five, that is, formation of a semiconductor region, formation of a gate wiring and an electrode, formation of a pixel electrode, formation of an electrode hole for an interlayer insulator, and formation of an upper metal wiring.

However, in such a structure, the upper metal wiring (functioning as a drain wiring) is located above the pixel electrode, and as a result, when the opposing electrode is provided,
A phenomenon occurs in which the electric field in the drain wiring portion is large and the electric field in the pixel electrode portion is small. In a normal operation, the drain wiring is in a state where a signal can be constantly applied. Therefore, even if the area of the drain wiring is small, the voltage applied thereto is large, so that regardless of the image, It always presents a bright or dark state, giving serious problems to the image. Further, since the signal of the drain wiring includes information of another pixel, a phenomenon similar to crosstalk occurs as a result. Therefore, when adopting the structure as shown in FIG. 7, pay sufficient attention to this point. For example, the TFT panel is arranged on the near side (the drain wiring is always invisible and cannot be seen. (The effect of the signal does not appear visually.)

In the examples of FIGS. 1 and 3, the pixel electrode was not flat because the storage capacitor wiring and the like exist below the pixel electrode. For this reason, a difference in the magnitude of the electric field occurs in the same pixel electrode, and further, a slight difference in the width of the wiring may cause a difference in the brightness of each pixel. For this reason, in order to obtain a pixel with little variation, it is desirable that the pixel electrode is flat and the height of each pixel is the same. FIG. 8 is an example of the present invention which solves such a problem.

1 and 7, a passivation film 802 is formed on an insulating substrate 801, a semiconductor region 803 is formed, a gate oxide film 804 is formed, a gate wiring 805, a gate electrode 806, and a storage capacitor are formed. After forming the wiring 807,
The surfaces of these wirings and electrodes are anodized, and the gate insulating film is removed using the anodic oxide film 809 as a mask. Then, impurities are implanted in a self-aligned manner by ion implantation using the gate as a mask to form an impurity region 808. The gate insulating film may be left without being removed. Thus, FIG. 8A is obtained.

After that, a drain wiring 810 is formed as shown in FIG. Further, as shown in FIG. 8C, for example, a flat film 813 is formed with an organic material such as polyimide, and finally a hole 815 for a source electrode is formed, and a pixel electrode 812 is formed.
FIG. 3D is obtained.

The masks required for the above steps include formation of a semiconductor region, formation of gate wiring and electrodes,
There are five sheets: upper metal wiring formation, formation of an electrode hole for an interlayer insulator, and formation of pixel electrodes. As described above, by using the present invention, semiconductor devices for extremely various purposes can be manufactured.

In the present invention, an anodic oxidation method may be used as a method for oxidizing a metal wiring. In this anodic oxidation method, a high voltage of 50 to 200 V or more may be applied between the anode and the cathode in the electrolytic solution, and the area around the metal wiring / electrode during the anodization may be 10 MV / cm. Such a large potential gradient may occur. Therefore, it is necessary to protect the gate insulating film from such a high voltage. For this purpose, it is desired that the semiconductor region has the same potential as the gate wiring / electrode.

FIG. 9 illustrates the method. First, a semiconductor region 903 in a stripe shape is formed over an insulating substrate 901. Then, after forming a gate insulating film on the semiconductor region, holes 916 are provided in the gate insulating film at the end of each semiconductor region, and then a gate wiring / electrode 905 is formed. That is, the semiconductor region 903 and the gate wiring / electrode 905 are kept at the same potential via the hole 916. Thereafter, if anodization is performed, an electric field is not substantially generated between the semiconductor region and the gate wiring / electrode, so that the gate insulating film is less likely to be broken by an excessive voltage. This state is shown in FIG.

After the anodization, impurities are introduced, and the stripe-shaped semiconductor region is divided into appropriate lengths. Then, a hole 917 is provided in the gate wiring-shaped anodic oxide film, and then a drain wiring / electrode 910 is formed. In this state, the gate wiring 905 and the drain wiring 916 are kept at the same potential. As a result, at the intersection of the gate wiring and the drain wiring, dielectric breakdown caused by static electricity generated during the operation can be prevented. However, this step has nothing to do with the high voltage during anodization. After that, the pixel electrode 912 is formed, and then the peripheral metal wiring may be removed.

In the above steps, a lithography step is required in order to form a hole for connection between wirings around the substrate, but the accuracy of these is so low that it does not pose a problem as compared with that of the pixel portion. The addition of these steps hardly reduces the yield. Furthermore, for example, it is also possible to evaporate only the oxide film on the surface by using a laser, and if such a method is adopted, the process is greatly simplified.

The mask used in the method of FIG. 9 includes (1) formation of a stripe-shaped semiconductor region,
(2) Drilling holes in the gate insulating film, (3) forming gate wirings and electrodes, (4) cutting semiconductor regions in stripes, (5) drilling holes for anodized film formation, (6) drain wirings As compared with the method of FIG. 1 for obtaining the same structure, such as formation of electrodes and (7) formation of pixel electrodes, a larger number of masks are required.
1) and (5), the masks required in the steps do not need to be precise, so that five masks, one more than in FIG. 1, are required.

According to the present invention, a TFT can be manufactured using a smaller number of masks than in the related art. Further, according to the present invention, a TFT having higher reliability can be manufactured although the number of masks is not different from that of the related art. In particular, an object of the present invention is to provide a TFT
To improve the yield. In particular, the formation of the source and drain electrodes of the TFT is 1 μm.
This is an advanced operation that requires an accuracy of m or less, and the number of defective panels generated by this process was significantly larger than those generated by other processes.

The number of defects increased as the number of TFTs integrated in the panel increased, and as the area of the panel increased. That is, both the formation of the electrode holes and the formation of the electrode wiring required extremely advanced techniques. According to the present invention, for example, since it is not necessary to form a hole in the electrode, the yield is mainly only to form the electrode wiring. For example, the rate of occurrence of defects in drilling and electrode wiring formation is 2
If it is 0%, if these two steps are performed, only 64% of non-defective products are obtained.
If the present invention is used, a hole punching step is not required, and 80% of the products are non-defective.

On the other hand, particularly in a liquid crystal display, occurrence of a defect due to a short circuit between a gate wiring and a signal line (source / drain wiring) has been a serious problem. This is directly a defect caused by a problem in handling, but indirectly is considered to be a defect of the interlayer insulator. That is, the silicon oxide used as the interlayer insulator cannot completely cover the undulations of the wiring, and its thickness may be thick or thin. In particular, the film may not be formed on the side surface of the gate wiring as the lower wiring. It has become thin. On the other hand, a film having a sufficient thickness was formed on the upper surface of the lower wiring. When the upper wiring is formed in this state,
A short circuit was likely to occur on the side surface of the lower wiring. However, according to the present invention, such a problem can be solved because the anodic oxide insulating film having substantially the same thickness on both the side surface and the upper surface of the lower wiring can be formed. If an interlayer insulating film is formed as in the related art after forming the anodic oxide insulating film, the insulating effect can be further enhanced.

An embodiment using the present invention will be described with reference to FIG. In this embodiment, the present invention is applied to a CMOS type TFT formed on an AN glass substrate. First, as shown in FIG. 10A, an AN glass substrate 151 is formed by a low pressure CVD method.
A silicon nitride film 152a is formed to a thickness of 100 nm. The low-pressure CVD uses dichlorosilane (SiH ₂ Cl ₂ ) and ammonia as source gases, and has a pressure of 10 to 1000 P.
In a, the reaction may be performed at 500 to 800 ° C, preferably 550 to 750 ° C. Of course, silane (SiH ₄ ) or trichlorosilane (SiHCl ₃ ) may be used. Further, instead of the low pressure CVD method, a CVD technique such as a plasma CVD method, a photo CVD method, or a plasma enhanced CVD method may be used.

The silicon nitride film formed in this manner has a function of preventing mobile ions (such as sodium ions) contained in the glass substrate from entering the semiconductor. Therefore, it is not necessary to provide a silicon nitride film if the mobile ions are sufficiently small on the substrate.
Further, the silicon nitride film may be an aluminum oxide film. In forming the aluminum oxide film, trimethylaluminum (Al (CH ₃ ) ₃ ) and an oxidizing gas such as oxygen or dinitrogen monoxide (N ₂ O) may be used in the aforementioned low pressure CVD method. . A similar material may be used even when another CVD method is adopted. Further, it can also be formed by a sputtering method.

Although the figure shows a state in which the silicon nitride film is provided only on the element formation surface on the glass substrate, it is preferable to form the film so that the entire glass substrate is covered with the silicon nitride film if possible. . Because, in the later anodic oxidation step, the substrate is immersed in the solution, so if there is an exposed part of the glass, alkali ions will dissolve out of the part into the solution and adhere to the semiconductor region, This is because it is possible to invade.

Next, a silicon oxide film 152b is formed with a thickness of 70 nm. In this formation,
ECR plasma CVD or sputtering was suitable. A semiconductor region is formed on the silicon oxide film. If many interface states, trap centers, and the like are generated at the interface between the silicon oxide film and the semiconductor region, the conductivity of the semiconductor region is reduced. It cannot be controlled, and deteriorates the characteristics of the transistor. Therefore,
Care must be taken in forming this silicon oxide film. In particular, silicon nitride cannot be used instead of silicon oxide. That is, in many cases, the silicon nitride film itself has a property of trapping carriers inside.

According to the studies by the present inventors, a silicon oxide film formed by ECR plasma CVD or sputtering has a sufficiently low interface state density, and is therefore suitable for this purpose. In particular, when forming by sputtering, a silicon oxide bulk was used as the target, the atmosphere was a mixed atmosphere of oxygen and argon, and the oxygen concentration was 50 to 100%. Also, ECR
When formed by plasma CVD, silane (SiH ₄ ) and oxygen may be used. The density of the interface states between the silicon oxide film thus formed and the semiconductor film (silicon film) formed thereafter was -10 ¹¹ cm ^-2 , which was extremely excellent. Further, when forming a film by sputtering or ECR plasma CVD, 1 to 5% of hydrogen chloride or hydrogen fluoride is mixed in the atmosphere, or silane containing chlorine or fluorine (for example, If dichlorsilane or silicon tetrafluoride (SiF ₄ ) is mixed in an amount of 1 to 10%, chlorine or fluorine is taken into the silicon oxide film, these are strongly bonded to silicon, and unpaired silicon-oxygen bond is formed. Terminators, and the interface state can be further reduced. For example, 5-9 × 10 ¹⁰ c
m ⁻² .

Next, a silicon film is formed to a thickness of 30 nm by a low pressure CVD method. 6N or more silane (SiH ₄ , Si ₂ H ₆ , Si ₃ H ₈ ) was used as a silicon source, and impurity doping was not performed. However, especially when used as CMOS,
When it is required that the threshold voltages of the NMOS and the PMOS are substantially equal to each other, the source gas contains diborane (boron) so as to contain boron in an amount of 10 ¹⁵ to 10 ¹⁶ cm ^−3.
B ₂ H ₆ ) may be mixed in a trace amount. Alternatively, an equivalent treatment is to use
This can also be performed by implanting impurity ions (for example, BF ₂ ⁺ ) into the silicon film.

The above three layers were formed by a film forming apparatus capable of forming a film continuously without exposing the substrate to the atmosphere, that is, a so-called multi-chamber type film forming apparatus. In particular, in a thin film transistor, the characteristics of the interface of the semiconductor are important, and therefore, a continuous film formation method capable of preventing the interface from being contaminated is indispensable.

Thereafter, the silicon film was patterned by a known photolithography method to form a P-channel TFT region 153a and an N-channel TFT region 153b. Then, annealing was performed at 600 ° C. for 24 to 72 hours in a hydrogen atmosphere to crystallize. Further, a silicon oxide film 154 to be a gate insulating film was formed by the sputtering method or the ECR plasma CVD method described above. As with the silicon oxide film 152b, the interface characteristics with the semiconductor region are important as in the case of the silicon oxide film 152b. This silicon oxide film was formed with a thickness of 100 nm.

Thereafter, the aluminum film was formed to a thickness of 0.8 to 1 by electron beam evaporation.
Only 0 μm was formed. In addition, a sputtering method or an organic metal CVD method can be used for forming the aluminum film. Then, these aluminum films are patterned by a known photolithography method to form a gate electrode 156.
a and 156b, and further, a gate wiring 155 were formed. Thus, FIG.
A) was obtained. The width of the gate electrode was 10 μm.

Then, the surface of the gate electrode / wiring was oxidized by an anodizing method to form an aluminum oxide film having a thickness of 0.3 to 0.5 μm. Anodization was performed according to the following procedure. Here, it should be noted that the numerical values used in the following description are merely examples, and the optimum value is determined according to the size of the element to be manufactured and the like. That is, the numerical values used in the following description are not absolute. First, an ethylene glycol solution of tartaric acid having a sufficiently low alkali ion concentration was prepared. The concentration of tartaric acid is 0.1 to 10
%, For example, 3%, and 1-20%, for example, 10% aqueous ammonia was added thereto to adjust the pH to 7 ± 0.5.

A platinum electrode was provided as a cathode in the solution, and the substrate and the substrate were immersed in the solution. And
Gate wiring and electrodes on the substrate were connected to the positive electrode of the DC power supply. At first, the current was passed so as to be constant at 2 mA. The voltage between the anode and the cathode (platinum electrode) changes with time depending on the concentration of the solution and the thickness of the oxide film formed on the gate electrode and wiring, and generally, as the thickness of the oxide film increases, , A high voltage is required. In this way, the current was kept flowing, and when the voltage became 150 V, the voltage was kept constant, and the current was kept flowing until the current reached 0.1 mA. The constant current state lasted about 50 minutes, and the constant voltage state lasted about 2 hours. Thus, an aluminum oxide film 159 having a thickness of 0.3 to 0.5 μm was formed on the surface of the gate electrode / wiring. The aluminum oxide film thus formed was sufficiently dense by itself, but was kept in hot water for 10 minutes in order to further increase the insulating property. By this step, a high withstand voltage film of 6 to 12 MV / cm was formed. This state is shown in FIG.

After that, the substrate is immersed in a hydrofluoric acid solution, for example, 1/10 hydrofluoric acid, and the silicon oxide film 154 is etched to expose the surface of the semiconductor region. At this time, since the aluminum oxide is insoluble in hydrofluoric acid, the silicon oxide film under the gate electrode and wiring is not removed but remains as it is. However, care must be taken if the silicon oxide film is left in hydrofluoric acid for a long time, because the silicon oxide film under the gate electrode and wiring will also be dissolved.

Thereafter, boron ions or boron compound ions (for example, BF ₂ ⁺ ) are first implanted by 10 ¹⁸ cm ^-3 by a known ion implantation method. At that time, no ions enter the portion of the semiconductor region below the gate electrode except for secondary scattering of the implanted ions, that is, the impurity region may be formed in a self-aligned manner (self-alignment). it can. Thus, a P-type impurity region 158a is formed.

Next, as shown in FIG. 10C, a semiconductor region 1 is formed with a photoresist 157.
Phosphorus ions are implanted in a state where only the semiconductor region 153b is exposed, covering 53a. At this time, the phosphorus concentration is set to 10 ²⁰ cm ⁻³ . Then, the semiconductor region 153b
Already has boron, but phosphorus has a higher concentration, so that it shows N-type and an N-type impurity region 158b is obtained. As described above, the impurity element can be introduced into the semiconductor region. However, in the region into which such an impurity is introduced, the crystal is destroyed by an impact at the time of ion implantation, and an amorphous or microcrystalline state is obtained. Or, they are in a mixed state. Since there is no appropriate term to describe this state, it is described here as an amorphous state.

Next, the photoresist was removed, and laser annealing such as an excimer laser or an argon ion laser was applied from above to perform laser annealing. Laser annealing is performed, for example, with a KrF excimer laser (wavelength 248 n).
m, pulse width 10 nsec), the energy density is 150 to 250 m.
When 10 shots of a beam of J / cm ² , for example, 210 mJ / cm ² are added, crystallization can be performed almost certainly. If the number of shots is less than this, the degree of crystallization is not uniform due to uncontrollable fluctuations and variations in laser output. Also,
In this laser annealing, since no light beam enters below the gate electrode, crystallization cannot be performed below the gate electrode. However, when the semiconductor region is thick, the laser beam is wrapped by the diffraction of the light beam and crystallization proceeds. The extent to which the laser light wraps around is about the wavelength of the laser when the thickness of the semiconductor region is larger than the wavelength of the laser, and is about the thickness of the semiconductor region when the thickness of the semiconductor region is smaller than the wavelength of the laser. is there. As in this embodiment, the thickness of the semiconductor region is 30 nm and the wavelength of the laser light (
248 nm), the degree of the wraparound is sufficiently smaller than the width (10 μm) of the gate electrode. Therefore, there is a portion where the crystallinity cannot be recovered by this laser annealing, while being in an amorphous state by ion implantation. The significance of that part will be described later.

As described above, the structure of the CMOS type TFT was largely obtained. After that, this TF
It is sufficient to form a metal wiring on T. However, unlike conventional TFTs, it is very simple because the trouble of forming source and drain electrode holes can be omitted. That is, since the semiconductor region is already exposed, an ohmic junction can be obtained only by forming a metal film such as aluminum thereon. Therefore, for example, after forming a multilayer film of aluminum or aluminum and chromium 163 as shown in FIG.
Unnecessary portions may be etched by a known photolithography method to form the second wirings 160a and 160b, 161 and the like.

Alternatively, if the element does not require much accuracy, use a metal mask,
These wirings may be formed directly by a vacuum evaporation method or the like. Thereafter, FIG.
), A film 162 of the pixel electrode of the liquid crystal display is selectively formed,
Liquid crystal pixels were formed.

The number of masks used in the above steps is (1) for forming the semiconductor region 153, (2) for forming the gate electrode and wiring, (3) for forming the photoresist 157, (4) for forming the second wiring, (5) Five sheets for forming pixel electrodes. Focusing on the TFT of the present embodiment, in addition to the normal impurity region 164, there is an offset region due to a geometrical deviation between the gate electrode and the impurity region. A doped region 165 has been formed. The usefulness of providing such an amorphous portion is described in "Insulated Gate Semiconductor Device and Fabrication Thereof" filed on August 26, 1991 by the Semiconductor Energy Laboratory Co., Ltd. The method is described in detail in “Method” and will not be described here.

A polyimide film was formed as an alignment film of a liquid crystal material on the substrate (hereinafter referred to as a first substrate) manufactured by the above steps. The surface of this polyimide film was treated by a known rubbing method, and after forming a transparent electrode on the other second substrate, an orientation film was formed in the same manner as the first substrate, and rubbing treatment was performed. These substrates were bonded together so that the rubbing directions were parallel to each other to produce a liquid crystal cell.

Thereafter, a nematic liquid crystal material is injected into the liquid crystal cell, and the two change numbers are set so that the polarization axes are crossed on both sides of the liquid crystal cell, and the rubbing direction of both substrates is at an angle of 45 degrees. A liquid crystal electro-optical device was attached in the direction shown below.
In this NON-TWISTED-NEMATIC type liquid crystal electro-optical device, when turned off, light (white) is displayed due to the birefringence of the liquid crystal material, and when turned on, the liquid crystal molecules stand in the vertical direction with respect to the substrate, and thus dark (black). ) Is displayed.
The application of the semiconductor device of the present invention can be applied not only to the above-mentioned liquid crystal electro-optical device but also to other types of liquid crystal electro-optical devices, for example, antiferroelectric liquid crystal electro-optical devices. Is also applicable.

An example of a manufacturing process of a TFT according to the present invention will be described. 1 shows an example of a pixel of a liquid crystal display manufactured according to the present invention. An example of a manufacturing process of a TFT according to the present invention will be described. An example of a manufacturing process of a TFT according to the present invention will be described. 1 shows an example of a pixel of a liquid crystal display manufactured according to the present invention. An example of a manufacturing process of a TFT according to the present invention will be described. An example of a manufacturing process of a TFT according to the present invention will be described. An example of a manufacturing process of a TFT according to the present invention will be described. 1 shows an example of manufacturing a liquid crystal display panel according to the present invention. The manufacturing process of the TFT according to the present embodiment will be described.

Explanation of reference numerals

Reference Signs List 101 Insulating substrate 102 Passivation film 103 Semiconductor region 104 Gate insulating film 105 First wiring (gate wiring)
106 Gate electrode 107 First wiring (storage capacitor wiring)
108 Impurity region 109 Anodized insulating film 110 Second wiring (drain electrode / wiring)
111 Second wiring (source electrode / wiring)
112 Pixel electrode and wiring

Claims (8)

A silicon nitride film in contact with the glass substrate surface,
A silicon oxide film in contact with the silicon nitride film;
A silicon film in contact with the silicon oxide film;
Has,
The silicon nitride film, the silicon oxide film and the silicon film are films formed continuously without exposing the glass substrate to the atmosphere,
A semiconductor integrated circuit, wherein the silicon film has crystallinity. A silicon nitride film in contact with the glass substrate surface,
A silicon oxide film containing chlorine or fluorine in contact with the silicon nitride film;
A silicon film in contact with the silicon oxide film;
Has,
The silicon nitride film, the silicon oxide film and the silicon film are films formed continuously without exposing the glass substrate to the atmosphere,
A semiconductor integrated circuit, wherein the silicon film has crystallinity. In contact with the surface of the glass substrate, three layers of a silicon nitride film, a silicon oxide film and a crystalline silicon film are laminated,
In the three-layer stack, a semiconductor integrated circuit is characterized in that an interface between the silicon nitride film and the silicon oxide film and an interface between the silicon oxide film and the crystalline silicon film are not exposed to the air. In contact with the glass substrate surface, three layers of a silicon nitride film, a silicon oxide film containing chlorine or fluorine, and a crystalline silicon film are stacked,
In the three-layer stack, the interface between the silicon nitride film and the silicon oxide film and the interface between the silicon oxide film and the crystalline silicon film are not exposed to the air. An aluminum oxide film in contact with the glass substrate surface,
A silicon oxide film in contact with the aluminum oxide film;
A silicon film in contact with the silicon oxide film;
Has,
The aluminum oxide film, the silicon oxide film and the silicon film are films continuously formed without exposing the glass substrate to the atmosphere,
A semiconductor integrated circuit, wherein the silicon film has crystallinity. An aluminum oxide film in contact with the glass substrate surface,
A silicon oxide film containing chlorine or fluorine in contact with the aluminum oxide film;
A silicon film in contact with the silicon oxide film;
Has,
The aluminum oxide film, the silicon oxide film and the silicon film are films continuously formed without exposing the glass substrate to the atmosphere,
A semiconductor integrated circuit, wherein the silicon film has crystallinity. In contact with the glass substrate surface, three layers of an aluminum oxide film, a silicon oxide film, and a crystalline silicon film are laminated,
In the three-layer stack, the interface between the aluminum oxide film and the silicon oxide film and the interface between the silicon oxide film and the crystalline silicon film are not exposed to the air. In contact with the surface of the glass substrate, three layers of an aluminum oxide film, a silicon oxide film containing chlorine or fluorine, and a crystalline silicon film are stacked,
In the three-layer stack, a semiconductor integrated circuit is characterized in that an interface between the aluminum oxide film and the silicon oxide film and an interface between the silicon oxide film and the crystalline silicon film are not exposed to the air.

Images