JP2006019647A - Semiconductor integrated circuit - Google Patents

Abstract

A semiconductor integrated circuit capable of providing a structure for setting a well potential (substrate potential) of a transistor without increasing a layout area.
A first and second semiconductor regions of a second conductivity type formed on a first conductivity type semiconductor substrate, and a semiconductor substrate between the first and second semiconductor regions. Formed in the first conductive type third semiconductor region (13) and below the first, second and third semiconductor regions, and is electrically connected to the first semiconductor region and the second semiconductor region. The second conductivity type fourth semiconductor region (14) is electrically connected to the fourth semiconductor region, and the first potential supplied to the first and second semiconductor regions is applied through the fourth semiconductor region. A first potential terminal (16); and a second potential terminal (19) which is electrically connected to the semiconductor substrate and to which a second potential supplied to the third semiconductor region via the semiconductor substrate is applied.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor integrated circuit, for example, a semiconductor integrated circuit that fixes a potential of a semiconductor substrate (well region) in the semiconductor integrated circuit.

  Conventionally, in a semiconductor integrated circuit (LSI), a semiconductor substrate or well region in which a transistor is formed is short-circuited with a source region of the transistor, and a power supply potential VDD or a ground potential GND is provided in the semiconductor substrate or well region and the source region. Is often used. However, when the power supply potential VDD or the ground potential GND is supplied to the semiconductor substrate or the well region and the source region, there is a disadvantage that the leakage current of the transistor increases.

  Therefore, in order to reduce the leakage current of the transistor and further reduce the leakage current of the entire semiconductor integrated circuit, the potential of the semiconductor substrate or well region (hereinafter referred to as well potential) in which the transistor is formed is changed to the potential of the source region (hereinafter referred to as well potential). Hereinafter, a method of changing the source potential separately from the source potential is known. For example, in recent years, a semiconductor integrated circuit in which the well potential of a transistor is set as follows has been proposed. When in the normal operation mode (Active mode), the well potential of the N channel MOS transistor is set to the same ground potential 0 V as the source potential, and the well potential of the P channel MOS transistor is set to the power supply voltage 1.8 V which is the same as the source potential. The On the other hand, when in the standby mode, the well potential of the N-channel MOS transistor is set to −1.5 V different from the source potential, and the well potential of the P-channel MOS transistor is set to 3.3 V different from the source potential. The Further, a wiring for supplying a potential is formed for each well region (see, for example, Non-Patent Document 1).

As described in Non-Patent Document 1, when the well potential is set lower than the source potential in the N channel MOS transistor and the well potential is set higher than the source potential in the P channel MOS transistor, the leakage current of the transistor is reduced. On the other hand, the driving current decreases and the operation speed decreases. For this reason, the method of changing the well potential is generally used for the purpose of reducing the leakage current when in the standby mode or the test mode. The normal operation mode is a state in which the semiconductor integrated circuit is operating in order to realize the originally intended function, and the standby mode is not in the normal operation mode although the power is applied, but immediately enters the normal operation mode by an instruction. This is the state of the power saving mode that can be transferred. The test mode indicates a state of an operation test for selecting good products and defective products.
koichiro Ishibashi et al., Central Research Laboratory, Hitachi Ltd., “Substrate-Bias Techniques for SH4”, 2001 VLSI Circuit Short Course, p.13-28

  However, in Non-Patent Document 1 described above, in order to change the well potential, a potential for fixing the well potential is prepared separately from the power supply potential VDD and the ground potential GND, and wiring for supplying these potentials is provided in the well well. It is formed for each region. Therefore, there is a problem that the layout area increases with the formation of wiring.

  Accordingly, the present invention has been made to solve the above-described problems, and provides a semiconductor integrated circuit capable of providing a configuration for setting the well potential (substrate potential) of a transistor without increasing the layout area. The purpose is to provide.

  According to an embodiment of the present invention, the first and second semiconductor regions of the second conductivity type formed on the semiconductor substrate of the first conductivity type, and between the first semiconductor region and the second semiconductor region. A first conductive type third semiconductor region formed in the semiconductor substrate; and formed under the first, second, and third semiconductor regions, and electrically connected to the first semiconductor region and the second semiconductor region. A fourth semiconductor region of a second conductivity type connected to the first semiconductor region, and a first potential electrically connected to the fourth semiconductor region and supplied to the first and second semiconductor regions via the fourth semiconductor region And a second potential terminal that is electrically connected to the semiconductor substrate and that is supplied to the third semiconductor region through the semiconductor substrate. A circuit is provided.

  According to the present invention, it is possible to provide a semiconductor integrated circuit capable of providing a configuration for setting the well potential (substrate potential) of a transistor without increasing the layout area.

  Before describing the embodiment of the present invention, a method for changing the well potential of a transistor in order to reduce the leakage current of the transistor in a semiconductor integrated circuit will be described. As described above, when the method of changing the well potential is used, the leakage current of the transistor can be reduced, while the driving current is reduced and the operation speed is lowered. Therefore, in the normal operation mode, the well potential is made the same as the source potential, and in the standby mode and the test mode, the well potential is changed to a potential different from the source potential in order to reduce the leakage current.

  In order to change the well potential, a well potential control circuit is provided outside or inside the semiconductor integrated circuit. FIG. 1 shows a configuration for well potential control in a semiconductor integrated circuit. The well potential control circuit 1 supplies a well potential suitable for each of the normal operation mode 2, the standby mode 3, or the test mode 4. That is, in the normal operation mode, a ground potential (source potential) or a potential higher than the ground potential is applied as the well potential in the N channel MOS transistor, and a power supply potential (source potential) or a power supply potential as the well potential in the P channel MOS transistor. By applying a low potential, the transistor is operated without reducing the driving current. On the other hand, in the standby mode and the test mode, a potential lower than the ground potential is applied as the well potential in the N channel MOS transistor, and a potential higher than the power supply potential is applied as the well potential in the P channel MOS transistor. To reduce.

  Hereinafter, an embodiment of the present invention having a configuration for setting a well potential capable of using the above-described method for changing the well potential will be described. In the description, common parts are denoted by common reference symbols throughout the drawings.

[First Embodiment]
First, a semiconductor integrated circuit according to a first embodiment of the present invention will be described.

  FIG. 2 is a schematic layout diagram showing the configuration of the semiconductor integrated circuit according to the first embodiment. This semiconductor integrated circuit includes a standard cell SC, a clock buffer circuit CB, potential supply wirings 5 and 6, a power supply wiring 23, and a ground wiring 24. A plurality of standard cells SC and clock buffer circuits CB are arranged on a semiconductor substrate as shown in FIG. The potential supply wirings 5 and 6 supply a predetermined well potential to the well region (semiconductor region) of the semiconductor substrate on which the standard cell SC is formed. The configuration for supplying the well potential will be described in detail later. The power supply wiring 7 supplies the power supply potential VDD to the well region of the semiconductor substrate where the standard cells SC are formed and the well region of the semiconductor substrate where the clock buffer circuit CB is formed. Further, the ground wiring 8 supplies the ground potential GND to the well region of the semiconductor substrate where the standard cell SC is formed and the well region of the semiconductor substrate where the clock buffer circuit CB is formed.

  The standard cell SC includes a combinational circuit and a sequential circuit. The combinational circuit is a switching circuit in which an output is determined only by several inputs that are input simultaneously, and is configured by a combination of basic logic gate circuits such as a NOT circuit, a NAND circuit, and a NOR circuit. The sequential circuit is a switching circuit whose output depends not only on the current input state but also on past input conditions, and a flip-flop circuit or the like corresponds to this. A logic circuit is constituted by a plurality of standard cells SC. The clock buffer circuit CB is a circuit that amplifies and transmits a clock signal, and supplies a clock signal CLK for synchronizing operations to the standard cell SC.

  FIG. 3 is an enlarged layout of the inside of the broken line A in the semiconductor integrated circuit shown in FIG. In the transistor constituting the standard cell SC, the potential supply to the well region where the transistor is formed is N-type well region (WN) 12, P-type well region (WP) 13, deep N-type well region (WB) 14, And the P-type semiconductor substrate 11. More specifically, the well potential of the N-channel MOS transistor (NMOS) is supplied by the P-type well region 13 and the P-type semiconductor substrate 11, and the well potential of the P-channel MOS transistor (PMOS) is the N-type well region 12 and the deep N-type. Supplied by well region 14. The deep N-type well region (WB) 14 is a semiconductor region formed deeper from the surface of the semiconductor substrate than the N-type well region (WN) 12 and the P-type well region (WP) 13. In FIG. 3, illustration of power supply wiring and ground wiring is omitted.

  First, the configuration of the standard cell SC will be described.

  As shown in FIG. 3, in the surface region of the P-type semiconductor substrate 11, N-type well regions (WN) 12 and P-type well regions (WP) 13 on an elongated rectangular shape are alternately arranged. Standard cells SC are formed on the N-type well region (WN) 12 and the P-type well region (WP) 13. Under the N-type well region 12 and the P-type well region 13, a deep N-type well region (WB) 14 is formed so as to be in contact with the N-type well region 12. The deep N-type well region (WB) 14 is arranged in a direction substantially perpendicular to the longitudinal direction of the N-type well region (WN) 12 and the P-type well region (WP) 13.

  An N-type well region 15 is formed on a part of the deep N-type well region (WB) 14 so as to be in contact with the deep N-type well region (WB) 14. A wiring (first potential terminal) 16 is disposed on the N-type well region 15, and the wiring 16 is electrically connected to the deep N-type well region (WB) 14 via the contact plug 17 and the N-type well region 15. Connected. Here, when the potential Vbp is supplied to the wiring 16, as shown by a broken line 14A in FIG. 3, the potential Vbp is deeply connected to the N-type well region (WB) via the contact plug 17 and the N-type well region 15. 14. Further, the potential Vbp is supplied from the deep N-type well region (WB) 14 to the plurality of N-type well regions (WN) 12 arranged. As described above, the potential supply wiring 5 is configured by the wiring 16 and the deep N-type well region (WB) 14.

  A P-type well region 18 is formed in the surface region of the P-type semiconductor substrate 11. A wiring (second potential terminal) 19 is disposed on the P-type well region 18, and the wiring 19 is electrically connected to the P-type semiconductor substrate 11 via the contact plug 20 and the P-type well region 18. ing. Here, when the potential Vbn is supplied to the wiring 19, the potential Vbn is supplied to the P-type semiconductor substrate 11 through the contact plug 20 and the P-type well region 18 as indicated by a broken line 11A in FIG. The Further, the potential Vbp supplied to the P-type semiconductor substrate 11 is supplied to a plurality of P-type well regions (WP) 13 arranged. Thus, the potential supply wiring 6 is configured by the wiring 19 and the P-type semiconductor substrate 11.

  Next, the configuration of the clock buffer circuit CB will be described.

  As shown in FIG. 3, N-type well regions (WN) 12 </ b> R and P-type well regions (WP) 13 </ b> R are alternately arranged on the surface region of the P-type semiconductor substrate 11. A clock buffer circuit CB is formed on the N-type well region (WN) 12R and the P-type well region (WP) 13R. The N-type well region (WN) 12R and the P-type well region (WP) 13R where the clock buffer circuit CB is formed are surrounded by a deep N-type well region (WB) 21. In other words, deep N-type well regions (WB) 21 are formed on the bottom and side surfaces of the N-type well region (WN) 12R and the P-type well region (WP) 13R. Further, the periphery of the deep N-type well region (WB) 21 is surrounded by a P-type well region 22.

  Due to the deep N-type well region (WB) 21 and the P-type well region 22 arranged in this way, the N-type well region (WN) 12R and the P-type well region (WP) 13R become the N-type well region (WN) 12 And electrically insulated from the P-type well region (WP) 13. Thereby, different potentials are supplied between the N-type well region (WN) 12R and the N-type well region (WN) 12, and between the P-type well region (WP) 13R and the P-type well region (WP) 13. Even if it is performed, these regions do not conduct and the well potential does not fluctuate.

  Next, an outline of the layout of the well region in which the standard cell SC and the clock buffer circuit CB shown in FIG. 3 are formed will be described.

  FIG. 4 is a schematic diagram of the layout of the well region in which the standard cell SC is formed. As shown in FIG. 4, N-type well regions (WN) 12 and P-type well regions (WP) 13 are alternately arranged in the semiconductor region where the standard cells SC are formed. Under the N-type well region 12 and the P-type well region 13, a deep N-type well region (WB) 14 is disposed so as to contact the N-type well region 13. The deep N-type well region (WB) 14 functions as a wiring layer that electrically connects a plurality of N-type well regions (WN) 12.

  FIG. 5 is a schematic diagram of a layout of a well region in which the clock buffer circuit CB is formed. As shown in FIG. 5, N-type well regions (WN) 12R and P-type well regions (WP) 13R are alternately arranged in the semiconductor region in which the clock buffer circuit CB is formed. The N-type well region (WN) 12R and the P-type well region (WP) 13R are surrounded by a deep N-type well region (WB) 21. The deep N-type well region (WB) 21 is in contact with the plurality of N-type well regions (WN) 12R, and electrically connects the plurality of N-type well regions (WN) 12R. Thus, by forming the deep N-type well region (WB) 21 surrounding the N-type well region (WN) 12R and the P-type well region (WP) 13R, the N-type well region (WN) 12R and the P-type well are formed. Noise generated from the clock buffer circuit formed in the region (WP) 13R is prevented from leaking outside the deep N-type well region (WB) 21.

  Next, an example of the circuit pattern of the standard cell SC shown in FIG. 3 will be described.

  FIG. 6 is a layout showing a circuit pattern of the standard cell SC. As shown in FIG. 6, an N-type well region (WN) 12 and a P-type well region (WP) 13 are formed on the semiconductor substrate. In the N-type well region (WN) 12, P-type semiconductor regions (source or drain regions) 12A and 12B are formed. A gate electrode 35A is formed on the N-type well region (WP) 12 between the P-type semiconductor regions 12A and 12B constituting the source and drain. A power supply wiring (power supply terminal) 23 to which a power supply potential VDD is supplied is disposed on the N-type well region (WN) 12, and a wiring 23 </ b> A is drawn from the power supply wiring 23. The wiring 23A is connected to the P-type semiconductor region 12A (or 12B) by a contact plug 23B. Further, as shown in FIG. 3, the potential Vbp is supplied to the N-type well region (WN) 12 through the deep N-type well region (WB) 14, and the N-type well region (WN) 12 is The potential is fixed at Vbp.

  In the P-type well region (WP) 13, N-type semiconductor regions (source or drain regions) 13A and 13B are formed. A gate electrode 35B is formed on the P-type well region (WP) 13 between the N-type semiconductor regions 13A and 13B constituting the source and drain. A ground wiring (ground terminal) 24 to which a ground potential GND is supplied is disposed on the P-type well region (WP) 13, and a wiring 24 A is drawn from the ground wiring 24. The wiring 24A is connected to the N-type semiconductor region 13A (or 13B) by a contact plug 24B. Further, as shown in FIG. 3, the potential Vbn is supplied to the P-type well region (WP) 13 via the P-type semiconductor substrate 11, and the P-type well region (WP) 13 is set to the potential Vbn. It is fixed.

  Furthermore, a wiring 36 for connecting the P-type semiconductor region 12A (or 12B) and the N-type semiconductor region 13A (or 13B) and a wiring 37 for connecting the gate electrodes are formed. Note that the circuit pattern in the broken line SC shown in FIG. 6 constitutes the standard cell SC. The dimension of the standard cell SC along the wiring direction of the gate electrode is about 3.0 μm, the channel width of the P channel MOS transistor in the standard cell SC is about 1.0 μm, and the channel width of the N channel MOS transistor is 0.5 μm. Degree.

  FIG. 7 is a cross-sectional view taken along line XX ′ in the circuit pattern of the standard cell SC shown in FIG.

  A deep N-type well region (WB) 14 is formed on the P-type semiconductor substrate (P-sub) 11, and an N-type well region 12 and a P-type well region 13 are formed on the deep N-type well region (WB) 14. Is formed. In the surface region of the N-type well region 12, P-type semiconductor regions 12A and 12B that are sources or drains are formed. A gate insulating film 12D is formed on the N-type well region 12 between the P-type semiconductor regions 12A and 12B, and a gate electrode 12E is formed on the gate insulating film 12D.

In the surface region of the P-type well region 13, N-type semiconductor regions 13A and 13B that are sources or drains are formed. A gate insulating film 13D is formed on the P-type well region 13 between the N-type semiconductor regions 13A and 13B, and a gate electrode 13E is formed on the gate insulating film 13D. An element isolation insulating film 30 made of STI (Shallow Trench Isolation) or the like is formed between the transistors. In the cross-sectional structure shown in FIG. 7, the N-type well region 12, the P-type semiconductor regions 12A, 12B, The gate insulating film 12D and the gate electrode 12E constitute a P-channel MOS transistor (PMOS). Similarly, the P-type well region 13, the N-type semiconductor regions 13A and 13B, the gate insulating film 13D, and the gate electrode 13E constitute an N-channel MOS transistor (NMOS). The well potential of the P channel MOS transistor is given by an N type well region (WN) 12 and a deep N type well region (WB) 14. The well potential of the N channel MOS transistor is given by a P type well region (WP) 13 and a P type semiconductor substrate (P-sub) 11. In addition, a deep N-type well region (WB) 14 under the P-type well region (WP) 13 is used to connect the N-type well regions 12 to each other. For example, in FIG. 7, the P-type well region (WP) 13 of the N-channel MOS transistor at first glance appears to be separated by a deep N-type well region (WB) 14. However, as shown in FIG. 4, in the P-type well region (WP) 13, regions where the deep N-type well region (WB) 14 does not exist below are both sides of the deep N-type well region (WB) 14. Therefore, the potential is applied from there and the well potential of the N channel MOS transistor is fixed at the potential Vbn.

  Next, an example of the circuit pattern of the clock buffer circuit CB shown in FIG. 3 will be described.

  FIG. 8 is a layout showing a circuit pattern of the clock buffer circuit CB. As shown in FIG. 8, an N-type well region (WN) 12R and a P-type well region (WP) 13R are formed on the semiconductor substrate. Further, a deep N-type well region 21 is formed so as to surround the N-type well region (WN) 12R and the P-type well region (WP) 13R.

  In the N-type well region (WN) 12R, P-type semiconductor regions (source or drain regions) 12A and 12B and an N-type semiconductor region 12C are formed. A power supply wiring (power supply terminal) 23 to which a power supply potential VDD is supplied is disposed on the N-type semiconductor region 12C. The power supply wiring 23 is connected to the N-type semiconductor region 12C by a contact plug 25. As a result, the N-type well region (WN) 12R is fixed at the power supply potential VDD.

  In the P-type well region (WP) 13R, N-type semiconductor regions (source or drain regions) 13A and 13B and a P-type semiconductor region 13C are formed. A ground wiring (ground terminal) 24 to which a ground potential GND is supplied is disposed on the P-type semiconductor region 13C, and the ground wiring 24 is connected to the P-type semiconductor region 13C by a contact plug 26. Thereby, the P-type well region (WP) 13R is fixed to the ground potential GND.

  A gate electrode 27A is formed on the N-type well region (WP) 12R between the P-type semiconductor regions 12A and 12B constituting the source and drain. A gate electrode 27B is formed on the P-type well region (WP) 13R between the N-type semiconductor regions 13A and 13B constituting the source and drain.

  A wiring 23A is drawn from the power supply wiring 23 and connected to the P-type semiconductor region 12A (or 12B) by a contact plug 23B. A wiring 24A is drawn from the ground wiring 24 and connected to the N-type semiconductor region 13A (or 13B) by a contact plug 24B. Further, a wiring 28 for connecting the P-type semiconductor region 12A (or 12B) and the N-type semiconductor region 13A (or 13B) and a wiring 29 for connecting the gate electrodes are formed. The channel width of the P channel MOS transistor constituting the clock buffer circuit CB is about 1.0 μm, and the channel width of the N channel MOS transistor is about 0.5 μm. In the clock buffer circuit, a large transistor is configured by connecting a large number of these P-channel MOS transistors and N-channel MOS transistors in parallel.

  FIG. 9 is a cross-sectional view taken along line YY ′ in the circuit pattern of the clock buffer circuit shown in FIG.

  A deep N-type well region (WB) 21 is formed on the P-type semiconductor substrate 11, and an N-type well region 12R and a P-type well region 13R are formed on the deep N-type well region (WB) 21. . The deep N-type well region (WB) 21 is disposed on the bottom and side surfaces of the N-type well region 12R and the P-type well region 13R so as to surround the N-type well region 12R and the P-type well region 13R.

  In the surface region of the N-type well region 12R, P-type semiconductor regions 12A and 12B, which are sources or drains, and an N-type semiconductor region 12C for supplying a power supply potential VDD to the N-type well region 12R are formed. A gate insulating film 12D is formed on the N-type well region 12R between the P-type semiconductor regions 12A and 12B, and a gate electrode 12E is formed on the gate insulating film 12D.

In the surface region of the P-type well region 13, N-type semiconductor regions 13A and 13B, which are sources or drains, and a P-type semiconductor region 13C for supplying the ground potential GND to the P-type well region 13R are formed. A gate insulating film 13D is formed on the P-type well region 13R between the N-type semiconductor regions 13A and 13B, and a gate electrode 13E is formed on the gate insulating film 13D. Further, an element isolation insulating film 30 made of STI (Shallow Trench Isolation) or the like is formed between the transistors. In the cross-sectional structure shown in FIG. 9, the N-type well region 12R, the P-type semiconductor regions 12A, 12B, The gate insulating film 12D and the gate electrode 12E constitute a P-channel MOS transistor (PMOS). Similarly, the P-type well region 13R, the N-type semiconductor regions 13A and 13B, the gate insulating film 13D, and the gate electrode 13E constitute an N-channel MOS transistor (NMOS). The well potential of the P channel MOS transistor is supplied by the power supply wiring 23, and the well potential of the N channel MOS transistor is supplied by the ground wiring 24.

  In the clock buffer circuit CB shown in FIGS. 8 and 9, the N-type well region (WN) 12R and the P-type well region (WP) 13R are surrounded by the deep N-type well region 21, so that the clock buffer circuit CB is externally provided. Leakage noise can be reduced.

  According to the semiconductor integrated circuit having the configuration according to the first embodiment, the well potential of the transistor on the semiconductor integrated circuit (LSI) is divided into two terminals (potential Vbn terminal and potential Vbp terminal) independently of the power supply voltage. And can be set to an appropriate well potential in the normal operation mode, standby mode, or test mode.

  Here, for example, when the power supply potential VDD in the standard cell SC is 1.0 V and the ground potential GND is 0 V, if the well potential of the P channel MOS transistor is Vbp and the well potential of the N channel MOS transistor is Vbn, the normal operation is performed. In the mode, the well potential Vbp is set to 1.0 V and the well potential Vbn is set to 0 V. In the standby mode and the test mode, the well potential Vbp is set to 2.0 V, and the well potential Vbn is set to -1.0 V.

  As described above, by setting the well potential of the transistor to an appropriate potential in the standard cell, the leakage current can be reduced in the standby mode and the test mode, and in the normal operation mode, the operation speed can be reduced without reducing the drive current of the transistor. Decrease can be prevented. Further, by surrounding the clock buffer circuit with a deep N well region, noise due to fluctuations in the well potential generated in the normal operation mode can be reduced. Thereby, performance degradation due to leakage current and noise can be prevented.

  Further, the first bias voltage can be commonly applied to the plurality of N-type well regions (WN) by using the deep N-type well region (WB) 14, and the P-type well regions (WP) can be applied to the P-type. Since the second bias voltage can be commonly applied using the semiconductor substrate, it is not necessary to form a wiring for applying the bias voltage to the well region, and an increase in layout area due to the wiring formation can be prevented.

[Second Embodiment]
Next explained is a semiconductor integrated circuit according to the second embodiment of the invention. The same reference numerals are given to the same parts as those in the first embodiment, and the description thereof is omitted. In the first embodiment shown in FIG. 3, an example in which the potential Vbp is supplied to the N-type well region (WN) 12 in which the standard cell SC is formed using the deep N-type well region (WB) 14 is shown. However, in the second embodiment, another configuration example for supplying the potential Vbp to the N-type well region (WN) 12 will be described.

  FIG. 10 is a layout showing the configuration of the semiconductor integrated circuit according to the second embodiment.

  In the surface region of the P-type semiconductor substrate (P-sub) 11, elongated rectangular N-type well regions (WN) 12 and P-type well regions (WP) 13 are alternately arranged. Standard cells SC are formed on the N-type well region (WN) 12 and the P-type well region (WP) 13. At one end of the N-type well region (WN) 12 and the P-type well region (WP) 13, an N-type well region 45 is formed on the surface region of the P-type semiconductor substrate 11, and the N-type well region (WN) 12 and the P-type well region. (WP) 13 is formed in a direction substantially perpendicular to the longitudinal direction of 13. Alternatively, the N-type well region 45 is formed above the N-type well region (WN) 12 and the P-type well region (WP) 13 in a direction substantially perpendicular to the longitudinal direction thereof. The N-type well region 45 is in contact with the N-type well region (WN) 12 and electrically connects the plurality of N-type well regions (WN) 12.

  A wiring 16 is disposed on a part of the N-type well region 45. The wiring 16 is electrically connected to the N-type well region 45 by a contact plug 17. Here, when the potential Vbp is supplied to the wiring 16, the potential Vbp is supplied to the N-type well region 45 through the contact plug 17. Further, the potential Vbp is supplied from the N-type well region 45 to a plurality of N-type well regions (WN) 12 arranged. Other configurations are the same as those of the first embodiment shown in FIG.

  FIG. 11 is a schematic diagram of the layout of the well region in which the standard cell SC shown in FIG. 10 is formed.

  As shown in FIG. 11, N-type well regions (WN) 12 and P-type well regions (WP) 13 are alternately arranged in the semiconductor region where the standard cells SC are formed. At one end and the other end of the N-type well region 12 and the P-type well region 13, an N-type well region 45 formed in the surface region of the P-type semiconductor substrate 11 is in contact with the N-type well region 12 and the P-type well region 13. It is formed to do. The N-type well region 45 functions as a wiring layer that electrically connects the plurality of N-type well regions (WN) 12, and supplies the potential Vbp of the wiring 16 to the plurality of N-type well regions (WN) 12.

  According to the semiconductor integrated circuit having the configuration according to the second embodiment, the N-type well region 12 in which the standard cell SC is formed is formed by the N-type well region 45 formed in the surface region of the P-type semiconductor substrate 11. An appropriate potential can be set, and the P-type well region 13 in which the standard cell SC is formed by the P-type semiconductor substrate 11 can also be set to an appropriate potential. By using this, if the N-type well region 12 and the P-type well region 13 are set to appropriate well potentials in the normal operation mode, standby mode, or test mode, the leakage current generated in the transistors constituting the standard cell can be reduced. . Further, as in the first embodiment, since the N-type well region (WN) 12R and the P-type well region (WP) 13R in which the clock buffer circuit CB is formed are surrounded by the deep N-type well region 21, Noise from the transistors constituting the clock buffer circuit can be reduced.

  Further, the first bias voltage can be commonly applied to the plurality of N-type well regions (WN) using the N-type well region 45, and a P-type semiconductor substrate is used for the plurality of P-type well regions (WP). Since the second bias voltage can be applied in common, it is not necessary to form a wiring for applying a bias voltage to the well region, and an increase in layout area due to the wiring formation can be prevented.

[Third Embodiment]
Next explained is a semiconductor integrated circuit according to the third embodiment of the invention. The same reference numerals are given to the same parts as those in the first embodiment, and the description thereof is omitted. In the third embodiment, another configuration example for supplying the potential Vbp to the N-type well region (WN) 12 different from the first and second embodiments described above will be described.

  FIG. 12 is a layout showing the configuration of the semiconductor integrated circuit according to the third embodiment. In the first and second embodiments shown in FIGS. 3 and 10, the N-type well region (WN) 12 in which the standard cell SC is formed is connected in the N-type well region, and the standard cell SC is formed. In the third embodiment, the N-type well region (WN) 12 is connected by the metal wiring 31, and the P-type well region (WP) 13 is connected by the P-type semiconductor substrate 11. The mold well regions (WP) 13 are connected by metal wiring 32. The metal wirings 31 and 32 are made of copper, aluminum, or the like.

  In the surface region of the P-type semiconductor substrate 11, elongated rectangular N-type well regions (WN) 12 and P-type well regions (WP) 13 are alternately arranged. Standard cells SC are formed on the N-type well region (WN) 12 and the P-type well region (WP) 13.

  An N-type well region 33 having an impurity concentration higher than that of the N-type well region (WN) 12 is formed on a part of the N-type well region (WN) 12. A metal wiring 31 is disposed on the N-type well region 33, and the metal wiring 31 is electrically connected to the N-type well region (WN) 12 through the N-type well region 33 by a contact plug 34. . Here, when the potential Vbp as the first bias voltage is supplied to the metal wiring 31, the potential Vbp is supplied to the N-type well region (WN) 12 through the contact plug 34 and the N-type well region 33.

  A P-type well region 38 having an impurity concentration higher than that of the P-type well region (WP) 13 is formed on a part of the P-type well region (WP) 13. A metal wiring 32 is disposed on the P-type well region 38, and the metal wiring 32 is electrically connected to the P-type well region (WP) 13 through the P-type well region 38 by a contact plug 39. . Here, when the potential Vbn as the second bias voltage is supplied to the metal wiring 32, the potential Vbn is supplied to the P-type well region (WP) 13 through the contact plug 39 and the P-type well region 38.

  According to the semiconductor integrated circuit having the configuration according to the third embodiment, the potential is supplied to the P-type well region (WP) 12 and the N-type well region (WN) 13 by using the deep N-type well region 14 or the N-type well region. Since the metal wirings 31 and 32 having lower electric resistance than the well region 45 are used, the potential fixing of the N-type well region (WN) 12 and the P-type well region (WP) 13 is strengthened and further hardly fluctuated. Can do. By using this, if the N-type well region 12 and the P-type well region 13 are set to appropriate well potentials in the normal operation mode, standby mode, or test mode, the leakage current generated in the transistors constituting the standard cell can be reduced. . Further, as in the first embodiment, since the N-type well region (WN) 12R and the P-type well region (WP) 13R in which the clock buffer circuit CB is formed are surrounded by the deep N-type well region 21, Noise from the transistors constituting the clock buffer circuit can be reduced.

  FIG. 13 shows a layout of a semiconductor integrated circuit according to a modification of the third embodiment. In the third embodiment shown in FIG. 12, the metal wiring 31 or 32 is connected to a part of the N-type well region (WN) 12 and the P-type well region (WP) 13, but in this modification, Metal wirings 40 and 41 are arranged along the respective longitudinal directions of the N-type well region (WN) 12 and the P-type well region (WP) 13, and the N-type well region (WN) 12 and the P-type well region (WP) are arranged. 13, the N-type well region (WN) 12 and the metal wiring 40, and the P-type well region (WP) 13 and the metal wiring 41 are connected at equal intervals. The metal wiring 40 is connected to the metal wiring 31 by a contact plug, and the metal wiring 41 is connected to the metal wiring 32 by a contact plug. The metal wirings 40 and 41 are made of copper, aluminum or the like. The power supply wiring 7 is connected to a power supply wiring 23 via a contact plug, and the ground wiring 8 is connected to a ground wiring 24 via a contact plug.

  FIG. 14 is an enlarged layout of the standard cell SC in the semiconductor integrated circuit shown in FIG. As shown in FIG. 14, an N-type semiconductor region 12C is formed in an N-type well region (WN) 12 in which standard cells SC are formed. On the N-type semiconductor region 12C, a metal wiring 40 supplied with the potential Vbp is disposed along the longitudinal direction of the N-type well region (WN) 12. The metal wiring 40 is connected to the N-type semiconductor region 12C at equal intervals along the longitudinal direction of the N-type semiconductor region 12C by contact plugs 42. As a result, the potential Vbp supplied to the metal wiring 40 is supplied to the N-type well region (WN) 12 via the contact plug 42 and the N-type semiconductor region 12C.

  A P-type semiconductor region 13C is formed in the P-type well region (WP) 13 where the standard cell SC is formed. On the P-type semiconductor region 13C, a metal wiring 41 supplied with the potential Vbn is disposed along the longitudinal direction of the P-type well region (WP) 13. The metal wiring 41 is connected to the P-type semiconductor region 13C at equal intervals along the longitudinal direction of the P-type semiconductor region 13C by contact plugs 43. Thereby, the potential Vbn supplied to the metal wiring 41 is supplied to the P-type well region (WP) 13 through the contact plug 43 and the P-type semiconductor region 13C.

  In the semiconductor integrated circuit according to the modification of the third embodiment shown in FIG. 14, the potential supply to the N-type well region (WN) 12 and the P-type well region (WP) 13 is performed using the N-type well region (WN). 12 and the P-type well region (WP) 13 can be performed by the metal wirings 40 and 41 having a low electric resistance over the entire region, so that the N-type well region (WN) 12 and the P-type well region (WP) 13 It is possible to further increase the potential fixation and make it more difficult to fluctuate. Other effects are the same as those of the third embodiment.

[Fourth Embodiment]
Next explained is a semiconductor integrated circuit according to the fourth embodiment of the invention. The same reference numerals are given to the same parts as those in the first embodiment, and the description thereof is omitted.

  In a semiconductor integrated circuit, it is effective as a noise countermeasure to surround all clock buffer circuits that distribute clock signals with a deep N-well region as shown in FIGS. The increase in the layout area becomes large. This is because the minimum layout dimension necessary for forming a deep well region is much larger than that of a metal wiring made of copper, aluminum, or the like.

  Therefore, in the fourth embodiment, in the plurality of clock buffer circuits arranged in the clock signal transmission path, the upper layer clock buffer circuit is surrounded by a deep N-type well region, and the lower layer clock buffer circuit is deep N. The structure is not surrounded by the mold well region. Regarding the configuration of the standard cell SC, any of the configurations described in the first, second, and third embodiments shown in FIGS. 3, 10, and 12 may be provided.

  FIG. 15 is a block diagram showing a configuration of a clock buffer circuit in the semiconductor integrated circuit of the fourth embodiment, and FIG. 16 is a layout of the clock buffer circuit in the semiconductor integrated circuit.

  As shown in FIG. 15, the clock signal output from the (phase-locked loop) 44 is input to the clock buffer circuit C1 via the clock buffer circuits C01, C02, and C03. The clock signal output from the clock buffer circuit C1 is input to the clock buffer circuits C11 and C12 and other circuits. The clock signal output from the clock buffer circuit C11 is input to the clock buffer circuits C111, C112 and other circuits, and the clock signal output from the clock buffer circuit C111 is input to the clock buffer circuits C1111, C1112 and other circuits. . Further, the clock signal output from the clock buffer circuit C1111 is input to the clock buffer circuits C1111-1, C1111-2, and other circuits. The clock signal output from the clock buffer circuit C1111-1 is supplied to flip-flop circuits (FF) F11 and F12 included in the standard cell. The flip-flops F11 and F12 operate based on the clock signal supplied from the clock buffer circuit C1111-1. As shown in FIG. 16, clock buffer circuits are also formed in the subsequent stages of C12, C112, and C1112.

  The clock buffer circuits C01, C02, C03, C1, C11, C12, C111, C112, C121, and C122 arranged in the subsequent stage of the PLL 44 constitute a higher-level clock buffer circuit, and have a deep N-type well region It is surrounded by 21. On the other hand, the clock buffer circuits C1111, C1111-1, C1111-2, C1112, C1112-1, and C1112-2, which are arranged at the subsequent stage of the upper layer clock buffer circuit, constitute a lower layer clock buffer circuit. And not surrounded by a deep N-type well region.

  In the semiconductor integrated circuit according to the fourth embodiment shown in FIG. 15 and FIG. 16, among the clock buffer circuits that distribute the clock signal to the entire semiconductor integrated circuit, no noise countermeasure is taken for the lower-level clock buffer circuit. The noise countermeasure is executed only for the upper layer clock buffer circuit arranged between the clock signal oscillation circuit (PLL) and the lower layer clock buffer circuit. That is, a deep N-type well region (WB) is formed around the N-type well region and the P-type well region in which the upper layer clock buffer circuit is formed, while the N layer in which the lower layer clock buffer circuit is formed. A deep N-type well region is not formed around the type well region and the P-type well region. With such a configuration, an increase in layout area in the semiconductor integrated circuit is suppressed.

  As shown in FIG. 16, the upper layer clock buffer circuit needs to drive a large load of a long-distance wiring from the clock buffer circuit C01 to the flip-flop circuit F11, for example. Therefore, the transistors constituting the upper layer clock buffer circuit have a large size (channel width) and a large amount of current flowing, and therefore a large amount of noise is generated. Therefore, it is possible to greatly reduce the amount of noise generated by surrounding only the upper layer clock buffer circuit with the deep N-type well region (WB).

  In addition, each of the above-described embodiments can be implemented not only independently but also in an appropriate combination. Furthermore, the above-described embodiments include inventions at various stages, and the inventions at various stages can be extracted by appropriately combining a plurality of constituent elements disclosed in the embodiments.

It is a block diagram which shows well potential control performed with respect to various modes in a semiconductor integrated circuit. 1 is a schematic layout diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. It is the layout which expanded the inside of the broken line A in the semiconductor integrated circuit shown in FIG. FIG. 3 is a schematic diagram of a layout of a well region in which a standard cell SC is formed in the first embodiment. FIG. 3 is a schematic diagram of a layout of a well region where a clock buffer circuit CB is formed in the first embodiment. 4 is a layout showing a circuit pattern of a standard cell SC in the first embodiment. FIG. 7 is a cross-sectional view taken along line XX ′ in the circuit pattern of the standard cell SC shown in FIG. 6. 6 is a layout showing a circuit pattern of the clock buffer circuit CB in the first embodiment. FIG. 9 is a cross-sectional view taken along line YY ′ in the circuit pattern of the clock buffer circuit CB illustrated in FIG. 8. 4 is a layout showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention. It is the schematic of the layout of the well area | region in which the standard cell SC in the said 2nd Embodiment is formed. 4 is a layout showing a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention. It is a layout which shows the structure of the semiconductor integrated circuit which concerns on the modification of the said 3rd Embodiment. It is a layout which shows the circuit pattern of the standard cell SC in the modification of the said 3rd Embodiment. It is a block diagram which shows the structure of the clock buffer circuit in the semiconductor integrated circuit which concerns on 4th Embodiment of this invention. 10 is a layout of a clock buffer circuit in the semiconductor integrated circuit according to the fourth embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... p-type semiconductor substrate (P-sub), 12, 12R ... N-type well region (WN), 13, 13R ... P-type well region (WP), 14, 21 ... Deep N-type well region (WB), 16 ... Wiring, 19 ... Wiring, 23 ... Power supply wiring (power supply terminal), 24 ... Ground wiring (grounding terminal), C01, C02, C03, C1, C11, C12, C111, C112, C121, C122 ... Higher-level clock buffer C1111, C1112, C1111-1, C1111-2, C1112-1, C1112-2 ... lower layer clock buffer circuit, SC ... standard cell, CB ... clock buffer circuit.

Claims (5)

First and second semiconductor regions of the second conductivity type formed on the semiconductor substrate of the first conductivity type;
A third semiconductor region of a first conductivity type formed in the semiconductor substrate between the first semiconductor region and the second semiconductor region;
A fourth semiconductor region of a second conductivity type formed below the first, second, and third semiconductor regions and electrically connected to the first semiconductor region and the second semiconductor region;
A first potential terminal electrically connected to the fourth semiconductor region, to which a first potential supplied to the first and second semiconductor regions through the fourth semiconductor region is applied;
A second potential terminal which is electrically connected to the semiconductor substrate and to which a second potential supplied to the third semiconductor region through the semiconductor substrate is applied;
A semiconductor integrated circuit comprising: First and second semiconductor regions of the second conductivity type formed on the semiconductor substrate of the first conductivity type;
A third semiconductor region of a first conductivity type formed in the semiconductor substrate between the first semiconductor region and the second semiconductor region;
The semiconductor substrate is disposed between the semiconductor substrate and the first, second, and third semiconductor regions, further encloses the first, second, and third semiconductor regions, and includes the first semiconductor region and the second semiconductor region. A fourth semiconductor region of the second conductivity type electrically connected;
A first potential terminal electrically connected to the first semiconductor region and supplied with a first potential supplied to the first semiconductor region;
A second potential terminal electrically connected to the third semiconductor region and supplied with a second potential supplied to the third semiconductor region;
A transistor forming a clock buffer circuit for transmitting a clock signal is formed in the first, second, and third semiconductor regions. First and second semiconductor regions of the second conductivity type formed on the semiconductor substrate of the first conductivity type;
A third semiconductor region of a first conductivity type formed in the semiconductor substrate between the first semiconductor region and the second semiconductor region;
A second conductive type fourth semiconductor region formed above the first semiconductor region, the second semiconductor region, and the third semiconductor region;
A first potential terminal electrically connected to the fourth semiconductor region, to which a first potential supplied to the first and second semiconductor regions through the fourth semiconductor region is applied;
A second potential terminal which is electrically connected to the semiconductor substrate and to which a second potential supplied to the third semiconductor region through the semiconductor substrate is applied;
A semiconductor integrated circuit comprising: First and second semiconductor regions of the second conductivity type formed on the semiconductor substrate of the first conductivity type;
A third semiconductor region of a first conductivity type formed in the semiconductor substrate between the first semiconductor region and the second semiconductor region;
A second conductivity type fourth semiconductor region formed in the first semiconductor region and having an impurity concentration higher than that of the first semiconductor region;
A second conductivity type fifth semiconductor region formed in the second semiconductor region and having an impurity concentration higher than that of the second semiconductor region;
A sixth semiconductor region of a first conductivity type formed in the third semiconductor region and having an impurity concentration higher than that of the third semiconductor region;
The fourth semiconductor is formed by a first contact plug disposed on the first semiconductor region including the fourth semiconductor region and on the second semiconductor region including the fifth semiconductor region and formed on the fourth semiconductor region. Electrically connected to the first semiconductor region via a region and electrically connected to the second semiconductor region via the fifth semiconductor region by a second contact plug formed on the fifth semiconductor region. A connected first metal wiring;
A third contact plug disposed on the third semiconductor region including the sixth semiconductor region and electrically connected to the third semiconductor region through the sixth semiconductor region by a third contact plug formed on the sixth semiconductor region. A second metal wiring formed,
A semiconductor integrated circuit comprising: A rectangular second conductivity type first and second semiconductor region formed on a first conductivity type semiconductor substrate;
A rectangular first conductive type third semiconductor region formed in the semiconductor substrate between the first semiconductor region and the second semiconductor region;
A first metal line disposed along a longitudinal direction of the first semiconductor region and applying a first bias voltage to the first semiconductor region;
A second metal wiring disposed along a longitudinal direction of the second semiconductor region and applying the first bias voltage to the second semiconductor region;
A third metal wiring disposed along a longitudinal direction of the third semiconductor region and applying a second bias voltage to the third semiconductor region;
A fourth semiconductor region of a first conductivity type formed in the first semiconductor region;
A fifth semiconductor region of a second conductivity type formed in the third semiconductor region;
A power supply line disposed along a longitudinal direction of the first semiconductor region and supplying a power supply potential to the fourth semiconductor region;
A ground wiring disposed along a longitudinal direction of the third semiconductor region and supplying a ground potential to the fifth semiconductor region;
A semiconductor integrated circuit comprising:

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