JP2008140894A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique capable of efficiently dissipating heat generated during operation of a semiconductor device.
An aluminum pad is connected to a conductive region on the front surface of a semiconductor substrate, and a back electrode is formed on the conductive region on the back surface. The insulating passivation film 10 is formed so as to cover the surface, side surfaces, and part of the back side electrode of the silicon substrate 4. A wiring 14 is provided on the passivation film 10, and the wiring 14 is connected to the aluminum pad 12, and the insulating passivation film 10 on the back-side electrode 22 on the back side along the side surface of the semiconductor substrate 4. It is drawn up to the top. A peripheral solder base 16 is connected and fixed on the wiring 14 on the passivation film 10 formed on the back surface side electrode 22, and a central solder base is formed on the back surface side electrode 22 on which the passivation film 10 is not formed. 18 is formed.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a surface mount type semiconductor device mounted on a substrate by soldering and a method for manufacturing the same.

  A surface-mount type semiconductor device that can be mounted on a substrate by soldering is known. In a surface-mount type semiconductor device, connection terminals must be integrated on one surface of a package. A semiconductor device having electrodes on both front and back surfaces of a semiconductor substrate is known. To package a semiconductor substrate with electrodes on both front and back sides in a surface-mount type semiconductor device, it is formed on one side of the semiconductor substrate (the side opposite to the package side where the connection terminals are integrated) It is necessary to form a wiring for connecting the connected electrode and the connection terminal in the package. In this case, in order to improve the mounting density on the substrate, it is necessary to accommodate the semiconductor substrate and the wiring in a small package.

In order to realize the above problem, the present inventor has proposed the technique of Patent Document 1. However, this application has not yet been published.
In this technology, the wiring that connects the electrodes formed on the entire back surface of the semiconductor substrate and the connection terminals (the base for soldering, hereinafter referred to as the solder base) formed on the front surface of the package is packaged. Is housed inside. For this purpose, an insulating layer is formed on the side surface of the semiconductor substrate, and wiring is formed on the outer surface of the insulating layer from the back-side electrode of the semiconductor substrate to the surface of the semiconductor substrate through the side surface of the semiconductor substrate. Since the wiring extends to the surface of the semiconductor substrate, conduction between the solder base formed on the surface of the package and the back side electrode of the semiconductor substrate can be ensured. According to this technique, a semiconductor substrate having electrodes on both the front and back sides of the semiconductor substrate can be packaged in a surface-mount type semiconductor device, and the package can be reduced in size.

Description and drawing of Japanese Patent Application No. 2006-099916

  When electrodes are formed on both the front and back surfaces of a semiconductor substrate, an electrode that largely spreads is provided on one surface, and a plurality of electrodes are often distributed on the other surface. In this case, one electrode is greatly expanded on one surface, whereas a plurality of electrodes having a small area are individually distributed on the other surface. In the above-described technique, the back-side electrodes of the semiconductor substrate are widely spread, and a plurality of electrodes each having a small area are dispersedly arranged on the front side of the semiconductor substrate. The wiring in the package extends from the back surface side electrode through the side surface of the semiconductor substrate to a plurality of electrodes distributed on the surface of the semiconductor substrate and gaps left between the electrodes. On the surface side of the semiconductor substrate of the wiring, the size is adjusted so as to remain in the gap between the plurality of electrodes arranged in a distributed manner.

In the case of a semiconductor device that controls high power, its heat dissipation capability needs to be high. That is, the heat transfer efficiency for the substrate needs to be high. In the case of having a back-side electrode that is widely spread, heat transfer efficiency from the semiconductor substrate to the substrate can be increased by soldering a wide range of the back-side electrode to the substrate.
However, in the technique described above, soldering is performed on the wiring extending to the surface side of the semiconductor substrate for surface mounting. The wiring extending to the front surface side of the semiconductor substrate is restricted to a size that remains in the gaps remaining between the plurality of electrodes distributed on the surface of the package, compared to the back side electrode. And remarkably small. The area to be soldered is small, and the heat transfer efficiency from the semiconductor substrate to the substrate cannot be increased.

The semiconductor device of the present invention reverses the idea and provides a wiring that reaches from the front surface side electrode to the back surface through the side surface of the semiconductor substrate. As used herein, the back surface refers to a surface having electrodes extending over almost the entire surface of the semiconductor substrate. If the front side electrode is connected to the back side by wiring, the back side of the package can be soldered to the substrate, and a wide area of the back side electrode that is widened can be soldered to the substrate. The heat transfer efficiency from the semiconductor substrate to the substrate can be increased.
On the other hand, on the back side, the back side electrode spreads over almost the entire back side of the semiconductor substrate, and if wiring that reaches the back side from the front side electrode through the side surface of the semiconductor substrate is simply provided, the back side electrode and the front side The electrode is short-circuited.

The semiconductor device of the present invention overcomes the above problem by adopting the following configuration. That is, the semiconductor device of the present invention includes a semiconductor substrate, a back surface side electrode, an insulating layer, wiring, a central solder base, a peripheral solder base, and an insulator.
The back surface side electrode is formed on the back surface of the semiconductor substrate. The insulating layer covers at least a part of the surface of the semiconductor substrate excluding a part, the side surface of the semiconductor substrate, and the peripheral part of the back surface side electrode. The wiring contacts a part of the surface of the semiconductor substrate not covered with the insulating layer, extends on the outer surface of the insulating layer along the side surface of the semiconductor substrate, and covers the part of the back-side electrode. Has reached. The central solder base is connected and fixed to the back side electrode within a range not covered with the insulating layer. The peripheral solder base is connected and fixed to a wiring formed in a range where the insulating layer covers the back side electrode. The insulator insulates the central solder base and the peripheral solder base.

Although the back surface side electrode of the semiconductor substrate is partially covered with an insulating layer, it still has a large exposed area. The central solder base can have a large area, and the semiconductor device and the substrate can be soldered in a wide range. The heat transfer efficiency from the semiconductor substrate to the substrate can be increased.
The wiring extending from the surface of the semiconductor substrate remains in the range of the insulating layer covering a part of the peripheral portion of the back surface side electrode, and is insulated from the back surface side electrode. There is no short circuit between the back side electrode and the front side electrode.
The front surface side electrode of the semiconductor substrate extends substantially to the back surface side of the semiconductor substrate by wiring, and is connected to a solder base collected on the back surface of the package. By soldering on one surface of the package, the semiconductor device can be surface mounted on the substrate.

In the above, an electrode pad or the like fixed to the surface of the semiconductor substrate is also referred to as wiring. The semiconductor substrate contains a high concentration of impurities, and a conductive region is formed on the surface of the semiconductor substrate that is well connected to the conductive material. In the above, all the conductors connected to the conduction region formed on the semiconductor substrate are referred to as wiring.
The material of the semiconductor substrate is not particularly limited. For example, a Si substrate, a GaN substrate, a SiC substrate, or the like can be used. The material of the back side electrode is not particularly limited. For example, metals such as titanium, aluminum, nickel, and gold can be used. The material of the insulating layer is not particularly limited. For example, an organic insulating material such as polyimide (PI) or polybenzoxazole (PBO) can be used. Alternatively, an insulating material such as an oxide film or a nitride film can be used.

  The semiconductor device of the present invention can obtain high heat transfer efficiency because the central solder base having a large area is soldered to the substrate. On the other hand, when the area to be soldered becomes large, voids are likely to occur. When voids are generated, not only the heat transfer efficiency from the central solder base to the substrate is lowered, but also the reliability of soldering is lowered.

If the central solder base remains on a part of the backside of the package, voids are likely to occur. On the other hand, when the center solder base reaches the outer periphery of the back surface of the package, it is difficult to form a void.
Therefore, in the improved semiconductor device of the present invention, the insulating layer does not cover at least a part of the peripheral part of the back surface side electrode, and the central solder base passes through a part of the peripheral part not covered with the insulating layer. Extending to the outer periphery of the back surface of the semiconductor device.
Here, the outer periphery of the back surface of the semiconductor device refers to the outline of the back surface of the packaged semiconductor device in contact with the substrate. For example, the central solder base can be formed in a strip shape from the central region of the back surface side electrode to the outer periphery of the back surface. For example, the central solder base may extend so as to connect a pair of opposing sides on the outer periphery of the back surface, or may extend so as to connect a pair of opposing diagonals.

When the central solder base is formed to extend to the outer periphery of the back surface of the semiconductor device, even if bubbles are generated in the solder paste in the central region of the central solder base, the central solder base extended to the outer periphery of the back surface is the escape route for the bubbles. It becomes. Even if the central solder base is formed large, generation of voids can be prevented.
If the central solder base extends to the outer periphery of the back surface of the semiconductor device, voids can be prevented, the thermal resistance of the solder layer can be prevented from increasing, and the reliability can be prevented from decreasing.

In addition to surface-mounting a semiconductor device on a substrate, another semiconductor device may be surface-mounted on the surface of the surface-mounted semiconductor device.
In that case, another semiconductor device surface-mounted on the semiconductor device can be used as the semiconductor device of the present invention. Further, a semiconductor device on the substrate side for mounting another semiconductor device is obtained by adding the upper surface solder base connected to the wiring on the surface side of the semiconductor substrate to the semiconductor device of the present invention described above. It is preferable.

  By providing the upper surface solder base, it becomes possible to stack another semiconductor device on the surface of the semiconductor device. By connecting and fixing the upper surface solder base of the semiconductor device located in the lower stage and the peripheral solder base of the semiconductor device located in the upper stage, a plurality of semiconductor devices stacked vertically are mechanically connected and at the same time Can be connected. A semiconductor device can be easily multi-chiped.

The present invention can also be embodied in a method for manufacturing a semiconductor device. The manufacturing method includes a step of forming a semiconductor structure, a step of forming a front surface side groove, a step of forming a front side insulating layer, a step of forming a front side wiring, and a step of forming a back side groove. A step of forming a back-side electrode, a step of forming a back-side insulating layer, a step of forming a back-side wiring, a step of forming a central solder base, a step of forming a peripheral solder base, and an insulator The process of filling is included.
In the step of forming the semiconductor structure, a semiconductor structure having a conductive region that is electrically connected to a conductor on a part of the surface of the semiconductor substrate and the back surface of the semiconductor substrate is formed for each region partitioned by the dicing line of the semiconductor substrate before dicing. To do. In the step of forming the surface-side groove, the surface-side groove is formed along the dicing line from the surface side of the semiconductor substrate to a depth that does not penetrate the semiconductor substrate. In the step of forming the surface-side insulating layer, the surface-side insulating layer is formed on the surface other than the conductive region formed on the surface of the semiconductor substrate and on the side surface forming the surface-side groove. In the step of forming the surface side wiring, on the outer surface of the surface side insulating layer, the surface extending from the conductive region formed on the surface of the semiconductor substrate along the side surface of the surface side groove and reaching the bottom surface of the surface side groove Side wiring is formed. In the step of forming the groove on the back surface side, the groove on the back surface side reaching the bottom surface of the groove on the front surface side from the back surface side of the semiconductor substrate is formed along the dicing line. In the step of forming the back surface side electrode, the back surface side electrode is formed on the back surface of the semiconductor substrate. In the step of forming the back-side insulating layer, a back-side insulating layer that covers at least a part of the peripheral portion of the back-side electrode and the side surface of the groove on the back-side is formed. In the step of forming the back surface side wiring, on the outer surface of the back surface side insulating layer, it extends along the side surface of the back surface side groove from the front surface side wiring formed along the bottom surface of the front surface side groove, and the peripheral portion of the back surface side electrode A back-side wiring reaching the outer surface of the back-side insulating layer covering a part of the back-side insulating layer is formed. In the step of forming the central solder base, the central solder base is formed on the outer surface of the back-side electrode in a range not covered with the back-side insulating layer. In the step of forming the peripheral solder base, the peripheral solder base is formed on the outer surface of the back surface side wiring formed within the range where the back surface side insulating layer covers the back surface side electrode. In the step of filling the insulator, the insulator that insulates the central solder base and the peripheral solder base is filled.

According to the method for manufacturing a semiconductor device of the present invention, the groove is formed from the surface side of the semiconductor substrate to a depth not penetrating the semiconductor substrate, and the insulating layer is formed from the surface other than the conductive region of the semiconductor substrate to the side surface of the groove. A wiring is formed on the layer. This wiring is in contact with the conduction region of the semiconductor substrate and extends to the back side along the side surface of the groove.
Grooves are also formed from the back side of the semiconductor substrate. This groove is formed so as to expose the wiring formed on the bottom surface of the groove on the surface side of the semiconductor substrate. A back side electrode is formed on the back side of the semiconductor substrate in which the back side groove is not formed. An insulating layer is formed on at least a part of the peripheral portion of the back surface side electrode and the side surface of the groove on the back surface side. This insulating layer is connected to the insulating layer formed from the surface side of the semiconductor substrate. Next, a wiring is formed on the upper surface of the insulating layer on the back surface side. The wiring is connected to the wiring formed from the front surface side of the semiconductor substrate through the side surface of the groove on the back surface side from the outer surface of the insulating layer covering a part of the peripheral portion of the back surface side electrode.
A central solder base is formed in a range not covered with the back-side insulating layer of the back-side electrode. The central solder base may be composed of a heat sink such as a copper plate. A peripheral solder base is formed on the outer surface of the back surface side wiring formed within the range covered with the back surface side insulating layer of the back surface side electrode. An insulator (for example, resin) that insulates the central solder base and the peripheral solder base is filled.
After each process, when each semiconductor device is separated along the dicing line, the insulating layer and the wiring formed from both the front surface side and the back surface side of the semiconductor substrate are connected so as to cover the side surface of the semiconductor device. It will be in the state. Since both the peripheral solder base connected to the conduction region on the front surface side and the central solder base connected to the back surface side electrode are formed on the back surface side, this semiconductor device is a substrate with the front surface facing up. Can be surface mounted.

  According to the present invention, since the central solder base and the peripheral solder base are formed on the back surface side of the semiconductor device, it can be surface-mounted on the substrate with the surface facing up. The semiconductor device is mechanically fixed to the substrate by soldering the central solder base connected to and fixed to the back side electrode to the substrate. Further, since the soldering area is large, heat generated in the semiconductor device can be efficiently transferred to the substrate. Even a power semiconductor device that generates a large amount of heat during operation can prevent the semiconductor device from being overheated. A stable operation of the semiconductor device can be obtained.

First, the main features of the embodiments described below are listed.
(Mode 1) The central solder base is larger than the peripheral solder base.
(Mode 2) On the front surface side and the back surface side of the semiconductor substrate, grooves whose bottom portions are located on the dicing line and whose bottom area is smaller than the area of the opening are formed.
(Mode 3) The front side and / or the back side of the semiconductor device is sealed with resin.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 2 shows the appearance of the semiconductor device 2 of this embodiment. The semiconductor device 2 of the present embodiment is a wafer level (WL) chip scale package (CSP) type semiconductor device, and is hereinafter referred to as WL-CSP. The package size of WL-CSP is the same size as the chip size after dicing, and WL-CSP is small. When WL-CSP is used, the electronic circuit can be miniaturized and highly integrated.

  FIG. 1 shows a cross-sectional view of the semiconductor device 2. FIG. 1 is a cross-sectional view taken along the line II of the semiconductor device 2 of FIG. The semiconductor device 2 has a semiconductor structure having regions 4a, 4b, and 4c containing impurities at a high concentration and well conducting with a conductor on a part of the front surface and the back surface of the semiconductor substrate 4. A back side electrode 22 is formed on the back side of 4. The semiconductor substrate 4 may be an elemental semiconductor made of a single crystal of silicon or a compound semiconductor. The semiconductor device 2 is packaged by sealing both the front surface side and the back surface side of the semiconductor substrate 4 with an insulating resin 20.

  Conductive regions 4a and 4b are formed on the surface of the semiconductor substrate 4 of FIG. Aluminum pads 12 are formed on the surface of the semiconductor substrate 4 corresponding to the conductive regions 4a and 4b. The surface of the semiconductor substrate 4 is covered with an insulating film 8 made of silicon nitride, silicon oxide or the like, except for regions corresponding to the conductive regions 4a and 4b (that is, regions where the aluminum pads 12 are formed). On the insulating film 8, an insulating passivation film 10 made of polyimide (PI) or polybenzoxazole (PBO) is formed. The insulating passivation film 10 extends along the front surface side and the side surface of the semiconductor substrate 4 and covers a part of the peripheral portion of the back surface side electrode 22. A contact hole 10 a is formed in the insulating passivation film 10 at a position corresponding to the conduction regions 4 a and 4 b or the aluminum pad 12.

  A wiring 14 made of a metal such as copper or nickel is formed on the outer surface of the insulating passivation film 10. The wiring 14 penetrates into the contact hole 10a, and is electrically connected to the aluminum pad 12 by the penetration part 14a. The wiring 14 starts from a portion connected to the aluminum pad 12, extends along the side surface of the semiconductor substrate 4, and extends to the outer surface of the insulating passivation film 10 formed around the back surface side electrode 22. The wiring 14 is insulated by the back surface side electrode 22 insulating passivation film 10.

The back surface side electrode 22 formed on the back surface side of the semiconductor substrate 4 is made of a metal such as titanium, aluminum, nickel, or gold. A central solder base 18 made of a metal such as copper is connected and fixed in a range where the back surface side electrode 22 is not covered with the passivation film 10. The central solder base 18 is a base to which a solder layer 26 that connects the semiconductor device 2 to the substrate 30 is fixed, and also serves as a heat sink. When the central solder base 18 is soldered to the substrate-side wiring 28 fixed to the substrate 30 with the solder layer 26, the back electrode 22 of the semiconductor device 2 is electrically connected to the substrate-side wiring 28.
A wiring 14 is formed in the range of the insulating passivation film 10 covering the back surface side electrode 22. A peripheral solder base 16 is connected and fixed to the outer surface of the wiring 14 on the back surface side. The peripheral solder base 16 is a base to which a solder layer 24 that connects the semiconductor device 2 to the substrate 30 is fixed. When the peripheral solder base 16 is soldered to the substrate-side wiring 27 fixed to the substrate 30 with the solder layer 24, the aluminum pad 12 of the semiconductor device 2 is electrically connected to the substrate-side wiring 27. In FIG. 1, the pair of left and right aluminum pads 12 may eventually be conductive electrodes that operate simultaneously, or may be different electrodes that operate independently.
When the central solder base 18 is soldered to the substrate side wiring 28 with the solder layer 26 and the peripheral solder base 16 is soldered to the substrate side wiring 27 with the solder layer 24, the semiconductor device 2 is mechanically fixed to the substrate 30.

The insulating passivation film 10 covers only a part of the peripheral portion of the back surface side electrode 22. The central solder base 18 passes through a region not covered with the passivation film 10 and reaches the outer periphery of the semiconductor device 2. FIG. 3 shows a back view of the semiconductor device 2. 3A to 3D show an example of the formation pattern of the central solder base 18. The back surface of the package of the semiconductor device 2 is sealed with resin 20 so that the peripheral solder base 16 and the central solder base 18 are exposed. The central region of the central solder base 18 is located so as to be surrounded by the peripheral solder base 16, and extends from the central region of the back surface side electrode 22 to the back surface of the packaged semiconductor device 2 toward the outer periphery.
By forming the central solder base 18 so as to reach the outer periphery on the back surface of the packaged semiconductor device 2, when the semiconductor device 2 is surface-mounted on the substrate 30, the solder paste 26 extends the central solder base 18. As a result, the bubbles in the solder paste easily move toward the outer periphery of the packaged semiconductor device 2. By adopting such a configuration, as shown in FIG. 3, even when the large central solder base 18 is soldered and surface-mounted, no void is generated in the solder layer 26. The thermal resistance and electrical resistance of the central solder base 18 can be reduced.

  In the semiconductor device 2 of the present embodiment, the central solder base 18 is directly connected and fixed to the back-side electrode 22, and the area of the central solder base 18 is larger than that of the peripheral solder base 16. For this reason, the efficiency of releasing heat generated inside the semiconductor substrate 4 when the semiconductor device 2 is energized is very good. Further, since the central solder base 18 is formed to extend to the outer periphery of the packaged semiconductor device 2, the central solder base 18 extending to the outer periphery becomes a bubble escape path, and the central solder base 18 has a large area. Even so, the generation of voids in the solder layer 26 for soldering the central solder base 18 can be prevented.

  Next, the manufacturing method of the semiconductor device 2 of the present embodiment will be described with reference to FIGS. At the time of starting the process shown in FIG. 5, for each region partitioned by the dicing line of the wafer 50 before dicing, there are regions 4 a, 4 b, 4 c that are electrically connected to the conductors on a part of the front surface and the back surface of the wafer 50 A semiconductor structure is formed. Aluminum pads 12 are formed in regions corresponding to the conductive regions 4a and 4b on the surface, and the surface of the wafer 50 in other regions is covered with an insulating film 8 made of a silicon nitride film or a silicon oxide film. Yes.

  In the process shown in FIG. 5, the groove 52 on the surface side is formed from the surface side of the wafer 50 along the dicing line to a depth that does not penetrate the wafer 50. For example, by performing wet etching, it is possible to form the groove 52 having the side surface 52a inclined to the side where the width becomes narrower with the depth. The groove 52 has a bottom 52b located on the dicing line and a side surface 52a inclined. Due to the inclination of the side surface 52a, the groove 52 is formed in a tapered shape in which the area of the bottom 52b is smaller than the area of the opening. The groove 52 can also be formed by, for example, a blade dicing method or a dry etching method.

In the process shown in FIG. 6, the insulating passivation film 10 is applied so as to cover the surface of the wafer 50 and the side surface 52 a forming the groove 52 on the front surface side. The applied insulating passivation film 10 is patterned in order to rewire the conductive region in a later step. Specifically, the contact hole 10a is formed in the insulating passivation film 10 applied on the aluminum pad 12, and the aluminum pad 12 is exposed.
The insulating passivation film 10 may also be applied to the bottom 52b of the groove 52. Alternatively, the insulating passivation film 10 may not be applied to the bottom 52b. The insulating material applied to the bottom 52b may be removed by patterning the insulating passivation film 10 applied to the bottom. The insulating passivation film 10 is made of an organic resin material such as polyimide.

  After forming the insulating passivation film 10 in the above process, in the process shown in FIG. 7, the outer surface of the passivation film 10 on the front surface side of the wafer 50 passes through the side surface 52 a of the groove 52 from the position where the aluminum pad 12 is electrically connected. The front surface side wiring 14 reaching the bottom surface 52b of the groove 52 is formed. The wiring 14 is connected to the aluminum pad 12 exposed from the insulating passivation film 10. The wiring 14 is applied to the entire surface of the bottom 52 b of the groove 52. The surface-side wiring 14 can be formed by a technique such as sputtering. When the pair of left and right aluminum pads 12 are separate electrodes, the wiring 14 connected to the left aluminum pad 12 and the wiring 14 connected to the right aluminum pad 12 are formed in a pattern that does not short-circuit.

  In the step shown in FIG. 8, the surface side of the wafer 50 to which the surface side wiring 14 is applied is sealed with the resin 20. The semiconductor device 2 can be resin-sealed in a state at the wafer level. By sealing the wafer 50 with resin, it is possible to protect the wiring 14 from dust and humidity, and to enhance the resistance against the impact and the like of the semiconductor device 2.

In the process shown in FIG. 9, first, a back-side groove 58 that reaches the bottom surface 52 b of the front-side groove 52 is formed along the dicing line from the back side of the wafer 50. The bottom portion 58b of the groove 58 is located on the dicing line, and the side surface 58a is inclined. Due to the inclination of the side surface 58a, the groove 58 is formed in a tapered shape in which the area of the bottom 58b is smaller than the area of the opening. The groove 58 is formed such that its bottom 58b overlaps with the bottom 52b of the groove 52 formed from the surface side of the wafer 50, and exposes the insulating passivation film 10 and the wiring 14 applied from the surface side. Formed. The groove 58 can be formed by a technique such as blade dicing, wet etching, or dry etching.
Next, the back surface side electrode 22 is formed so as to cover the conduction region 4 c on the back surface side of the wafer 50. The groove 58 and the back surface side electrode 22 can be formed in the same process, for example, by forming the groove 58 after forming a metal layer on the entire back surface side. The back side electrode 22 can be formed by a technique such as vapor deposition, sputtering, printing, spin coating or the like.

In the step shown in FIG. 10, the passivation film 10 on the back surface side is applied so as to cover a part of the peripheral portion of the back surface side electrode 22 and the side surface 58a of the groove 58 on the back surface side. The passivation film 10 that covers the side surface 52 a of the groove 52 is in contact with a part of the bottom 58 b of the groove 58. The front surface side passivation film 10 and the back surface side passivation film 10 are continuous, and the passivation film 10 covers the entire side surface of the semiconductor substrate 4.
The insulating passivation film 10 is not applied to the bottom 58b of the groove 58 on the back surface side. Alternatively, the insulating material applied to the bottom 58b may be removed by patterning the insulating passivation film 10 applied to the bottom.
After forming the back-side passivation film 10 in the above process, the back-side wiring 14 is formed. The wiring 14 can be formed by a technique such as sputtering. The wiring 14 extends along the side surface 58a of the back surface side groove 58 from the front surface side wiring 14 formed along the bottom surface 52b of the front surface side groove 52 on the outer surface of the passivation film 10 on the back surface side. 22 reaches the outer surface of the passivation film 10 on the back surface side that covers a part of the peripheral portion of 22. As a result, the passivation film 10 is connected to the aluminum pad 12 on the front surface side, extends along the outer surface of the passivation film 10 formed on the side surface of the semiconductor substrate 4, and is formed on the periphery of the back surface side electrode 22. A wiring 14 extending to the outer surface is formed.

  Next, in the step shown in FIG. 11, the central solder base 18 is formed on the outer surface of the back-side electrode 22 in a range not covered with the back-side passivation film 10, and the range in which the passivation film 10 covers the back-side electrode 22. A peripheral solder base 16 is formed on the outer surface of the wiring 14 formed inside. That is, the central solder base 18 is directly connected and fixed on the back side electrode 22, and the peripheral solder base 16 is connected and fixed to the wiring 14 provided on the passivation film 10 on the back side electrode 22. In this step, the central solder base 18 is formed in a formation pattern that extends from the central region of the back-side electrode 22 until it reaches the outer periphery of the package, as shown in FIGS.

  When the peripheral solder base 16 and the central solder base 18 are formed, the resin 20 that insulates both the central solder base 18 and the peripheral solder base 16 is filled in the process shown in FIG. By encapsulating the entire back surface of the wafer 50 with resin, the central solder base 18 and the peripheral solder base 16 are insulated, the wiring 14 is protected from dust and humidity, and the resistance of the semiconductor device 2 to impact and the like is enhanced. Can do. After the resin sealing, the peripheral solder base 16 and the central solder base 18 are exposed to the outside of the package as shown in FIG.

After the above series of manufacturing steps, the resin-sealed silicon wafer 50 is separated into pieces along the dicing lines shown in FIGS. FIG. 13 shows the semiconductor device 2 after being singulated. The semiconductor device 2 of this embodiment can be packaged at the wafer level. In addition, the package size of the semiconductor device 2 after separation is approximately equal to the size of the semiconductor substrate 4. A small semiconductor device can be manufactured.
In the semiconductor device 2 of this embodiment, the inclination of the side surface 52a of the semiconductor substrate 4 and the inclination of the side surface 58a form a ridge line. By this inclination, the conductive material constituting the wiring 14 can be brought into close contact with the side surface 52a and the side surface 58a of the semiconductor substrate 4 without causing partial disconnection in the wiring 14 routed from the front surface side to the back surface side. .

As shown in FIG. 13, solder balls 24 can be attached to the peripheral solder base 16 exposed on the back surface of the semiconductor device 2. A solder paste 26 can be attached to the central solder base 18. The solders 24 and 26 can be attached to the peripheral solder base 16 and the central solder base 18 in the state shown in FIG. 12, that is, at the timing before dicing after sealing with resin.
When the semiconductor device 2 is surface-mounted on the substrate 30, the solder paste 26 wets and spreads from the central region of the central solder base 18 in the circumferential direction, and bubbles generated in the paste move in the package outer peripheral direction of the semiconductor device 2. To do. By using the end of the central solder base 18 as a vent, bubbles in the solder paste that cause voids can be released to the outside.

(Other Embodiments of Semiconductor Device 2)
According to the semiconductor device 2 of the present embodiment, it can be surface-mounted on the substrate 30 with the surface facing up (see FIG. 1). For this reason, by providing an upper surface solder base for stacking on the surface side facing up, a plurality of semiconductor devices can be stacked and easily formed into a multichip. FIG. 4 shows a cross-sectional view of a state where another semiconductor device 40 is stacked on the semiconductor device 2 and surface-mounted.
The lower semiconductor device 2 includes upper surface solder bases 32 and 34 for stacking on the surface side. The upper surface solder base 32 is formed on the wiring 14 provided on the surface side of the semiconductor device 2 and can be connected to the peripheral solder base 42 of another semiconductor device 40 stacked on the upper stage. The upper surface solder base 34 is formed on the passivation film 10 on the surface side of the semiconductor device 2 and can be connected to the central solder base 44 of another semiconductor device.
Similar to the lower semiconductor device 2, the upper semiconductor device 40 includes a peripheral solder base 42 and a central solder base 44 on the back side, and is stacked on the semiconductor device 2 with the surface of the semiconductor substrate 46 faced up. be able to. A solder ball 36 is attached to the peripheral solder base 42, and a solder paste 38 is attached to the central solder base 44. The upper semiconductor device 40 can be surface mounted on the semiconductor device 2 by being connected and fixed to the upper surface solder bases 32 and 34 of the lower semiconductor device 2 by the solders 36 and 38.
When the multi-chip semiconductor devices 2 and 40 are energized while being fixed to the substrate 30, the semiconductor device 2 and the semiconductor device 40 are connected to (1) in FIG. 4 via the peripheral solder bases 16 and 42. An electric signal is transmitted in the direction indicated by the arrow (2). On the other hand, the heat generated in the semiconductor substrates 4 and 46 is transferred through the central solder bases 18 and 44 in the directions shown by arrows (3) and (4) in FIG.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. For example, in the above embodiment, the technical features of the present invention have been described by taking WL-CSP as an example, but this may be an IC chip that is barely mounted such as a flip chip.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

FIG. 4 is a cross-sectional view taken along the line II of the semiconductor device 2. FIG. 3 is a diagram illustrating an appearance of a semiconductor device 2. The figure which shows the front view of the semiconductor device 2 back surface. FIG. 4 is a diagram illustrating a stack module of a semiconductor device 2 and a semiconductor device 40. The figure showing the mode (1) of the manufacture process of the semiconductor device. The figure showing the mode (2) of the manufacture process of the semiconductor device. The figure showing the mode (3) of the manufacture process of the semiconductor device 2. FIG. The figure showing the mode (4) of the manufacture process of the semiconductor device. The figure showing the mode (5) of the manufacture process of the semiconductor device. The figure showing the mode (6) of the manufacture process of the semiconductor device 2. FIG. The figure showing the mode (7) of the manufacture process of the semiconductor device 2. FIG. The figure showing the mode (8) of the manufacture process of the semiconductor device 2. FIG. The figure showing the mode (9) of the manufacture process of the semiconductor device 2. FIG.

Explanation of symbols

2, 40: Semiconductor device (WL-CSP)
4, 46: Semiconductor substrate 8: Insulating film 10: Passivation film 12: Aluminum pad 14: Wiring 16, 42: Peripheral solder base 18, 44: Central solder base 20: Resin 22: Back side electrodes 24, 26, 36, 38 : Solder 27, 28: Substrate side wiring 30: Substrate 32, 34: Upper surface solder base 50: Wafer 52, 58: Groove

Claims (4)

A semiconductor substrate;
A back side electrode formed on the back side of the semiconductor substrate;
The surface of the semiconductor substrate excluding a part, the side surface of the semiconductor substrate, and an insulating layer covering at least a part of the peripheral part of the back surface side electrode,
It contacts a part of the surface of the semiconductor substrate not covered with the insulating layer, extends on the outer surface of the insulating layer along the side surface of the semiconductor substrate, and reaches the outer surface of the insulating layer covering a part of the back side electrode. With the wiring
A central solder base that is connected and fixed to the backside electrode in a range not covered with an insulating layer;
A peripheral solder base connected and fixed to the wiring formed in the range where the insulating layer covers the back side electrode;
An insulator that insulates the central solder base from the peripheral solder base;
A semiconductor device comprising: The insulating layer does not cover at least a part of the periphery of the back side electrode,
The semiconductor device according to claim 1, wherein the central solder base passes through a part of the peripheral portion not covered with the insulating layer and extends to the outer periphery of the back surface of the semiconductor device. A semiconductor device for mounting the semiconductor device of claim 1 on a surface,
The semiconductor device according to claim 1, further comprising an upper surface solder base connected and fixed to the wiring on the surface side of the semiconductor substrate. Forming a semiconductor structure having a conductive region electrically connected to a conductor on a part of the front surface of the semiconductor substrate and the back surface of the semiconductor substrate for each region partitioned by the dicing line of the semiconductor substrate before dicing;
Forming a groove on the surface side along the dicing line from the surface side of the semiconductor substrate to a depth not penetrating the semiconductor substrate;
Forming a surface-side insulating layer on a surface other than the conductive region formed on the surface of the semiconductor substrate and on a side surface forming a groove on the surface side;
Forming a surface-side wiring extending from the conductive region formed on the surface of the semiconductor substrate on the outer surface of the surface-side insulating layer along the side surface of the surface-side groove and reaching the bottom surface of the surface-side groove;
A step of forming a groove on the back surface reaching the bottom surface of the groove on the front surface side from the back surface side of the semiconductor substrate along the dicing line;
Forming a back side electrode on the back side of the semiconductor substrate;
Forming a back side insulating layer covering at least a part of the periphery of the back side electrode and the side surface of the back side groove;
On the outer surface of the back surface side insulating layer, the back surface side that extends along the side surface of the groove on the back surface side from the surface side wiring formed along the bottom surface of the groove on the front surface side and covers a part of the peripheral portion of the back surface side electrode Forming a backside wiring that reaches the outer surface of the insulating layer;
Forming a central solder base on the outer surface of the backside electrode in a range not covered with the backside insulating layer;
Forming a peripheral solder base on the outer surface of the back-side wiring formed within the range in which the back-side insulating layer covers the back-side electrode;
Filling the periphery of the central solder base and the peripheral solder base with an insulator that insulates both,
A method for manufacturing a semiconductor device comprising:

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