JP2010177683A - Semiconductor device, and method manufacturing the same - Google Patents

Abstract

A DRAM type semiconductor device capable of reducing junction leakage current is provided.
A thickness of a gate insulating film in a memory cell portion is made larger than a thickness of a gate insulating film in a peripheral circuit portion. Further, the source / drain of the MOS transistor in the memory cell portion is set to the double diffusion layer structure 5, 6, and the source / drain of the MOS transistor in the peripheral circuit portion is set to the triple diffusion layer structure 5, 6, 7. Thus, by setting the thickness of the gate insulating film 8 in the memory cell portion to be larger than the thickness of the gate insulating film 9 in the peripheral circuit portion, the concentration of the p-type impurity region 4a in the memory cell portion can be lowered. It becomes possible to reduce the junction leakage current.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a dynamic random access memory (hereinafter referred to as DRAM).

  In recent years, the demand for semiconductor devices has been rapidly expanding due to the remarkable spread of information devices such as computers. Furthermore, there is a demand for a functionally large storage capacity and capable of high-speed operation. Along with this, technological development relating to high integration, high-speed response, and high reliability of semiconductor devices has been advanced.

  Among semiconductor devices, a DRAM is one that can randomly input and output stored information. Generally, a DRAM is composed of a memory cell array, which is a storage area for storing a large number of stored information, and peripheral circuits necessary for input / output with the outside.

  FIG. 37 shows a DRAM having a conventional stack type memory cell. Referring to FIG. 37, p-type impurity region 3 is formed on the main surface of p-type semiconductor substrate 1. Field insulating film 2 and p-type impurity regions 4a and 4b are formed on p-type impurity region 3, respectively. The p-type impurity regions 4a and 4b are impurity regions for controlling the threshold voltage of the transistor.

  Low-concentration n-type impurity regions 5 are formed at intervals on the surface of p-type impurity region 4a. Further, a low-concentration n-type impurity region 5 and a high-concentration n-type impurity region 7 are formed on the surface of the p-type impurity region 4b at an interval.

  A gate electrode 12 is formed on the main surface of the semiconductor substrate 1 in the memory cell portion via a gate insulating film 8b, and the gate electrode 12 is formed on the main surface of the semiconductor substrate 1 in the peripheral circuit portion via a gate insulating film 9. It is formed. The gate insulating films 8 and 9 have the same thickness. The gate electrode 12 is composed of a polysilicon film 10 and a WSi film 11.

  A TEOS (Tetra Ethyl Ortho Silicate) is formed on the gate electrode 12, and a sidewall insulating film 14 is formed on the sidewall of the gate electrode 12. Interlayer insulating film 15 is formed to extend from the memory cell portion to the peripheral circuit portion so as to cover gate electrode 12. Contact holes 15a and 15b are formed in the interlayer insulating film 15, respectively.

  A bit line 16a is formed extending from the contact hole 15a onto the interlayer insulating film 15, and a wiring layer 16b is formed extending from the contact hole 15b onto the interlayer insulating film 15. Interlayer insulating film 17 is formed so as to cover bit line 16a and wiring layer 16b. A contact hole 17a is formed so as to penetrate through interlayer insulating film 17 and interlayer insulating film 15 to reach low concentration n-type impurity region 5.

  Storage node 18 is formed to extend from within contact hole 17 a onto interlayer insulating film 17. A capacitor insulating film 19 is formed so as to cover the surface of the storage node 18, and a cell plate 20 is formed on the capacitor insulating film 19. The cell plate 20, the capacitor insulating film 19, and the storage node 18 constitute a capacitor 21.

  An interlayer insulating film 22 is formed so as to cover the capacitor 21 and the interlayer insulating film 17. In the peripheral circuit portion, a contact hole 23a penetrating the interlayer insulating film 22 and the interlayer insulating film 17, a contact hole 23b reaching the gate electrode 12, and a contact hole 23c reaching the high concentration n-type impurity region 7 are formed. . Metal wiring 24b is formed so as to extend from the contact hole 23a onto the interlayer insulating film 22, and metal wiring 24c is formed so as to extend from the contact hole 23b onto the interlayer insulating film 22, and within the contact hole 23c. A metal wiring 24 d is formed so as to extend on the interlayer insulating film 22. In the memory cell portion, metal wiring 24 a is formed on interlayer insulating film 22.

  In recent years, the miniaturization of elements has been progressed more and more, and the thickness of the gate insulating films 8b and 9 has been reduced. Accompanying this, the concentration of the p-type impurity region 4a for controlling the threshold voltage of the transistor in the memory cell portion is increasing. As a result, a problem of increasing leakage current at the pn junction (hereinafter simply referred to as “junction leakage current”) is becoming apparent.

  In the trench type isolation structure as shown in FIG. 37, stress is likely to concentrate in the vicinity of the peripheral portion of the field insulating film 2 such as the region A and the region B. In this case, since the source / drain of the transistor in the memory cell portion is constituted only by the low-concentration n-type impurity region 5, the junction leakage current cannot be sufficiently suppressed. Furthermore, etching damage during the etching of the sidewall insulating film 14 is likely to occur in the region A, which also causes a junction leakage current. There is a concern that the data accumulated in the storage node 18 may be lost due to such a junction leakage current.

  Furthermore, since the concentration of the p-type impurity region 4a for controlling the threshold voltage is increased as described above, there is a problem that the sheet resistance of the low-concentration n-type impurity region 5 is increased.

  The present invention has been made to solve the above-described problems. An object of the present invention is to reduce junction leakage current.

  In one aspect, the semiconductor device according to the present invention includes a first transistor having a gate insulating film having a first thickness, and a second transistor having a gate insulating film having a second thickness smaller than the first thickness. Is provided. At least one of the source / drain of the first transistor is composed of a first low concentration region and a first high concentration region. At least one of the source / drain of the second transistor includes a second low concentration region and a second high concentration region having a higher concentration than the first high concentration region.

  By making the gate insulating film of the first transistor thicker than the gate insulating film of the second transistor as described above, the concentration of the impurity region for controlling the threshold voltage of the first transistor can be lowered. . As a result, the junction leakage current can be reduced. In addition, since at least one of the source / drain of the first transistor has the first high-concentration region, for example, even when the field insulating film is formed adjacent to the source / drain, the junction leakage current is reduced as compared with the prior art. It becomes possible. Furthermore, by forming the first high concentration region, the sheet resistance of the source / drain can be reduced. On the other hand, since the second transistor has a second high concentration region that is higher in concentration than the first high concentration region, the sheet resistance of the source / drain can be sufficiently reduced.

  At least one of the source / drain of the second transistor may have a medium concentration region having a higher concentration than the second low concentration region and a lower concentration than the second high concentration region.

  By providing the intermediate concentration region as described above, the second high concentration region can be surrounded by the intermediate concentration region. Accordingly, it is possible to avoid the second high concentration region from being in direct contact with the impurity region having a different conductivity type, and the occurrence of electric field concentration can be suppressed. This can also contribute to reduction of junction leakage current.

  In addition, the semiconductor device may include a memory cell for storing data and a peripheral circuit for performing input / output with the outside. In this case, it is preferable that the memory cell includes a first transistor and the peripheral circuit includes a second transistor.

  As described above, when the memory cell includes the first transistor, the junction leakage current in the memory cell portion can be reduced. In the peripheral circuit portion, a high-performance transistor having a source / drain with reduced sheet resistance is formed.

  The diffusion depth (peak concentration depth) of the second high concentration region is preferably smaller than the diffusion depth of the medium concentration region.

  Accordingly, the second high concentration region can be surrounded by the medium concentration region. Thereby, the junction leakage current can be reduced as described above.

  Further, a field insulating film may be formed so as to be in contact with the first high concentration region. At this time, an interlayer insulating film having a contact hole reaching the high concentration region and the field insulating film is formed so as to cover the first and second transistors, and a recess is formed in the field insulating film located immediately below the contact hole. The A storage node is formed in the recess and on the high concentration region.

  By forming the field insulating film in contact with the high concentration region as described above, it becomes possible to reduce the junction leakage current in the vicinity of the peripheral edge of the field insulating film. In addition, by forming a recess in the field insulating film located immediately below the contact hole, it is possible to remove the field insulating film in a portion where stress is likely to concentrate. This can also contribute to reduction of junction leakage current. Furthermore, by providing the concave portion, the contact area between the storage node and the high concentration region can be increased. Thereby, the contact resistance can be improved.

  In another aspect, the semiconductor device according to the present invention includes a semiconductor substrate having a main surface, first and second impurity regions for controlling a threshold voltage, and first and second transistors. The first impurity region has a peak concentration at a position of the first depth from the main surface. The second impurity region is formed at a distance from the first impurity region, and has a peak concentration at a position of a second depth larger than the first depth. The first transistor is formed on the first impurity region and has a gate insulating film having a first thickness. The second transistor is formed on the second impurity region and has a gate insulating film having a second thickness smaller than the first thickness.

  By making the thickness of the gate insulating film of the first transistor larger than the thickness of the gate insulating film of the second transistor, the concentration of the first impurity region can be lowered. In addition, by forming the peak concentration of the first impurity region at a position shallower than the peak concentration of the second impurity region as described above, the concentration of the first impurity region can be further reduced. . As a result, the junction leakage current can be more effectively reduced.

  A third impurity region having a lower concentration than the first impurity region may be formed under the first impurity region. The first transistor preferably has a pair of first source / drain, and at least one of the first source / drain preferably reaches the third impurity region. The second transistor has a pair of second source / drain, and the diffusion depth of the second source / drain is smaller than the second depth.

  As described above, when at least one of the first source / drain reaches a position deeper than the first impurity region, the junction area between the first impurity region and the source / drain can be reduced. As a result, the junction leakage current can be further reduced.

  In yet another aspect, the semiconductor device according to the present invention includes a first transistor having a gate insulating film having a first thickness and a second transistor having a gate insulating film having a second thickness smaller than the first thickness. A transistor. The first transistor has a relatively large first diffusion depth and a relatively small second diffusion depth, respectively, and has first and second impurity regions serving as source / drain. The second transistor has third and fourth impurity regions having a diffusion depth smaller than the first diffusion depth and greater than or equal to the second diffusion depth and serving as a source / drain.

  As described above, the junction leakage current can be reduced by making the thickness of the gate insulating film of the first transistor larger than the thickness of the gate insulating film of the second transistor. In addition, since the diffusion depth is increased only in the first impurity region, the punch-through resistance when miniaturized as compared with the case where the diffusion depth of both the first and second impurity regions is increased. There is little deterioration.

  The concentration of the first impurity region having the first diffusion depth is preferably higher than the concentration of the second impurity region. At this time, a field insulating film may be formed so as to be in contact with the first impurity region.

  By forming the first impurity region having a relatively high impurity concentration deep as described above, the peripheral portion of the field insulating film can be covered with the first impurity region. Thereby, it is possible to reduce the junction leakage current in the vicinity of the bottom of the field insulating film.

  In still another aspect, the semiconductor device according to the present invention includes first and second transistors, an interlayer insulating film, a plug electrode, a bit line, and first and second metal silicides. The first transistor is formed on the main surface of the semiconductor substrate and has a first source / drain. The second transistor is formed on the main surface at a distance from the first transistor and has a second source / drain. The interlayer insulating film covers the first and second transistors and has a contact hole reaching one of the first source / drain. The plug electrode is formed in the contact hole. The first metal silicide is formed on the surface of the second source / drain. The bit line is formed on the plug electrode via the second metal silicide.

  Since the metal film for forming the metal silicide is usually formed by sputtering, it is difficult to form a thick metal silicide at the bottom of the contact hole. On the other hand, the second metal silicide can be formed thick by forming the second metal silicide on the plug electrode as described above. On the other hand, it is possible to form a thick metal silicide film on the surface of the second source / drain of the second transistor by a known method. By forming such a thick metal silicide, the heat resistance can be improved. As a result, it is possible to avoid such a situation that the junction leakage current characteristic is deteriorated and the contact resistance is increased due to the metal silicide being deteriorated by a heat treatment of about 800 ° C. or more.

  In one aspect, a method for manufacturing a semiconductor device according to the present invention includes the following steps. A relatively thick first gate insulating film and a relatively thin second gate insulating film are formed on the main surface of the semiconductor substrate with a gap therebetween. A first gate electrode of the first transistor is formed over the first gate insulating film, and a second gate electrode of the second transistor is formed over the second gate insulating film. First impurity regions having a first concentration are formed on both sides of the first and second gate electrodes. A second impurity region having a second concentration higher than the first concentration is formed on at least one side of the first gate electrode. A third impurity region having a third concentration higher than the second concentration is formed on at least one side of the second gate electrode.

  By forming the first, second, and third impurity regions as described above, at least one of the source / drain of the first transistor is constituted by the first and second impurity regions, and the second transistor At least one of the source / drain can be constituted by the first and third impurity regions. Thereby, the first and second transistors with reduced source / drain sheet resistance are obtained. Further, as described above, the junction leakage current can be reduced by making the thickness of the first gate electrode of the first transistor larger than the thickness of the second gate insulating film of the second transistor. As a result, it is possible to obtain a high-performance semiconductor device that can suppress the junction leakage current.

  In another aspect, the method for manufacturing a semiconductor device according to the present invention includes the following steps. First and second gate electrodes of the first and second transistors are formed on the main surface of the semiconductor substrate at intervals. A nitride film is formed so as to cover the first and second gate electrodes. Source / drains of the first and second transistors are formed. An interlayer insulating film is formed so as to cover the nitride film. A first contact hole reaching one source / drain of the first transistor is formed in the interlayer insulating film. A second contact hole reaching one source / drain of the second transistor and a third contact hole reaching the second gate electrode through the interlayer insulating film and the nitride film are formed in the interlayer insulating film. . A bit line is formed so as to be connected to one source / drain of the first transistor through the first contact hole, and the first and second are extended into the second and third contact holes. The wiring is formed.

  When the element is further miniaturized and the first contact hole connecting the bit line and the source / drain is formed in a self-aligned manner with respect to the gate electrode, the first contact hole, the second and third The contact hole is preferably formed in a separate process. That is, when the first contact hole is formed, a part of the first contact hole is defined by the nitride film on the side wall of the first gate electrode, whereas the third contact hole penetrates the nitride film. It is because it is formed. By forming the first contact hole and the second and third contact holes in separate steps as described above, the size and shape of each contact hole can be made desired. In addition, the plug electrode can be formed only in the first contact hole. By forming the plug electrode, a thick metal silicide can be formed on the surface, and the deterioration of the junction leakage current characteristic can be effectively suppressed as described above.

  The source / drain of the second transistor has a high concentration region, and the step of forming the source / drain of the second transistor includes a step of forming a first metal silicide on the surface of the high concentration region. May be included. The step of forming the bit line includes a step of forming a plug electrode in the first contact hole, a step of forming a second metal silicide on the surface of the plug electrode, and a step on the second metal silicide. Forming a bit line.

  As described above, by forming the first metal silicide on the surface of the high concentration region in the source / drain of the second transistor, the sheet resistance of the source / drain of the second transistor can be reduced. Further, by forming the plug electrode in the first contact hole, it is possible to suppress the deterioration of the junction leakage current characteristic as described above.

  In still another aspect, the method for manufacturing a semiconductor device according to the present invention includes the following steps. First and second gate electrodes of the first and second transistors are formed on the main surface of the semiconductor substrate at an interval. A nitride film is formed so as to cover the side walls of the first and second gate electrodes. First impurity regions are formed on both sides of the first and second gate electrodes. An interlayer insulating film is formed so as to cover the first and second gate electrodes. A contact hole reaching one of the first impurity region of the first transistor and the nitride film is formed in the interlayer insulating film. By introducing an impurity into the semiconductor substrate through the contact hole, a second impurity region having a higher concentration than the first impurity region is formed so as to overlap with one first impurity region of the first transistor. A storage node electrically connected to the second impurity region through the contact hole is formed.

  By forming the second impurity region as described above, the diffusion depth of the source / drain on the side connected to the storage node can be selectively increased. Thereby, when the field insulating film is formed so as to be in contact with the source / drain on the side where the second impurity region is formed, the junction leakage current can be effectively reduced. In addition, since the source / drain on the side where the second impurity region is not formed can be formed shallowly, deterioration of punch-through resistance can be suppressed.

  As described above, according to the present invention, the junction leakage current can be reduced. Thereby, a highly reliable semiconductor device can be obtained.

1 is a cross sectional view showing a DRAM according to a first embodiment of the present invention. FIG. 7 is a cross-sectional view showing a characteristic first step in the manufacturing process of the DRAM shown in FIG. 1. FIG. 8 is a cross-sectional view showing a characteristic second step of the DRAM manufacturing step shown in FIG. 1. FIG. 9 is a cross-sectional view showing a characteristic third step of the manufacturing process of the DRAM shown in FIG. 1. FIG. 9 is a cross-sectional view showing a characteristic fourth step of the manufacturing process of the DRAM shown in FIG. 1. FIG. 9 is a cross-sectional view showing a characteristic fifth step of the DRAM manufacturing step shown in FIG. 1. FIG. 10 is a cross-sectional view showing a sixth characteristic step of the DRAM manufacturing process shown in FIG. 1. FIG. 12 is a cross-sectional view showing a characteristic seventh step of the manufacturing process of the DRAM shown in FIG. 1. FIG. 10 is a cross-sectional view showing a characteristic first step in a modification of the first embodiment. FIG. 10 is a cross-sectional view showing a characteristic second step in a modification of the first embodiment. FIG. 10 is a cross-sectional view showing another modification of the first embodiment. It is sectional drawing which shows the 1st process in the case of forming a p-channel MOS transistor in a peripheral circuit part. It is sectional drawing which shows the 2nd process in the case of forming a p-channel MOS transistor in a peripheral circuit part. It is sectional drawing which shows DRAM in Embodiment 2 of this invention. FIG. 15 is a cross-sectional view showing a characteristic first process in a manufacturing process of the DRAM shown in FIG. 14. FIG. 15 is a cross-sectional view showing a characteristic second step in the manufacturing process of the DRAM shown in FIG. 14. FIG. 15 is a cross-sectional view showing a characteristic third step of the manufacturing process of the DRAM shown in FIG. 14. FIG. 10 is a cross-sectional view showing a DRAM in a modification of the second embodiment. It is sectional drawing which shows DRAM in Embodiment 3 of this invention. FIG. 10 is a cross-sectional view showing a characteristic manufacturing process of the DRAM in the third embodiment. It is sectional drawing which shows DRAM in Embodiment 4 of this invention. FIG. 22 is a cross-sectional view showing a characteristic first step in the manufacturing process of the DRAM shown in FIG. 21. FIG. 22 is a cross-sectional view showing a characteristic second step in the manufacturing process of the DRAM shown in FIG. 21. FIG. 22 is a cross-sectional view showing a characteristic third step of the DRAM manufacturing step shown in FIG. 21. It is sectional drawing which shows DRAM in Embodiment 5 of this invention. FIG. 26 is a cross-sectional view showing a characteristic first step in the manufacturing process of the DRAM shown in FIG. 25. FIG. 26 is a cross-sectional view showing a characteristic second step in the manufacturing process of the DRAM shown in FIG. 25. FIG. 26 is a cross-sectional view showing a characteristic third step of the manufacturing process of the DRAM shown in FIG. 25. FIG. 26 is a cross-sectional view showing a characteristic fourth step in the manufacturing process of the DRAM shown in FIG. 25. FIG. 26 is a cross-sectional view showing a characteristic fifth step of the DRAM manufacturing step shown in FIG. 25. It is sectional drawing which shows the 1st process in the modification of the formation method of a titanium silicide film | membrane. It is sectional drawing which shows the 2nd process in the modification of the formation method of a titanium silicide film | membrane. It is sectional drawing which shows the other modification of the formation method of a titanium silicide film | membrane. It is a top view of the memory cell part of DRAM in Embodiment 6 of this invention. It is sectional drawing which shows DRAM in Embodiment 6 of this invention. FIG. 36 is a cross-sectional view showing a modification of the DRAM shown in FIG. 35. It is sectional drawing which shows an example of the conventional DRAM.

Hereinafter, embodiments of the present invention will be described with reference to FIGS.
(Embodiment 1)
First, Embodiment 1 of this invention and its modification are demonstrated using FIGS. FIG. 1 is a cross sectional view showing a DRAM according to the first embodiment of the present invention.

Referring to FIG. 1, a trench is formed in the main surface of p-type semiconductor substrate 1, and field insulating film 2 is formed in the trench. Under the field insulating film 2, a p-type impurity region 3 is formed for increasing the separation capability. On the p-type impurity region 3, p-type impurity regions 4a and 4b for controlling the threshold voltage of the transistor are formed. The impurity concentration of p-type impurity region 4a located in the memory cell part is about 10 ¹⁷ atoms / cm ³ , and the impurity concentration of p-type impurity region 4b located in the peripheral circuit part is about 10 ¹⁸ atoms / cm ³ .

A source / drain composed of a low-concentration n-type impurity region 5 and a medium-concentration n-type impurity region 6 is formed on the surface of the p-type impurity region 4a. The concentration of the low concentration n-type impurity region 5 is about 10 ¹⁶ to 10 ¹⁹ atoms / cm ³ , and the concentration of the medium concentration n-type impurity region 6 is about 10 ¹⁷ to 10 ²⁰ atoms / cm ³ . More preferably, the concentration of the medium concentration n-type impurity region 6 is about 3 to 10 times the concentration of the low concentration n-type impurity region 5.

On the other hand, on the surface of the p-type impurity region 4b in the peripheral circuit portion, a source / drain composed of regions having three different impurity concentrations is formed. Specifically, the source / drain includes a low-concentration n-type impurity region 5, a medium-concentration n-type impurity region 6, and a high-concentration n-type impurity region 7. The concentration of the high-concentration n-type impurity region 7 is about 10 ²⁰ to 10 ²¹ atoms / cm ³ .

  On the main surface of the p-type semiconductor substrate 1 sandwiched between the source / drain, a gate electrode 12 is formed via a gate insulating film 8 in the memory cell portion, and via a gate insulating film 9 in the peripheral circuit portion. A gate electrode 12 is formed. The thickness of the gate insulating film 8 is about 10 nm, for example, and the thickness of the gate insulating film 9 is about 5 nm, for example. Thus, by setting the thickness of the gate insulating film 8 in the memory cell portion to be larger than the thickness of the gate insulating film 9 in the peripheral circuit portion, the concentration of the p-type impurity region 4a in the memory cell portion can be lowered. Become. This is because the threshold voltage of the MOS transistor can be increased by increasing the thickness of the gate insulating film 8. By reducing the concentration of the p-type impurity region 4a as described above, the junction leakage current can be reduced.

  Further, by reducing the concentration of the p-type impurity region 4a, junction leakage can be reduced even if the intermediate concentration n-type impurity region 6 is formed. By forming the medium concentration n-type impurity region 6, it is possible to reduce the leakage current in the vicinity of the contact portion between the medium concentration n-type impurity region 6 and the field insulating film 2. In addition, the sheet resistance of the source / drain in the memory cell portion can be reduced. Thereby, a high-performance and high-reliability MOS transistor is formed in the memory cell portion.

  In the peripheral circuit portion, since the source / drain of the MOS transistor has the high concentration n-type impurity region 7, even if the concentration of the p-type impurity region 4b for controlling the threshold voltage is high, the source / The sheet resistance of the drain can be reduced. Therefore, it is possible to suppress the deterioration of the performance of the MOS transistor. Further, as shown in FIG. 1, the diffusion depth of the high concentration n-type impurity region 7 is smaller than the diffusion depth of the medium concentration n-type impurity region 6. Thereby, the medium concentration n-type impurity region 6 can be formed so as to surround the high concentration n-type impurity region 7. As a result, electric field concentration can be suppressed, and junction leakage current in the peripheral circuit portion can also be reduced.

  A TEOS oxide film 13 is formed on the gate electrode 12, and a sidewall insulating film 14 is formed on the side wall of the gate electrode 12. Then, an interlayer insulating film 15 is formed so as to cover the gate electrode 12. Contact holes 15a and 15b are provided in the interlayer insulating film 15. A bit line 16a extends in the contact hole 15a, and a wiring layer 16b extends in the contact hole 15b. The bit line 16a and the wiring layer 16b are constituted by a laminated structure of WSi and polysilicon, for example.

  Interlayer insulating film 17 is formed so as to cover bit line 16a and wiring layer 16b. A contact hole 17a is formed so as to penetrate through interlayer insulating film 17 and interlayer insulating film 15 to reach medium concentration n-type impurity region 6. Storage node 18 is formed to extend from within contact hole 17 a onto interlayer insulating film 17. A capacitor insulating film 19 is formed so as to cover the storage node 18, and a cell plate 20 is formed on the capacitor insulating film 19. The cell plate 20, the capacitor insulating film 19 and the storage node 18 constitute a capacitor 21.

  An interlayer insulating film 22 is formed on the interlayer insulating film 17 so as to cover the capacitor 21. Metal wiring 24a is formed on interlayer insulating film 22 located in the memory cell portion. In the peripheral circuit portion, a contact hole 23a penetrating the interlayer insulating film 22 and the interlayer insulating film 17, a contact hole 23b reaching the gate electrode 12, and a contact hole 23c reaching the high concentration n-type impurity region 7 are formed. The Metal interconnections 24b-24d are formed to extend from contact holes 23a-23c onto interlayer insulating film 22.

  Next, a method of manufacturing the DRAM shown in FIG. 1 will be described with reference to FIGS. 2 to 8 are sectional views showing characteristic first to seventh steps of the manufacturing process of the DRAM shown in FIG.

  Referring to FIG. 2, a trench is formed in the main surface of p-type semiconductor substrate 1, and a field insulating film 2 is formed by embedding an insulating film such as a silicon oxide film therein. Thereafter, p-type impurity regions 3, 4a and 4b are formed by using an ion implantation method or the like. Thereafter, a silicon oxide film 25 is formed on the entire surface by using a thermal oxidation method or the like. The thickness of the silicon oxide film 25 is about 7 to 8 nm.

  Next, as shown in FIG. 3, by selectively etching the silicon oxide film 25, the silicon oxide film 25 formed in the peripheral circuit portion is removed. Thereafter, a silicon oxide film having a thickness of about 5 nm is formed again using a thermal oxidation method or the like. As a result, as shown in FIG. 4, a gate insulating film 8 having a thickness of about 10 nm is formed in the memory cell portion, and a gate insulating film 9 having a thickness of about 5 nm is formed in the peripheral circuit portion.

Next, referring to FIG. 5, a polysilicon film 10, a WSi film 11, and a TEOS oxide film 13 are sequentially deposited and patterned. Thereby, the gate electrode 12 is formed. Thereafter, for example, phosphorus ions are implanted into the semiconductor substrate 1 under the conditions of a dose of 5 × 10 ^{12 to} 5 × 10 ¹³ atoms / cm ² and 5 to 50 keV. Thereby, the low concentration n-type impurity region 5 is formed in the memory cell portion and the peripheral circuit portion.

Next, referring to FIG. 6, after forming sidewall insulating film 14 on the side wall of gate electrode 12, for example, phosphorus ions are dosed at 3 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² and 10 to 100 keV. It is injected into the semiconductor substrate 1 under conditions. Thereby, medium concentration n-type impurity regions 6 are formed in the memory cell portion and the peripheral circuit portion, respectively. As a result, the low-concentration n-type impurity region 5 as in the conventional example is insufficient due to stress or damage during etching of the sidewall insulating film 14 in the region A in the vicinity of the peripheral portion of the field insulating film 2. It is possible to reduce the leak current.

  Next, referring to FIG. 7, a pair of high-concentration n-type impurity regions 7 are formed only in the peripheral circuit portion. At this time, the dose amount or implantation energy of the n-type impurity is controlled so that the diffusion depth of the high-concentration n-type impurity region 7 is smaller than the diffusion depth of the medium-concentration n-type impurity region 6. Thereby, as shown in FIG. 7, a high concentration n-type impurity region 7 surrounded by the medium concentration n-type impurity region 6 can be formed.

  Next, referring to FIG. 8, interlayer insulating film 15 is formed on the entire main surface of semiconductor substrate 1, and contact holes 15a and 15b are respectively formed thereon. Thereafter, the bit line 16a and the wiring layer 16b are formed.

  Next, an interlayer insulating film 17 is formed so as to cover the bit line 16a and the wiring layer 16b, and a contact hole 17a is formed in the memory cell portion. Then, after sequentially forming the storage node 18, the capacitor insulating film 19, and the cell plate 20, an interlayer insulating film 22 is formed. Next, contact holes 23a to 23c are formed in the peripheral circuit portion, and metal wirings 24a to 24d are formed. Through the above steps, the DRAM shown in FIG. 1 is formed.

  Next, a modification of the first embodiment will be described with reference to FIGS. First, a modification of the method for manufacturing the gate insulating films 8 and 9 will be described with reference to FIGS. In the first embodiment, the gate insulating films 8 and 9 having different thicknesses are formed by forming the silicon oxide film twice. However, as shown in FIG. 9, the silicon oxynitride film 33 may be formed after the silicon oxide film 25 is patterned. The silicon oxynitride film 33 can be formed by depositing a gas containing nitrogen.

  Thereafter, through the same process as in the first embodiment, as shown in FIG. 10, the MOS transistor having the gate insulating film 8a and the MOS transistor having the gate insulating film 9a are formed in the memory cell portion and the peripheral circuit portion. And formed respectively. By employing the silicon oxynitride film as the gate insulating film as described above, highly reliable gate insulating films 8a and 9a can be obtained.

  Next, another modification will be described with reference to FIG. As shown in FIG. 11, in this modification, the diffusion depth of the p-type impurity region 4a1 for controlling the threshold voltage is made shallower than the diffusion depth of the p-type impurity region 4b in the peripheral circuit portion. Thereby, the peak concentration of the p-type impurity region 4a1 can be further reduced. As a result, the junction leakage current can be further reduced. Further, since the concentration of the p-type impurity region 4a1 can be reduced, the sheet resistance of the low-concentration n-type impurity region 5 can also be reduced.

  Further, by making the diffusion depth of the p-type impurity region 4a1 smaller than the diffusion depth of the medium-concentration n-type impurity region 6, the medium-concentration n-type impurity region 6 is further reduced below the p-type impurity region 4a1. It will extend into the p-type impurity region of concentration. Thereby, the junction leakage current can be further reduced.

  The threshold voltage control impurity may be implanted after the gate insulating films 8 and 9 are formed or after the gate electrode 12 is formed. Further, the thickness of the gate insulating film may be changed in the peripheral circuit portion. By changing the thickness of the gate insulating film in the peripheral circuit portion, MOS transistors having different threshold voltages with the same channel injection amount can be formed.

  In the first embodiment described above, the case where the n-channel MOS transistor is formed in the peripheral circuit portion has been described. However, the p-channel MOS transistor in the peripheral circuit portion can be formed as follows.

  Referring to FIG. 12, n type impurity regions 27 and 28 are formed on the surface of n well region 26, respectively. Low-concentration n-type impurity region 5 and medium-concentration n-type impurity region 6 are formed on the surface of n-type impurity region 28 by the same method as in the first embodiment.

  Next, referring to FIG. 13, a pair of high-concentration p-type impurity regions 29 serving as source / drains are formed by implanting p-type impurities into semiconductor substrate 1.

  By forming the p-channel MOS transistor as described above, it is necessary to form a mask that covers the p-channel MOS transistor formation region when the low-concentration n-type impurity region 5 and the medium-concentration n-type impurity region 6 are formed. Disappear. Thereby, the manufacturing process can be simplified. Further, as shown in FIG. 13, punch-through resistance can be improved by making the diffusion depth of the high-concentration p-type impurity region 29 smaller than the diffusion depth of the medium-concentration n-type impurity region 6.

(Embodiment 2)
Next, Embodiment 2 of this invention and its modification are demonstrated using FIGS. 14-18. FIG. 14 is a cross sectional view showing a DRAM according to the second embodiment of the present invention.

  Referring to FIG. 14, in the present second embodiment, one of the source / drain of the MOS transistor in the memory cell portion is constituted only by low-concentration n-type impurity region 5 and the other of the source / drain is low-concentration n-type impurity. Region 5 and medium concentration n-type impurity region 6a are formed. Further, the source / drain of the MOS transistor in the peripheral circuit portion is composed of the low concentration n-type impurity region 5 and the high concentration n-type impurity region 7. Other structures are the same as those shown in FIG.

  As shown in FIG. 14, since the source / drain on the side connected to the bit line 16a is constituted only by the low-concentration n-type impurity region 5, the junction capacitance is reduced as compared with the case of the first embodiment. Can also improve punch-through resistance. Further, as in the case of the first embodiment, it is possible to reduce the leakage current in the vicinity of the region A.

  Next, a method of manufacturing the DRAM shown in FIG. 14 will be described with reference to FIGS. 15 to 17 are sectional views showing characteristic first to third steps of the manufacturing process of the DRAM shown in FIG.

  Referring to FIG. 15, up to low concentration n-type impurity region 5 is formed through the same steps as in the first embodiment. Thereafter, the sidewall insulating film 14 is formed, and the high concentration n-type impurity region 7 is formed only in the peripheral circuit portion. At this time, the high-concentration n-type impurity region 7 in the peripheral circuit portion may be formed by implanting both arsenic and phosphorus. As a result, the sheet resistance of the source / drain under the sidewall insulating film 14 can be reduced.

Next, as shown in FIG. 16, bit lines 16a and wiring layers 16b are formed by the same method as in the first embodiment. Then, an interlayer insulating film 17 is formed so as to cover the bit line 16a, and a contact hole 17a is formed as shown in FIG. Phosphorus ions are implanted through the contact hole 17a under the conditions of a dose of 3 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² and 30 to 200 keV. Thereby, medium concentration n-type impurity region 6a is formed. Thereafter, the DRAM shown in FIG. 14 is formed through the same steps as in the first embodiment.

  Next, a modification of the second embodiment will be described with reference to FIG. FIG. 18 is a cross-sectional view showing a DRAM according to this modification.

  Referring to FIG. 18, in this modification, p-type impurity region 4a1 is formed at a position shallower than p-type impurity region 4b. At this time, since the source / drain connected to the bit line 16a is constituted only by the low-concentration n-type impurity region 5, the junction leakage current can be further reduced as compared with the case shown in FIG.

(Embodiment 3)
Next, Embodiment 3 of the present invention will be described with reference to FIG. 19 and FIG. FIG. 19 is a cross sectional view showing a DRAM according to the third embodiment of the present invention.

Referring to FIG. 19, in the third embodiment, high concentration n-type impurity region 7a is formed so as to extend under intermediate concentration n-type impurity region 6a in the second embodiment. The concentration of the high-concentration n-type impurity region 7a is about 10 ¹⁸ to 10 ²⁰ atoms / cm ³ and is set to be higher than the concentration of the medium-concentration n-type impurity region 6a. Further, the high concentration n-type impurity region 7 a is formed to reach the bottom of the field insulating film 2.

  By providing the high-concentration n-type impurity region 7a as described above, the leakage current in the vicinity of the region B in FIG. 19 can be reduced. As a result, the leakage current can be further reduced as compared with the case of the second embodiment.

  Next, a manufacturing method of the DRAM shown in FIG. 19 will be described with reference to FIG. FIG. 20 is a cross-sectional view showing characteristic steps in the manufacturing process of the DRAM shown in FIG.

Referring to FIG. 20, through the same process as in the second embodiment described above, up to medium concentration n-type impurity region 6a is formed. Thereafter, phosphorus ions are implanted through the contact hole 17a under conditions of a dose amount of 3 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² and 30 to 200 keV. As a result, a high concentration n-type impurity region 7a extending under the medium concentration n-type impurity region 6a is formed. Thereafter, the DRAM shown in FIG. 19 is formed through the same process as in the first embodiment.

(Embodiment 4)
Next, a fourth embodiment of the present invention will be described with reference to FIGS. FIG. 21 is a cross sectional view showing a DRAM according to the fourth embodiment of the present invention.

  Referring to FIG. 21, in the fourth embodiment, thin silicon oxide film 31 is formed so as to cover gate electrode 12, and silicon nitride film 30 is formed thereon. The bit line 16a1 is made of a metal such as W / TiN / Ti. A titanium silicide film 32 is formed between the bit line 16a1 and the medium concentration n-type impurity region 6.

  In the peripheral circuit portion, wiring layers 16b1 and 16c made of the same material as the bit line 16a1 are formed. A titanium silicide film 32 is also formed between the wiring layer 16b1 and the high-concentration n-type impurity region 7. The metal wiring 24c is connected to the gate electrode 12 through the wiring layer 16c. The structure below that is the same as that shown in FIG.

  In the fourth embodiment, as shown in FIG. 21, a silicon nitride film 30 is formed so as to cover the gate electrode 12. The silicon nitride film 30 is for forming a contact hole 15a1 for connection between the bit line 16a1 and the medium concentration n-type impurity region 6 in a self-aligning manner. Providing such a silicon nitride film 30 can cope with further miniaturization.

  Further, the contact resistance can be stabilized by forming the titanium silicide film 32 at the contact portion between the bit line 16a1 or the wiring layer 16b1 and the source / drain. At this time, the titanium silicide film 32 is formed on the surface of the low concentration impurity region by forming the titanium silicide film 32 on the surface of the medium concentration n type impurity region 6 or the surface of the high concentration n type impurity region 7. Compared to the above, it becomes possible to reduce the leakage current.

  Next, a method for manufacturing the DRAM shown in FIG. 21 will be described with reference to FIGS. 22 to 24 are sectional views showing characteristic first to third steps of the manufacturing process of the DRAM shown in FIG.

  Referring to FIG. 22, gate insulating films 8 and 9 are formed through the same steps as in the first embodiment. Then, a polysilicon film, a WSi film, a silicon oxide film, and a silicon nitride film are sequentially deposited and patterned. Thereafter, the low concentration n-type impurity region 5 is formed by the same method as in the first embodiment. Next, a silicon oxide film 31 is formed on the side wall of the gate electrode 12, and a silicon nitride film is formed thereon. Thereby, the silicon nitride film 30 shown in FIG. 22 is formed. Then, using this silicon nitride film 30 as a mask, medium concentration n-type impurity region 6 and high concentration n-type impurity region 7 are formed by the same method as in the first embodiment. Thereafter, an interlayer insulating film 15 is formed, and a contact hole 15a1 is formed only in the memory cell portion.

  Next, referring to FIG. 23, contact holes 15b and 15c are respectively formed in the peripheral circuit portion. As described above, the contact hole 15a1 in the memory cell portion and the contact holes 15b and 15c in the peripheral circuit portion are formed in different processes, so that the size and shape of the contact hole 15a1 formed in a self-aligned manner and the contact hole 15c are reduced. Better control.

  Next, referring to FIG. 24, a titanium film, a TiN film, and a W film are sequentially formed, and heat treatment is performed. As a result, a titanium silicide film 32 is formed in a portion in contact with the semiconductor substrate 1. Thereafter, the above laminated structure is patterned. Thereby, the bit line 16a1 and the wiring layers 16b1 and 16c are formed. Thereafter, the DRAM shown in FIG. 22 is formed through the same process as in the first embodiment. Instead of the intermediate concentration n-type impurity region 6 located immediately below the bit line 16a1, an intermediate concentration n-type impurity region 6a may be formed.

(Embodiment 5)
A fifth embodiment of the present invention and a modification thereof will be described with reference to FIGS. FIG. 25 is a cross sectional view showing a DRAM according to the fifth embodiment of the present invention.

  Referring to FIG. 25, in the fifth embodiment, a polysilicon plug 36 is formed in contact hole 15a, and bit line 16a2 is formed on polysilicon plug 36 with titanium silicide film 37 interposed. The bit line 16a2 is made of the same material as the bit line 16a1.

  On the other hand, in the peripheral circuit portion, a titanium silicide film 35 is formed on the surface of the high-concentration n-type impurity region 7. The metal wiring 24 c is directly connected to the gate electrode 12. Other structures are the same as those shown in FIG.

  By forming the titanium silicide film 37 on the polysilicon plug 36 as described above, a thicker titanium silicide film can be formed than in the case of the titanium silicide film 32 shown in FIG. This is because a titanium film for forming the titanium silicide film 32 is usually formed by sputtering, and it is difficult to form a thick film at the bottom of the contact hole 15a1. Also, in the peripheral circuit portion, the titanium silicide film 35 can be formed thicker than that in the fourth embodiment for the same reason. By forming the titanium silicide films 35 and 37 thick as described above, when the heat treatment at about 800 ° C. or higher is performed in the subsequent process, the titanium silicide films are aggregated to increase the junction leakage current and the contact resistance. It is possible to effectively suppress the increase.

  In FIG. 25, the intermediate concentration n-type impurity region 6 directly under the polysilicon plug 36 may be omitted. Further, although the titanium silicide film is used in the fourth embodiment and the fifth embodiment, other metal silicide films such as cobalt silicide may be used.

  Next, a method of manufacturing the DRAM shown in FIG. 25 will be described with reference to FIGS. 26 to 30 are sectional views showing characteristic first to fifth steps of the manufacturing process of the DRAM shown in FIG.

  Referring to FIG. 26, up to high concentration n-type impurity region 7 is formed through the same steps as in the fourth embodiment. At this time, the silicon oxide film 31 is left so as to cover the surface of the medium concentration n-type impurity region 6 in the memory cell portion. Thereby, it is possible to prevent the semiconductor substrate 1 from being damaged during the etching of the silicon nitride film 30.

  Next, as shown in FIG. 27, a titanium film 34 is formed on the entire surface by sputtering or the like. At this time, since the silicon oxide film 31 is formed so as to cover the intermediate concentration n-type impurity region 6 in the memory cell portion, the intermediate concentration n-type impurity region 6 and the titanium film 34 in the memory cell portion are not in contact with each other. On the other hand, in the peripheral circuit portion, the high concentration n-type impurity region 7 and the titanium film 34 are in contact with each other. In this state, the titanium film 34 is subjected to lamp annealing.

  Next, referring to FIG. 28, a titanium silicide film 35 is formed in a self-aligned manner on the surface of high-concentration n-type impurity region 7 in the peripheral circuit portion by the lamp annealing process described above.

  Next, referring to FIG. 29, after forming interlayer insulating film 15, contact hole 15a is formed in the memory cell portion. A polysilicon plug 36 is formed in the contact hole 15a. Thereafter, contact holes 15b are formed in the peripheral circuit portion.

  Next, a titanium silicide film 37 is formed on the surface of the polysilicon plug 36, and a bit line 16a2 and a wiring layer 16b1 are formed thereon by the same method as in the fourth embodiment. Thereafter, the DRAM shown in FIG. 25 is formed through the same process as in the first embodiment.

  Next, a modification of the fifth embodiment will be described with reference to FIGS. 31 to 33 are cross-sectional views showing characteristic steps in this modification. First, referring to FIG. 31, in this modification, the silicon nitride film 30 is left on the surface of the semiconductor substrate 1 located between the gate electrodes 12 in the memory cell portion. In this state, the medium concentration n-type impurity region 6 is formed. Thereby, in the peripheral circuit portion, a medium concentration n-type impurity region 6b having a diffusion depth larger than that in the memory cell portion is formed. By providing the intermediate concentration n-type impurity region 6b at a deep position as described above, it is possible to effectively suppress the high concentration n-type impurity region 7 formed in a later step from penetrating the intermediate concentration n-type impurity region 6b. Similarly to the case shown in FIG. 26, it is possible to effectively suppress the etching damage from entering the surface of the semiconductor substrate in the memory cell portion.

  Next, referring to FIG. 32, after forming high concentration n-type impurity region 7 in the peripheral circuit portion, titanium film 34 is formed on the entire surface. In this state, the titanium film 34 is subjected to lamp annealing. Thereby, a titanium silicide film 35 is formed.

  As shown in FIG. 33, after the titanium film 34 is formed on the entire surface, the lamp film may be subjected to the lamp annealing after the titanium film 34 in the memory cell portion is selectively removed. Also in this case, the titanium silicide film 35 can be selectively formed on the surface of the high concentration n-type impurity region 7.

(Embodiment 6)
Next, Embodiment 6 of the present invention will be described with reference to FIGS. FIG. 34 is a plan view of the memory cell portion of the DRAM according to the sixth embodiment of the present invention. FIG. 35 is a cross sectional view showing a DRAM according to the sixth embodiment. Note that the cross-sectional view of the memory cell portion of FIG. 35 shows a cross section taken along the line AA ′ of FIG.

In the sixth embodiment, contact hole 17a1 for connecting storage node 18 and medium concentration n-type impurity region 6a is formed to reach silicon nitride film 30 located on both sides thereof. Then, the silicon nitride film 30 on the side wall of the gate electrode 12 is etched using CF ₄ + O ₂ gas or the like. Accordingly, the width W of the low-concentration n-type impurity region 5 connected to the medium-concentration n-type impurity region 6a can be reduced. Thereby, the sheet resistance of the source / drain can be reduced, and the transistor characteristic deterioration is suppressed.

On the other hand, as shown in FIGS. 34 and 35, the contact hole 17a1 is formed so as to reach the field insulating film 2. However, since the intermediate concentration n-type impurity region 6a is formed, the stress in the region A described above is formed. In addition, it becomes possible to reduce the leakage current in the vicinity of the peripheral portion of the field insulating film 2 due to etching damage when the contact hole 17a1 is formed. Even if etching damage is applied to the main surface of the semiconductor substrate 1 during the formation of the contact hole 17a1, it is possible to reduce the etching damage by, for example, thinly cutting the main surface of the semiconductor substrate 1 with CF ₄ + O ₂ gas. Is possible.

  Next, a modification of the sixth embodiment will be described with reference to FIG. FIG. 36 is a cross sectional view showing a DRAM according to a modification of the sixth embodiment.

  Referring to FIG. 36, in this modification, a part of field insulating film 2 is etched when contact hole 17a1 is formed. Thereby, a recess 38 is formed in the field insulating film 2. By removing a part of the peripheral portion of the field insulating film 2 in this way, it becomes possible to reduce the leakage current due to the stress caused by the formation of the field insulating film 2. In addition, since the contact area between the storage node and the medium concentration n-type impurity region 6a can be increased, the contact resistance can also be improved.

  Although the embodiments of the present invention have been described above, the embodiments disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 p-type semiconductor substrate, 2 field insulating film, 3, 4a, 4a1, 4b p-type impurity region, 6, 6a, 6b medium-concentration n-type impurity region, 5 low-concentration n-type impurity region, 7, 7a high-concentration n-type Impurity region, 8, 9, 8a, 8b, 9a Gate insulating film, 10 Polysilicon film, 11 WSi film, 12 Gate electrode, 13 TEOS oxide film, 14 Side wall insulating film, 15, 17, 22 Interlayer insulating film, 15a , 15b, 15c, 15a1, 17a, 23a, 23b, 23b1, 23c Contact hole, 16a, 16a1, 16a2 Bit line, 16b, 16b1, 16c Wiring layer, 18 storage node, 19 capacitor insulating film, 20 cell plate, 21 capacitor 24a-24d Metal wiring, 30 Silicon nitride film, 32, 35, 37 Titanium series Side film, 33 silicon oxynitride film, 34 titanium film, 36 polysilicon plug, 38 recess, 39 element formation region.

Claims (3)

A method of manufacturing a semiconductor device having a memory cell portion and a peripheral circuit portion of a dynamic random access memory,
A first step of forming a trench on each of the main surfaces of the semiconductor substrate in the memory cell portion and the peripheral circuit portion;
A second step of forming a field insulating film by embedding an insulating film in the trench;
A first gate electrode is formed on a portion of the main surface of the semiconductor substrate in the memory cell portion where the trench is not formed, and the trench on the main surface of the semiconductor substrate is formed in the peripheral circuit portion. A third step of forming a second gate electrode on the non-existing portion;
After the third step, an impurity is implanted into the main surface of the semiconductor substrate in the presence of the first and second gate electrodes, and the memory cell is in contact with the field insulating film in the memory cell portion. A fourth step of forming a first impurity region in the portion and a second impurity region in the peripheral circuit portion so as to be in contact with the field insulating film in the peripheral circuit portion;
After the fourth step, a fifth step of forming first and second sidewall insulating films on the side surfaces of the first and second gate electrodes, respectively;
After the fifth step, impurities are implanted into the main surface of the semiconductor substrate in a state where the first and second gate electrodes and the first and second sidewall insulating films exist, and the memory cell unit Forming a third impurity region in the memory cell portion so as to be in contact with the field insulating film, and forming a fourth impurity region in the peripheral circuit portion so as to be in contact with the field insulating film in the peripheral circuit portion. A sixth step of:
A seventh step of forming a capacitor electrically connected to the third impurity region after the sixth step;
One source or drain region of the first transistor having the first gate electrode includes the first impurity region and the third impurity region,
The method of manufacturing a semiconductor device, wherein one source or drain region of the second transistor having the second gate electrode includes the second impurity region and the fourth impurity region.   The method for manufacturing a semiconductor device according to claim 1, wherein a dose amount of the impurity implanted in the sixth step is larger than a dose amount of the impurity implanted in the fourth step.   The impurity concentration of the third impurity region is higher than the impurity concentration of the first impurity region, and the impurity concentration of the fourth impurity region is higher than the impurity concentration of the second impurity region. 2. A method of manufacturing a semiconductor device according to 1.

Images