JP2011198909A - Resistance-change type nonvolatile memory device - Google Patents

Abstract

A variable resistance nonvolatile memory element capable of avoiding an increase in current during a break in an initial break process is provided.
A variable resistance nonvolatile memory element includes a first electrode, an interlayer insulating layer formed on a substrate, a columnar second electrode formed inside the interlayer insulating layer, A resistance change layer which is interposed between the first electrode 17 and the second electrode 13 and whose resistance value reversibly changes based on electrical signals having different polarities given between the electrodes. 14 is a first region 16a containing a first oxygen-deficient transition metal oxide having a composition represented by MO _x , and a second oxygen-deficient transition metal having a composition represented by NO _y A second region 15a containing an oxide, the oxygen deficiency rate of the second region 15a is smaller than the oxygen deficiency rate of the first region 16a, and the second region 15a and the second electrode 13 are in contact with each other. The area of the second region 15 a is larger than the electrode surface of the second electrode 13. It is formed.
[Selection] Figure 2

Description

  The present invention relates to a variable resistance nonvolatile memory element in which a resistance value changes according to an applied electrical signal, and more specifically, a bipolar operation type resistance change in which a resistance value reversibly changes based on electrical signals having different polarities. The present invention relates to a type nonvolatile memory element.

  In recent years, with the advancement of digital technology, electronic devices such as portable information devices and information home appliances have become more sophisticated. As these electronic devices have higher functions, the semiconductor elements used have been rapidly miniaturized and increased in speed. Among them, the use of a large-capacity nonvolatile memory represented by a flash memory is rapidly expanding. Furthermore, research and development of a nonvolatile memory device having a so-called variable resistance nonvolatile memory element is progressing as a next-generation new nonvolatile memory that replaces the flash memory. Here, the variable resistance nonvolatile memory element has a property that a resistance value reversibly changes by an electrical signal, and is an element capable of storing information corresponding to the resistance value in a nonvolatile manner. That means.

  As disclosed in Patent Document 1, a variable resistance nonvolatile memory element has a structure in which a variable resistance layer made of a variable resistance material is sandwiched between a pair of electrodes, and its electrical characteristics. Based on the difference, it is roughly classified into a bipolar operation type and a unipolar operation type.

A bipolar operation type nonvolatile memory element (hereinafter referred to as a “bipolar operation element”) is a type of element that uses voltages of different polarities in order to change the resistance state between a high resistance state and a low resistance state. is there. On the other hand, unipolar operation type nonvolatile memory elements (hereinafter referred to as “unipolar operation type elements”) are elements of the same type that use voltages of the same polarity in order to change the resistance state. For example, a single transition metal oxide such as nickel oxide (NiO _x ) or titanium oxide (TiO _x ) is used.

Of the two types of nonvolatile memory elements described above, the unipolar operation type element has the following problems. In the case of a unipolar operation type element using a transition metal oxide such as NiO _x, as disclosed in Non-Patent Document 1, the resistance change material is changed from a high resistance state to a low resistance state by a short electric pulse of about 100 ns. Can be changed. However, in order to change from the low resistance state to the high resistance state, a long pulse on the order of μs is required, and it is difficult to increase the operation speed.

  In addition, the unipolar element has a problem that the resistance state hardly changes immediately after the structure in which the variable resistance layer is sandwiched between the upper and lower electrodes is formed. In general, in the operation of a resistance change type nonvolatile memory element, an initial break process similar to dielectric breakdown of an insulator is required before steady resistance change is reached. In this initial break process, a voltage higher than the voltage required for steady resistance change is applied to the element, which hinders low voltage operation. In the case of the unipolar operation type element, there is a demerit that the voltage required for the initial break process becomes high.

  On the other hand, as disclosed in Patent Document 2, a bipolar operation type element having a resistance change layer composed of a laminated structure of a high resistance layer (high oxygen concentration layer) and a low resistance layer (low oxygen concentration layer). In this case, stable high-speed driving can be realized at a low voltage. In addition, since the thickness of the high-resistance layer is as thin as about 5 nm, there is an advantage that the voltage required for the initial break process is lower than that in the case of the unipolar operation type element.

International Publication No. 2007/013174 International Publication No. 2008/149484

I.G.Beak et al., Tech. Digest IEDM 2004, p. 587

  As described above, the initial break process hinders low voltage operation. In particular, when the initial break process is performed in a state where a load element such as a diode or a transistor is connected to the variable resistance nonvolatile memory element, if the current at the time of the break is large, the nonvolatile element is nonvolatile due to IR drop at the load element. In some cases, the effective applied voltage to the memory element is lowered, and as a result, the initial break does not occur. Therefore, in order to surely cause an initial break, it is necessary to increase the applied voltage by an amount that compensates for the IR drop in the load element.

  In a unipolar element, the resistance change layer is made of a relatively thick metal oxide having a high oxygen concentration of 10 nm or more. Therefore, although the breakdown voltage itself of the element is high, the current during the break is very small. As a result, the voltage drop by the IR drop due to the load element hardly occurs.

  On the other hand, in the case of a bipolar operation type element having a resistance change layer composed of a laminated structure of a high resistance layer and a low resistance layer as described above, the high resistance layer is thin, so the break voltage of the element alone Although the voltage itself is low, since the current at the time of break is large, a voltage increase due to the IR drop by the load element can be a problem.

  The present invention has been made in view of such circumstances, and a main object thereof is to provide a variable resistance nonvolatile memory element that can solve the above-described problems.

  The inventors of the present invention have made extensive studies in order to avoid an increase in current during a break in the bipolar operation type element as described above. The magnitude of the current at the time of the break is proportional to the area where the high resistance layer (high oxygen concentration layer) and the electrode are in contact, and reducing the area is effective for avoiding an increase in the current at the time of the break. I got the knowledge. The present invention has been made based on this finding.

In order to solve the above-described problem, a variable resistance nonvolatile memory element according to one embodiment of the present invention is formed in a first electrode, an interlayer insulating layer formed over a substrate, and the interlayer insulating layer. A columnar second electrode and a reversible resistance based on electrical signals having different polarities provided between the first electrode and the second electrode, and interposed between the first electrode and the second electrode. A variable resistance layer having a variable value, wherein the variable resistance layer has a first oxygen deficiency having a composition represented by MO _x where M is the first transition metal and N is the second transition metal. A first region containing a transition metal oxide of a type and a second region containing a second oxygen-deficient transition metal oxide having a composition represented by NO _y , and a stoichiometric state in a lack of oxygen index of the NO _y the oxide of the second transition metal N is, stoichiometric Less than the oxygen deficiency rate of the MO _y with respect to the a cytometry state oxides of first transition metal M, wherein is in contact with the second region and the second electrode, the second region is the first The area is larger than the electrode surface of the two electrodes.

  With this configuration, the contact area between the second region serving as the high resistance layer and the second electrode can be reduced, so that an increase in current during the break in the initial break process can be avoided. It becomes possible.

  Further, the same transition metal may be used as M for the first transition metal and N for the second transition metal.

  In this aspect, a load element electrically connected to the resistance change layer may be further provided. The load element may be a transistor, or a diode having a stacked structure of a semiconductor layer or insulator layer and a metal electrode layer sandwiching the semiconductor layer or insulator layer.

  In this aspect, the first electrode functions as the metal electrode layer positioned on the resistance change layer side, and a contact area between the semiconductor layer or the insulator layer and the first electrode is the second region. And the contact area between the second electrode and the second electrode.

  In this aspect, the diode may be formed inside the interlayer insulating layer.

  In this aspect, the metal electrode layer and the semiconductor layer or the insulator layer located on the resistance change layer side may be formed in a hole formed in the interlayer insulating layer.

  In this aspect, the first electrode and the variable resistance layer may be formed integrally with a wiring that supplies an electrical signal to the first electrode. In this case, the diode may be formed between the second electrode and a wiring that supplies an electrical signal to the second electrode.

In this embodiment, the variable resistance layer includes a first region containing a first oxygen-deficient tantalum oxide having a composition represented by TaO _x (where 0.8 ≦ x ≦ 1.9). And a second region containing a second oxygen-deficient tantalum oxide having a composition represented by TaO _y (where 2.1 ≦ y <2.5). In addition, the variable resistance layer includes a first region containing a first oxygen-deficient hafnium oxide having a composition represented by HfO _x (where 0.9 ≦ x ≦ 1.6). And a second region containing a second oxygen-deficient hafnium oxide having a composition represented by HfO _y (where 1.8 <y <2.0), and The variable resistance layer includes a first region containing a first oxygen-deficient zirconium oxide having a composition represented by ZrO _x (where 0.9 ≦ x ≦ 1.4), and ZrO _y (where And a second region containing a second oxygen-deficient zirconium oxide having a composition represented by 1.9 <y <2.0).

Furthermore, the variable resistance layer includes the first region containing an oxygen-deficient tantalum oxide having a composition represented by TaO _x (where 0.8 ≦ x ≦ 1.9), and HfO _y (where And the second region including an oxygen-deficient hafnium oxide having a composition represented by 1.8 <y <2.0).

  In this aspect, the semiconductor device further includes an upper wiring that supplies an electrical signal to the first electrode, and a lower wiring that supplies an electrical signal to the second electrode, and the second electrode is electrically connected to the lower wiring. It is preferable that the contact plug be used for connection. Here, the contact plug may be made of any one of copper, silver, palladium, iridium, platinum, and gold, and the second region may contain an oxide of tantalum, niobium, zirconium, hafnium, or titanium. The contact plug is made of tungsten, rhenium, ruthenium, copper, silver, palladium, iridium, platinum, or gold, and the second region contains an oxide of niobium, zirconium, hafnium, or titanium. Also good.

  In this embodiment, the first region may contain an oxide of tantalum or hafnium.

  Furthermore, in this aspect, the first electrode and the resistance change layer may be formed integrally with a wiring that supplies an electrical signal to the first electrode.

  According to the variable resistance nonvolatile memory element according to the present invention, it is possible to avoid an increase in current during the break in the initial break process.

1 is a block diagram showing a configuration of a 1T1R type nonvolatile memory device including a nonvolatile memory element according to Embodiment 1 of the present invention. Sectional drawing which shows an example of a structure of the non-volatile memory element which concerns on Embodiment 1 of this invention. (A) thru | or (d) is sectional drawing which shows the manufacturing process of the non-volatile memory element which concerns on Embodiment 1 of this invention. (A) thru | or (c) is sectional drawing which shows the manufacturing process of the non-volatile memory element which concerns on Embodiment 1 of this invention. (A) thru | or (d) is sectional drawing which shows the manufacturing process of the non-volatile memory element which concerns on Embodiment 1 of this invention. Sectional drawing which shows the structure of the modification 1 of the non-volatile memory element which concerns on Embodiment 1 of this invention. (A) thru | or (d) is sectional drawing which shows the manufacturing process of the modification 1 of the non-volatile memory element based on Embodiment 1 of this invention. (A) thru | or (d) is sectional drawing which shows the manufacturing process of the modification 1 of the non-volatile memory element based on Embodiment 1 of this invention. Sectional drawing which shows the structure of the modification 2 of the non-volatile memory element which concerns on Embodiment 1 of this invention. (A) And (b) is sectional drawing which shows the structure of the modification 3 of the non-volatile memory element which concerns on Embodiment 1 of this invention. (A) And (b) is sectional drawing which shows the structure of the modifications 4 and 5 of the non-volatile memory element based on Embodiment 1 of this invention. The block diagram which shows the structure of the non-volatile memory device which concerns on Embodiment 2 of this invention. FIG. 12 is a perspective view showing the configuration (configuration for 4 bits) of part A in FIG. Sectional drawing which shows an example of a structure of the non-volatile memory element which concerns on Embodiment 2 of this invention. (A) thru | or (d) is sectional drawing which shows the manufacturing process of the non-volatile memory element which concerns on Embodiment 2 of this invention. (A) thru | or (c) is sectional drawing which shows the manufacturing process of the non-volatile memory element which concerns on Embodiment 2 of this invention. (A) thru | or (d) is sectional drawing which shows the manufacturing process of the non-volatile memory element which concerns on Embodiment 2 of this invention. Sectional drawing which shows the structure of the modification 6 of the non-volatile memory element which concerns on Embodiment 2 of this invention. Sectional drawing which shows the structure of the modification 7 of the non-volatile memory element which concerns on Embodiment 2 of this invention. (A) thru | or (c) is sectional drawing which shows the structure of the modifications 8 thru | or 10 of the non-volatile memory element based on Embodiment 2 of this invention. (A) thru | or (e) is sectional drawing which shows the manufacturing process of the modification 9 of the non-volatile memory element based on Embodiment 2 of this invention. (A) thru | or (c) is sectional drawing which shows the structure of the modifications 11 thru | or 13 of the non-volatile memory element based on Embodiment 2 of this invention. Sectional drawing which shows an example of a structure of the non-volatile memory element which concerns on Embodiment 3 of this invention. Sectional drawing which shows the structure of the modification 14 of the non-volatile memory element which concerns on Embodiment 3 of this invention. (A) thru | or (d) is sectional drawing which shows the manufacturing process of the modification 14 of the non-volatile memory element based on Embodiment 3 of this invention. (A) thru | or (d) is sectional drawing which shows the manufacturing process of the modification 14 of the non-volatile memory element based on Embodiment 3 of this invention. Sectional drawing which shows the structure of the modification 15 of the non-volatile memory element which concerns on Embodiment 3 of this invention. (A) thru | or (c) is sectional drawing which shows the structure of the modifications 16 thru | or 18 of the non-volatile memory element based on Embodiment 3 of this invention. A graph showing the correlation between the difference between the standard electrode potential of the transition metal constituting the oxygen-deficient transition metal oxide and the standard electrode potential of the electrode material, and the resistance change of the oxygen-deficient metal oxide The graph for demonstrating the combination of the appropriate material of the high resistance layer and the 2nd electrode in the non-volatile memory element which concerns on Embodiment 1 of this invention The graph for demonstrating the combination of the appropriate material of the high resistance layer and the 2nd electrode in the non-volatile memory element which concerns on Embodiment 1 of this invention The graph for demonstrating the combination of the appropriate material of the high resistance layer and the 2nd electrode in the non-volatile memory element which concerns on Embodiment 1 of this invention

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In addition, the same element is attached | subjected the same code | symbol in each drawing, and description may be abbreviate | omitted. Moreover, in each drawing, in order to make it easy to understand, each component is typically shown, and the shape, dimension, etc. may not be accurate.

(Embodiment 1)
The variable resistance nonvolatile memory element according to the first embodiment (hereinafter simply referred to as “nonvolatile memory element”) has a MOS at the intersection of a bit line and a word line arranged so as to be orthogonal to each other. Resistance change provided in a so-called 1T1R nonvolatile memory device in which a transistor and a resistance variable nonvolatile memory element (resistance variable element) are connected in series to form a nonvolatile memory unit with one transistor and one resistance variable element. It is an element. First, the configuration of the 1T1R type nonvolatile memory device will be described.

[Configuration of non-volatile storage device]
FIG. 1 is a block diagram showing a configuration of a 1T1R type nonvolatile memory device including the nonvolatile memory element according to Embodiment 1 of the present invention. As shown in FIG. 1, the nonvolatile memory device 100 includes a memory main body 101 on a semiconductor substrate. The memory main body 101 includes a memory array 102, a row selection circuit / driver 103, and a column selection. A circuit 104, a write circuit 105 for writing information, a sense amplifier 106 for detecting the amount of current flowing through the selected bit line and determining data “1” or “0”, and a terminal DQ. A data input / output circuit 107 that performs input / output processing of output data is provided.

  The nonvolatile memory device 100 also includes a cell plate power supply (VCP power supply) 108, an address input circuit 109 that receives an address signal input from the outside, and a control signal input from the outside. And a control circuit 110 for controlling the operation.

  The memory array 102 includes a plurality of word lines WL0, WL1, WL2,... And bit lines BL0, BL1, BL2,... , WL1, WL2,... And bit lines BL0, BL1, BL2,... And a plurality of transistors T11, T12, T13, T21, T22, T23, T31, T32, T33,. , “Transistors T11, T12,...”) And a plurality of memory cells M111, M112, M113, M121, M122, M123, M131, M132, M133 (one-to-one with the transistors T11, T12,. Hereinafter, “represented as“ memory cells M111, M112,... ”” Are provided. Here, the memory cells M111, M112,... Correspond to a nonvolatile memory element according to the first embodiment described later.

  The memory array 102 includes a plurality of plate lines PL0, PL1, PL2,... Arranged in parallel with the word lines WL0, WL1, WL2,. The plurality of plate lines may be arranged in parallel with the bit lines.

  The drains of the transistors T11, T12, T13,... Are connected to the bit line BL0, the drains of the transistors T21, T22, T23, ... are connected to the bit line BL1, and the drains of the transistors T31, T32, T33,. Has been.

  In addition, the gates of the transistors T11, T21, T31,... Are on the word line WL0, the gates of the transistors T12, T22, T32, ... are on the word line WL1, and the gates of the transistors T13, T23, T33,. Each is connected.

  Further, the sources of the transistors T11, T12,... Are connected to the memory cells M111, M112,.

  The memory cells M111, M121, M131,... Are connected to the plate line PL0, the memory cells M112, M122, M132,... Are connected to the plate line PL1, and the memory cells M113, M123, M133,. ing.

  In FIG. 1, a plurality of plate lines are connected to a common power supply VCP, but each plate line may have an individual selection circuit and a driver.

  The address input circuit 109 receives an address signal from an external circuit (not shown), outputs a row address signal to the row selection circuit / driver 103 based on the address signal, and outputs a column address signal to the column selection circuit 104. To do. Here, the address signal is a signal indicating the address of a specific memory cell selected from among the plurality of memory cells M111, M112,. The row address signal is a signal indicating a row address among the addresses indicated by the address signal, and the column address signal is a signal indicating a column address among the addresses indicated by the address signal.

  In the information write cycle, the control circuit 110 outputs a write signal instructing application of a write voltage to the write circuit 105 in accordance with the input data Din input to the data input / output circuit 107. On the other hand, in the information read cycle, the control circuit 110 outputs a read signal instructing application of the read voltage to the column selection circuit 104.

  The row selection circuit / driver 103 receives the row address signal output from the address input circuit 109, selects one of the plurality of word lines WL0, WL1, WL2,... According to the row address signal, A predetermined voltage is applied to the selected word line to turn on a transistor connected to the selected word line.

  The column selection circuit 104 receives the column address signal output from the address input circuit 109, selects one of the plurality of bit lines BL0, BL1, BL2,... According to the column address signal, A write voltage or a read voltage is applied between the selected bit line and the corresponding plate line.

  When the write circuit 105 receives the write signal output from the control circuit 110, the write circuit 105 outputs a signal instructing the column selection circuit 104 to apply the write voltage to the selected bit line.

  Further, the sense amplifier 106 detects the amount of current flowing through the selected bit line to be read in the information read cycle, and determines that the data is “1” or “0”. The output data DO obtained as a result is output to an external circuit via the data input / output circuit 107.

  By operating as described above, the nonvolatile memory device 100 realizes reading and writing with respect to a nonvolatile memory element to be described later.

[Configuration of Nonvolatile Memory Element]
FIG. 2 is a cross-sectional view showing an example of the configuration of the nonvolatile memory element according to Embodiment 1 of the present invention. As shown in FIG. 2, the nonvolatile memory element 10A of the present embodiment is formed between an upper wiring 20 (for example, aluminum (Al) wiring) and a lower wiring 11 (for example, Al wiring). The nonvolatile memory element 10A includes a first electrode 17 (for example, made of tantalum nitride (TaN)) connected to the upper wiring 20 through the contact plug 19, a second electrode 13 connected to the lower wiring 11, And a resistance change layer 14 sandwiched between these electrodes. The contact plug 19 here functions as a contact plug for electrically connecting the upper wiring 20 and the first electrode 17. Similarly, the second electrode 13 functions as a contact plug for electrical connection with the lower wiring 11. The same applies to contact plugs and second electrodes described in the second and subsequent embodiments.

The resistance change layer 14 includes a transition metal oxide layer 16a composed of a first oxygen-deficient transition metal oxide and a transition metal oxide layer 15a composed of a second oxygen-deficient transition metal oxide. It is composed of a laminated structure. Here, the first transition metal is M, the second transition metal is N, the composition of the transition metal oxide of the first oxygen-deficient transition metal oxide layer 16a located on the upper side is MO _x , and the lower side Where the composition of the transition metal oxide of the second oxygen-deficient transition metal oxide layer 15a located at NO is NO _y , the NO with respect to the second transition metal N oxide in the stoichiometric state The oxygen deficiency rate of _y is smaller than the oxygen deficiency rate of MO _x with respect to the oxide of the first transition metal M in the stoichiometric state. For example, when the first transition metal is tantalum and the second transition metal is hafnium, the tantalum oxide in the stoichiometric state is Ta ₂ O ₅ , and the hafnium oxide in the stoichiometric state is HfO ₂ . Become. When the first oxygen-deficient transition metal oxide is TaO _x (x = 1.9) and the second oxygen-deficient transition metal oxide is HfO _y (y = 1.9), the first oxygen The oxygen deficiency rate of the deficient transition metal oxide (TaO _x ) is 24% (= 1-1.9 / 2.5), and the oxygen deficiency rate of the second oxygen deficient transition metal oxide (HfO _y ) Is 5% (= 1-1.9 / 2.0), and the oxygen deficiency rate of the second oxygen-deficient transition metal oxide (HfO _y ) is equal to the first oxygen-deficient transition metal oxide (TaO). _x ) less than the oxygen deficiency rate. In this way, the second electrode 13 can be obtained by making the oxygen deficiency rate of the second oxygen-deficient transition metal oxide layer 15a smaller than the oxygen deficiency rate of the first oxygen-deficient transition metal oxide layer 16a. It is possible to facilitate the phenomenon of resistance change due to oxidation / reduction at the interface with the. Therefore, a memory element that can be driven at a low voltage can be realized.

Hereinafter, the second oxygen-deficient transition metal oxide layer 15a that is a high oxygen concentration layer is referred to as a high resistance layer, and the first oxygen-deficient transition metal oxide layer 16a that is a low oxygen concentration layer is referred to as a low resistance layer. This is called a resistance layer. In the present embodiment, the high resistance layer 15a and the low resistance layer 16a are both made of tantalum (Ta) oxide, the composition of the low resistance layer 16a is TaO _x, and the composition of the high resistance layer 15a is TaO _y. In this case, adjustment is made so that x is 0.8 or more and 1.9 or less and y is 2.1 or more and less than 2.5. When x and y are in this range, a stable resistance changing operation can be realized.

The second electrode 13 is a columnar electrode composed of a stacked structure of contact plugs 13a and noble metal electrodes 13b, and is formed on a first interlayer insulating layer (SiO ₂ layer) 12 on a substrate (not shown). It is provided in the contact hole 21. In the specification of the present invention, the “columnar electrode” includes both those formed by dry etching after depositing an electrode layer and those formed by being buried in a contact hole. Here, the contact plug 13a is made of tungsten (W), for example, and the noble metal electrode 13b is made of iridium (Ir), platinum (Pt), or the like. The reason why the noble metal electrode 13b is formed on the contact plug 13a is that, as will be described later, when tantalum oxide is used as the resistance change layer 14, the resistance change occurs at the interface with the electrode made of tungsten. This is because the phenomenon hardly occurs and the resistance change phenomenon is good at the interface with the electrode made of iridium, platinum or the like (see the description of FIGS. 29 and 30 described below).

A high resistance layer 15a is formed on the noble metal electrode 13b included in the second electrode 13 so as to cover the electrode surface. That is, the outer shape of the high resistance layer 15a is formed larger than the outer shape of the noble metal electrode 13b. A contact plug 19 composed of a low resistance layer 16a, a first electrode 17 and tungsten is formed on the high resistance layer 15a. The high resistance layer 15 a, the low resistance layer 16 a, the first electrode 17, and the contact plug 19 are provided so as to be covered with a _second interlayer insulating layer (SiO ₂ layer) 18.

  As described above, in the present embodiment, the first electrode 17 is made of, for example, tantalum nitride (TaN), and the noble metal electrode 13b that forms the second electrode 13 is iridium (Ir), platinum (Pt), or the like. It consists of Here, the standard electrode potential V2 of iridium is 1.16 eV, and the standard electrode potential V1 of tantalum nitride is 0.48 eV. In general, the standard electrode potential is used as one index of the degree of oxidization, and if this value is large, it means that it is difficult to oxidize, and if it is small, it means that it is easily oxidized. The greater the difference in the standard electrode potential between the electrode and the resistance change layer, the more likely the resistance change to occur, and the resistance change does not easily occur as the difference decreases. Therefore, the ease of oxidation plays a major role in the mechanism of the resistance change phenomenon. It is estimated that Since the standard electrode potential Vt of tantalum is −0.6 eV, the relationship of Vt <V2 is satisfied. Therefore, an oxidation-reduction reaction occurs at the interface between the noble metal electrode 13b made of iridium and the high resistance layer 15a, and the resistance change The phenomenon appears. In addition, since the relationship of V2> V1 is satisfied, this oxidation-reduction reaction causes the noble metal electrode 13b made of iridium and the higher resistance than the interface between the first electrode 17 made of tantalum nitride and the low resistance layer 16a. It appears preferentially at the interface with the layer 15a. For this reason, the interface where the resistance change phenomenon appears can be fixed to one interface, and a malfunction due to the resistance change phenomenon occurring at the other interface can be prevented.

  As described above, since the second electrode 13 is a columnar electrode formed in the contact hole 21 of the first interlayer insulating layer 12, the area where the high resistance layer 15a and the second electrode 13 are in contact with each other is reduced. (The area of the second electrode is the same as the area of the resistance change layer). Therefore, an increase in current during the break in the initial break process can be avoided. Further, since the conduction region is formed not only in the entire region of the high resistance layer 15a but only in the region on the second electrode 13 in the high resistance layer 15a, low power consumption can be realized. In particular, when the initial break process is performed in a state where a load resistor such as a transistor is connected, it is effective because the voltage increase due to the current during the break can be suppressed.

  Furthermore, since the side portion of the resistance change layer 14 may be damaged by etching in the manufacturing process, there is a possibility that the element characteristics may be deteriorated. However, in the case of the present embodiment, as described above, in the high resistance layer 15a. A conductive region is formed only in the region on the second electrode 13, and no conductive region is formed on the side portion of the resistance change layer 14, so that it is not affected by etching damage and has a high yield and stable operation. Can be realized.

[Method of Manufacturing Nonvolatile Memory Element]
Next, a method for manufacturing the nonvolatile memory element 10A configured as described above will be described.

  3 to 5 are cross-sectional views showing manufacturing steps of the nonvolatile memory element 10A according to Embodiment 1 of the present invention. First, as shown in FIG. 3A, a lower wiring 11 (here, Al wiring) is formed on a substrate S such as a silicon substrate using a desired mask, and the entire surface of the substrate S including the lower wiring 11 is formed. Then, a first interlayer insulating layer 12 which is a silicon oxide film having a thickness of about 150 to 500 nm is formed.

  Next, as shown in FIG. 3B, a contact hole 21 having a diameter of about 50 to 100 nm that penetrates the first interlayer insulating layer 12 and is connected to the lower wiring 11 is formed by, for example, a dry etching method. Thereafter, as shown in FIG. 3C, a tungsten layer 13a is deposited by a chemical vapor deposition (CVD) method. As a result, the tungsten layer 13 a is embedded in the contact hole 21 of the first interlayer insulating layer 12. Further, an adhesion layer or a barrier layer may be formed under the tungsten layer (not shown).

  Then, as shown in FIG. 3D, planarization is performed by removing the tungsten layer 13a by CMP (Chemical Mechanical Polishing) until the first interlayer insulating layer 12 is exposed.

  Thereafter, as shown in FIG. 4A, the contact plug 13a in the contact hole 21 of the first interlayer insulating layer 12 is removed by etch back so that the thickness thereof becomes about 50 nm. Next, as shown in FIG. 4B, a noble metal layer 13b (here, an iridium layer) is buried and deposited in the contact hole 21. Next, as shown in FIG. As a result, the noble metal electrode 13b is formed on the contact plug 13a. Then, as shown in FIG. 4C, planarization is performed by removing the noble metal layer 13b until the first interlayer insulating layer 12 is exposed by etch back, and the noble metal electrode 13b is formed in the contact plug 13a. Form.

Next, as shown in FIG. 5A, a high resistance layer 15a (on the noble metal electrode 13b and the first interlayer insulating layer 12 is formed by a so-called reactive sputtering method in which a tantalum target is sputtered in argon gas and oxygen gas. Here, tantalum oxide (TaO _y ), 2.1 ≦ y <2.5) is formed. Further, a low resistance layer 16a (here, tantalum oxide (TaO _x ), 0.8 ≦ x ≦ 1.9) is formed on the high resistance layer 15a by an oxygen reactive sputtering method, and further the low resistance is formed. A first electrode 17 (here, a tantalum nitride layer) is formed on the layer 16a by a reactive sputtering method. At this time, the thickness of the high resistance layer 15a is 1 to 8 nm, the thickness of the low resistance layer 16a is 10 to 100 nm, and the thickness of the first electrode 17 is 20 to 100 nm.

  Next, as shown in FIG. 5B, the laminated structure of the high resistance layer 15a, the low resistance layer 16a, and the first electrode 17 is formed by batch etching by a dry etching method, and the noble metal electrode 13b and the first interlayer insulating layer are formed. 12 is formed. Here, this laminated structure is formed so as to cover the surface (electrode surface) of the noble metal electrode 13b. That is, the outer shape of the high resistance layer 15a is formed to be larger than the outer shape of the noble metal electrode 13b, and is formed so as to cover the entire surface (electrode surface) of the noble metal electrode 13b.

  Then, as shown in FIG. 5C, a second interlayer insulation which is a silicon oxide film having a thickness of about 300 to 500 nm so as to cover the laminated structure of the high resistance layer 15a, the low resistance layer 16a and the first electrode 17. A layer 18 is formed, and a contact hole 22 having a diameter of about 50 to 100 nm is formed by dry etching to penetrate the second interlayer insulating layer 18 and connect to the first electrode 17. Thereafter, a tungsten layer 19 (which constitutes a contact plug) 19 is buried and deposited in the contact hole 22 by CVD, and the tungsten layer 19 is removed by CMP until the second interlayer insulating layer 18 is exposed. Process.

  Finally, as shown in FIG. 5D, an upper wiring 20 that is an Al wiring is formed on the second interlayer insulating layer 18 including the contact plug 19 using a desired mask.

  As described above, in this embodiment, a favorable nonvolatile memory element can be obtained with a simple process.

[Variation of non-volatile memory element]
Hereinafter, modifications of the nonvolatile memory element of this embodiment will be described. Note that the non-volatile memory element of the following modified example excluding the modified example 3 is composed of only the contact plug 13a in which the second electrode is made of tungsten, unlike the non-volatile memory element 10A. It does not have a noble metal electrode. With the change of the configuration, the material of the resistance change layer 14 is different from that of the nonvolatile memory element 10A.

[Modification 1]
FIG. 6 is a cross-sectional view showing a configuration of Modification Example 1 of the nonvolatile memory element according to Embodiment 1 of the present invention. As shown in FIG. 6, the nonvolatile memory element 10 </ b> B of Modification 1 includes a resistance change layer configured by a stacked structure of a high resistance layer 15 b and a low resistance layer 16 b on a contact plug 13 a configured by tungsten. 14 is provided. In the first modification, the tungsten contact plug 13a functions as the second electrode.

Both the high resistance layer 15b and the low resistance layer 16b are made of hafnium (Hf) oxide. When the composition of the low resistance layer 16b is HfO _x and the composition of the high resistance layer 15b is HfO _y , x Is 0.9 or more and 1.6 or less, and y is adjusted to be larger than 1.8 and smaller than 2.0. When x and y are in this range, a stable resistance changing operation can be realized.

  In the case of using hafnium oxide for the high resistance layer 15b of the resistance change layer 14 as in the first modification, the resistance change occurs at the interface with the electrode made of tungsten. It is not necessary to form the noble metal electrode 13b such as iridium on the contact plug 13a as in the case where the high resistance layer is formed of tantalum oxide as in the embodiment described (see the description of FIG. 29 described later). The same applies to other embodiments and modifications described below.

  Since the other configuration of the nonvolatile memory element 10B of the first modification is the same as that of the nonvolatile memory element 10A of the present embodiment, the same reference numerals are given and description thereof is omitted.

  As described above, in the nonvolatile memory element 10B of the first modification, the second electrode is configured only by the tungsten contact plug 13a and does not include the noble metal that is a difficult-to-etch material. Therefore, there is an advantage that manufacturing is easy and fine processing is possible. Note that the reason why the second electrode can operate even if the second electrode is composed of only the tungsten contact plug 13a in the first modification will be described in the section [Material of resistance change layer and electrode] below.

  7 and 8 are cross-sectional views showing manufacturing steps of Modification Example 1 of the nonvolatile memory element according to Embodiment 1 of the present invention. As in the case of manufacturing the nonvolatile memory element 10A, first, as shown in FIG. 7A, the lower wiring 11 (here, Al wiring or the like) is formed on the substrate S, and the substrate S including the lower wiring 11 is formed. A first interlayer insulating layer 12 which is a silicon oxide film having a thickness of about 150 to 500 nm is formed on the entire surface. Next, as shown in FIG. 7B, a contact hole 21 having a diameter of about 50 to 100 nm that penetrates the first interlayer insulating layer 12 and is connected to the lower wiring 11 is formed. ), A tungsten layer 13a is buried and deposited by the CVD method. Then, as shown in FIG. 7D, planarization is performed by removing the tungsten layer 13a by CMP until the first interlayer insulating layer 12 is exposed. Further, an adhesion layer or a barrier layer may be formed under the tungsten layer (not shown).

Next, as shown in FIG. 8A, hafnium oxide (HfO _y , 1.8 <y <2.0) is formed on the contact plug 13a and the first interlayer insulating layer 12 by reactive sputtering. A high resistance layer 15b is formed, and further, a low resistance layer made of hafnium oxide (HfO _x , 0.9 ≦ x ≦ 1.6) is formed on the high resistance layer 15b by an oxygen reactive sputtering method. The resistance layer 16b is formed. Then, a tantalum nitride layer (first electrode) 17 is formed on the low resistance layer 16b by a reactive sputtering method. At this time, the thickness of the high resistance layer 15b is about 5 nm, the thickness of the low resistance layer 16b is about 30 nm, and the thickness of the first electrode 17 is about 50 nm.

  Next, as shown in FIG. 8B, a laminated structure of the high resistance layer 15b, the low resistance layer 16b, and the first electrode 17 so as to cover the surface (electrode surface) of the contact plug 13a by dry etching. Are formed on the contact plug 13 a and the first interlayer insulating layer 12. That is, the outer shape of the high resistance layer 15b is formed so as to be larger than the outer shape of the contact plug 13a, and is formed so as to cover the entire surface (electrode surface) of the contact plug 13b.

  Then, as shown in FIG. 8C, the second interlayer insulating film is a silicon oxide film having a thickness of about 300 to 500 nm so as to cover the laminated structure of the high resistance layer 15b, the low resistance layer 16b, and the first electrode 17. After the layer 18 is formed, a contact hole 22 having a diameter of about 50 to 100 nm is formed through the second interlayer insulating layer 18 and connected to the first electrode 17. Then, after a tungsten layer 19 is buried and deposited in the contact hole 22, the tungsten layer 19 is removed until the second interlayer insulating layer 18 is exposed, and a planarization process is performed to form a contact plug 19. Finally, as shown in FIG. 8D, an upper wiring 20 that is an Al wiring is formed on the second interlayer insulating layer 18 including the contact plug 19 using a desired mask.

  As described above, the nonvolatile memory element 10B of the first modification example can be more easily manufactured because it does not include a noble metal that is a difficult-to-etch material.

In the first modification, the high resistance layer 15b and the low resistance layer 16b are made of hafnium (Hf) oxide, but other materials may be used, for example, zirconium (Zr) oxide. May be. In that case, when the composition of the low resistance layer is expressed as HfO _x and the composition of the high resistance layer is expressed as ZrO _y , x is 0.9 or more and 1.6 or less, and y is larger than 1.9 and 2.0. It is adjusted to be less than. When x and y are in this range, a stable resistance changing operation can be realized.

[Modification 2]
FIG. 9 is a cross-sectional view showing a configuration of Modification Example 2 of the nonvolatile memory element according to Embodiment 1 of the present invention. As shown in FIG. 9, in the nonvolatile memory element 10C of the second modification, the resistance change layer 14 is provided on the contact plug 13a made of tungsten, similarly to the nonvolatile memory element 10B of the first modification. ing. However, the configuration of the resistance change layer 14 is different from that in the first modification.

The variable resistance layer 14 included in the nonvolatile memory element 10C of Modification 2 has a stacked structure of a high resistance layer 15b made of hafnium oxide and a low resistance layer 16a made of tantalum oxide. Here, when the composition of the low resistance layer 16a is TaO _x and the composition of the high resistance layer 15b is HfO _y , x is 0.8 or more and 1.9 or less, and y is larger than 1.8 and 2 It is adjusted to be less than 0.0. In this case, the oxygen deficiency rate of HfO _y is smaller than the oxygen deficiency rate of TaO _x , and stable resistance change operation can be realized when x and y are in the above-described range.

  Since the other configuration of the nonvolatile memory element 10C according to the second modification is the same as that of the nonvolatile memory element 10B according to the first modification, the same reference numerals are given and description thereof is omitted.

  As described above, in the nonvolatile memory element 10C of Modification 2 as well, in the case of Modification 1, the second electrode is configured only by the contact plug 13a and does not include the noble metal that is a difficult-to-etch material. There is an advantage that manufacturing is easy and fine processing is possible.

Instead of the configuration of the second modification, the transition metals constituting the high resistance layer and the low resistance layer may be reversed. That is, the resistance change layer 14 may have a laminated structure of a high resistance layer 15b made of tantalum oxide and a low resistance layer 16a made of hafnium oxide. Here, when the composition of the low resistance layer 16a is HfO _x and the composition of the high resistance layer 15b is TaO _y , x is 0.9 or more and 1.6 or less, and y is 2.1 or more and 2. A stable resistance change operation can be realized when x and y are adjusted to be less than 5 and x and y are within this range.

[Modifications 3 to 5]
The nonvolatile memory elements of Modifications 3 to 5 in the present embodiment are elements in which the first electrode and the resistance change layer are formed integrally with the upper wiring. When the first electrode, the resistance change layer, and the upper wiring are integrally formed as described above, a plurality of conduction regions can be easily formed by connecting the resistance change layer to the plurality of second electrodes. it can. Note that the nonvolatile memory elements of these modified examples 3 to 5 have configurations corresponding to the nonvolatile memory elements 10A to 10C described above, respectively.

  FIG. 10 is a cross-sectional view showing a configuration of Modification Example 3 of the nonvolatile memory element according to Embodiment 1 of the present invention. As shown in FIG. 10A, the nonvolatile memory element 10D of Modification 3 includes a resistance change layer 14 having a stacked structure of a high resistance layer 15a and a low resistance layer 16a, a first electrode 17, and an upper portion. The wiring 20 is integrally formed. FIG. 10B shows a cross-sectional view of a memory array including a plurality of such nonvolatile memory elements 10D of Modification 3 in a matrix. The plurality of nonvolatile memory elements 10D provided in the memory array operate individually because the conductive regions unique to each other are formed in the region of the high resistance layer 15a in the surface of each contact plug 13b. Is possible. As described above, by integrally forming the first electrode 17 and the resistance change layer 14 and the upper wiring 20, it is possible to achieve high integration of the memory element.

  FIG. 11 is a cross-sectional view showing the configuration of Modifications 4 and 5 of the nonvolatile memory element according to Embodiment 1 of the present invention, where (a) shows the configuration of Modification 4 and (b) shows Modification 5. Each of the configurations is shown. As shown in FIG. 11A, the nonvolatile memory element 10E of Modification 4 includes a resistance change layer 14 configured by a stacked structure (stacked hafnium oxide) of a high resistance layer 15b and a low resistance layer 16b, The first electrode 17 and the upper wiring 20 are integrally formed. As shown in FIG. 11B, the nonvolatile memory element 10F according to the modified example 5 has a stacked structure of a high resistance layer 15b and a low resistance layer 16a. The resistance change layer 14 configured by (lamination of hafnium oxide and tantalum oxide), the first electrode 17, and the upper wiring 20 are integrally formed.

  Similarly to the case of the modification 3, in the case of a memory array including a plurality of these modifications 4 and 5, the nonvolatile memory elements 10E and 10F can be individually operated, so that high integration can be achieved. it can.

[Material of variable resistance layer and electrode]
Next, what materials are suitable for the high resistance layer and the second electrode in the present embodiment will be examined.

  The inventors of the present invention sandwiched an oxygen-deficient hafnium oxide in the same manner as a first sample element formed by sandwiching an oxygen-deficient tantalum oxide between a lower electrode (first electrode) and an upper electrode (second electrode). The formed second sample element was produced. Here, the material of the first electrode was fixed to W (tungsten), and the material of the second electrode was changed to a plurality of types of materials shown in Tables 1 and 2. Table 1 shows the configuration of the first sample element, and Table 2 shows the configuration of the second sample element. The reason why the material of the first electrode is fixed to W is that W is relatively resistant to oxidation, is a stable material, and is relatively easy to process.

  The inventors examined the state of resistance change of the first and second sample elements. In the measurement of the resistance change in the first sample element shown in Table 1, although there are some differences in the sample, the voltage pulse for increasing the resistance is +1.8 to +2.5 V, 100 ns, and the resistance is decreased. The voltage pulse of −1.3V to −1.6V was set to 100 ns. In the case of the second sample element shown in Table 2, the voltage pulse when the resistance is increased is +1.6 to +1.9 V and 100 ns, and the voltage pulse when the resistance is decreased is −1.1 V to −1.3 V. 100 ns. The voltage is the voltage applied to the electrode on the high resistance layer side of the resistance change layer of each sample element when the electrode potential on the low resistance layer side of the resistance change layer of each sample element is taken as a reference (0 V). Show.

The above measurement results will be summarized below. FIG. 29 is a graph showing the correlation between the difference between the standard electrode potential of the transition metal constituting the oxygen-deficient transition metal oxide and the standard electrode potential of the electrode material, and the resistance change of the oxygen-deficient metal oxide. The graph of Figure 29, with respect to the difference between the standard electrode potential of the standard electrode potential of the transition metal constituting the oxygen-deficient transition metal oxide and (E _T) electrode material (E _E), oxygen deficient transition metal It is obtained by arranging a graph showing the state of resistance change of the oxide HfO _y or TaO _y (the vertical axis indicates the resistance value, and the horizontal axis indicates the number of application of the voltage pulse). Referring to the graph of FIG. 29, it can be confirmed that there is a good correlation between the resistance change in the difference and the oxygen-deficient metal oxide E _E and E _T. That is, when the electrode is made of a material whose standard electrode potential is larger than that of Ta and Hf which are transition metals constituting the resistance change layer, the resistance change occurs. On the other hand, when the electrode is made of a small material, It can be seen that resistance change is less likely to occur. As the difference between the standard electrode potential of the transition metal and the standard electrode potential of the electrode material is larger, the resistance change is more likely to occur, and on the contrary, the resistance change is less likely to occur (E _E −E _T ≦ 0 is satisfied). It can be seen that the element using the electrode material does not show a resistance change phenomenon.

  This agrees with the reasoning of the mechanism of resistance change described above. That is, as described above, since the resistance change is likely to occur when the transition metal contained in the variable resistance layer is easily oxidized, the transition metal includes a transition metal that is easily oxidized (small standard electrode potential) compared to the electrode material. It can be said that stable resistance change operation can be realized by using the oxide layer at the electrode side interface of the resistance change layer.

By the way, referring to the graph of FIG. 29, it can be seen that a stable resistance changing operation can be obtained if the value of E _E -E _T is increased by about 1 eV or more. Therefore, in the case of the present embodiment, it can be said that it is desirable to configure the high resistance layer and the second electrode by using a material that satisfies E _E− E _T ≧ 1 eV. 30 to 32 are graphs for explaining a combination of appropriate materials for the high resistance layer and the second electrode in the present embodiment. As shown in FIG. 30, as a material having a standard electrode potential 1 eV or more higher than that of circled tantalum (Ta), gold (Au), platinum (Pt), iridium (Ir) surrounded by a square , Palladium (Pd), silver (Ag), copper (Cu) and ruthenium (Ru). Although not shown in the drawing, the standard electrode potential of tantalum nitride (TaN) is 0.48 eV, which is 1 eV or more higher than tantalum. Therefore, in the case where the high resistance layer is made of an oxide of tantalum, such as the nonvolatile memory element 10A of the present embodiment shown in FIG. 2 and the nonvolatile memory element 10C of the modification 2 shown in FIG. It is desirable to employ Au, Pt, Ir, Pd, Ag, Cu, TaN or Ru as the material of the two electrodes.

  Similarly, in the case where the high resistance layer is composed of hafnium oxide, in addition to the above as the material of the second electrode, rhenium (Re), tungsten (W), molybdenum (Mo), nickel (Ni), or iron (Fe ) Can be adopted.

  As shown in FIG. 31, tantalum (Ta), niobium (Nb), zirconium (Zr), hafnium (Hf) are materials whose standard electrode potential is 1 eV or more smaller than that of copper (Cu) surrounded by a circle. ), Titanium (Ti), and aluminum (Al). Therefore, when the second electrode is made of Cu, it is desirable to use Ta, Nb, Zr, Hf, Ti, or Al as the metal material constituting the metal oxide that becomes the high resistance layer. In other words, when Ta, Nb, Zr, Hf, Ti, or Al is used as the metal material constituting the metal oxide that becomes the high resistance layer, the first electrode is made of a material having a standard electrode potential higher than that of these materials by 1 eV or more. Two electrodes may be configured, and as the second electrode material, any one of Cu, Ag, Pd, Ir, Pt, Au, or an alloy thereof can be used.

  Furthermore, as shown in FIG. 32, materials whose standard electrode potential is 1 eV or more smaller than that of tungsten (W) surrounded by circles are niobium (Nb), zirconium (Zr), hafnium (Hf), titanium (Ti And aluminum (Al). Therefore, in the case where the second electrode is composed only of a contact plug composed of W, such as the nonvolatile memory element 10B of the third modification shown in FIG. 6, the metal constituting the metal oxide that becomes the high resistance layer It is desirable to employ Nb, Zr, Hf, Ti or Al as the material.

  In other words, when Nb, Zr, Hf, Ti, or Al is used as the metal material constituting the metal oxide to be the high resistance layer, the second electrode is made of a material having a standard electrode potential of 1 eV or higher than these materials. Any of W, Re, TaN, Ru, Cu, Ag, Pd, Ir, Pt, Au, or an alloy thereof can be used as the second electrode material.

(Embodiment 2)
The variable resistance nonvolatile memory element according to the second embodiment is a so-called cross point in which a nonvolatile memory part is interposed at an intersection (three-dimensional intersection) between a word line and a bit line arranged so as to be orthogonal (cross) each other. Element provided in a nonvolatile memory device of the type. First, the configuration of the cross-point type nonvolatile memory device will be described.

[Configuration of non-volatile storage device]
FIG. 12 is a block diagram showing a configuration of the nonvolatile memory device according to Embodiment 2 of the present invention. FIG. 13 is a perspective view showing the configuration (configuration corresponding to 4 bits) of part A in FIG.

  As shown in FIG. 12, the nonvolatile memory device 200 according to the present embodiment includes a memory main body 201 on a semiconductor substrate. The memory main body 201 includes a memory array 202 and a row selection circuit / driver. 203, a column selection circuit / driver 204, a writing circuit 205 for writing information, a sense amplifier 206 for detecting the amount of current flowing through the selected bit line and determining data “1” or “0” And a data input / output circuit 207 for performing input / output processing of input / output data via a terminal DQ.

  The nonvolatile memory device 200 further includes an address input circuit 208 that receives an address signal input from the outside, and a control circuit 209 that controls the operation of the memory body 201 based on the control signal input from the outside. I have.

  As shown in FIGS. 12 and 13, the memory array 202 includes a plurality of word lines WL0, WL1, WL2,... Formed in parallel to each other on a semiconductor substrate, and these word lines WL0, WL1, WL2,. A plurality of bit lines BL0, BL1, BL2,... Formed above and parallel to each other in a plane parallel to the main surface of the semiconductor substrate and three-dimensionally intersecting the plurality of word lines WL0, WL1, WL2,. And.

  Further, a plurality of memory cells M211, M212, M213, M221, M222, M223 provided in a matrix corresponding to the intersections of these word lines WL0, WL1, WL2,... And bit lines BL0, BL1, BL2,. , M231, M232, M123,... (Hereinafter referred to as “memory cells M211, M212,...”) Are provided.

  12, memory cells M211, M212,... Are denoted by reference numeral 30A in FIG. Details of the configuration of the memory cell (nonvolatile memory element) 30A will be described later.

  The address input circuit 208 receives an address signal from an external circuit (not shown), outputs a row address signal to the row selection circuit / driver 203 based on the address signal, and outputs a column address signal to the column selection circuit / driver 204. Output to. Here, the address signal is a signal indicating the address of a specific memory cell selected from among the plurality of memory cells M211, M212,. The row address signal is a signal indicating a row address among the addresses indicated by the address signal, and the column address signal is also a signal indicating a column address.

  In the information write cycle, the control circuit 209 outputs a write signal instructing application of a write voltage to the write circuit 205 in accordance with the input data Din input to the data input / output circuit 207. On the other hand, in the information read cycle, the control circuit 209 outputs a read signal for instructing a read operation to the column selection circuit / driver 204.

  The row selection circuit / driver 203 receives the row address signal output from the address input circuit 208, selects one of the plurality of word lines WL0, WL1, WL2,... According to the row address signal, A predetermined voltage is applied to the selected word line.

  Further, the column selection circuit / driver 204 receives the column address signal output from the address input circuit 208, and selects one of the plurality of bit lines BL0, BL1, BL2,... According to the column address signal. Then, a write voltage or a read voltage is applied to the selected bit line.

  When the write circuit 205 receives the write signal output from the control circuit 209, the write circuit 205 outputs a signal for instructing the row selection circuit / driver 203 to apply a voltage to the selected word line, and the column selection circuit / A signal instructing the driver 204 to apply a write voltage to the selected bit line is output.

  Further, the sense amplifier 206 detects the amount of current flowing through the selected bit line to be read in the information read cycle, and determines data “1” or “0”. The output data DO obtained as a result is output to an external circuit via the data input / output circuit 207.

  By operating as described above, the nonvolatile memory device 200 realizes reading and writing with respect to a nonvolatile memory element to be described later.

  Note that it is also possible to realize a nonvolatile memory device having a multilayer structure by stacking the memory arrays in the nonvolatile memory device according to the present embodiment shown in FIGS. 12 and 13 three-dimensionally. By providing the multi-layered memory array configured as described above, it is possible to realize an ultra-large capacity nonvolatile memory device.

[Configuration of Nonvolatile Memory Element]
FIG. 14 is a cross-sectional view showing an example of the configuration of the nonvolatile memory element according to Embodiment 2 of the present invention. Note that FIG. 14 shows a configuration in the B part of FIG. As shown in FIG. 14, the non-volatile memory element 30A of the second embodiment includes an upper wiring 42 (corresponding to the word line WL1 in FIG. 13, here composed of Al wiring or the like) and a lower wiring 31 (bits in FIG. 13). Corresponding to the line BL1, here also composed of Al wiring or the like). The nonvolatile memory element 30A includes a first electrode 37 (here, composed of tantalum nitride (TaN) or the like), a second electrode 33, and a resistance change layer 34 sandwiched between the two electrodes. .

As in the case of the first embodiment, the resistance change layer 34 is composed of the high resistance layer 35a made of the second oxygen-deficient transition metal oxide and the first oxygen-deficient transition metal oxide. A low-resistance layer 36a. When the first transition metal is M and the second transition metal is N, the composition of the transition metal oxide of the low resistance layer 36a is represented by MO _x , and the composition of the transition metal oxide of the high resistance layer 35a is NO _y It is represented by At this time, the oxygen shortage rate of the NO _y with respect to the oxide of the second transition metal N in the stoichiometric state is equal to the MO with respect to the oxide of the first transition metal M in the stoichiometric state. _It is smaller than the oxygen deficiency rate of _x . In the present embodiment, the high resistance layer 35a and the low resistance layer 36a are both made of tantalum (Ta) oxide, the composition of the low resistance layer 36a is TaO _x, and the composition of the high resistance layer 35a is TaO _y. In this case, adjustment is made so that x is 0.8 or more and 1.9 or less and y is 2.1 or more and less than 2.5.

A barrier layer 38 (here, composed of silicon nitride (SiN _z ) or the like) is formed on the first electrode 37, and a third electrode 39 (here, TaN or the like) is formed on the barrier layer 38. Structure) is formed. The third electrode 39 is connected to the upper wiring 42 via the contact plug 41. Here, the interface between the first electrode 37 and the third electrode 39 in the barrier layer 38 functions as a Schottky barrier. If the barrier layer 38 using silicon nitride (SiN _z), silicon this nitride (SiN _z) If the value of z is smaller in accordance with the nitrogen composition z is a semiconducting, if it is greater, the insulator behavior . In the case of having semiconductor characteristics, a larger current can be obtained than in the case of having insulating characteristics. For example, when the range of z of SiN _z is 0 <z ≦ 0.85, a current density of 10000 A / cm ² or more can be obtained. The first electrode 37 and the third electrode 39 may be any material whose interface functions as a Schottky barrier with respect to silicon nitride (SiN _z ). For example, α-tungsten (W) or titanium nitride (TiN) having a body-centered cubic (bcc) structure in addition to TaN that is stable against heat generated by a current flowing when the resistance change layer 34 changes its resistance. Can also be used. By using these refractory metals and their nitrides for the electrodes, stable operation is possible even when a large current flows. The first electrode 37 and the third electrode 39 do not need to be the same material, and may be different materials.

In the present embodiment, since the barrier layer 38 is composed of a semiconductor layer as described above, the stacked structure of the first electrode 37, the barrier layer 38, and the third electrode 39 is an MSM (metal / semiconductor / metal). Functions as a diode. The present invention is not limited to this, and the barrier layer 38 is formed of an insulator layer, and the laminated structure of the first electrode 37, the barrier layer 38, and the third electrode 39 is MIM (metal (/ Insulator / metal) may function as a diode. As the insulator in this case, SiO ₂ , Si ₃ N ₄ , Ta ₂ O ₅ or the like can be used.

The second electrode 33 is a columnar electrode composed of a stacked structure of contact plugs 33a and noble metal electrodes 33b, and is formed on a first interlayer insulating layer (SiO ₂ layer) 32 on a substrate (not shown). It is provided in the contact hole 46. In the second embodiment, as in the first embodiment, the contact plug 33a is made of tungsten (W) and the noble metal electrode 33b is made of iridium (Ir) or platinum (Pt).

  On the noble metal electrode 33b included in the second electrode 33, a high resistance layer 35a is formed so as to cover the electrode surface. That is, the outer shape of the high resistance layer 35a is formed larger than the outer shape of the noble metal electrode 33b. On the high resistance layer 35a, a low resistance layer 36a, a first electrode 37, a barrier layer 38, a third electrode 39, and a contact plug 41 made of tungsten are formed. A layer (SiO 2 layer) 40 is provided so as to be covered.

  As described above, the second electrode 33 is a columnar electrode formed in the contact hole 46 of the first interlayer insulating layer 32, and the high resistance layer 15 a is formed so as to cover the electrode surface of the second electrode 33. It is the structure formed. Therefore, the contact area between the barrier layer 38 and the first electrode 37 is larger than the contact area between the high resistance layer 35 a and the second electrode 33. With such a configuration, since the electrode area on the diode side increases, a large current can be realized, and a high driving force can be obtained. In addition, since the current density can be increased at the interface between the high resistance layer 35a and the second electrode 33 having a smaller contact area than the contact area between the barrier layer 38 and the first electrode 37, the resistance state is likely to change at the interface. Become. Therefore, the resistance state of the resistance change layer 34 can be reliably changed.

  In addition, as in the case of the first embodiment, it is possible to obtain an effect such as avoiding an increase in current during a break and realizing a high yield and a stable operation without being affected by etching damage.

[Method of Manufacturing Nonvolatile Memory Element]
Next, a method for manufacturing the nonvolatile memory element 30A configured as described above will be described.

  15 to 17 are cross-sectional views showing manufacturing steps of the nonvolatile memory element 30A according to Embodiment 2 of the present invention. As in the case of manufacturing the nonvolatile memory element 10A of the first embodiment, first, as shown in FIG. 15A, a lower wiring 31 that is an Al wiring is formed on a substrate S, and the lower wiring 31 is included. A first interlayer insulating layer 32 which is a silicon oxide film having a thickness of about 150 to 500 nm is formed on the entire surface of the substrate S. Next, as shown in FIG. 15B, a contact hole 46 having a diameter of about 50 to 100 nm is formed through the first interlayer insulating layer 32 and connected to the lower wiring 31. Further, as shown in FIG. ), A tungsten layer 33a is buried and deposited by the CVD method. Then, as shown in FIG. 15D, planarization is performed by removing the tungsten layer 33a by CMP until the first interlayer insulating layer 32 is exposed.

  Thereafter, as shown in FIG. 16A, the tungsten layer (composing a contact plug) 33a in the contact hole 46 of the first interlayer insulating layer 32 is removed by etch back so that the thickness thereof becomes about 50 nm. Next, as shown in FIG. 16B, an iridium layer is buried and deposited in the contact hole 46 to form a noble metal electrode 33b. As shown in FIG. A planarization process is performed by removing the noble metal electrode 33b until the interlayer insulating layer 32 is exposed.

Next, as shown in FIG. 17A, a high resistance layer 35a made of tantalum oxide (TaO _y ) is formed on the noble metal electrode 33b and the first interlayer insulating layer 32 by reactive sputtering. Further, a low resistance layer 36a made of tantalum oxide (TaO _x ) is formed on the high resistance layer 35a by an oxygen reactive sputtering method. Then, a tantalum nitride layer (first electrode) 37, a silicon nitride layer (barrier layer) 38, and a tantalum nitride layer (third electrode) 39 are formed in this order on the low resistance layer 36a by the reactive sputtering method. At this time, the thickness of the high resistance layer 35a is about 5 nm, the thickness of the low resistance layer 36a is about 30 nm, the thickness of the first electrode 37 is about 20 nm, the thickness of the barrier layer 38 is about 10 nm, and the thickness of the third electrode 39 is 20 nm. Degree.

  Next, as shown in FIG. 17B, a high resistance layer 35a, a low resistance layer 36a, a first electrode 37, and a barrier layer are formed so as to cover the surface (electrode surface) of the noble metal electrode 33b by dry etching. A laminated structure of 38 and the third electrode 39 is formed on the noble metal electrode 33 b and the first interlayer insulating layer 32. That is, the outer shape of the high resistance layer 35a is formed to be larger than the outer shape of the noble metal electrode 33b.

  Then, as shown in FIG. 17C, silicon having a thickness of about 300 to 500 nm so as to cover the laminated structure of the high resistance layer 35a, the low resistance layer 36a, the first electrode 37, the barrier layer 38, and the third electrode 39. After forming the second interlayer insulating layer 40 which is an oxide film, a contact hole 47 having a diameter of about 50 to 100 nm is formed through the second interlayer insulating layer 40 and connected to the third electrode 39. Then, after the tungsten layer 41 is buried and deposited in the contact hole 47, the planarization process is performed by removing the tungsten layer 41 until the second interlayer insulating layer 40 is exposed.

  Finally, as shown in FIG. 17D, an upper wiring 42 which is an Al wiring is formed on the second interlayer insulating layer 40 including the contact plug 41 using a desired mask.

  As described above, in this embodiment, a favorable nonvolatile memory element can be obtained with a simple process.

[Variation of non-volatile memory element]
Hereinafter, modifications of the nonvolatile memory element of this embodiment will be described. Note that the non-volatile memory elements of the following modified examples excluding the modified examples 8 and 11 are composed of only the contact plug 33a in which the second electrode is made of tungsten, unlike the non-volatile memory element 30A. And no precious metal electrode layer. With the change of the configuration, the material of the resistance change layer 34 is different from that of the nonvolatile memory element 30A.

[Modification 6]
FIG. 18 is a cross-sectional view showing a configuration of Modification 6 of the nonvolatile memory element according to Embodiment 2 of the present invention. As shown in FIG. 18, the nonvolatile memory element 30 </ b> B according to Modification 6 includes a variable resistance layer having a stacked structure of a high resistance layer 35 b and a low resistance layer 36 b on a contact plug 33 a made of tungsten. 34 is provided. In the sixth modification, the contact plug 33a functions as the second electrode.

Both the high resistance layer 35b and the low resistance layer 36b are made of hafnium (Hf) oxide. When the composition of the low resistance layer 36b is HfO _x and the composition of the high resistance layer 35b is HfO _y , x Is 0.9 or more and 1.6 or less, and y is adjusted to be larger than 1.8 and smaller than 2.0.

  The other configuration of the nonvolatile memory element 30B according to Modification 6 is the same as that of the nonvolatile memory element 30A according to the present embodiment, and thus the same reference numerals are given and description thereof is omitted.

  Thus, in the case of the nonvolatile memory element 30B of Modification 6, the second electrode is composed only of the contact plug 33a and does not include the noble metal that is a difficult-to-etch material, so that the manufacturing is facilitated and the fine processing is performed. There is a merit that becomes possible.

[Modification 7]
FIG. 19 is a cross-sectional view showing a configuration of Modification Example 7 of the nonvolatile memory element according to Embodiment 2 of the present invention. As illustrated in FIG. 19, the nonvolatile memory element 30 </ b> C according to Modification 7 has the resistance change layer 14 provided on the contact plug 33 a made of tungsten, similarly to the nonvolatile memory element 30 </ b> B according to Modification 6. ing. However, the configuration of the resistance change layer 34 is different from that in the sixth modification.

The variable resistance layer 34 included in the nonvolatile memory element 30C of Modification 7 has a stacked structure of a high resistance layer 35b made of hafnium oxide and a low resistance layer 36a made of tantalum oxide. Here, when the composition of the low resistance layer 36a is TaO _x and the composition of the high resistance layer 35b is HfO _y , x is 0.8 or more and 1.9 or less, and y is larger than 1.8 and 2 It is adjusted to be less than 0.0.

  Since the other configuration of the nonvolatile memory element 30C according to the modified example 7 is the same as that of the nonvolatile memory element 30B according to the modified example 6, the same reference numerals are given and description thereof is omitted.

  As described above, in the nonvolatile memory element 30C of the modified example 7 as well, in the same manner as in the modified example 6, the second electrode is configured only by the contact plug 33a and does not include the noble metal that is a difficult-to-etch material. There is an advantage that manufacturing is easy and fine processing is possible.

[Modifications 8 to 10]
In the nonvolatile memory elements of Modifications 8 to 10 in the present embodiment, the first electrode and the resistance change layer are formed integrally with the upper wiring, as in Modifications 3 to 5 of Embodiment 1. It is an element. Note that the nonvolatile memory elements of these modified examples 8 to 10 have configurations corresponding to the nonvolatile memory elements 30A to 30C described above, respectively.

  FIG. 20 is a cross-sectional view showing a configuration of modified examples 8 to 10 of the nonvolatile memory element according to Embodiment 2 of the present invention, and FIGS. 20 (a) to (c) show the configurations of modified examples 8 to 10, respectively. ing.

  As shown in FIG. 20A, the nonvolatile memory element 30D of Modification 8 includes a resistance change layer 34 configured by a stacked structure of a high resistance layer 35a and a low resistance layer 36a formed of tantalum oxide, The first electrode 37 and the upper wiring 42 are integrally formed.

Between the columnar second electrode 33 and the lower wiring 31, a stacked structure of a fourth electrode 43 made of tantalum nitride, a barrier layer 44, and a fifth electrode 45 made of tantalum nitride is disposed. Yes. In the case of the modification 8, this laminated structure functions as an MSM diode. It is to be noted that the columnar second electrode 33 configured by a laminated structure of a contact plug 33a configured by tungsten (W) and a noble metal electrode 33b configured by iridium (Ir), and configured by tantalum nitride (TaN). The laminated structure of the fourth electrode 43, the barrier layer 44 made of silicon nitride (SiN _x ), and the fifth electrode 45 made of tantalum nitride is obtained by processing these layers by dry etching after being stacked.

  The lower wiring 31 is formed in the first interlayer insulating layer 32a, and the fourth electrode 43, the barrier layer 44, the fifth electrode 45, and the second electrode 33 are formed in the second interlayer insulating layer 32b.

  As shown in FIG. 20B, the nonvolatile memory element 30E of Modification 9 includes a resistance change layer 34 configured by a stacked structure of a high resistance layer 35b and a low resistance layer 36b formed of hafnium oxide, The first electrode 37 and the upper wiring 42 are integrally formed. As shown in FIG. 20C, the nonvolatile memory element 30F of Modification 10 has a stacked structure of a high resistance layer 35b made of hafnium oxide and a low resistance layer 36a made of tantalum oxide. The variable resistance layer 34, the first electrode 37, and the upper wiring 42 that are configured are integrally formed. Also in these modified examples 9 and 10, as in the modified example 8, the fourth electrode 43, the barrier layer 44, and the fifth electrode 45 are stacked between the columnar second electrode 33 a and the lower wiring 31. A structure is provided, and this stacked structure functions as an MSM diode.

  Note that, in the nonvolatile memory elements 30D to 30F of the modified examples 8 to 10 as well, the barrier layer 44 may be formed of an insulator layer so as to function as an MIM diode, as described above. .

  Similarly to the third to fifth modifications of the first embodiment, each of the nonvolatile memory elements 30D to 30D is also provided in the memory array including a plurality of nonvolatile memory elements 30D to 30F of the eighth to tenth modifications of the present embodiment. Since 30F can be operated individually, high integration can be achieved.

  Next, a method for manufacturing the nonvolatile memory element 30E of Modification 9 will be described. FIG. 21 is a cross-sectional view showing a manufacturing process of the nonvolatile memory element 30E according to Modification 9 of Embodiment 2 of the present invention. First, as shown in FIG. 21A, a lower wiring 31 which is an Al wiring is formed on a substrate S, and a silicon oxide film having a thickness of about 150 to 500 nm is formed on the entire surface of the substrate S including the lower wiring 31. A first interlayer insulating layer 32a is formed. Here, a planarization process is performed by CMP.

  Next, as shown in FIG. 21B, a tantalum nitride layer (fourth electrode) 43, a silicon nitride layer (barrier layer) 44, and a tantalum nitride layer (fifth electrode) 45 are formed in this order by reactive sputtering. Further, a tungsten layer (second electrode) 33a is formed thereon by CVD. At this time, the thickness of the fourth electrode 43 is about 20 nm, the thickness of the barrier layer 44 is about 10 nm, the thickness of the fifth electrode 45 is about 20 nm, and the thickness of the second electrode 33a is about 50 nm.

  Next, as shown in FIG. 21C, a columnar structure composed of a stacked structure of the fourth electrode 43, the barrier layer 44, the fifth electrode 45, and the second electrode 33a is formed by a dry etching method on the lower wiring 31. Form on top.

  Then, as shown in FIG. 21D, a silicon oxide film having a thickness of about 300 to 500 nm is formed so as to cover the laminated structure of the fourth electrode 43, the barrier layer 44, the fifth electrode 45, and the second electrode 33a. The second interlayer insulating layer 32b is formed, and then the planarization process is performed by removing the second interlayer insulating layer 32b until the second electrode 33a is exposed.

Next, as shown in FIG. 21E, a high resistance layer 35b made of hafnium oxide (HfO _y ) is formed by reactive sputtering so as to cover the surface (electrode surface) of the second electrode 33a. Further, a low resistance layer 36b made of hafnium oxide (HfO _x ) is formed on the high resistance layer 35b by oxygen reactive sputtering. Then, a tantalum nitride layer (first electrode) 37 and an Al wiring (upper wiring) 42 are formed in this order on the low resistance layer 36b by a reactive sputtering method. At this time, the thickness of the high resistance layer 35b is about 5 nm, the thickness of the low resistance layer 36b is about 30 nm, and the thickness of the first electrode 37 is about 50 nm. Thereafter, the high resistance layer 35b, the low resistance layer 36b, the first electrode 37, and the upper wiring 42 are processed into a line shape by a dry etching method, whereby the nonvolatile memory element 10E of Modification 9 is obtained.

[Modifications 11 to 13]
The nonvolatile memory elements of Modifications 11 to 13 in the present embodiment have configurations corresponding to the nonvolatile memory elements 30D to 30F of Modifications 8 to 10, respectively, but the second electrode is an interlayer insulating layer. This is different from Modifications 8 to 10 in that it is formed in the contact hole.

  FIG. 22 is a cross-sectional view showing a configuration of Modification Examples 11 to 13 of the nonvolatile memory element according to Embodiment 2 of the present invention, and FIGS. Each is shown.

As shown in FIG. 22A, the second electrode 33 provided in the nonvolatile memory element 30G of the modification 11 includes a contact plug 33a (here, composed of tungsten) and a noble metal electrode 33b (here, composed of iridium or the like). It is comprised by the laminated structure of. The contact plug 33 a of the second electrode 33 is embedded in a contact hole 46 formed so as to penetrate the second interlayer insulating layer 32 b and connect to the fifth electrode 45. Then, on the noble metal electrode 33b, as in the case of the modified example 8 shown in FIG. 20A, a high resistance layer 35a made of tantalum oxide (TaO _y ) and tantalum oxide (TaO _x ). The variable resistance layer 34 configured by a laminated structure of the configured low resistance layer 36a, the first electrode 37, and the upper wiring 42 are integrally formed.

  Further, as shown in FIGS. 22B and 22C, the nonvolatile memory element 30H of the modification 12 and the nonvolatile memory element 30I of the modification 13 include a second electrode (contact plug) 33a made of tungsten. The contact plug 33a is embedded in a contact hole 46 formed so as to penetrate the second interlayer insulating layer 32b and connect to the fifth electrode 45. Then, on the contact plug 33a, as in the modified examples 9 and 10 shown in FIGS. 20B and 20C, respectively, a high resistance layer 35b made of hafnium oxide and hafnium oxide are used. The variable resistance layer 34 configured by a stacked structure of the configured low resistance layer 36b or 36a configured by tantalum oxide, the first electrode 37, and the upper wiring 42 are integrally formed.

  As described above, the nonvolatile memory elements 30G to 30I of the modified examples 11 to 13 have a configuration in which a diode is formed below the contact plug 33a. Similarly to the above-described modification examples 8 to 10, in the case of a memory array including a plurality of nonvolatile storage elements 30G to 30I of these modification examples 11 to 13, each nonvolatile storage element 30G to 30I is operated individually. Therefore, high integration can be achieved.

(Embodiment 3)
The third embodiment is an element provided in a cross-point type nonvolatile memory device, as in the second embodiment. The difference from the second embodiment is that a diode is arranged in a contact hole formed in the interlayer insulating layer.

[Configuration of Nonvolatile Memory Element]
FIG. 23 is a cross-sectional view showing an example of the configuration of the nonvolatile memory element according to Embodiment 3 of the present invention. As shown in FIG. 23, the nonvolatile memory element 50A is formed between the upper wiring 63 that is an Al wiring and the lower wiring 51 that is the Al wiring. The nonvolatile memory element 50A is sandwiched between a first electrode 60 made of tantalum nitride (TaN) connected to the upper wiring 63 via a contact plug 62, a second electrode 56, and both of these electrodes. And a resistance change layer 57. Among these, the second electrode 56 is provided in the first interlayer insulating layer 53, and the resistance change layer 57, the first electrode 60, and the contact plug 62 are provided in the second interlayer insulating layer 61.

As in the case of the first embodiment, the resistance change layer 57 is composed of the high resistance layer 58a made of the second oxygen-deficient transition metal oxide and the first oxygen-deficient transition metal oxide. A low-resistance layer 59a. When the first transition metal is M and the second transition metal is N, the composition of the transition metal oxide of the low resistance layer 59a is expressed by MO _x , and the composition of the transition metal oxide of the high resistance layer 58a is NO _y It is represented by At this time, the oxygen shortage rate of the NO _y with respect to the oxide of the second transition metal N in the stoichiometric state is equal to the MO with respect to the oxide of the first transition metal M in the stoichiometric state. _It is smaller than the oxygen deficiency rate of _x . In the present embodiment, both the high resistance layer 58a and the low resistance layer 59a are made of tantalum (Ta) oxide, the composition of the low resistance layer 59a is TaO _x, and the composition of the high resistance layer 58a is TaO _y. In this case, adjustment is made so that x is 0.8 or more and 1.9 or less and y is 2.1 or more and less than 2.5.

A fourth electrode 52 made of tantalum nitride is formed on the lower wiring 51, and a first interlayer insulating layer 53 is provided so as to cover the lower wiring 51 and the fourth electrode 52. A contact hole 64 connected to the fourth electrode 52 is formed in the first interlayer insulating layer 53, and a barrier layer 54 (here, composed of silicon nitride (SiN _z )) is formed in the contact hole 64. And a fifth electrode 55 (here composed of titanium nitride (TiN)), a contact plug 56a (here composed of tungsten (W)) and a noble metal electrode 56b (here composed of iridium (Ir), etc.). The 2nd electrode 56 comprised by these is provided. More specifically, the laminated structure of the barrier layer 54 and the fifth electrode 55 is formed at the bottom and the side wall of the contact hole 64 formed in the first interlayer insulating layer 53, and the contact formed with this laminated structure. A contact plug 56 a is provided inside the hole 64. A noble metal electrode 56b is disposed on the barrier layer 54, the fifth electrode 55, and the contact plug 56a. Here, the bottom of the barrier layer 54 is in contact with the fourth electrode 52. The noble metal electrode 56b is in contact with the high resistance layer 58a, and the electrode surface of the noble metal electrode 13b is covered with the high resistance layer 58a. In the present embodiment, the stacked structure of the region in contact with the barrier layer 54 in the fourth electrode 52, the barrier layer 54, and the fifth electrode 55 functions as an MSM diode.

  As described above, in the case of the present embodiment, since the barrier layer 54 and the fifth electrode 55 can be embedded in the contact hole 64 formed in the first interlayer insulating layer 53, the element can be miniaturized. it can.

[Variation of non-volatile memory element]
Hereinafter, modifications of the nonvolatile memory element of this embodiment will be described. Note that the non-volatile memory element of the following modified example excluding the modified example 16 is composed of only the contact plug 56a in which the second electrode is made of tungsten or the like, unlike the non-volatile memory element 50A. And no precious metal electrodes. As the configuration is changed, the material of the resistance change layer 57 is different from that of the nonvolatile memory element 50A.

[Modification 14]
FIG. 24 is a cross-sectional view showing a configuration of Modification 14 of the nonvolatile memory element according to Embodiment 3 of the present invention. As shown in FIG. 24, the nonvolatile memory element 50B of Modification 14 includes a variable resistance layer formed of a stacked structure of a high resistance layer 58b and a low resistance layer 59b on a contact plug 56a formed of tungsten. 57 is provided. In the case of the modification 14, this contact plug 56a functions as a second electrode.

Both the high resistance layer 58b and the low resistance layer 59b are made of hafnium (Hf) oxide. When the composition of the low resistance layer 59b is HfO _x and the composition of the high resistance layer 58b is HfO _y , x Is 0.9 or more and 1.6 or less, and y is adjusted to be larger than 1.8 and smaller than 2.0.

  Since the other configuration of the nonvolatile memory element 50B of the modification 14 is the same as that of the nonvolatile memory element 50A of the present embodiment, the same reference numerals are given and description thereof is omitted.

  Thus, in the case of the nonvolatile memory element 50B of the modified example 14, since the second electrode is composed only of the contact plug 56a and does not include the noble metal that is a difficult-to-etch material, the manufacturing is facilitated and the fine processing is performed. There is a merit that becomes possible.

  Next, a method for manufacturing the nonvolatile memory element 50B of Modification 14 will be described. 25 and 26 are cross-sectional views showing a manufacturing process for the nonvolatile memory element 50B according to Modification 14 of Embodiment 3 of the present invention. First, as shown in FIG. 25A, a lower wiring 51 (here composed of Al) and a fourth electrode (here composed of a tantalum nitride layer) 52 are formed on a substrate S, and these lower wiring 31 and A first interlayer insulating layer 53 that is a silicon oxide film having a thickness of about 150 to 500 nm is formed on the entire surface of the substrate S including the fourth electrode 52.

Next, as shown in FIG. 25B, a contact hole 64 having a diameter of about 50 to 100 nm is formed through the first interlayer insulating layer 53 and connected to the fourth electrode 52. Then, as shown in FIG. 25C, a silicon nitride layer (barrier layer) 54 (semiconductor film having a thickness of about 15 nm (within a range of 5 to 25 nm) is formed by atomic layer deposition (ALD) method. depositing a 0 <z ≦ 0.85) when expressed as SiN _z, is deposited further 10nm approximately titanium nitride layer having a thickness of (fifth electrode) 55. Thereafter, a tungsten layer 56a is buried and deposited in the contact hole 64 in which the barrier layer 54 and the fifth electrode 55 are formed by a CVD method. Next, as shown in FIG. 25D, planarization is performed by removing the tungsten layer 56a, the fifth electrode 55, and the barrier layer 54 by CMP until the first interlayer insulating layer 53 is exposed.

Next, as shown in FIG. 26A, a hafnium oxide (HfO) is formed on the first interlayer insulating layer 53 so as to cover the barrier layer 54, the fifth electrode 55, and the contact plug 56a by reactive sputtering. _y , 1.8 <y <2.0) is formed, and a hafnium oxide (HfO _x , 0...) is formed on the high resistance layer 58b by an oxygen reactive sputtering method. The low resistance layer 59b configured by 9 ≦ x ≦ 1.6) is formed. Further, the first electrode (here, composed of a tantalum nitride layer) 60 is formed on the low resistance layer 59b by a reactive sputtering method. At this time, the thickness of the high resistance layer 58b is about 5 nm, the thickness of the low resistance layer 59b is about 30 nm, and the thickness of the first electrode 37 is about 50 nm.

  Next, as shown in FIG. 26B, the high resistance layer 58b, the low resistance layer 59b, and the first electrode 60 are covered by a dry etching method so as to cover the barrier layer 54, the fifth electrode 55, and the contact plug 56a. Is formed on the first interlayer insulating layer 53. That is, the outer shape of the high resistance layer 58b is formed to be larger than the outer shapes of the barrier layer 54, the fifth electrode 55, and the contact plug 56a.

  Then, as shown in FIG. 26C, the second interlayer insulation which is a silicon oxide film having a thickness of about 300 to 500 nm so as to cover the laminated structure of the high resistance layer 58b, the low resistance layer 59b and the first electrode 60. After the layer 61 is formed, a contact hole 65 having a diameter of about 50 to 100 nm is formed through the second interlayer insulating layer 61 and connected to the first electrode 60. Then, after the tungsten layer 62 is buried and deposited in the contact hole 65, the planarization process is performed by removing the tungsten layer 62 until the second interlayer insulating layer 61 is exposed.

  Finally, as shown in FIG. 26D, an upper wiring 63 which is an Al wiring is formed on the second interlayer insulating layer 61 including the contact plug 62 by using a desired mask.

  As described above, in this embodiment, a favorable nonvolatile memory element can be obtained with a simple process.

[Modification 15]
FIG. 27 is a cross-sectional view showing a configuration of Modification 15 of the nonvolatile memory element according to Embodiment 3 of the present invention. As shown in FIG. 27, the nonvolatile memory element 50C of Modification 15 has a resistance change layer 57 provided on a contact plug 56a made of tungsten, like the nonvolatile memory element 50B of Modification 14. ing. However, the configuration of the resistance change layer 57 is different from that of the modification 14.

The variable resistance layer 57 included in the nonvolatile memory element 50C of Modification 15 has a stacked structure of a high resistance layer 58b made of hafnium oxide and a low resistance layer 59a made of tantalum oxide. Here, when the composition of the low resistance layer 59a is TaO _x and the composition of the high resistance layer 58b is HfO _y , x is 0.8 or more and 1.9 or less, and y is larger than 1.8 and 2 It is adjusted to be less than 0.0.

  Note that the other configuration of the nonvolatile memory element 50C according to the modification 15 is the same as that of the nonvolatile memory element 50B according to the modification 14, and thus the same reference numerals are given and description thereof is omitted.

  As described above, in the nonvolatile memory element 50C of the modified example 15 as well, in the same manner as in the modified example 14, the second electrode is configured only by the contact plug 56a and does not include the noble metal that is a difficult-to-etch material. There is an advantage that manufacturing is easy and fine processing is possible.

[Modifications 16 to 18]
In the nonvolatile memory elements of Modifications 16 to 18 in the present embodiment, the first electrode and the resistance change layer are formed integrally with the upper wiring, as in Modifications 3 to 5 of Embodiment 1. It is an element. Note that the nonvolatile memory elements of these modified examples 16 to 18 have configurations corresponding to the nonvolatile memory elements 50A to 50C described above, respectively.

  FIG. 28 is a cross-sectional view showing a configuration of Modification Examples 16 to 18 of the nonvolatile memory element according to Embodiment 3 of the present invention. FIGS. 28A to 28C are configurations of Modification Examples 16 to 18. Each is shown.

  As shown in FIG. 28A, in the nonvolatile memory element 50D of Modification 16, the resistance change layer 57 configured by a laminated structure (laminated tantalum oxide) of a high resistance layer 58a and a low resistance layer 59a; The first electrode 60 and the upper wiring 63 are integrally formed. As shown in FIG. 28B, in the nonvolatile memory element 50E of Modification 17, the resistance change layer configured by a stacked structure (stacked layer of hafnium oxide) of a high resistance layer 58b and a low resistance layer 59b. 57, the first electrode 60, and the upper wiring 63 are integrally formed. As shown in FIG. 28C, in the nonvolatile memory element 50F of Modification 18, a stacked structure of a high resistance layer 58b and a low resistance layer 59a (hafnium oxide as a high resistance layer and a low resistance layer as The variable resistance layer 57 composed of a tantalum oxide laminate), the first electrode 60, and the upper wiring 63 are integrally formed.

  Similarly to the modifications 3 to 5 of the first embodiment, each of the nonvolatile memory elements 50D to 50D is also provided in the case of a memory array including a plurality of nonvolatile memory elements 50D to 50F of the modifications 16 to 18 of the present embodiment. Since 50F can be operated individually, high integration can be achieved.

(Other embodiments)
In each of the above embodiments, Al is used as a material for the upper wiring and the lower wiring, but tungsten (W), platinum (Pt), copper (Cu), or the like may be used instead.

  In the above-described embodiment, the resistance change layer only needs to contain a metal oxide that exhibits resistance change as the main resistance change material. Therefore, a trace amount of other elements other than the metal oxide may be included in the resistance change layer. For example, a small amount of other elements can be intentionally included in the resistance change layer for fine adjustment of the resistance value. If nitrogen is added to the resistance change layer, the resistance value of the resistance change layer increases and the reactivity of resistance change can be improved. In addition, when the variable resistance layer is formed by sputtering, an unintended trace element may be mixed into the variable resistance layer due to residual gas or outgassing from the vacuum vessel wall. Thus, it is a matter of course that the case where a trace amount of elements is mixed in the resistance change layer is also included in the scope of the present invention.

  It goes without saying that various modifications are possible by appropriately combining the above-described embodiments.

  The variable resistance nonvolatile element of the present invention is useful as a nonvolatile memory element used in various electronic devices such as a personal computer or a mobile phone.

10A to 10F, 30A to 30I, 50A to 50F Nonvolatile memory element 11, 31, 51 Lower wiring 12, 32, 32a, 53 First interlayer insulating layer 13, 33, 56 Second electrode 13a, 33a, 56a Contact plug 13b, 33b, 56b Noble metal electrode 14, 34, 57 Resistance change layer 15a, 15b, 35a, 35b, 58a, 58b High resistance layer (transition metal oxide layer)
16a, 16a, 36a, 36b, 59a, 59b Low resistance layer (transition metal oxide layer)
17, 37, 60 First electrode 18, 32b, 40, 61 Second interlayer insulating layer 19, 41, 62 Contact plug 20, 42, 63 Upper wiring 38, 44, 54 Barrier layer 39 Third electrode 43, 52 First 4 electrodes 45, 55 5th electrode 100 Non-volatile memory device 101 Memory body portion 102 Memory array 103 Row selection circuit / driver 104 Column selection circuit 105 Write circuit 106 Sense amplifier 107 Data input / output circuit 108 Cell plate power supply (VCP power supply)
DESCRIPTION OF SYMBOLS 109 Address input circuit 110 Control circuit M111, M112 Memory cell BL0, BL1 Bit line WL0, WL1 Word line PL0, PL1 Plate line T11, T12 Transistor 200 Non-volatile memory device 201 Memory main body 202 Memory array 203 Row selection circuit / driver 204 Column selection circuit / driver 205 Write circuit 206 Sense amplifier 207 Data input / output circuit 208 Address input circuit 209 Control circuit M211 and M212 Memory cell

Claims (19)

A first electrode;
An interlayer insulating layer formed on the substrate;
A columnar second electrode formed inside the interlayer insulating layer;
A resistance change layer interposed between the first electrode and the second electrode and having a resistance value reversibly changed based on electrical signals having different polarities applied between the first electrode and the second electrode; With
The variable resistance layer has a first transition metal M and a second transition metal N,
A first region containing a first oxygen-deficient transition metal oxide having a composition represented by MO _x and a second oxygen-deficient transition metal oxide having a composition represented by NO _y A second region,
The oxygen-deficient rate of the NO _y with respect to the oxide of the second transition metal N that is in the stoichiometric state indicates that the oxygen of the MO _x with respect to the oxide of the first transition metal M that is in the stoichiometric state Smaller than the deficiency rate,
The variable resistance nonvolatile memory element, wherein the second region and the second electrode are in contact with each other, and the second region has a larger area than the electrode surface of the second electrode.   The variable resistance nonvolatile memory element according to claim 1, wherein the first transition metal M and the second transition metal N are the same transition metal.   The variable resistance nonvolatile memory element according to claim 1, further comprising a load element electrically connected to the variable resistance layer.   The variable resistance nonvolatile memory element according to claim 3, wherein the load element is a transistor.   4. The variable resistance nonvolatile memory according to claim 3, wherein the load element is a diode having a stacked structure of a semiconductor layer or insulator layer and two metal electrode layers sandwiching the semiconductor layer or insulator layer from both sides. element.   The first electrode functions as the metal electrode layer located on the resistance change layer side, and a contact area between the semiconductor layer or the insulator layer and the first electrode is the second region and the second electrode. The variable resistance nonvolatile memory element according to claim 5, wherein the variable resistance nonvolatile memory element is larger than a contact area of the resistance variable nonvolatile memory element.   The variable resistance nonvolatile memory element according to claim 5, wherein the diode is formed inside the interlayer insulating layer.   6. The variable resistance nonvolatile memory according to claim 5, wherein the metal electrode layer and the semiconductor layer or insulator layer located on the variable resistance layer side are formed in a hole formed in the interlayer insulating layer. element.   The variable resistance nonvolatile memory element according to claim 5, wherein the first electrode and the variable resistance layer are formed integrally with a wiring that supplies an electrical signal to the first electrode.   The variable resistance nonvolatile memory element according to claim 9, wherein the diode is formed between the second electrode and a wiring that supplies an electric signal to the second electrode. The variable resistance layer includes a first region containing a first oxygen-deficient tantalum oxide having a composition represented by TaO _x (0.8 ≦ x ≦ 1.9), TaO _y ( However, the second region containing a second oxygen-deficient tantalum oxide having a composition represented by 2.1 ≦ y <2.5). The variable resistance nonvolatile memory element according to claim 1. The variable resistance layer includes a first region containing a first oxygen-deficient hafnium oxide having a composition represented by HfO _x (where 0.9 ≦ x ≦ 1.6), and HfO _y ( Provided that the second region containing the second oxygen-deficient hafnium oxide having a composition represented by 1.8 <y <2.0). The variable resistance nonvolatile memory element according to claim 1. The variable resistance layer includes a first region containing a first oxygen-deficient zirconium oxide having a composition represented by ZrO _x (where 0.9 ≦ x ≦ 1.4), and ZrO _y ( However, the second region containing the second oxygen-deficient zirconium oxide having a composition represented by 1.9 <y <2.0). The variable resistance nonvolatile memory element according to claim 1. The variable resistance layer includes the first region containing an oxygen-deficient tantalum oxide having a composition represented by TaO _x (where 0.8 ≦ x ≦ 1.9), HfO _y (where 1 And the second region containing the oxygen-deficient hafnium oxide having a composition represented by .8 <y <2.0). Type nonvolatile memory element. An upper wiring for supplying an electrical signal to the first electrode;
A lower wiring for supplying an electrical signal to the second electrode;
Further comprising
The variable resistance nonvolatile memory element according to claim 1, wherein the second electrode is a contact plug for electrically connecting to the lower wiring.   The contact plug is made of any one of copper, silver, palladium, iridium, platinum, and gold, and the second region includes an oxide of tantalum, niobium, zirconium, hafnium, or titanium. The variable resistance nonvolatile memory element described.   The contact plug is made of tungsten, rhenium, ruthenium, copper, silver, palladium, iridium, platinum, or gold, and the second region includes an oxide of niobium, zirconium, hafnium, or titanium. The variable resistance nonvolatile memory element according to claim 15.   The variable resistance nonvolatile memory element according to claim 16, wherein the first region contains an oxide of tantalum or hafnium.   The resistance according to claim 1, wherein the first electrode and the resistance change layer are formed integrally with a wiring that supplies an electrical signal to the first electrode. Changeable nonvolatile memory element.

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