JP2012227275A - Resistive nonvolatile memory cell, and resistive nonvolatile memory device - Google Patents

Abstract

A variable resistance nonvolatile memory cell and a variable resistance nonvolatile memory device in which a current control element is not easily destroyed.
A resistance change element that reversibly transitions between a plurality of resistance states having different resistance values by applying electrical signals having different polarities, and a predetermined application that is connected in series to the resistance change element. In the voltage range, as the absolute value of the applied voltage increases, the slope of the voltage-current curve increases, and the current control element 104 having nonlinear voltage-current characteristics and the inside of the hole penetrating the interlayer insulating layers 108, 109, 110 And plugs 105, 106, 107 that are formed and are in contact with at least one of the resistance change element 103 or the current control element 104 and have load resistance portions 131A, 131B, 131C.
[Selection] Figure 1

Description

  The present invention relates to a variable resistance nonvolatile memory cell and a variable resistance nonvolatile memory device. More specifically, the present invention relates to a variable resistance nonvolatile memory cell including a variable resistance element and a current control element, and a variable resistance nonvolatile memory device.

  In recent years, with the advancement of digital technology, electronic devices such as portable information devices and information home appliances have become more sophisticated. As these electronic devices have higher functions, the semiconductor elements used have been rapidly miniaturized and increased in speed. Among them, the use of a large-capacity nonvolatile memory represented by a flash memory is rapidly expanding. Further, as a next-generation nonvolatile memory device that replaces the flash memory, research and development of a nonvolatile memory device including a so-called variable resistance element is progressing. Here, the resistance change element is an element that has a property that the resistance value reversibly changes by an electrical signal and can store information in a nonvolatile manner by associating the resistance value with information. Say. A nonvolatile memory device in which the variable resistance elements are arranged in an array has been proposed, and large-scale, high integration, and high speed are expected.

  As disclosed in Patent Document 1, typically, a resistance change element has a structure in which a resistance change layer made of a resistance change material is sandwiched between a pair of electrodes, and a difference in electrical characteristics between the resistance change elements. Based on the above, it is roughly divided into a bipolar type and a unipolar type.

A bipolar resistance change element is an electrical signal specified by voltages of different polarities (or predetermined voltages and pulse widths) in order to transition between a plurality of resistance states including a high resistance state and a low resistance state. ). On the other hand, a unipolar variable resistance element is a type of element that uses a voltage of the same polarity (or an electrical signal specified by a predetermined voltage and a pulse width) in order to transition between a plurality of resistance states. It is. A unipolar variable resistance element is typically configured using a single transition metal oxide such as nickel oxide (NiO _x ) or titanium oxide (TiO _x ) as a variable resistance material.

Of the two types of variable resistance elements described above, the unipolar variable resistance elements have the following problems. In the case of a unipolar variable resistance element using a transition metal oxide such as NiO _x, as disclosed in Patent Document 2, the variable resistance material is changed from a high resistance state to a low resistance state by a short electric pulse. be able to. However, in order to change from the low resistance state to the high resistance state, a long pulse with a pulse width of the order of microseconds is required, and it is difficult to increase the operation speed.

  The resistance change element has a high resistance value immediately after forming a structure in which the resistance change layer is sandwiched between the upper and lower electrodes, and there is no current path, and a voltage for resistance change operation (steady resistance change) is applied. However, the resistance value does not change. In the operation of the variable resistance element, an initial breakdown process similar to a dielectric breakdown of an insulator is required to form a current path that causes a steady resistance change. The unipolar variable resistance element has a demerit that it is necessary to apply a voltage (5 V or more and 10 V or less) higher than the voltage used for the resistance change operation to the element in the initial break process.

  On the other hand, as disclosed in Patent Document 3, a bipolar resistor having a resistance change layer composed of a stacked structure of a high resistance layer (high oxygen concentration layer) and a low resistance layer (low oxygen concentration layer). In the case of a change element, stable high-speed driving can be realized at a low voltage. In addition, the thickness of the high resistance layer is as small as about 5 nm, and there is an advantage that the voltage required for the initial break process is lower than that in the case of the unipolar variable resistance element.

  In a nonvolatile memory device in which these variable resistance elements are arranged in an array, generally, a current control element such as a transistor or a rectifying element is connected in series with the variable resistance element. With this configuration, a write disturb due to a bypass current and crosstalk between adjacent memory cells are prevented, and a reliable memory operation is realized.

  In Patent Document 4, when a voltage whose absolute value exceeds a certain value is applied to both ends, a current flows in both directions according to the voltage polarity, and a predetermined minute current is applied when the absolute value of the applied voltage is equal to or less than the certain value. Disclosed is a two-terminal device having switching characteristics that do not allow a larger current to flow.

  Patent Document 5 discloses a bidirectional Schottky diode having a metal / semiconductor / metal back-to-back structure.

International Publication No. 2007/013174 JP 2010-218615 A International Publication No. 2008/149484 JP 2006-203098 A JP 2007-158325 A

  When a nonvolatile memory cell is configured by connecting a bipolar variable resistance element and a current control element in series, there is a problem that the current control element is easily destroyed at the initial break.

  The present invention solves the above problems, and an object thereof is to provide a variable resistance nonvolatile memory cell and a variable resistance nonvolatile memory device in which a current control element is not easily destroyed.

  There is a bidirectional (bipolar) current control element (hereinafter also referred to as “bidirectional current control element”) in which the resistance value is high while the applied voltage is low and the resistance value decreases rapidly as the applied voltage increases. Are known. As a bidirectional current control element, for example, an MIM diode (Metal-Insulator-Metal; metal-insulator-metal), an MSM diode (Metal-Semiconductor-Metal; metal-semiconductor-metal), and a varistor are known. .

  When a memory cell is configured by connecting a bidirectional current control element as a current control element in series to a resistance change element, bidirectional rectification characteristics (the absolute value of the voltage applied to the memory cell is low regardless of the polarity of the voltage) In such a case, it is possible to realize a non-volatile memory device that performs a bipolar operation with a characteristic that almost no current flows and a sufficient current flows when the applied voltage is high.

  FIG. 19 is a diagram illustrating voltage-current characteristics of a general bidirectional current control element. Hereinafter, the characteristics of the bidirectional current control element and the required performance will be described with reference to FIG.

  The bidirectional current control element exhibits non-linear voltage-current characteristics. For example, the voltage-current characteristics may be substantially symmetric with respect to the origin 0 by optimizing the electrode material and the material sandwiched between the electrodes. it can. That is, the relationship between the applied voltage and current when the applied voltage is positive and the change between the applied voltage and current when the applied voltage is negative are substantially point-symmetric with respect to the origin 0. A bidirectional current control element can be realized.

  In the bidirectional current control element, the applied voltage is not more than the first voltage (the lower limit voltage of the range A in FIG. 19) and not less than the second voltage (the upper limit voltage of the range B in FIG. 19) (that is, in FIG. 19). In the range C (when the absolute value of the voltage applied to the memory cell is low), the electric resistance is very high, and when the voltage exceeds the first voltage or falls below the second voltage, the electric resistance rapidly decreases. That is, the bidirectional current control element hardly flows current when the applied voltage is equal to or higher than the second voltage and equal to or lower than the first voltage, and becomes large when the applied voltage exceeds the first voltage or becomes lower than the second voltage. It has a non-linear voltage-current characteristic (bidirectional rectification characteristic) that allows current to flow.

  Therefore, by configuring the memory cell by connecting the bidirectional current control element in series with the variable resistance element, a high-speed cross-point type nonvolatile memory device that performs a bipolar operation can be realized.

  However, in the variable resistance nonvolatile memory cell and the variable resistance nonvolatile memory device in which the bidirectional current control element is connected in series with the variable resistance element, the present inventors have determined that in the initial break process of the variable resistance element, the bidirectional It was discovered that the current control element is easily destroyed.

  In the initial breaking process, a current path (hereinafter also referred to as a filament) is formed in the high resistance layer, so that a voltage or current larger than the drive voltage or drive current applied to the resistance change element is applied to the resistance change element. To do. After the initial break, a current path is formed in the high-resistance layer, thereby conducting, and the resistance rapidly decreases.

  In a cross-point structure in which a resistance change element and a current control element are connected in series, the resistance value of the resistance change element suddenly drops during the initial break, and the voltage applied to the resistance change element is divided into current control elements. Is done. When the voltage divided to the current control element at the time of the initial break exceeds the rated voltage (breakdown voltage) of the current control element, the risk that the current control element is destroyed increases.

  FIG. 20 is a circuit diagram of a single variable resistance element, a single current limiting element (referred to as a bidirectional current control element, hereinafter the same), one resistance variable element and one current limiting element connected in series. It is a figure which shows a current-voltage characteristic.

The experimental conditions in FIG. 20 are as follows. As a single resistance change element, a lower electrode (TaN, film thickness 30 nm, size 0.5 μm × 0.5 μm) and an upper electrode (material Ir, film thickness 50 nm, size 0.5 μm × 0.5 μm), Resistance change layer (material TaO _x , x = 1.5, film thickness 45 nm, size 0.5 μm × 0.5 μm low resistance layer, material TaO _y formed thereon, y = 2.5, film A structure sandwiching a high-resistance layer having a thickness of 5 nm and a size of 0.5 μm × 0.5 μm was used. As a single current control element, a lower electrode (material TaN, film thickness 30 nm, size 0.5 μm × 0.5 μm) and an upper electrode (material TaN, film thickness 50 nm, size 0.5 μm × 0.5 μm) A structure in which a semiconductor layer (material SiN _z , z = 0.3, film thickness 20 nm, size 0.5 μm × 0.5 μm) is sandwiched is used. In addition, as a circuit in which one variable resistance element and one current limiting element are connected in series, an element configured in the same manner as the single variable resistance element and the single current control element described above is used as a W-type plug. (Connected with W after forming a laminated barrier layer of Ti (film thickness 12 nm) and TiN (film thickness 10 nm) in a hole having a diameter of 260 nmφ). With respect to the above three types of elements and circuits, the applied voltage was gradually increased in a predetermined step, and the current value was measured.

  As shown in FIG. 20, the voltage applied to the resistance change element when the initial break of the resistance change element alone occurred was 1.66 V, and the current was 100 μA. The voltage applied to the current control element at the time of breakdown (insulation failure) of the current control element alone was 3.25 V, and the current was 204 μA. In a circuit in which a resistance change element and a current control element are connected in series, when the voltage applied to the entire circuit reaches 4.65 V and the current flowing through the circuit reaches 88 μA, an initial break of the resistance change element occurs. At the same time, the current control element was broken (insulation failure). It is thought that the resistance of the variable resistance element suddenly decreases simultaneously with the break of the variable resistance element, the voltage distributed to the current control element increases rapidly, and the current control element is destroyed.

  If the current control element becomes defective during the initial break, the leakage current flowing through the unselected memory cells cannot be controlled in the cross-point memory device.

  In addition, when data is written to or read from the variable resistance element, the selected memory cell uses the range A or B (bidirectional diode ON state) in FIG. 19 and at the same time is not selected. For the above, it is necessary to suppress the leakage current (OFF current) using the range C (OFF state of the bidirectional diode). If the leakage current cannot be sufficiently suppressed, data cannot be normally written to or read from the selected memory cell.

  Based on such findings, the present inventors have found that when the load resistance portion is formed inside the plug that contacts the variable resistance element or the current control element, the bidirectional current control element is not easily destroyed. .

That is, in order to solve the above-described problem, the variable resistance nonvolatile memory cell of the present invention has a resistance change that reversibly transitions between a plurality of resistance states having different resistance values by applying electrical signals having different polarities. A current control element having a non-linear voltage-current characteristic that is connected in series to the element and the variable resistance element, and the slope of the voltage-current curve increases as the absolute value of the applied voltage increases within a predetermined applied voltage range; A plug formed in a hole penetrating the interlayer insulating layer, in contact with at least one of the variable resistance element or the current control element and having a load resistance portion, wherein the load resistance portion is tantalum. silicon oxide _(Ta-SiO 2), tungsten oxide _(WO x), is composed of niobium oxide _(NbO x), tantalum oxide (TaO _x) It is composed of at least one material selected from the group.

  With the above configuration, the current control element is not easily destroyed in the initial break process. Since the load resistance portion is formed inside the hole, the shape of the load resistance portion and the resistance value determined thereby can be easily controlled.

  In the variable resistance nonvolatile memory cell, the variable resistance element and the current control element each include an electrode, and the plug is in contact with at least one of the variable resistance element and the current control element. And the said electrode may be comprised so that it may spread outside the said connection part in the perimeter of the connection part with the said plug.

  In the above configuration, since the area of the load resistance section (area of a cross section cut in a direction perpendicular to the direction of current flow) can be made smaller than the element, the load resistance section is formed integrally with the variable resistance element or the current control element. Compared with the case where it carries out, the resistance of a load resistance part can be made larger.

  In the variable resistance nonvolatile memory cell, the electrode and the load resistance portion may be connected by an ohmic junction.

  In the above configuration, the resistance value realized by the load resistance unit can be set to a desired value more easily.

  In the variable resistance nonvolatile memory cell, the plug may have a resistance value in a range of 170Ω to 5 kΩ.

  With the above configuration, the current control element is further hardly destroyed in the initial break process.

  In the variable resistance nonvolatile memory cell, the variable resistance element and the current control element are formed so as to form an integrated structure without vias, and the plug is configured by the variable resistance element and the current control element. It may be connected to the upper end surface of the integrated structure.

  In the variable resistance nonvolatile memory cell, the variable resistance element and the current control element are formed so as to form an integrated structure without vias, and the plug is configured by the variable resistance element and the current control element. It may be connected to the lower end surface of the integrated structure.

  The variable resistance nonvolatile memory device of the present invention includes a first wiring, a second wiring, and the variable resistance nonvolatile memory cell, and includes the interlayer insulating layer, the variable resistance element, and the current control. The element and the plug are formed between the first wiring and the second wiring.

  In the variable resistance nonvolatile memory device, a plurality of the first wirings are formed in parallel to each other in the same plane, and the second wirings are parallel to each other in a plane parallel to the plane above the plane. The first wiring and the second wiring are electrically connected to each of the three-dimensional intersections of the plurality of first wirings and the plurality of second wirings. The variable resistance nonvolatile memory cell may be formed so as to be connected.

  The variable resistance nonvolatile memory cell of the present invention includes a variable resistance element that reversibly transitions between a plurality of resistance states having different resistance values by applying electrical signals having different polarities, and the variable resistance element A current control element having a non-linear voltage-current characteristic in which the slope of the voltage-current curve increases as the absolute value of the applied voltage increases within a predetermined applied voltage range, and a hole penetrating the interlayer insulating layer And a plug having a load resistance portion in contact with at least one of the variable resistance element or the current control element, and a resistance value of the plug being 170Ω or more.

  In the variable resistance nonvolatile memory cell, the plug may have a resistance value of 2 kΩ or more.

  In the variable resistance nonvolatile memory cell, the variable resistance element and the current control element each include an electrode, and the plug is in contact with at least one of the variable resistance element and the current control element. And the said electrode may be comprised so that it may spread outside the said contact part in the perimeter of the contact part with the said plug.

  In the variable resistance nonvolatile memory cell, the variable resistance element and the current control element are formed so as to form an integrated structure without vias, and the plug is configured by the variable resistance element and the current control element. It may be connected to the upper end surface of the integrated structure.

  In the variable resistance nonvolatile memory cell, the variable resistance element and the current control element are formed so as to form an integrated structure without vias, and the plug is configured by the variable resistance element and the current control element. It may be connected to the lower end surface of the integrated structure.

  The variable resistance nonvolatile memory device of the present invention includes a first wiring, a second wiring, and the variable resistance nonvolatile memory cell, and includes the interlayer insulating layer, the variable resistance element, and the current control element. And the plug are formed between the first wiring and the second wiring.

  In the variable resistance nonvolatile memory device, a plurality of the first wirings are formed in parallel to each other in the same plane, and the second wirings are parallel to each other in a plane parallel to the plane above the plane. The first wiring and the second wiring are electrically connected to each of the three-dimensional intersections of the plurality of first wirings and the plurality of second wirings. The variable resistance nonvolatile memory cells may be formed so as to be connected to each other.

  According to the variable resistance nonvolatile memory cell and variable resistance nonvolatile memory device of the present invention, there is an effect that the current control element is hardly destroyed in the initial break process.

FIG. 1 is a side sectional view showing an example of a schematic configuration of the variable resistance nonvolatile memory cell according to the first embodiment. FIG. 2 is a plan view showing an example of the size relationship between the electrode and the plug in the variable resistance nonvolatile memory cell according to the first embodiment. FIG. 2A is a diagram illustrating the second electrode and the second electrode of the variable resistance element. FIG. 2B is a diagram showing the magnitude relationship between the plugs, and FIG. 2B is a diagram showing the magnitude relationship between the fourth electrode of the current control element and the third plug. FIG. 3 is a diagram illustrating an example of a method of manufacturing the variable resistance nonvolatile memory cell according to the first embodiment. FIG. 3A illustrates the first wiring in the interlayer insulating layer formed on the substrate. FIG. 3B is a diagram showing a process of forming a contact hole so as to reach, and FIG. 3B is a diagram showing a process of forming a plug in the contact hole. FIG. 4 is a diagram illustrating an example of a method of manufacturing the variable resistance nonvolatile memory cell according to the first embodiment. FIG. 4A illustrates a step of forming a variable resistance element material layer so as to cover the plug. FIG. 4B is a diagram showing a process of forming the resistance change element by etching the resistance change element material layer. FIG. 5 is a diagram illustrating an example of a method of manufacturing the variable resistance nonvolatile memory cell according to the first embodiment, in which an interlayer insulating layer covering the variable resistance element and a plug connected to the variable resistance element are formed. It is a figure which shows a process. FIG. 6 is a diagram illustrating an example of the method of manufacturing the variable resistance nonvolatile memory cell according to the first embodiment. FIG. 6A illustrates a step of forming a current limiting element material layer so as to cover the plug. FIG. 6B is a diagram illustrating a process of forming a current limiting element by etching a current limiting element material layer. FIG. 7 is a diagram illustrating an example of the method of manufacturing the variable resistance nonvolatile memory cell according to the first embodiment, and includes an interlayer insulating layer covering the current limiting element, a plug connected to the current limiting element, and a second wiring. It is a figure which shows the process of forming. FIG. 8 is a diagram showing the relationship between voltage and current in the first experimental example, FIG. 8A is an overall view, and FIG. 8B is an enlarged view of a portion surrounded by a broken line in FIG. FIG. FIG. 9 is a diagram showing the relationship between the load resistance and the voltage applied to the circuit when the current limiting element is destroyed in the first experimental example. FIG. 10 is a diagram illustrating the relationship between voltage and current in the second experimental example. FIG. 11 is a side cross-sectional view showing an example of a schematic configuration of a variable resistance nonvolatile memory cell according to a first modification of the first embodiment. FIG. 12 is a side cross-sectional view showing an example of a schematic configuration of a variable resistance nonvolatile memory cell according to a second modification of the first embodiment. FIG. 13 is a side cross-sectional view showing an example of a schematic configuration of a variable resistance nonvolatile memory cell according to a third modification of the first embodiment. FIG. 14 is a side cross-sectional view showing an example of a schematic configuration of a variable resistance nonvolatile memory cell according to a fourth modification of the first embodiment. FIG. 15 is a side cross-sectional view showing an example of a schematic configuration of a variable resistance nonvolatile memory cell according to a fifth modification of the first embodiment. FIG. 16 is a block diagram illustrating an example of a schematic configuration of a variable resistance nonvolatile memory device according to the second embodiment. FIG. 17 is a schematic perspective view in which the portion A of FIG. 16 is enlarged. FIG. 18 is a side sectional view showing an example of a schematic configuration of the portion indicated by 30A in FIG. FIG. 19 is a diagram illustrating voltage-current characteristics of the current limiting element. FIG. 20 is a diagram showing current-voltage characteristics of a single variable resistance element, a single current limiting element, a circuit in which one variable resistance element and one current limiting element are connected in series.

  Hereinafter, a variable resistance nonvolatile memory cell according to an embodiment of the present invention will be described with reference to the drawings. In addition, the same code | symbol may be attached | subjected to the same or corresponding component, and the overlapping detailed description may be abbreviate | omitted. In the drawings, the size and ratio may be exaggerated for convenience of explanation.

(First embodiment)
[First Experimental Example]
In the first experimental example, the voltage distribution between the current control element and the load resistor connected in series with the current control element, and the voltage and current when the current control element is destroyed were examined. The load resistance was formed on the substrate closest to the current control element, and the effects of delay and pulse waveform deterioration due to long wiring when the load resistance was externally attached were reduced as much as possible.

  The experimental method was as follows.

The size of the current control element viewed from the upper surface direction is 0.5 μm × 0.5 μm. Both the lower electrode and the upper electrode were made of tantalum nitride (TaN), and the film thickness was 30 nm. The current control layer was made of SiN _x , the value of x was 0.3, and the film thickness was 15 nm. Since TaN has good compatibility with Cu wiring, an electrode composed of TaN was examined.

  A load resistance composed of aluminum wiring (width 0.26 μm, film thickness of about 480 nm) with a long wiring length is connected in series to the current control element, and the voltage-current characteristics of the resulting circuit (current control element + aluminum wiring) It was confirmed.

  The resistance value and wiring length of the aluminum wiring are the following seven types. Case 1: No load resistance, Case 2: Wiring length 0.6 mm, Resistance value: 170Ω, Case 3: Wiring length 1.5 mm, Resistance value 420Ω, Case 4: Wiring length 2.4 mm, Resistance value 670Ω, Case 5: Wiring length 3.0 mm, resistance value 830Ω, case 6: wiring length 6.0 mm, resistance value 1700Ω, case 7: wiring length 15 mm, resistance value 4300Ω.

  FIG. 8 is a diagram showing the relationship between voltage and current in the first experimental example, FIG. 8A is an overall view, and FIG. 8B is an enlarged view of a portion surrounded by a broken line in FIG. FIG. FIG. 9 is a diagram showing the relationship between the load resistance and the voltage applied to the circuit when the current limiting element is destroyed in the first experimental example. Table 1 shows the breakdown voltage and breakdown current of the current control element in each case.

  As shown in FIGS. 8 and 9 and Table 1, in the configuration in which the load resistance is formed in the immediate vicinity of the current control element, as the resistance value of the load resistance increases, the breakdown voltage (when the current control element is destroyed) The voltage applied to the circuit in FIG. This is presumably because the voltage resistance of the current control element was apparently improved because the voltage was distributed to the load resistance portion connected in series with the current control element in the immediate vicinity of the current control element. Even when the load resistance is as low as 170Ω, the breakdown voltage is higher than when there is no load. From the results of FIGS. 8 and 9 and Table 1, it was found that the effect of preventing the current control element from being destroyed can be obtained when the load resistance is at least 170Ω or more and 4.3 kΩ or less.

  By disposing the 0.6 mm aluminum wiring, a load resistance of 170Ω can be obtained, and the current control element can be prevented from being destroyed. However, it is difficult to arrange such a large-area wiring pattern in each element in an element that requires miniaturization. Hereinafter, the area and resistance value where the load resistance is arranged will be examined.

Consider a case in which a load resistance of 500Ω is formed of a resistance layer made of a material having a specific resistance of 100 mΩcm. When the current control element has a size of 0.5 μm × 0.5 μm (area 0.25 μm ² ) when viewed from the top surface direction, if the resistance layer is formed with the same size as the element, the film thickness becomes as large as about 250 nm. End up. With the above-described film thickness, formation by photolithography is difficult. If the resistance layer is formed in a size different from that of the element, an increase in cost such as an increase in the number of masks occurs.

However, when a load resistance is formed as a part or all of a plug connecting an element and a wiring, for example, a plug formed in a circular hole (area 0.045 μm ² ) having a diameter of 0.24 μm, the same specific resistance film Can be formed with a film thickness of about 50 nm. Further, when forming in the hole, a resistance layer is also formed on the side wall by CVD or the like. The cross-sectional area of the metal (filling layer) embedded inside becomes smaller, and the resistance value of the plug increases. Therefore, the thickness of the resistance layer may be 15 nm to 20 nm.

  In addition, when there are a plurality of plugs between the lower wiring, the upper wiring, and the element, a material having a lower specific resistance value is used as a material of the load resistance portion by forming a load resistance portion in the plurality of plugs. It is also possible to reduce the thickness of the load resistance portion.

[Second Experimental Example]
In the second experimental example, the effect of the load resistance suppressing the destruction of the current control element in the initial break process of the variable resistance element was verified.

  The experimental method was as follows.

The dimension of the variable resistance element viewed from the upper surface was 0.5 μm × 0.5 μm. At this time, the lower electrode was made of tantalum nitride (TaN) to a thickness of 30 nm, and the upper electrode was made of iridium (Ir) to a thickness of 50 nm. Further, the variable resistance layer has a film thickness of 45 nm using oxygen-deficient tantalum oxide (when TaO _x is expressed, x = 1.5) as the low resistance layer, and similarly tantalum oxide as the high resistance layer. The film thickness was 5 nm using an object (when expressed as TaO _y , y = 2.5).

The current control element had a size of 0.5 μm × 0.5 μm when viewed from the upper surface, and both the lower electrode and the upper electrode were made of tantalum nitride (TaN), and the electrode thickness was 30 nm. The current control layer was made of SiN _x , the value of x was 0.3, and the film thickness was 15 nm.

  Each of the elements configured in the same manner as the single variable resistance element and the single current control element described above is a W-type plug (a laminated barrier layer of Ti (film thickness 12 nm) and TiN (film thickness 10 nm) in a hole having a diameter of 260 nmφ). After formation, the one connected by filling W was used.

  A load resistance composed of an aluminum wiring (width 0.26 μm, film thickness 480 nm) having a long wiring length was connected in series to the current control element, and the voltage-current characteristics of the obtained circuit were confirmed.

  A voltage-current characteristic was confirmed by forming an element in which a load in which a long wiring made of an aluminum wiring was connected to a structure in which a resistance change element (0.5 μm × 0.5 μm) and a current control element were stacked, was connected in series.

  The resistance value and wiring length of the aluminum wiring are the following three types. Case 1: No load resistance, Case 2: Wiring length 7.2 mm, Resistance value: 2 kΩ, Case 3: Wiring length 18 mm, Resistance value 5 kΩ.

  FIG. 10 is a diagram illustrating the relationship between voltage and current in the second experimental example. In each case, the voltage applied to the circuit when the initial break of the resistance change element occurs (voltage at the time of the break of the resistance change element), the current flowing through the circuit (current at the initial break of the resistance change element), and current control Table 2 shows the voltage applied to the circuit when the element is broken (voltage when the current control element is broken) and the current flowing through the circuit (current when the current control element is broken).

  As shown in FIG. 10 and Table 2, it was confirmed that an initial break of the resistance change element occurred in both case 2 (2 kΩ) and case 3 (5 kΩ). Immediately after the initial break occurred, the current control element was not broken. In Case 2 (2 kΩ), 0.4 V could be applied after the initial break until the current control element was destroyed. The breakdown current (allowable current) of the current control element dramatically improved from 88.4 μA to 907 μA in case 1 (no load resistance).

  The same result was obtained in case 3 (5 kΩ), and no breakdown of the current control element occurred in the measured range (voltage applied to the circuit: ˜6 V).

  From the above results, it is understood that by connecting a load resistor in series in the immediate vicinity of the current limiting element, the voltage described above is distributed to the load resistance to the current control element, and it is possible to suppress the breakdown of the current control element. It was. The initial break voltage (the voltage that must be applied to the memory cell composed of the resistance change element and the current control element in order to generate the initial break) is the high resistance layer material, the low resistance layer material, the electrode material, and the high resistance layer thickness. It can be reduced by adjusting. For example, the dielectric constant of the metal oxide (mainly transition metal oxide) constituting the high resistance layer material is larger than the dielectric constant of the metal oxide (mainly transition metal oxide) constituting the low resistance layer material, or high resistance. Satisfy at least one of the conditions that the band gap of the metal oxide (mainly transition metal oxide) constituting the layer material is smaller than the band gap of the metal oxide (mainly transition metal oxide) constituting the low-resistance layer material The variable resistance element may be made of a resistance layer material. This is because there is a correlation between the dielectric constant of the oxide layer and the breakdown strength, that is, the higher the dielectric constant, the smaller the strength of the dielectric breakdown field. Further, there is a correlation between the band gap of the oxide layer and the breakdown strength of the breakdown electric field, that is, the smaller the band gap, the smaller the intensity of the breakdown electric field.

  In addition, when platinum (Pt) or palladium (Pd) is used as the electrode material in contact with the high resistance layer, minute protrusions of the electrode material are generated on the high resistance layer side by the heat treatment, and the initial break voltage can be reduced. . Further, the initial break voltage can be reduced by reducing the thickness of the high resistance layer.

[Constitution]
FIG. 1 is a side sectional view showing an example of a schematic configuration of the variable resistance nonvolatile memory cell according to the first embodiment. Hereinafter, the direction in which the constituent elements of the element are stacked is defined as the vertical direction, and the layers are stacked from bottom to top.

  In the first embodiment, the load resistance is formed in the vias constituting the variable resistance nonvolatile memory cell, thereby preventing the current control element constituting the nonvolatile memory cell in the initial break from being destroyed.

  As illustrated in FIG. 1, the variable resistance nonvolatile memory cell 100 according to the present embodiment includes a first wiring 101 (for example, aluminum (Al) having a thickness of 300 nm formed on a substrate (not shown). And a hole penetrating through the first interlayer insulating layer 108 (for example, a layer made of silicon oxide and having a thickness of 300 nm or more and 500 nm or less) formed to cover the first wiring 101. A first plug 105 (diameter: for example, 50 nmΦ or more and 300 nmΦ or less) having a first load resistance portion 131 </ b> A formed so as to be in contact with and in series with the first wiring 101 is provided. The first plug 105 is formed in a hole formed in the first interlayer insulating layer 108.

  A first electrode 111 (lower electrode, film thickness: for example, 5 nm to 100 nm, size: for example, 0.5 μm × 0.5 μm) is formed on the first interlayer insulating layer 108 so as to cover the first plug 105. And the resistance change layer 113 (film thickness: 20 nm to 100 nm, size: 0.5 μm × 0.5 μm, for example) and the second electrode 112 (upper electrode, film thickness: 5 nm to 100 nm, size) : For example, 0.5 μm × 0.5 μm) is formed. A second interlayer insulating layer 109 (for example, a layer made of silicon oxide and having a thickness of 300 nm to 500 nm) is formed so as to cover the variable resistance element 103. A second plug 106 (diameter: 50 nmΦ or more and 300 nmΦ, for example, having a second load resistance portion 131B formed so as to be inscribed in a hole penetrating the second interlayer insulating layer 109 and in contact with the second electrode 112. Is formed). Note that the size refers to the size of the first interlayer insulating layer 108 as viewed from the film thickness direction (the same applies hereinafter).

  On the second interlayer insulating layer 109, the third electrode 121 (lower electrode, film thickness: for example, 5 nm to 100 nm, size: for example, 0.5 μm × 0.5 μm) so as to cover the second plug 106 Current control layer 123 (film thickness: for example, 5 nm to 30 nm, size: 0.5 μm × 0.5 μm, for example), and fourth electrode 122 (upper electrode, film thickness: for example, 5 nm to 100 nm, size) : For example, 0.5 μm × 0.5 μm) is formed. A third interlayer insulating layer 110 (for example, a layer made of silicon oxide and having a thickness of 300 nm to 500 nm) is formed so as to cover the current control element 104. A third plug 107 (diameter: 50 nmΦ, for example, having a third load resistance portion 131C formed so as to be inscribed in a hole penetrating the third interlayer insulating layer 110 and connected in series with the fourth electrode 122 More than 300 nmΦ) is formed.

  On the third interlayer insulating layer 110, the second wiring 102 (for example, a wiring made of Al and having a thickness of 300 nm to 500 nm) is formed so as to cover the third plug 107.

  As described above, the variable resistance nonvolatile memory cell of this embodiment includes the first wiring 101, the second wiring 102, and the variable resistance nonvolatile memory cell 100, and the interlayer insulating layers 108, 109, and 110. The resistance change element 103, the current control element 104, and the plugs 105, 106, and 107 are formed between the first wiring 101 and the second wiring 102. As described above, the variable resistance nonvolatile memory cell, the interlayer insulating layer, and the plug are disposed between the first wiring 101 and the second wiring 102 as described in the first modification described below. The same applies to the fifth modification and the second embodiment.

  Since the variable resistance element, the current control element, and the load resistance unit are connected in series, the current control element is less likely to be destroyed in the initial break process. By forming the load resistance portion as a plug in the hole, the contact area between the load resistance portion and the electrode (element), its shape, and the resistance value determined by them can be easily controlled. Therefore, the resistance value of the load resistance unit can be easily set to a desired value.

  The substrate can be a silicon single crystal substrate or a semiconductor substrate, but is not limited thereto. Since the variable resistance nonvolatile memory cell 100 can be formed at a relatively low substrate temperature, the variable resistance nonvolatile memory cell 100 (one current control element and one variable resistance element is formed on a resin material or the like. 1D1R element including each of them) can be formed.

  FIG. 2 is a plan view showing an example of the size relationship between the electrode and the plug in the variable resistance nonvolatile memory cell according to the first embodiment. FIG. 2A is a diagram illustrating the second electrode and the second electrode of the variable resistance element. FIG. 2B is a diagram showing the magnitude relationship between the plugs, and FIG. 2B is a diagram showing the magnitude relationship between the fourth electrode of the current control element and the third plug.

  In the example shown in FIG. 2A, the second electrode 112 is configured to spread outward from the connection portion on the entire circumference of the connection portion with the second plug 106 (or the second load resistance portion 131B). ing. That is, the second electrode 112 covers the entire lower end surface of the second plug 106 (or the second load resistance portion 131B), and further extends to the outside over the entire circumference. In other words, the second electrode 112 covers the entire hole in which the second plug 106 (or the second load resistance portion 131B) is formed, and further extends to the outside of the hole over the entire peripheral edge thereof. .

  In the example shown in FIG. 2B, the fourth electrode 122 is configured to spread outward from the connection portion in the entire periphery of the connection portion with the third plug 107 (or the third load resistance portion 131C). ing. That is, the fourth electrode 122 covers the entire lower end surface of the third plug 107 (or the third load resistance portion 131C), and further spreads outward over the entire circumference. In other words, the fourth electrode 122 covers the entire hole in which the third plug 107 (or the third load resistance portion 131C) is formed, and further extends to the outside of the hole over the entire periphery. .

  Thus, by making the area of the plug smaller than the area of the electrode (or element), the area of the load resistance portion can be reduced, and the resistance of the load resistance portion can be increased more easily.

  The resistance change layer 113 includes a low resistance layer 114 (hereinafter sometimes referred to as a first resistance change layer, a first transition metal oxide layer, a low oxygen concentration layer, or a high oxygen deficiency layer) and a high resistance layer 115 ( Hereinafter, it has a laminated structure composed of two layers (sometimes referred to as a second resistance change layer, a second transition metal oxide layer, a high oxygen concentration layer, or a low oxygen deficiency layer). The low resistance layer 114 and the high resistance layer 115 are in contact with each other, and the low resistance layer 114 is disposed so as to be in contact with the first electrode 111 and the high resistance layer 115 is in contact with the second electrode 112.

The resistance change layer 113 includes a low resistance layer made of an oxygen-deficient transition metal oxide and a high resistance layer made of a transition metal oxide having a lower degree of oxygen deficiency than the first transition metal oxide layer. It is configured by stacking. In the present embodiment, as an example, the low resistance layer 114 is composed of an oxygen-deficient first tantalum oxide layer, and the high resistance layer 115 is composed of a second tantalum oxide layer. When the composition of the low resistance layer 114 is TaO _x and the composition of the high resistance layer 115 is TaO _y , x and y are adjusted so that 0 <x <2.5 and x <y. Preferably, adjustment is made so that x is 0.8 or more and 1.9 or less and y is 2.1 or more. When x and y are in this range, a stable resistance changing operation can be realized.

The oxygen content of the high resistance layer 115 (second tantalum oxide layer) is higher than the oxygen content of the low resistance layer 114 (first tantalum oxide layer). In other words, the oxygen deficiency of the high resistance layer 115 is lower than the oxygen deficiency of the low resistance layer 114. The degree of oxygen deficiency refers to the proportion of oxygen that is deficient with respect to the amount of oxygen constituting the oxide of the stoichiometric composition in each transition metal. For example, when the transition metal is tantalum, the stoichiometric oxide composition is Ta ₂ O ₅ , and thus can be expressed as TaO _2.5 . The degree of oxygen deficiency of TaO _2.5 is 0%. On the other hand, for example, the oxygen deficiency of an oxygen deficient tantalum oxide having a composition of TaO _1.5 is oxygen deficiency = (2.5−1.5) /2.5=40%. The oxygen content of Ta ₂ O ₅ is the ratio of the number of oxygen atoms to the total number of atoms (O / (Ta + O)), which is 71.4 atm%. Therefore, the oxygen-deficient tantalum oxide has an oxygen content greater than 0 and less than 71.4 atm%.

The metal constituting the resistance change layer 113 may be a transition metal other than tantalum. As the transition metal, tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), niobium (Nb), tungsten (W), or the like can be used. Since transition metals can take a plurality of oxidation states, different resistance states can be realized by oxidation-reduction reactions. For example, when hafnium oxide is used, x is 0.9 to 1.6 when the composition of the low resistance layer 114 (first hafnium oxide layer) is HfO _x , and the high resistance layer 115 is used. When the composition of the (second hafnium oxide layer) is HfO _y and y is larger than the value of x, it can be confirmed that the resistance value of the resistance change layer 113 is stably changed at high speed. ing. In this case, the thickness of the high resistance layer 115 is preferably 3 nm or more and 4 nm or less. When zirconium oxide is used, x is 0.9 or more and 1.4 or less when the composition of the low resistance layer 114 (first zirconium oxide layer) is ZrO _x , and the high resistance layer 115 When the composition of the (second zirconium oxide layer) is ZrO _y and y is greater than the value of x, it can be confirmed that the resistance value of the resistance change layer 113 is stably changed at high speed. ing. In this case, the thickness of the high resistance layer 115 is preferably 1 nm or more and 5 nm or less.

Note that the first transition metal constituting the low resistance layer 114 (first transition metal oxide layer) and the second transition metal constituting the high resistance layer 115 (second transition metal oxide layer) Different transition metals may be used. In this case, it is preferable that the high resistance layer 115 has a lower degree of oxygen deficiency than the low resistance layer 114, that is, has a higher resistance. With such a configuration, a voltage applied between the first electrode 111 and the second electrode 112 at the time of resistance change is more distributed to the high resistance layer 115 and is generated in the high resistance layer 115. The oxidation-reduction reaction can be made easier to occur. In addition, when a material in which the first transition metal and the second transition metal are different from each other is used, the standard electrode potential of the second transition metal is preferably smaller than the standard electrode potential of the first transition metal. This is because the resistance change phenomenon is considered to occur when an oxidation-reduction reaction occurs in a minute filament (conductive path) formed in the high resistance layer 115 having a high resistance, and the resistance value changes. For example, an oxygen-deficient tantalum oxide is used for the low resistance layer 114 (first transition metal oxide layer), and titanium oxide (TiO ₂ ) is used for the high resistance layer 115 (second transition metal oxide layer). By using this, a stable resistance changing operation can be obtained. Titanium (standard electrode potential = −1.63 eV) is a material having a lower standard electrode potential than tantalum (standard electrode potential = −0.6 eV). The standard electrode potential represents a characteristic that the greater the value, the less likely it is to oxidize. By disposing a metal oxide having a standard electrode potential smaller than that of the low resistance layer 114 in the high resistance layer 115, a redox reaction is more likely to occur in the high resistance layer 115.

  The resistance change phenomenon in the variable resistance layer of the laminated structure of each material described above is caused by the oxidation-reduction reaction occurring in the minute filament formed in the high resistance layer 115 having high resistance, and the resistance value changes. It is thought that. That is, when a positive voltage is applied to the second electrode 112 on the high resistance layer 115 side with respect to the first electrode 111, the oxygen ions in the resistance change layer 113 are attracted to the high resistance layer 115 side, resulting in a high resistance. It is considered that an oxidation reaction occurs in the microfilament formed in the layer 115 and the resistance of the microfilament increases. On the other hand, when a negative voltage is applied to the second electrode 112 on the high resistance layer 115 side with respect to the first electrode 111, oxygen ions in the high resistance layer 115 are pushed to the low resistance layer 114 side to increase the high voltage. It is considered that the reduction reaction occurs in the microfilament formed in the resistance layer 115 and the resistance of the microfilament decreases.

  In the present embodiment, for example, the first electrode 111 constituting the resistance change element 103 can be made of tantalum nitride (TaN), and the second electrode 112 can be made of iridium (Ir). Here, the standard electrode potential V2 of iridium is 1.16 eV, and the standard electrode potential V1 of tantalum nitride is 0.48 eV.

  In general, the standard electrode potential is used as one index of the degree of oxidization, and if this value is large, it means that it is difficult to oxidize, and if it is small, it means that it is easily oxidized. Between the transition metal element contained in the variable resistance layer and the material constituting the electrode, the greater the difference in the standard electrode potential, the more likely the resistance change, and the smaller the standard electrode potential difference, the less likely the resistance change to occur. It is speculated that oxidization plays a major role in the mechanism of resistance change phenomenon.

Since the standard electrode potential Vt of tantalum is −0.6 eV, the relationship of Vt <V2 is satisfied. Therefore, an oxidation-reduction reaction occurs at the interface between the second electrode 112 made of iridium and the high resistance layer 115, and resistance Change phenomenon appears. Further, since the relationship of V2> V1 is satisfied, this oxidation-reduction reaction is higher than the interface between the first electrode 111 made of tantalum nitride and the low resistance layer 114 and the second electrode 112 made of iridium. It appears preferentially at the interface with the resistance layer 115. For this reason, the interface where the resistance change phenomenon appears can be fixed to one interface, and a malfunction due to the resistance change phenomenon occurring at the other interface can be prevented. Note that the standard electrode potential of the transition metal constituting the high resistance layer 115 (second transition metal oxide layer) is V _H , the standard electrode potential of the metal constituting the first electrode 111 is V ₁ , and the second electrode 112 is When the standard electrode potential of the constituent metal is V ₂ , another metal that satisfies V ₂ > V _H may be used. In addition, other metals satisfying V ₂ > V ₁ may be used. For example, platinum (Pt), palladium (Pd), or the like may be used for the second electrode 112, and tungsten (W) or the like may be used for the first electrode 111.

  In this embodiment, as the current control element 104, an MSM diode including the third electrode 121, the fourth electrode 122, and a current control layer 123 that is sandwiched between these electrodes and in contact with both electrodes is used. The MSM diode has a structure in which a semiconductor layer is sandwiched between metal electrodes. The metal and the semiconductor layer can be formed by a Schottky contact, and a higher current supply capability can be expected than the MIM diode.

The third electrode 121 can be made of, for example, tantalum nitride (TaN). The fourth electrode 122 can be made of, for example, tantalum nitride (TaN). The current control layer 123 can be made of, for example, silicon nitride (SiN _x ).

  FIG. 19 is a diagram illustrating voltage-current characteristics of the current limiting element. As shown in FIG. 19, the current control element is nonlinear in which the slope (ΔI / ΔV) of the voltage-current curve increases as the absolute value of the applied voltage increases in a predetermined applied voltage range (B to C to A). The voltage-current characteristic is as follows.

  More specifically, even when a positive or negative voltage is applied to the fourth electrode 122 with the third electrode 121 as a reference, a resistor (the third electrode 121 and the fourth electrode 122 is used when the absolute value of the voltage is small. The electrical resistance between the first and second electrodes increases, and when the absolute value of the voltage increases beyond a predetermined value, the resistance decreases rapidly. The current control element 104 is a so-called bidirectional diode that has such nonlinear current-voltage characteristics [on / off characteristics] and can flow current in both directions.

The value of _x in SiN _x exemplified as the material of the current control layer 123 is the number of moles of nitrogen atoms relative to 1 mole of Si atoms, and indicates the so-called degree of nitriding (composition ratio). The electrical conductivity characteristics of SiN _x vary greatly depending on the value of x. Specifically, the so-called stoichiometric composition (x = 1.33, that is, Si ₃ N ₄ ) is an insulator, but if the nitrogen ratio is made smaller than this (ie, the value of x is reduced). SiN _x will gradually behave as a semiconductor. As a material of the current control layer 123, it is preferable that the value of x satisfies 0 <x ≦ 0.85. With such a configuration, it is possible to obtain the current control element 104 capable of flowing an on-current of 10,000 A / cm ² or more necessary for resistance change.

  The current control element 104 is not limited to an MSM diode, and an MIM diode or a varistor may be used. However, since MSM diodes and MIM diodes do not use characteristics such as crystal grain boundaries like varistors, it can be expected to obtain a current control element that is less affected by thermal history during the manufacturing process and has little variation.

Thus, when SiN _x is used for the current control layer 123 of the MSM diode, the third electrode 121 and the fourth electrode 122 in contact with the current control layer 123 are tantalum nitride (TaN) that provides a good Schottky interface with SiN _x. ) Is preferable.

  The first plug 105 is in contact with the first wiring 101 and the first electrode 111. The second plug 106 is in contact with the second electrode 112 and the third electrode 121. The third plug 107 is in contact with the fourth electrode 122 and the second wiring 102.

The first plug 105, the second plug 106, and the third plug 107 formed between the first wiring 101 and the second wiring 102 function as high resistance plugs. The first load resistor 131A, the second load resistor 131B, and the third load resistor 131C are tantalum silicon oxide (Ta—SiO ₂ : specific resistance = about 100 mΩcm) in the hole formed in the interlayer insulating layer. Can be formed as a layer having a thickness of 15 nm to 20 nm. On top of that, an adhesion layer 132 (for example, composed of titanium (Ti)) and a barrier layer 133 (for example, composed of titanium nitride (TiN)) are sequentially stacked. The hole on the barrier layer 133 is filled with, for example, tungsten (W) to form the filling layer 134.

  For example, copper may be used as the material of the filling layer 134 instead of tungsten. In that case, it is preferable to form the barrier layer 133 using Ta or TaN, for example.

  As the material of the first wiring 101 and the second wiring 102, for example, aluminum or copper can be used.

  It is preferable that the 1st wiring 101 and the 1st load resistance part 131A are connected by ohmic junction. It is preferable that the 2nd electrode 112 and the 2nd load resistance part 131B are connected by ohmic junction. It is preferable that the 4th electrode 122 and the 3rd load resistance part 131C are connected by ohmic junction.

The first load resistor 131A, the second load resistor 131B, and the third load resistor 131C are tantalum silicon oxide (Ta—SiO ₂ ), tungsten oxide (WO _x ), niobium oxide (NbO _x ), It may be made of at least one material selected from the group consisting of tantalum oxide (TaO _x ). Tantalum silicon oxide _(Ta-SiO 2), tungsten oxide _(WO x), niobium oxide _(NbO x), tantalum oxide (TaO _x) may be a consists of two or more combination of materials.

The first load resistor 131A, the second load resistor 131B, and the third load resistor 131C may be made of a material having a specific resistance of 500 μΩcm to 100 mΩcm. The specific resistance of a material used for a normal plug is about 42 μΩcm for titanium (Ti), about 22 μΩcm for titanium nitride (TiN), about 5.65 μΩcm for tungsten (W), and about 1.67 μΩcm for copper (Cu). With a low value. Specific resistances of those exemplified above as the material of the load resistance portion are tantalum silicon oxide (Ta—SiO _x ), tungsten oxide (WO _x ), niobium oxide (NbO _x ), and tantalum oxide (TaO _x ). The resistance value can be appropriately adjusted by changing the oxygen flow rate ratio when forming by sputtering with an oxygen deficient metal oxide such as about 100 μΩcm or more, and a desired resistance value can be easily obtained. Therefore, it is suitable for realizing a high resistance with a relatively thin layer in the hole.

  The total resistance value of the first plug 105, the second plug 106, and the third plug 107 is preferably in the range of 170Ω to 5kΩ. The total resistance value is more preferably in the range of 170Ω to 4300Ω. The lower limit of the total resistance value may be any one of 170Ω, 420Ω, 670Ω, 830Ω, and 1700Ω. The upper limit of the total resistance value may be 420Ω, 670Ω, 830Ω, 1700Ω, or 4300Ω.

  As described above, in order to stably change the resistance of the resistance change layer 113 formed by stacking the high resistance layer 115 and the low resistance layer 114, an initial break is required from the high resistance state after formation. During the initial break, the voltage applied to the variable resistance element is divided into the current control element, and the divided voltage during the initial break applied to the current control element is the rated voltage (breakdown voltage) of the current control element. If it exceeds, the current control element will be destroyed. By arranging the high resistance plug in series with the current control element, the voltage is distributed to the high resistance plug at the time of the initial break, and the voltage applied to the current control element itself can be reduced. Therefore, it is possible to prevent destruction of the current control element, to realize a stable operation after the initial break for the variable resistance nonvolatile memory cell, to prevent variation in characteristics, and to improve reliability.

  In the present embodiment, the resistance change layer does not necessarily have a two-layer structure, and may have a one-layer structure or a structure of three or more layers. In the above example, the load resistance portion is provided in any of the first plug 105, the second plug 106, and the third plug 107, but the load resistance portion may be provided in only one of them, A load resistance portion may be provided in any two combinations of plugs. Of the first plug 105, the second plug 106, and the third plug 107, one or any two may be omitted. The first plug 105, the second plug 106, and the third plug 107 do not necessarily have a laminated structure, and the plug itself constitutes a load resistance unit by being formed of a single material. May be.

  In the example of FIG. 1, the current control element 104 is formed on the resistance change element 103, but the resistance change element 103 may be formed on the current control element 104. The resistance change element 103 and the current control element 104 may be in direct contact with the second plug 106 omitted.

[Production method]
Next, an example of a manufacturing method of the variable resistance nonvolatile memory cell 100 including the variable resistance element 103 and the current control element 104 configured as described above will be described with reference to the cross-sectional views of FIGS. . The following manufacturing method is merely an example, and specific materials, layer thicknesses, areas, and the like can be changed as appropriate.

  FIG. 3A is a diagram illustrating a process of forming a contact hole so as to reach the first wiring in the interlayer insulating layer formed on the substrate, and FIG. 3B is a diagram in which a plug is formed in the contact hole. It is a figure which shows a process. FIG. 4A is a diagram illustrating a process of forming a variable resistance element material layer so as to cover the plug, and FIG. 4B illustrates a process of forming the variable resistance element by etching the variable resistance element material layer. FIG. FIG. 5 is a diagram illustrating a process of forming an interlayer insulating layer covering the variable resistance element and a plug connected to the variable resistance element. FIG. 6A is a diagram showing a process of forming a current limiting element material layer so as to cover the plug, and FIG. 6B shows a process of forming a current limiting element by etching the current limiting element material layer. FIG. FIG. 7 is a diagram illustrating a process of forming an interlayer insulating layer covering the current limiting element, a plug connected to the current limiting element, and a second wiring.

First, as shown in FIG. 3A, the first wiring 101 is formed of, for example, aluminum so as to be in contact with the substrate on a single crystal silicon substrate (not shown). A 200-nm-thick first interlayer insulating layer 108 made of, for example, SiO ₂ is formed by a thermal oxidation method so as to cover the first wiring 101. Further, a contact hole 130 is formed so as to penetrate the first interlayer insulating layer 108 and reach the first wiring 101 (FIG. 3A: step of forming a contact hole).

  Next, as shown in FIG. 3B, a tantalum silicon oxide layer having a thickness of, for example, 10 nm is formed in the contact hole 130 by sputtering a tantalum silicon oxide target in an argon atmosphere. Subsequently, a Ti layer having a thickness of 10 nm and a TiN layer having a thickness of 10 nm are sequentially formed by a CVD method. Thereafter, the inside of the hole formed by the TiN layer is filled with tungsten (W), which is the main material of the wiring, by CVD. Further, the tantalum silicon oxide layer, the Ti layer, the TiN layer, and tungsten (W) are removed by CMP until the first interlayer insulating layer 108 is exposed, so that the first load resistance portion 131A is adhered. The first plug 105 composed of the layer 132, the barrier layer 133, and the filling layer 134 is formed (FIG. 3B: step of forming a high resistance plug).

Next, as shown in FIG. 4A, the first electrode layer 111 ′ before pattern formation, for example, a TaN layer having a film thickness of 50 nm is formed so as to cover the upper surface of the first plug 105, and the Ta target is argon and nitrogen. And sputtering under a mixed gas atmosphere. Subsequently, a low resistance layer 114 ′ before pattern formation, for example, a TaO _x layer with a thickness of 30 nm, and a high resistance layer 115 ′ before pattern formation, for example, a TaO _y layer with a thickness of 5 nm, a tantalum target with argon and oxygen. Sputtering is performed under a mixed gas atmosphere. The oxygen content of the resistance change layer (low resistance layer and high resistance layer), in this case, the values of x and y in TaO _x and TaO _y are changed by changing the sputtering conditions (such as the gas flow ratio between argon and oxygen). It can be made. Thereafter, the second electrode layer 112 ′ before pattern formation, for example, an Ir layer having a thickness of 50 nm, is sputtered with an Ir target in an argon gas atmosphere.

  Next, as shown in FIG. 4B, the first electrode layer 111 ′, the low resistance layer 114 ′, the high resistance layer 115 ′ before pattern formation, and the second electrode layer 112 ′ before pattern formation are patterned. By performing the annealing, the variable resistance element 103 including the first electrode 111, the low resistance layer 114, the high resistance layer 115, and the second electrode 112 is formed (FIGS. 4A to 4B). Forming a variable resistance element).

Next, as shown in FIG. 5, the second plug 106 is formed in the same manner as the first plug 105. That is, the second interlayer insulating layer 109 made of, for example, SiO ₂ is formed by a thermal oxidation method. Further, a contact hole is formed so as to penetrate the second interlayer insulating layer 109 and reach the second electrode 112, and a tantalum silicon oxide layer, a Ti layer, a TiN layer, and tungsten (W) are stacked in this order in the inside. The excess plug is removed by CMP until the second interlayer insulating layer 109 is exposed, thereby forming the second plug 106 (FIG. 5: step of forming the second plug).

Next, as shown in FIG. 6A, the third electrode layer 121 ′ before pattern formation, for example, a TaN layer with a film thickness of 50 nm is formed to cover the upper surface of the second plug 106, and the Ta target is argon and nitrogen. And sputtering under a mixed gas atmosphere. Thereafter, a current control layer 123 ′ before pattern formation, for example, a SiN _x layer having a thickness of 10 nm is formed by sputtering a polycrystalline silicon target in a mixed gas atmosphere of argon and nitrogen. The value of _x in SiN _x can be changed by changing the sputtering conditions (such as the gas flow ratio between argon and nitrogen). Next, a fourth electrode layer 122 ′ before pattern formation, for example, a TaN layer having a thickness of 50 nm, is formed by sputtering in the same manner as the third electrode layer 121 ′ before pattern formation.

  Next, as shown in FIG. 6B, the third electrode layer 121 ′ before pattern formation, the current control layer 123 ′ before pattern formation, and the fourth electrode layer 122 ′ before pattern formation are patterned. Thus, the current control element 104 composed of the third electrode 121, the current control layer 123, and the fourth electrode 122 is formed (FIGS. 6A to 6B: step of forming the current control element). .

Next, as shown in FIG. 7, the third plug 107 is formed in the same manner as the second plug 106. That is, the third interlayer insulating layer 110 made of, for example, SiO ₂ is formed by a thermal oxidation method. Further, a contact hole is formed so as to penetrate the third interlayer insulating layer 110 and reach the fourth electrode 122, and a tantalum silicon oxide layer, a Ti layer, a TiN layer, and tungsten (W) are stacked in this order inside the contact hole. The third plug 107 is formed by removing the excess layer by CMP until the third interlayer insulating layer 110 is exposed. Thereafter, the second wiring 102 is formed of, for example, aluminum (step of forming a third plug and a second wiring).

  The variable resistance nonvolatile memory cell 100 can be manufactured by the above method.

[First Modification]
FIG. 11 is a side cross-sectional view showing an example of a schematic configuration of a variable resistance nonvolatile memory cell according to a first modification of the first embodiment.

  As illustrated in FIG. 11, the variable resistance nonvolatile memory cell 100 </ b> A according to the first modification includes a first plug 105, a second plug 106, and a third plug 107 in the variable resistance nonvolatile memory cell 100. The first low resistance plug 143, the second low resistance plug 148, and the fourth plug 107D are replaced.

  The first low resistance plug 143 is obtained by omitting the first load resistance portion 131 </ b> A from the first plug 105, and the adhesion layer 132 is in direct contact with the first wiring 101. The second low resistance plug 148 is obtained by omitting the second load resistance portion 131B from the second plug 106, and the adhesion layer 132 is in direct contact with the second electrode 112. In the fourth plug 107D, the third load resistance portion 131C is omitted from the third plug 107, the adhesion layer 132 directly contacts the fourth electrode 122, and the fourth load resistance portion 131D formed at the upper end portion of the hole. Have The fourth load resistance portion 131D is in contact with the second wiring 102.

  For example, after forming the adhesion layer 132, the barrier layer 133, and the filling layer 134 in the hole, the fourth load resistance portion 131D forms a recess in the hole by etch back, and uses CVD and CMP for the recess. And can be formed by filling a load resistance material. Since the material of the fourth load resistance portion 131D can be the same as that of the first load resistance portion 131A, detailed description thereof is omitted.

  The variable resistance nonvolatile memory cell 100 </ b> A can have the same configuration as the variable resistance nonvolatile memory cell 100 except for the above points.

[Second Modification]
FIG. 12 is a side cross-sectional view showing an example of a schematic configuration of a variable resistance nonvolatile memory cell according to a second modification of the first embodiment.

  As illustrated in FIG. 12, the variable resistance nonvolatile memory cell 100 </ b> B according to the second modified example includes a first plug 105, a second plug 106, and a third plug 107 in the variable resistance nonvolatile memory cell 100. The first low resistance plug 143, the fifth plug 106E, and the third low resistance plug 149 are replaced.

  Since the first low-resistance plug 143 is the same as that of the first modification, description thereof is omitted. In the fifth plug 106E, the second load resistor 131B is omitted from the second plug 106, the adhesion layer 132 is in direct contact with the second electrode 112, and the fifth load resistor 131E formed at the upper end of the hole is replaced with the fifth plug 106E. Have. The fifth load resistance portion 131E is in contact with the third electrode 121. The third low resistance plug 149 is obtained by omitting the third load resistance portion 131C from the third plug 107, and the adhesion layer 132 is in direct contact with the fourth electrode 122.

  Since the manufacturing method and material of the fifth load resistance portion 131E can be the same as those of the fourth load resistance portion 131D, detailed description thereof is omitted.

  The variable resistance nonvolatile memory cell 100 </ b> B may have the same configuration as the variable resistance nonvolatile memory cell 100 except for the above points.

  A sixth load resistor 131F is formed at the upper end of the hole in which the first low-resistance plug 143 is formed, and the sixth load resistor 131F may be in contact with the first electrode 111 to constitute the sixth plug 105F (illustrated). (Omitted).

  The first load resistor 131A, the second load resistor 131B, the third load resistor 131C, the fourth load resistor 131D, the fifth load resistor 131E, and the sixth load resistor 131F can be arbitrarily combined.

[Third Modification]
FIG. 13 is a side cross-sectional view showing an example of a schematic configuration of a variable resistance nonvolatile memory cell according to a third modification of the first embodiment.

  As shown in FIG. 13, the variable resistance nonvolatile memory cell 140 according to the third modification is formed by integrally forming a variable resistance element and a current control element with an integrated structure without vias. In the variable resistance nonvolatile memory cell 140, the second plug 106 is omitted from the configuration of FIG. 7, and the variable resistance element 103 and the current control element 104 are replaced with an integrated structure 147.

  The unitary structure 147 can be configured as follows. A fifth electrode 145 (lower electrode, film thickness: 5 nm to 100 nm, size: 0.5 μm × 0, for example) is formed on the first interlayer insulating layer 108 so as to cover the upper end surface of the first plug 105. 0.5 μm), current control layer 123, sixth electrode 144 (common electrode, film thickness: for example, 5 nm to 100 nm, size: 0.5 μm × 0.5 μm, for example), resistance change layer 113, seventh electrode 146 (Upper electrode, film thickness: 5 nm to 100 nm, size: 0.5 μm × 0.5 μm, for example) are stacked in this order. Since the current control layer 123 and the resistance change layer 113 can have the same configuration as that of the resistance change nonvolatile memory cell 100, detailed description thereof is omitted. The fifth electrode 145, the current control layer 123, and the sixth electrode 144 constitute a current control element. The sixth electrode 144, the resistance change layer 113, and the seventh electrode 146 constitute a resistance change element.

  A second interlayer insulating layer 109 (for example, a layer made of silicon oxide and having a thickness of 300 nm to 500 nm) is formed so as to cover the integrated structure 147. A third low-resistance plug 149 (diameter: for example, 50 nmΦ or more and 300 nmΦ, mainly composed of tungsten) formed so as to be inscribed in a hole penetrating the second interlayer insulating layer 109 and in contact with the seventh electrode 146. Is formed). Further, the second wiring 102 is formed on the second interlayer insulating layer 109 so as to cover the third low resistance plug 149.

  In the present modification, the first plug 105 is in contact with the lower end surface of the integrated structure 147 composed of a resistance change element and a current control element.

  By forming a nonvolatile memory cell composed of a current control element and a resistance change element as an integral structure, the upper electrode of the current control element and the lower electrode of the resistance change element can be formed as the sixth electrode 144. is there. In addition, the number of masks for elements and the number of masks for plug portions can be reduced, and the manufacturing process can be simplified. Moreover, by forming a high resistance plug in the lower layer portion connected in series with the nonvolatile memory cell, it is possible to divide the voltage at the initial break of the resistance change element.

[Fourth Modification]
FIG. 14 is a side cross-sectional view showing an example of a schematic configuration of a variable resistance nonvolatile memory cell according to a fourth modification of the first embodiment.

  As illustrated in FIG. 14, the variable resistance nonvolatile memory cell 141 according to the fourth modified example includes a first plug 105 and a third low resistance plug 149 in the variable resistance nonvolatile memory cell 140 according to the third modified example. Are replaced by the first low-resistance plug 143 and the third plug 107.

  Each component can be configured in the same manner as described above, and detailed description thereof is omitted.

  In the present modification, the third plug 107 is in contact with the upper end surface of the integrated structure 147 composed of a resistance change element and a current control element.

[Fifth Modification]
FIG. 15 is a side cross-sectional view showing an example of a schematic configuration of a variable resistance nonvolatile memory cell according to a fifth modification of the first embodiment.

  As illustrated in FIG. 15, the variable resistance nonvolatile memory cell 142 according to the fifth modification is the same as the variable resistance nonvolatile memory cell 140 according to the third modification, in which the third low resistance plug 149 is replaced by the third plug 107. Has been replaced.

  Each component can be configured in the same manner as described above, and detailed description thereof is omitted.

  In this modification, the first plug 105 is in contact with the lower end surface of the integrated structure 147 configured by a resistance change element and a current control element, and the third plug 107 is an integrated structure configured by a resistance change element and a current control element. 147 is in contact with the upper end surface.

(Second Embodiment)
The variable resistance nonvolatile memory device according to the second embodiment is a so-called cross-point nonvolatile memory device in which a nonvolatile memory part is interposed at an intersection (a solid intersection) between a word line and a bit line.

  The variable resistance nonvolatile memory device according to the present embodiment includes a variable resistance nonvolatile memory cell including a first wiring, a second wiring, a variable resistance element, and a current control element. The non-volatile memory cell, the plug, the first wiring, and the second wiring are formed so as to be filled.

  In the variable resistance nonvolatile memory device of the present embodiment, the first wiring is on the substrate, a plurality of first wirings are formed in parallel to each other on a plane parallel to the main surface of the substrate, and the second wiring is above the plane. A first wiring corresponding to each of the three-dimensional intersections of the plurality of first wirings and the plurality of second wirings; A variable resistance nonvolatile memory cell may be formed so as to be electrically connected to the second wiring.

  As the variable resistance nonvolatile memory cell included in the variable resistance nonvolatile memory device according to the present embodiment, the variable resistance nonvolatile memory cell according to the first embodiment or the modification thereof can be used.

[Configuration of non-volatile storage device]
FIG. 16 is a block diagram illustrating an example of a schematic configuration of a variable resistance nonvolatile memory device according to the second embodiment. FIG. 17 is a schematic perspective view in which the portion A of FIG. 16 is enlarged.

  As shown in FIG. 16, the variable resistance nonvolatile memory device 200 includes a memory main body 201 on a semiconductor substrate. The memory main body 201 includes a memory array 202, a row selection circuit / driver 203, A column selection circuit / driver 204, a write circuit 205 for writing information, a sense amplifier 206 for detecting the amount of current flowing through the selected bit line and discriminating data “1” or “0”; and a terminal DQ And a data input / output circuit 207 for performing input / output processing of the input / output data via the.

  The variable resistance nonvolatile memory device 200 also includes an address input circuit 208 that receives an address signal input from the outside, and a control circuit 209 that controls the operation of the memory body 201 based on the control signal input from the outside. And further.

  As shown in FIGS. 16 and 17, the memory array 202 includes a plurality of word lines WL0, WL1, WL2,... Formed in parallel to each other on a semiconductor substrate, and these word lines WL0, WL1, WL2,. A plurality of bits formed so as to be parallel to each other in a plane parallel to the main surface of the semiconductor substrate and to form a three-dimensional intersection (orthogonal in the present embodiment) with the plurality of word lines WL0, WL1, WL2,. Lines BL0, BL1, BL2,.

  Further, a plurality of variable resistance nonvolatile memory cells M211, M212, M213 provided in a matrix corresponding to the intersections of these word lines WL0, WL1, WL2,... And bit lines BL0, BL1, BL2,. M221, M222, M223, M231, M232, M123,... (Hereinafter referred to as “memory cells M211, M212,...”) Are provided.

  Note that memory cells M211, M212,... In FIG. Details of the configuration of the variable resistance nonvolatile memory cell 150 will be described later.

  The address input circuit 208 receives an address signal from an external circuit (not shown), outputs a row address signal to the row selection circuit / driver 203 based on the address signal, and outputs a column address signal to the column selection circuit / driver 204. Output to. Here, the address signal is a signal indicating the address of a specific memory cell selected from among the plurality of memory cells M211, M212,. The row address signal is a signal indicating a row address among the addresses indicated by the address signal, and the column address signal is also a signal indicating a column address.

  In the information write cycle, the control circuit 209 outputs a write signal instructing application of a write voltage to the write circuit 205 in accordance with the input data Din input to the data input / output circuit 207. On the other hand, in the information read cycle, the control circuit 209 outputs a read signal for instructing a read operation to the column selection circuit / driver 204.

  The row selection circuit / driver 203 receives the row address signal output from the address input circuit 208, selects one of the plurality of word lines WL0, WL1, WL2,... According to the row address signal, A predetermined voltage is applied to the selected word line.

  Further, the column selection circuit / driver 204 receives the column address signal output from the address input circuit 208, and selects one of the plurality of bit lines BL0, BL1, BL2,... According to the column address signal. Then, a write voltage or a read voltage is applied to the selected bit line.

  When the write circuit 205 receives the write signal output from the control circuit 209, the write circuit 205 outputs a signal for instructing the row selection circuit / driver 203 to apply a voltage to the selected word line, and the column selection circuit / A signal instructing the driver 204 to apply a write voltage to the selected bit line is output.

  Further, the sense amplifier 206 detects the amount of current flowing through the selected bit line to be read in the information read cycle, and determines data “1” or “0”. The output data DO obtained as a result is output to an external circuit via the data input / output circuit 207.

  By operating as described above, the variable resistance nonvolatile memory device 200 realizes reading and writing with respect to a nonvolatile memory cell to be described later.

  Note that it is also possible to realize a nonvolatile memory device having a multilayer structure by stacking the memory arrays in the nonvolatile memory device according to the present embodiment shown in FIGS. 16 and 17 three-dimensionally. By providing the multi-layered memory array configured as described above, it is possible to realize an ultra-large capacity nonvolatile memory device.

[Configuration of non-volatile memory cell]
Hereinafter, the configuration of the nonvolatile element of the second embodiment will be exemplified.

FIG. 18 is a cross-sectional view showing an example of the configuration of the variable resistance nonvolatile memory cell according to the second embodiment of the present invention. Note that FIG. 18 shows a configuration in the B part of FIG. As shown in FIG. 18, the variable resistance nonvolatile memory cell 150 according to the second embodiment includes a lower wiring 212 made of aluminum wiring or the like (first wiring: corresponding to the word line WL1 in FIGS. 16 and 17). And the lower wiring at the intersection with the upper wiring 211 (second wiring: corresponding to the bit line BL1 in FIGS. 16 and 17), which is also made of aluminum wiring or the like and arranged to be orthogonal to the lower wiring 212. 212 and the upper wiring 211 are connected to each other. In the variable resistance nonvolatile memory cell 150, a first plug 105 having a load resistance portion is formed on a lower wiring 212, and a current control element and a variable resistance element are connected in series with the first plug 105. A structure 147 is formed. A current control layer 123 (for example, composed of silicon nitride (SiN _z )) is formed on the fifth electrode 145 (lower electrode) of the integrated structure 147 of the current control element and the resistance change element. On the layer 123, a sixth electrode 144 (common electrode: composed of, for example, tantalum nitride (TaN)) is formed. The sixth electrode 144 also functions as a lower electrode of the resistance change element. A sixth electrode 144 and a seventh electrode 146 (upper electrode: made of, for example, iridium) and a resistance change layer 113 sandwiched between these electrodes are provided.

As in the case of the first embodiment, the resistance change layer 113 includes a low resistance layer 114 made of an oxygen-deficient transition metal oxide, and a high resistance that has a lower oxygen deficiency and a higher resistance than the low resistance layer 114. A layered structure of layers 115 is formed. When the low resistance layer 114 and the high resistance layer 115 are made of the same type of transition metal, the composition of the transition metal oxide of the low resistance layer 114 is MO _x and the composition of the transition metal oxide of the high resistance layer 115 is MO. _{When y} is satisfied, x <y is established. In the present embodiment, the high resistance layer 115 and the low resistance layer 114 are both made of tantalum (Ta) oxide, the composition of the low resistance layer 114 is TaO _x, and the composition of the high resistance layer 115 is TaO _y. In this case, adjustment is made so that x is 0.8 or more and 1.9 or less and y is 2.1 or more and less than 2.5. A third plug 107 having a load resistance portion is arranged in series on the integrated structure 147 of the current control element and the resistance change element, and is connected to the upper wiring 211 via the third plug 107. Here, the interface between the current control layer 123 and the fifth electrode 145 and the interface between the current control layer 123 and the sixth electrode 144 function as a Schottky barrier. Silicon nitride (SiN _z ) behaves like a semiconductor when the value of z is small, depending on the nitrogen composition z, and as an insulator when it is large. In the case of having semiconductor characteristics, a larger current can be obtained than in the case of having insulating characteristics. For example, when the z range of SiN _z is 0 <z ≦ 0.85, a current density of 10000 A / cm ² or more can be obtained by adjusting the film thickness of the current control layer 123. Note that the fifth electrode 145 and the sixth electrode 144 may be any material whose interface functions as a Schottky barrier with respect to silicon nitride (SiN _z ). For example, α-tungsten (W) or titanium nitride (TiN) having a body-centered cubic (bcc) structure in addition to TaN that is stable against heat generated by a current flowing when the resistance change layer 113 undergoes resistance change. Refractory metals such as these and nitrides thereof can also be used. The fifth electrode 145 and the sixth electrode 144 need not be the same material, and may be different materials.

In the present embodiment, since the current control layer 123 is formed of a semiconductor layer as described above, the stacked structure of the fifth electrode 145, the current control layer 123, and the sixth electrode 144 has an MSM (metal / semiconductor / It functions as a (metal) diode. Note that the present invention is not limited to this, and the current control layer 123 is formed of an insulator layer, and the stacked structure of the fifth electrode 145, the current control layer 123, and the sixth electrode 144 is MIM. It may function as a (metal / insulator / metal) diode. As the insulator in this case, SiO ₂ , Si ₃ N ₄ , Ta ₂ O ₅ or the like can be used.

The first plug 105 and the third plug 107 having a load resistance portion are composed of a first load resistance portion 131A and a third load resistance portion 131C made of Ta—SiO ₂ , an adhesion layer made of Ti, and TiN. After the formed barrier layer is formed, W is filled therein.

  Although the load resistance plug having the load resistance portion described in this embodiment is arranged at both the lower and upper portions of the nonvolatile memory cell, the via formed between the lower wiring and the upper wiring functions as a load resistance as a whole. The load resistance portion may be formed only on one side of the upper layer and the lower layer.

Tantalum silicon oxide (Ta—SiO ₂ ) was used as the high resistance film used for the high resistance plug, but oxygen-deficient tungsten oxide (WO _x ) and niobium oxide (NbO _x ) were used instead. Alternatively, tantalum oxide (TaO _x ) or the like may be used.

  In such a cross-point structure, when a 1-bit current control element is destroyed, not only the destroyed current control element but also other bits malfunction. Furthermore, a detour current affects other bits, and the destruction bit does not function. In addition, a write disturb due to a detour current to the element performing normal operation also occurs. By forming the load resistance portion in each bit, it is possible to prevent the current control element from being destroyed, to realize a stable operation after the initial break, to prevent variations, and to improve reliability. In particular, since the probability of malfunction of some bits of a gigabit (Gbit) class large capacity memory can be extremely reduced, a large capacity nonvolatile memory can be realized.

  From the foregoing description, many modifications and other embodiments of the present invention are obvious to one skilled in the art. Accordingly, the foregoing description should be construed as illustrative only and is provided for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details of the structure and / or function may be substantially changed without departing from the spirit of the invention.

  The variable resistance nonvolatile memory cell and the variable resistance nonvolatile memory device are useful as a variable resistance nonvolatile memory cell and a variable resistance nonvolatile memory device in which the current control element is not easily destroyed in the initial break process.

100 variable resistance nonvolatile memory cell 101 first wiring 102 second wiring 103 variable resistance element 104 current control element 105 first plug 105F sixth plug 106 second plug 106E fifth plug 107 third plug 107D fourth plug 108 first 1st interlayer insulation layer 109 2nd interlayer insulation layer 110 3rd interlayer insulation layer 111 1st electrode 111 '1st electrode layer before pattern formation 112 2nd electrode 112' 2nd electrode layer before pattern formation 113 Resistance change layer 114 Low Resistance layer 114 ′ Low resistance layer before pattern formation 115 High resistance layer 115 ′ High resistance layer before pattern formation 121 Third electrode 121 ′ Third electrode layer before pattern formation 122 Fourth electrode 122 ′ Fourth before pattern formation Electrode layer 123 Current control layer 123 ′ Current control layer 130 before pattern formation 130 Contact hole 13 DESCRIPTION OF SYMBOLS 1A 1st load resistance part 131B 2nd load resistance part 131C 3rd load resistance part 131D 4th load resistance part 131E 5th load resistance part 131F 6th load resistance part 132 Adhesion layer 133 Barrier layer 134 Filling layer 140 Resistance change non-volatile Volatile memory cell 141 variable resistance nonvolatile memory cell 142 variable resistance nonvolatile memory cell 143 first low resistance plug 144 sixth electrode 145 fifth electrode 146 seventh electrode 147 integrated structure 148 second low resistance plug 149 third low resistance Resistive plug 150 Variable resistance nonvolatile memory cell 200 Variable resistance nonvolatile memory device 201 Memory body 202 Memory array 203 Row selection circuit / driver 204 Column selection circuit / driver 205 Write circuit 206 Sense amplifier 207 Data input / output circuit 208 Address Input circuit 20 DESCRIPTION OF SYMBOLS 9 Control circuit 211 Upper wiring 212 Lower wiring WL0, WL1, WL2, ... Word line BL0, BL1, BL2, ... Bit line M211, M212, ... Memory cell

Claims (14)

A resistance change element that reversibly transitions between a plurality of resistance states having different resistance values by applying electrical signals having different polarities;
A current control element connected in series to the variable resistance element and having a non-linear voltage-current characteristic in which the slope of the voltage-current curve increases as the absolute value of the applied voltage increases in a predetermined applied voltage range;
A plug formed in a hole penetrating the interlayer insulating layer, in contact with at least one of the variable resistance element or the current control element, and having a load resistance portion;
The load resistance portion is at least selected from the group consisting of tantalum silicon oxide (Ta—SiO ₂ ), tungsten oxide (WO _x ), niobium oxide (NbO _x ), and tantalum oxide (TaO _x ). Composed of one material,
Variable resistance nonvolatile memory cell. The resistance change element and the current control element each include an electrode,
The plug is in contact with at least one of the resistance change element and the current control element;
2. The variable resistance nonvolatile memory cell according to claim 1, wherein the electrode is configured to spread outward from the contact portion in a whole periphery of a contact portion with the plug.   The variable resistance nonvolatile memory cell according to claim 2, wherein the electrode and the load resistance portion are connected by an ohmic junction.   The variable resistance element and the current control element are formed so as to form an integral structure without vias, and the plug is connected to an upper end surface of the integral structure including the variable resistance element and the current control element. 4. The variable resistance nonvolatile memory cell according to claim 1.   The variable resistance element and the current control element are formed so as to form an integral structure without vias, and the plug is connected to a lower end surface of the integral structure composed of the variable resistance element and the current control element. 4. The variable resistance nonvolatile memory cell according to claim 1. A first wiring;
A second wiring;
A variable resistance nonvolatile memory cell according to claim 1,
The interlayer insulating layer, the resistance change element, the current control element, and the plug are formed between the first wiring and the second wiring;
A variable resistance nonvolatile memory device. A plurality of the first wires are formed in parallel to each other in the same plane,
The second wiring is formed above the plane so as to intersect the plurality of first wirings in parallel with each other in a plane parallel to the plane,
The variable resistance nonvolatile memory cell is configured to electrically connect the first wiring and the second wiring corresponding to each of the three-dimensional intersections of the plurality of first wirings and the plurality of second wirings. Formed,
The variable resistance nonvolatile memory device according to claim 6. A resistance change element that reversibly transitions between a plurality of resistance states having different resistance values by applying electrical signals having different polarities;
A current control element connected in series to the variable resistance element and having a non-linear voltage-current characteristic in which the slope of the voltage-current curve increases as the absolute value of the applied voltage increases in a predetermined applied voltage range;
A plug formed in a hole penetrating the interlayer insulating layer, in contact with at least one of the variable resistance element or the current control element, and having a load resistance portion;
The resistance value of the plug is 170Ω or more,
Variable resistance nonvolatile memory cell. The resistance value of the plug is 2 kΩ or more,
The variable resistance nonvolatile memory cell according to claim 8. The resistance change element and the current control element each include an electrode,
The plug is in contact with at least one of the resistance change element and the current control element;
10. The variable resistance nonvolatile memory cell according to claim 8, wherein the electrode is configured to spread outward from the contact portion in the entire periphery of the contact portion with the plug. 11.   The variable resistance element and the current control element are formed so as to form an integral structure without vias, and the plug is connected to an upper end surface of the integral structure including the variable resistance element and the current control element. The variable resistance nonvolatile memory cell according to claim 8.   The variable resistance element and the current control element are formed so as to form an integral structure without vias, and the plug is connected to a lower end surface of the integral structure composed of the variable resistance element and the current control element. The variable resistance nonvolatile memory cell according to claim 8. A first wiring;
A second wiring;
A variable resistance nonvolatile memory cell according to claim 8,
The interlayer insulating layer, the resistance change element, the current control element, and the plug are formed between the first wiring and the second wiring;
A variable resistance nonvolatile memory device. A plurality of the first wires are formed in parallel to each other in the same plane,
The second wiring is formed above the plane so as to intersect the plurality of first wirings in parallel with each other in a plane parallel to the plane,
The variable resistance nonvolatile memory cell is configured to electrically connect the first wiring and the second wiring corresponding to each of the three-dimensional intersections of the plurality of first wirings and the plurality of second wirings. Formed,
The variable resistance nonvolatile memory device according to claim 13.