JP2012064715A - Semiconductor wafer, semiconductor circuit, and method of manufacturing semiconductor circuit - Google Patents

Abstract

In manufacturing a WLBGA, a semiconductor circuit in which chipping due to stress after mounting does not occur is provided by preventing members other than silicon from being exposed in a dicing section.
A semiconductor circuit manufacturing method according to the present invention is a semiconductor circuit manufacturing method for manufacturing a plurality of semiconductor circuits from a semiconductor wafer in which a plurality of semiconductor chips are mounted on a silicon substrate, and around each semiconductor chip. Dicing along the scribe line by a dicing cutter with a space equivalent to or slightly larger than the width of the scribe line provided with a space made of silicon only between the seal part that protects the enclosed semiconductor chip and the scribe line This is a method for manufacturing a semiconductor circuit.
[Selection] Figure 3

Description

  The present invention relates to a technique for manufacturing a semiconductor circuit on which a semiconductor chip is mounted from a semiconductor wafer on which a plurality of semiconductor circuits are formed.

  In manufacturing a semiconductor circuit including a dicing process, measures for improving chipping in a process after dicing are already known. For example, the silicon surface is exposed by a laser to the portion that becomes the chip end after dicing of the scribe line, and then dicing is performed.

  However, the above improvement measures do not solve the following problems. Like WLBGA (referred to as Wafer Level Ball Grid Array or Wafer Level Chip Size Package), it has external connection terminals on one side and has the same external dimensions as the semiconductor chip to be mounted. In a semiconductor device (semiconductor package), dicing on the scribe line exposes other than silicon such as metal to the dicing section.

  That is, on the WLBGA scribe line, usually, semiconductor elements such as resistance elements and transistors for monitoring the results of the manufacturing process are mounted. These elements are formed on the silicon substrate by using polysilicon or metal. Etc. If a member other than silicon, such as metal, is exposed in the dicing section, chipping occurs from a portion where the member other than silicon is exposed due to stress after mounting. The post-mounting stress is generated, for example, by applying a reinforcing resin (underfill) to the entire substrate in order to increase the mounting strength.

  For example, Patent Document 1 below discloses a technique for protecting a semiconductor chip by providing a space between a dicing region and the inside of a chip for the purpose of preventing chipping due to dicing. However, even in this technique, the above-described problem that chipping occurs due to stress after mounting due to exposure of members other than silicon on the dicing cross section cannot be solved. In the prior art disclosed in Patent Document 1, it is considered that silicon, oxide film, and metal are exposed on the dicing surface.

  An object of the present invention is to provide a semiconductor circuit that prevents a member other than silicon from being exposed in a dicing cross section during manufacture of a WLBGA and suppresses occurrence of chipping due to stress after mounting.

The present invention has been made to achieve the above object. According to a first aspect of the present invention, there is provided a semiconductor circuit manufacturing method comprising:
A semiconductor circuit manufacturing method for manufacturing a plurality of semiconductor circuits from a semiconductor wafer comprising a plurality of semiconductor chips mounted on a silicon substrate,
A space portion made only of silicon is provided between the seal portion that surrounds each semiconductor chip and protects the semiconductor chip, and the scribe line,
Dicing along the scribe line with a dicing cutter having a width equal to or slightly larger than the width of the scribe line,
A semiconductor circuit manufacturing method.

A semiconductor wafer according to claim 2 of the present invention is
A semiconductor wafer in which a plurality of semiconductor circuits are formed based on a silicon substrate on which a plurality of semiconductor chips are mounted,
This is a semiconductor wafer in which a space portion made of only silicon is provided between a scribe line and a seal portion that surrounds each semiconductor chip and protects the semiconductor chip.

The semiconductor wafer according to claim 3 of the present invention is
3. The semiconductor wafer according to claim 2, wherein the width of the scribe line is 40 microns or less.

According to a fourth aspect of the present invention, there is provided a semiconductor circuit comprising:
A semiconductor circuit manufactured by dicing a semiconductor wafer according to claim 2 or 3 with a dicing cutter having a width equal to or larger than a width of a scribe line,
This is a semiconductor circuit in which only silicon is exposed on the cut surface after dicing.

A semiconductor circuit manufacturing method according to claim 5 of the present invention is
A semiconductor circuit manufacturing method for manufacturing a plurality of semiconductor circuits from a semiconductor wafer comprising a plurality of semiconductor chips mounted on a silicon substrate,
Between the semiconductor chip included in each semiconductor circuit and the scribe line, a space portion made only of silicon is provided,
Dicing along the scribe line with a dicing cutter having a width equal to or slightly larger than the width of the scribe line,
A semiconductor circuit manufacturing method.

A semiconductor wafer according to claim 6 of the present invention is
A semiconductor wafer in which a plurality of semiconductor circuits are formed based on a silicon substrate on which a plurality of semiconductor chips are mounted,
This is a semiconductor wafer in which a space portion made of only silicon is provided between a semiconductor chip included in each semiconductor circuit and a scribe line.

A semiconductor wafer according to claim 7 of the present invention is
7. The semiconductor wafer according to claim 6, wherein the width of the scribe line is 40 microns or less.

The semiconductor circuit according to claim 8 according to the present invention includes:
A semiconductor circuit manufactured by dicing a semiconductor wafer according to claim 6 or 7 by a dicing cutter having a width equal to or larger than a width of a scribe line,
This is a semiconductor circuit in which only silicon is exposed on the cut surface after dicing.

  By utilizing the present invention, when manufacturing WLBGA, it is possible to prevent exposure of members other than silicon to the dicing cross section, and thus it is possible to provide a semiconductor circuit that suppresses chipping due to stress during mounting. it can. Further, by utilizing the present invention, it is possible to avoid exposing members other than silicon to the dicing section only by dicing along the scribe line in the semiconductor wafer, that is, by simple work.

1 is a plan view of a semiconductor wafer according to a preferred embodiment and a partially enlarged view of the plan view. It is a top view which shows the arrangement | positioning relationship between the semiconductor circuit which concerns on suitable embodiment, and a scribe line, and is a one part enlarged view of the semiconductor wafer shown in FIG. FIG. 3 is a side sectional view of FIG. 2 taken along a vertical plane passing through the line segment AA ′ of FIG. It is a sectional side view which shows the arrangement | positioning relationship between the semiconductor circuit which concerns on suitable embodiment, and a scribe line, and has shown the state which has fallen to the lowest position for the dicing cutter.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

  The layout creation of the semiconductor circuit and the dicing of the chip of the semiconductor circuit of this embodiment will be described below.

  In the semiconductor circuit of the present embodiment, a space portion is provided between the seal portion that surrounds the semiconductor chip and protects the semiconductor chip, and the scribe line. This space portion is formed only of silicon, and no semiconductor element is disposed. Furthermore, it is cut along the scribe line by a dicing cutter having a cutting width equal to or slightly larger than the width of the scribe line. By this dicing, the space portion becomes a dicing cross section, so that members other than silicon are not exposed in the dicing cross section. In other words, by adjusting the width of the scribe line and the width of the dicing, or by increasing the width of the dicing (slightly), all the scribe lines are removed, and other than silicon is not exposed in the dicing section.

  The present embodiment will be described in detail with reference to the drawings. FIG. 1 is a plan view of a semiconductor wafer 20 according to the present embodiment and a partially enlarged view of the plan view. The semiconductor wafer 20 has a semiconductor element region 1 in which a semiconductor circuit is formed and a scribe line region 2 on a substrate made of silicon. A plurality of semiconductor circuits 3 are formed on the semiconductor wafer 20, and are cut along the scribe line region 2, thereby creating a large number of semiconductor circuits 3 each including a semiconductor chip.

  FIG. 2 is a plan view showing the positional relationship between the semiconductor circuit 3 and the scribe line 2 according to this embodiment, and is an enlarged view of a part of the semiconductor wafer 20 shown in FIG. 3 is a side cross-sectional view of FIG. 2 taken along a vertical plane passing through the line segment AA ′ of FIG. 2, and is a side cross-sectional view showing the positional relationship between the semiconductor circuit 3 and the scribe line 2 according to the present embodiment. is there. Each semiconductor circuit includes a semiconductor chip 6, a ring-shaped seal portion 8 that surrounds the semiconductor chip 6 and protects the semiconductor chip 6, and a silicon substrate 10.

  As shown in FIGS. 2 and 3, a scribe line 2 is provided between the individual semiconductor circuits 3. In each semiconductor circuit 3, between the semiconductor chip 6 and the scribe line 2, a seal portion 8 that is made of metal (encloses the semiconductor chip 6) and has a ring-shaped layout is disposed. A space portion 4 is disposed between the seal portion 8 and the scribe line 2. This space portion 4 is a region in which no semiconductor element is arranged during manufacturing of a semiconductor device. That is, the space portion 4 is formed only of silicon.

  When dicing the semiconductor wafer 20, the dicing line 2 and the silicon substrate 10 immediately below the dicing line 2 are cut by a dicing cutter 12, as shown in FIG. The dicing cutter 12 is a means for performing crushing processing by rotating at high speed an annular dicing saw in which particles such as diamond are held on the blade edge by a bond material.

  FIG. 4 is a side sectional view showing the positional relationship between the semiconductor circuit 3 and the scribe line 2 according to the present embodiment as in FIG. 3, but the dicing cutter 12 is lowered to the lowest position for cutting. Show.

  As shown in FIGS. 3 and 4, the semiconductor circuit 3 is formed on the silicon substrate 10, but no semiconductor element is disposed between the seal portion 8 of the semiconductor circuit 3 and the scribe line 2. Only silicon is present.

  Further, the dicing cutter 12 has a width equal to or slightly wider than the scribe line 2. By dicing with such a dicing cutter 12, the semiconductor elements included in the scribe line, and further, members such as polysilicon and metal constituting the semiconductor elements are completely removed. That is, as shown in particular in FIG. 4, the entire width of the scribe line 2 is cut off.

  Therefore, only silicon is exposed on the cut surface of the semiconductor circuit after dicing by the dicing cutter 12. As a result, it is possible to solve the problem that chipping occurs from a portion where a member other than silicon is exposed due to stress after mounting.

  As the width of the dicing cutter 12 and the width of the scribe line 2, those of about 40 microns are usually employed. Accordingly, the dicing cutter according to a preferred embodiment of the present invention preferably has a width of at least 40 microns (for example, a width of 50 microns). The scribe line according to a preferred embodiment of the present invention preferably has a width of 40 microns or less (for example, a width of 35 microns).

  In the embodiment shown in FIGS. 2 to 4, the seal portion 8 that protects the semiconductor chip 6 is provided on the semiconductor circuit 3, but the present invention can also be applied to a semiconductor wafer 20 without the seal portion 8. It is. At this time, it is sufficient that a sufficient space portion 4 is provided between the semiconductor chip and the scribe line 2.

  By using the embodiment according to the present invention, it is possible to avoid exposing a member other than silicon to the dicing section only by performing a dicing operation along the scribe line 2 in the semiconductor wafer 20.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor element area | region, 2 ... Scribe line, 3 ... Semiconductor circuit, 4 ... Space part, 6 ... Semiconductor chip, 8 ... Seal part, 10 ... Silicon substrate, 12 ... dicing cutter, 20 ... semiconductor wafer.

Japanese Patent Laid-Open No. 2007-067372

Claims (8)

A semiconductor circuit manufacturing method for manufacturing a plurality of semiconductor circuits from a semiconductor wafer comprising a plurality of semiconductor chips mounted on a silicon substrate,
A space portion made only of silicon is provided between the seal portion that surrounds each semiconductor chip and protects the semiconductor chip, and the scribe line,
Dicing along the scribe line with a dicing cutter having a width equal to or slightly larger than the width of the scribe line,
Semiconductor circuit manufacturing method. A semiconductor wafer in which a plurality of semiconductor circuits are formed based on a silicon substrate on which a plurality of semiconductor chips are mounted,
A semiconductor wafer in which a space portion made of only silicon is provided between a scribe line and a seal portion that surrounds each semiconductor chip and protects the semiconductor chip.   The semiconductor wafer according to claim 2, wherein the width of the scribe line is 40 microns or less. A semiconductor circuit manufactured by dicing a semiconductor wafer according to claim 2 or 3 with a dicing cutter having a width equal to or larger than a width of a scribe line,
A semiconductor circuit in which only silicon is exposed on the cut surface after dicing. A semiconductor circuit manufacturing method for manufacturing a plurality of semiconductor circuits from a semiconductor wafer comprising a plurality of semiconductor chips mounted on a silicon substrate,
Between the semiconductor chip included in each semiconductor circuit and the scribe line, a space portion made only of silicon is provided,
Dicing along the scribe line with a dicing cutter having a width equal to or slightly larger than the width of the scribe line,
Semiconductor circuit manufacturing method. A semiconductor wafer in which a plurality of semiconductor circuits are formed based on a silicon substrate on which a plurality of semiconductor chips are mounted,
A semiconductor wafer in which a space portion made of only silicon is provided between a semiconductor chip included in each semiconductor circuit and a scribe line.   7. The semiconductor wafer according to claim 6, wherein the width of the scribe line is 40 microns or less. A semiconductor circuit manufactured by dicing a semiconductor wafer according to claim 6 or 7 by a dicing cutter having a width equal to or larger than a width of a scribe line,
A semiconductor circuit in which only silicon is exposed on the cut surface after dicing.

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