JP2012189877A - Array substrate, liquid crystal display device, and manufacturing method of the array substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an array substrate having high manufacturing yield, a liquid crystal display device, and a manufacturing method of the array substrate.SOLUTION: An array substrate includes: a plurality of auxiliary capacitance electrodes 17; a plurality of semiconductor layers 15; a plurality of gate electrodes 20; a plurality of auxiliary capacitance lines 21; an interlayer insulation film 22 having a plurality of first contact hole CH1 and a plurality of second contact holes CH2; a plurality of signal lines 27 electrically connected to source areas of the plurality of the semiconductor layers through the plurality of the first contact holes; a plurality of connection electrodes 28 electrically connected to the plurality of the gate electrodes at least through the plurality of the second contact holes, and forming a plurality of scanning lines 19 with the plurality of the gate electrodes; and a plurality of pixel electrode 34. The auxiliary capacitance electrode 17 to which one of the adjacent pixel electrodes 34 is connected, and the auxiliary capacitance electrodes 17 to which the other pixel electrode 34 is connected are oppose to each other over the scanning line 19.

Description

  Embodiments described herein relate generally to an array substrate, a liquid crystal display device, and a method for manufacturing the array substrate.

  In general, a liquid crystal display device, an organic EL display device, or the like is used as an image display device. For example, liquid crystal display devices are used in displays for mobile phones, smartphones, PDAs, personal computers, and the like, taking advantage of thinness, light weight, and low power consumption. The liquid crystal display device includes an array substrate on which pixel switching TFTs (thin film transistors) and auxiliary capacitance elements are formed, a counter substrate disposed opposite to the array substrate, and a liquid crystal layer sandwiched between the array substrate and the counter substrate. It has.

  The structure of the TFT is roughly classified into a bottom gate / inverted stagger type generally used for amorphous silicon TFTs and a top gate / coplanar type commonly used for single crystal silicon MOSFETs. The top gate / coplanar type is more dominant than the bottom gate / inverted stagger type in many cases, and has become mainstream.

  When the top gate coplanar type is used for the TFT structure, the semiconductor layer is etched into an island shape, a gate insulating film is formed so as to cover it, and then a scanning line including the gate electrode is formed. It is common.

  Further, after forming the scanning line, an impurity such as P (phosphorus) or B (boron) is passed through the gate insulating film to adjust the carrier concentration in the source / drain region and the LDD (Lightly Doped Drain) region. Implant (ion implantation) into a certain semiconductor layer. Thereafter, an interlayer insulating film is formed, contact holes are opened to expose the source / drain regions, and signal lines electrically connected thereto are formed.

  When the contact hole is formed in the interlayer insulating film, the array substrate is placed on a stage having the electrostatic chuck electrode and the He cooling groove, and the array substrate is electrostatically chucked by applying a voltage to the electrostatic chuck electrode. Done in state.

JP 7-225394 A

  By the way, when a voltage is applied to the electrostatic chuck electrode, there may be a difference between an increase in the potential of the auxiliary capacitance element and an increase in the gate electrode (scanning line) due to the TFT unit capacitance. This phenomenon occurs at the boundary between the electrostatic chuck electrode and the He cooling groove. When the above phenomenon occurs, the gate insulating film is more likely to cause ESD (Electro Static Discharge) breakdown. When the gate insulating film causes ESD breakdown, the semiconductor layer and the gate electrode are short-circuited, and the TFT is damaged.

  The present invention has been made in view of the above points, and an object thereof is to provide an array substrate, a liquid crystal display device, and a method for manufacturing the array substrate, which have a high manufacturing yield.

An array substrate according to an embodiment is:
A plurality of auxiliary capacitance electrodes;
A plurality of semiconductor layers each having a source region and a drain region connected to the storage capacitor electrode;
A plurality of gate electrodes intersecting with the plurality of semiconductor layers via a gate insulating film and forming a plurality of thin film transistors together with the plurality of semiconductor layers;
A plurality of auxiliary capacitance lines that are arranged opposite to the plurality of auxiliary capacitance electrodes via the gate insulating film and form a plurality of auxiliary capacitance elements together with the plurality of auxiliary capacitance electrodes;
A plurality of first contact holes and a plurality of gate electrodes formed on the plurality of storage capacitor electrodes, a plurality of semiconductor layers, a plurality of gate electrodes, and a plurality of storage capacitor lines, respectively, facing the source regions of the plurality of semiconductor layers. An interlayer insulating film having a plurality of opposing second contact holes;
A plurality of gate electrodes and a plurality of auxiliary capacitance lines that intersect with each other through the interlayer insulating film and are electrically connected to source regions of the plurality of semiconductor layers through at least the plurality of first contact holes. A signal line;
The plurality of gate electrodes are arranged to face each other through the interlayer insulating film, and are electrically connected to the plurality of gate electrodes through at least the plurality of second contact holes, and a plurality of scanning lines together with the plurality of gate electrodes. A plurality of connection electrodes forming
A plurality of pixel electrodes electrically connected to the plurality of auxiliary capacitance electrodes,
The storage capacitor electrode to which one adjacent pixel electrode is connected and the storage capacitor electrode to which the other pixel electrode is connected are opposed to each other across the scanning line.

In addition, a liquid crystal display device according to an embodiment
An array substrate;
A counter substrate disposed opposite to the array substrate with a gap;
A liquid crystal layer sandwiched between the array substrate and the counter substrate,
The array substrate is
A plurality of auxiliary capacitance electrodes;
A plurality of semiconductor layers each having a source region and a drain region connected to the storage capacitor electrode;
A plurality of gate electrodes intersecting with the plurality of semiconductor layers via a gate insulating film and forming a plurality of thin film transistors together with the plurality of semiconductor layers;
A plurality of auxiliary capacitance lines that are arranged opposite to the plurality of auxiliary capacitance electrodes via the gate insulating film and form a plurality of auxiliary capacitance elements together with the plurality of auxiliary capacitance electrodes;
A plurality of first contact holes and a plurality of gate electrodes formed on the plurality of storage capacitor electrodes, a plurality of semiconductor layers, a plurality of gate electrodes, and a plurality of storage capacitor lines, respectively, facing the source regions of the plurality of semiconductor layers. An interlayer insulating film having a plurality of opposing second contact holes;
A plurality of gate electrodes and a plurality of auxiliary capacitance lines that intersect with each other through the interlayer insulating film and are electrically connected to source regions of the plurality of semiconductor layers through at least the plurality of first contact holes. A signal line;
The plurality of gate electrodes are arranged to face each other through the interlayer insulating film, and are electrically connected to the plurality of gate electrodes through at least the plurality of second contact holes, and a plurality of scanning lines together with the plurality of gate electrodes. A plurality of connection electrodes forming
A plurality of pixel electrodes electrically connected to the plurality of auxiliary capacitance electrodes,
The storage capacitor electrode to which one adjacent pixel electrode is connected and the storage capacitor electrode to which the other pixel electrode is connected are opposed to each other across the scanning line.

In addition, the method for manufacturing an array substrate according to an embodiment includes:
A plurality of semiconductor layers having a plurality of storage capacitor electrodes, a plurality of semiconductor layers each having a source region and a drain region connected to the storage capacitor electrode, and a plurality of semiconductor layers intersecting the plurality of semiconductor layers through a gate insulating film And a plurality of gate electrodes that form a plurality of thin film transistors, and a plurality of storage capacitors that are disposed opposite to the plurality of storage capacitors via the gate insulating film and that form a plurality of storage capacitors together with the plurality of storage capacitors Prepare an array substrate under production in which lines are formed,
Forming an interlayer insulating film on the plurality of auxiliary capacitance electrodes, the plurality of semiconductor layers, the plurality of gate electrodes, and the plurality of auxiliary capacitance lines;
On the stage having an electrostatic chuck electrode and an inert gas cooling groove positioned away from the electrostatic chuck electrode, the array substrate on which the interlayer insulating film is formed is placed,
Applying a voltage to the electrostatic chuck electrode, fixing the array substrate to the stage,
In a state where the array substrate is fixed to the stage, the interlayer insulating film is etched, and the plurality of first contact holes and the plurality of gates facing the source regions of the plurality of semiconductor layers are formed in the interlayer insulating film. Forming a plurality of second contact holes facing the electrodes;
After the array substrate is lowered from the stage, the plurality of gate electrodes and the plurality of auxiliary capacitance lines are crossed through the interlayer insulating film, and at least through the plurality of first contact holes, the plurality of semiconductor layers. Forming a plurality of signal lines electrically connected to the source region;
The plurality of gate electrodes are arranged to face each other through the interlayer insulating film, and are electrically connected to the plurality of gate electrodes through at least the plurality of second contact holes, and a plurality of scanning lines together with the plurality of gate electrodes. Forming a plurality of connection electrodes to form
After forming the plurality of signal lines and the plurality of connection electrodes, forming a plurality of pixel electrodes electrically connected to the plurality of auxiliary capacitance electrodes,
When forming the plurality of pixel electrodes, an auxiliary capacitance electrode to which one adjacent pixel electrode is connected and an auxiliary capacitance electrode to which the other pixel electrode is connected face each other across the scanning line. It is characterized by forming.

FIG. 1 is a perspective view showing a liquid crystal display device according to an embodiment. FIG. 2 is a plan view showing the array substrate shown in FIG. FIG. 3 is an enlarged plan view showing a wiring structure of pixels of the array substrate shown in FIGS. 1 and 2, and is a diagram showing two adjacent pixels. FIG. 4 is an equivalent circuit diagram of the pixel shown in FIGS. FIG. 5 is a cross-sectional view showing the liquid crystal display panel taken along line AA in FIG. 3, and is a view showing a TFT. FIG. 6 is a cross-sectional view showing the liquid crystal display panel taken along line BB in FIG. 3, and is a view showing auxiliary capacitance elements. FIG. 7 is a cross-sectional view showing the liquid crystal display panel taken along line CC in FIG. 3, and is a view showing gate electrodes and connection electrodes. FIG. 8 is a plan view showing a part of a stage of an etching apparatus used in the array substrate manufacturing method according to the embodiment. FIG. 9 is a schematic diagram showing an example of the positional relationship between the auxiliary capacitance electrode and the gate electrode with respect to the electrostatic chuck electrode and the He gas cooling groove 102 of the stage.

  Hereinafter, an array substrate, a liquid crystal display device including the array substrate, and a method for manufacturing the array substrate according to an embodiment will be described in detail with reference to the drawings. In this embodiment, the liquid crystal display device employs CCDI (capacitive coupling dot inversion) driving.

  As shown in FIGS. 1 to 7, the liquid crystal display device includes a liquid crystal display panel P and a backlight unit 7. The liquid crystal display panel P includes an array substrate 1, a counter substrate 2 disposed to face the array substrate, and a liquid crystal layer 3 sandwiched between the two substrates. The liquid crystal display panel P has a display region R1 in which the array substrate 1 and the counter substrate 2 overlap. The array substrate 1 has a plurality of pixels 13 arranged in a matrix in the display region R1. The pixel 13 will be described later.

  The array substrate 1 includes, for example, a glass substrate 10 as a transparent insulating substrate. A scanning line driving circuit 4, a signal line driving circuit 5, and an auxiliary capacitance line driving circuit 6 are formed on the glass substrate 10 outside the display region R1. The scanning line driving circuit 4 is connected to a plurality of scanning lines 19 extending outside the display region R1. The scanning line driving circuit 4 outputs a scanning line driving signal to the scanning line 19.

  The signal line drive circuit 5 is connected to a plurality of signal lines 27 extending outside the display region R1. The signal line drive circuit 5 outputs a signal line drive signal to the signal line 27. The auxiliary capacitance line driving circuit 6 is connected to a plurality of auxiliary capacitance lines 21 extending outside the display region R1.

  An undercoating layer 12 is formed on the glass substrate 10. In the display region R1, a plurality of scanning lines 19 extending in the first direction d1 and a plurality of signal lines 27 extending in a second direction d2 orthogonal to the first direction are arranged on the glass substrate 10. . A plurality of auxiliary capacitance lines 21 extending in the first direction d1 and parallel to the scanning lines 19 are formed on the glass substrate 10. In this embodiment, the auxiliary capacitance line 21 functions as a light shielding part. A pixel 13 is formed in each region surrounded by two adjacent signal lines 27 and two adjacent auxiliary capacitance lines 21.

Next, one pixel 13 is taken out and described.
The pixel 13 includes a TFT (thin film transistor) 14 provided in the vicinity of the intersection of the signal line 27 and the scanning line 19, a pixel electrode 34 electrically connected to the TFT 14 and overlapping the scanning line 19, and an electrical connection to the pixel electrode 34. And an auxiliary capacitance element 16 connected to the.

  More specifically, a plurality of semiconductor layers 15 and a plurality of auxiliary capacitance electrodes 17 are formed on the undercoating layer 12. The auxiliary capacitance electrodes 17 are arranged in the first direction d1 and arranged in the second direction d2 at intervals. The semiconductor layer 15 has a drain region RD connected one-to-one to the source region RS and the auxiliary capacitance electrode 17.

  The semiconductor layer 15 and the auxiliary capacitance electrode 17 are simultaneously formed of the same material by patterning the semiconductor film formed on the undercoating layer 12. In this embodiment, the semiconductor layer 15 and the auxiliary capacitance electrode 17 are made of polysilicon. Further, the semiconductor layer 15 and the auxiliary capacitance electrode 17 are integrally formed.

  A gate insulating film 18 is formed on the undercoating layer 12, the semiconductor layer 15, and the auxiliary capacitance electrode 17. A plurality of gate electrodes 20 and a plurality of auxiliary capacitance lines 21 are formed on the gate insulating film 18.

  The gate electrode 20 is positioned with respect to the storage capacitor electrode 17 in the second direction d2, arranged in the first direction d1, and arranged in the second direction d2. The gate electrode 20 intersects the semiconductor layer 15 via the gate insulating film 18, and forms a plurality of TFTs 14 together with the semiconductor layer 15.

  The auxiliary capacitance lines 21 extend in the first direction d1 and are arranged at intervals in the second direction d2. The auxiliary capacitance line 21 is disposed to face the plurality of auxiliary capacitance electrodes 17 with the gate insulating film 18 interposed therebetween, and forms a plurality of auxiliary capacitance elements 16 together with the plurality of auxiliary capacitance electrodes 17. In the region overlapping with the auxiliary capacitance electrode 17, an opening 21 a is formed in each auxiliary capacitance line 21.

  An interlayer insulating film 22 is formed on the plurality of auxiliary capacitance electrodes 17, the plurality of semiconductor layers 15, the plurality of gate electrodes 20, and the plurality of auxiliary capacitance lines 21. The interlayer insulating film 22 has a plurality of first contact holes CH1 facing the source regions RS of the plurality of semiconductor layers 15 and a plurality of second contact holes CH2 facing the plurality of gate electrodes 20. In this embodiment, the first contact hole CH1 is formed not only through the interlayer insulating film 22 but also through the gate insulating film 18.

A plurality of signal lines 27, a plurality of contact electrodes 30, and a plurality of connection electrodes 28 are formed on the interlayer insulating film 22.
The signal lines 27 extend in the second direction d2 and are arranged at intervals in the first direction d1. The signal line 27 intersects the plurality of gate electrodes 20 and the plurality of auxiliary capacitance lines 21 via the interlayer insulating film 22. The signal line 27 is electrically connected to the source regions RS of the plurality of semiconductor layers 15 through the plurality of first contact holes CH1.

  The contact electrode 30 is electrically connected to the auxiliary capacitance electrode 17 through a contact hole 25 penetrating a part of the gate insulating film 18 and the interlayer insulating film 22. The contact hole 25 passes through the opening 21 a of the auxiliary capacitance line 21. For this reason, the insulation state between the contact electrode 30 and the auxiliary capacitance line 21 is maintained. The contact electrode 30 is electrically connected to the drain region RD of the semiconductor layer 15 via the auxiliary capacitance electrode 17.

  The connection electrode 28 is disposed to face the plurality of gate electrodes 20 with the interlayer insulating film 22 interposed therebetween. The connection electrode 28 is electrically connected to the plurality of gate electrodes 20 through the plurality of second contact holes CH2, and electrically connects the adjacent gate electrodes 20 in the first direction d1. The plurality of connection electrodes 28 extend in the first direction d1 together with the plurality of gate electrodes 20, and form a plurality of scanning lines 19 arranged at intervals in the second direction d2.

  On the interlayer insulating film 22, the plurality of signal lines 27, the plurality of contact electrodes 30, and the plurality of connection electrodes 28, a planarizing film 31 is formed as an insulating film from a transparent resin. In this embodiment, the planarizing film 31 is an organic insulating film. The planarization film 31 has a plurality of contact holes 32 formed so as to overlap the contact electrode 30.

  On the planarizing film 31, a plurality of pixel electrodes 34 are formed of a transparent conductive material such as ITO (Indium Tin Oxide). The pixel electrodes 34 are arranged in a matrix along the first direction d1 and the second direction d2. The pixel electrode 34 is electrically connected to the contact electrode 30 through the contact hole 32. The pixel electrode 34 is formed by overlapping the periphery of two adjacent signal lines 27 and two adjacent auxiliary capacitance lines 21. The pixel electrode 34 has a long axis in the second direction d2.

  The pixel electrode 34 is electrically connected to the auxiliary capacitance electrode 17 on a one-to-one basis. The auxiliary capacitance electrode 17 connected to one pixel electrode 34 adjacent in the first direction d1 and the auxiliary capacitance electrode 17 connected to the other pixel electrode 34 face each other across the scanning line 19.

  As described above, a plurality of columnar spacers (not shown) are formed on the glass substrate 10 on which the planarizing film 31 and the pixel electrodes 34 are formed. An alignment film 37 is formed on the planarization film 31 and the pixel electrode 34 on which the columnar spacers are formed.

Each of the plurality of pixels 13 has one TFT 14, one auxiliary capacitance element 16, and one pixel electrode 34. Note that a capacitance between the gate electrode 20 and the drain region RD of the semiconductor layer 15, which is a capacitance of the TFT 14, is C _GD .

Next, the counter substrate 2 will be described.
The counter substrate 2 includes, for example, a glass substrate 40 as a transparent insulating substrate. A color filter 50 is formed on the glass substrate 40.

  The color filter 50 includes a plurality of red colored layers 50R, a plurality of green colored layers, and a plurality of blue colored layers. Each colored layer is formed in a stripe shape and extends in the second direction d2. The periphery of each colored layer overlaps the signal line 27. On the color filter 50, a common electrode 41 is formed of a transparent conductive material such as ITO. An alignment film 43 is formed on the common electrode 41.

  The array substrate 1 and the counter substrate 2 are arranged to face each other with a predetermined gap by a plurality of columnar spacers. The array substrate 1 and the counter substrate 2 are joined by a sealing material 60 disposed between both substrates on the outer periphery of the display region R1. The liquid crystal layer 3 is formed in a region surrounded by the array substrate 1, the counter substrate 2, and the sealing material 60. A liquid crystal inlet 61 is formed in a part of the sealing material 60, and the liquid crystal inlet is sealed with a sealing material 62.

  The backlight unit 7 includes a light guide plate 7a, and a light source and a reflection plate (not shown) disposed to face one side edge of the light guide plate. The light guide plate 7 a is disposed to face the array substrate 1. The liquid crystal display device also has a bezel and the like (not shown).

  Next, a method for manufacturing the array substrate 1 configured as described above will be described. In particular, a manufacturing method for forming the scanning line 19 after forming the first contact hole CH1 and the second contact hole CH2 will be described in detail.

  First, the glass substrate 10 is prepared. On the prepared glass substrate 10, the undercoating layer 12, the auxiliary capacitance electrode 17, the semiconductor layer 15, the gate insulating film 18, the gate electrode 20, and the auxiliary capacitance line are formed by a general manufacturing process such as repeated film formation and patterning. 21 is formed.

  Thereafter, in a plasma CVD apparatus (chamber) (not shown), interlayer insulation is performed on the plurality of auxiliary capacitance electrodes 17, the plurality of semiconductor layers 15, the plurality of gate electrodes 20, and the plurality of auxiliary capacitance lines 21 (the array substrate 1 being manufactured). A film 22 is formed.

Subsequently, the array substrate 1 on which the interlayer insulating film is formed is transferred from the plasma CVD apparatus into an etching apparatus (chamber) not shown.
As shown in FIG. 8, a stage having an electrostatic chuck electrode 101 and a He (helium) gas cooling groove 102 as an inert gas cooling groove positioned away from the electrostatic chuck electrode 101 in the etching apparatus. 100 is provided. The He gas cooling groove 102 is formed in a stripe shape.

  As shown in FIGS. 5 to 8, the array substrate 1 carried into the etching apparatus is placed on the stage 100. As shown in FIG. 9, at this time, the array substrate 1 is placed on the stage 100 so that the direction in which the scanning lines 19 and the auxiliary capacitance lines 21 extend is parallel to the direction in which the He gas cooling groove 102 extends. Placed.

  Subsequently, a voltage is applied to the electrostatic chuck electrode 101 to fix the array substrate 1 to the stage 100 (electrostatic chuck). In this embodiment, a voltage of 4.5 kV is applied to the electrostatic chuck electrode 101.

Next, in a state where the array substrate 1 is fixed to the stage 100, the interlayer insulating film 22 is etched using a photolithography method. As a result, a plurality of first contact holes CH1 facing the source regions RS of the plurality of semiconductor layers 15 are formed in the gate insulating film 18 and the interlayer insulating film 22, and a plurality of first contact holes CH1 facing the plurality of gate electrodes 20 are formed in the interlayer insulating film 22. Second contact hole CH2 is formed. Further, the source region RS and the gate electrode 20 of the semiconductor layer 15 are exposed.
In this embodiment, dry etching is used for etching, and etching is performed by adjusting etching conditions such as an etching gas.

  Subsequently, after the array substrate 1 is lowered from the stage 100 and carried out of the etching apparatus, a conductive film such as a metal film is formed on the interlayer insulating film 22, and the conductive film is etched (patterned). As a result, a plurality of signal lines 27, a plurality of contact electrodes 30, and a plurality of connection electrodes 28 are formed on the interlayer insulating film 22. Since the plurality of connection electrodes 28 are electrically connected to the plurality of gate electrodes 20, a plurality of scanning lines 19 are formed.

  Thereafter, the planarization film 31, the pixel electrode 34, the columnar spacer, and the alignment film 37 are formed on the glass substrate 10 by a general manufacturing process such as film formation and patterning, thereby completing the array substrate 1. To do. When the pixel electrode 34 is formed, the auxiliary capacitance electrode 17 to which one adjacent pixel electrode 34 is connected and the auxiliary capacitance electrode 17 to which the other pixel electrode 34 is connected face each other across the scanning line 19. It is formed as follows.

  Although not described in detail, the scanning line driving circuit 4, the signal line driving circuit 5, and the auxiliary capacitance line driving circuit 6 are appropriately formed. In the above-described method for manufacturing an array substrate, the case where one array substrate 1 is formed has been described. However, a plurality of array substrates 1 are formed using a single mother glass (mother substrate). Even when chamfering is performed, the above-described array substrate manufacturing method can be applied. In this case, a plurality of array substrates 1 can be formed simultaneously.

  According to the array substrate 1, the liquid crystal display device, and the method for manufacturing the array substrate 1 according to the embodiment configured as described above, the plurality of gate electrodes 20 are formed electrically independently. In a state where the plurality of gate electrodes 20 are electrically independent, the first contact hole CH1 can be formed in the gate insulating film 18 and the interlayer insulating film 22, and the second contact hole CH2 can be formed in the interlayer insulating film 22.

Since the gate electrode 20 is electrically independent, the potential of the gate electrode 20 can be easily increased. As a result, as shown in FIG. 9, when a voltage is applied to the electrostatic chuck electrode 101, the auxiliary capacitance electrode 17 (the auxiliary capacitance Cs of the auxiliary capacitance element 16) at the boundary between the electrostatic chuck electrode 101 and the He gas cooling groove 102. ) And the increase in the gate electrode 20 due to the capacitance C _GD of the TFT 14, these potential differences can be reduced.

  Thereby, ESD (Electro Static Discharge) breakdown of the gate insulating film 18 that causes a short circuit between the semiconductor layer 15 and the gate electrode 20 can be reduced, so that damage to the TFT 14 can be reduced.

  Further, the second contact hole CH2 can be formed at the same time in the manufacturing process of the first contact hole CH1, and the connection electrode 28 that forms the scanning line 19 together with the gate electrode 20 in the manufacturing process of the signal line 27 and the like is simultaneously made of the same material. Since it can be formed, the array substrate 1 can be manufactured without increasing the manufacturing cost.

  From the above, it is possible to obtain an array substrate, a liquid crystal display device, and a method for manufacturing the array substrate that have a high manufacturing yield.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment.

  The present invention is effective for the array substrate, the liquid crystal display device, and the array substrate manufacturing method for adopting the CCDI drive as described above. However, the present invention is not limited to this. The present invention can be applied to a liquid crystal display device and an array substrate manufacturing method. However, when CC driving is employed, it is preferable not to apply the present invention because the potential of the gate electrode is likely to rise and the TFT is not damaged.

DESCRIPTION OF SYMBOLS 1 ... Array substrate, 2 ... Opposite substrate, 3 ... Liquid crystal layer, 10 ... Glass substrate, 13 ... Pixel, 14 ... TFT, 15 ... Semiconductor layer, 16 ... Auxiliary capacitance element, 17 ... Auxiliary capacitance electrode, 18 ... Gate insulating film , 19 ... scanning line, 20 ... gate electrode, 21 ... auxiliary capacitance line, 22 ... interlayer insulating film, 27 ... signal line, 28 ... connection electrode, 34 ... pixel electrode, 100 ... stage, 101 ... electrostatic chuck electrode, 102 ... He gas cooling groove, P ... Liquid crystal display panel, R1 ... Display area, d1 ... First direction, d2 ... Second direction, RS ... Source area, RD ... Drain area, CH1 ... First contact hole, CH2 ... Second Contact hole, Cs: auxiliary capacity, _CGD : capacity.

Claims (4)

A plurality of auxiliary capacitance electrodes;
A plurality of semiconductor layers each having a source region and a drain region connected to the storage capacitor electrode;
A plurality of gate electrodes intersecting with the plurality of semiconductor layers via a gate insulating film and forming a plurality of thin film transistors together with the plurality of semiconductor layers;
A plurality of auxiliary capacitance lines that are arranged opposite to the plurality of auxiliary capacitance electrodes via the gate insulating film and form a plurality of auxiliary capacitance elements together with the plurality of auxiliary capacitance electrodes;
A plurality of first contact holes and a plurality of gate electrodes formed on the plurality of storage capacitor electrodes, a plurality of semiconductor layers, a plurality of gate electrodes, and a plurality of storage capacitor lines, respectively, facing the source regions of the plurality of semiconductor layers. An interlayer insulating film having a plurality of opposing second contact holes;
A plurality of gate electrodes and a plurality of auxiliary capacitance lines that intersect with each other through the interlayer insulating film and are electrically connected to source regions of the plurality of semiconductor layers through at least the plurality of first contact holes. A signal line;
The plurality of gate electrodes are arranged to face each other through the interlayer insulating film, and are electrically connected to the plurality of gate electrodes through at least the plurality of second contact holes, and a plurality of scanning lines together with the plurality of gate electrodes. A plurality of connection electrodes forming
A plurality of pixel electrodes electrically connected to the plurality of auxiliary capacitance electrodes,
An array substrate, wherein an auxiliary capacitance electrode to which one adjacent pixel electrode is connected and an auxiliary capacitance electrode to which the other pixel electrode is connected face each other across the scanning line. A plurality of auxiliary capacitance electrodes arranged in a first direction and spaced in a second direction perpendicular to the first direction;
A plurality of semiconductor layers each having a source region and a drain region connected to the plurality of auxiliary capacitance electrodes on a one-to-one basis;
The plurality of auxiliary capacitance electrodes are spaced from each other in the second direction, arranged in the first direction, arranged in the second direction at intervals, and the plurality of auxiliary capacitance electrodes via the gate insulating film. A plurality of gate electrodes intersecting the semiconductor layer and forming a plurality of thin film transistors together with the plurality of semiconductor layers;
A plurality of auxiliary capacitances extending in the first direction and arranged at intervals in the second direction, arranged to face the plurality of auxiliary capacitance electrodes via the gate insulating film, and together with the plurality of auxiliary capacitance electrodes A plurality of auxiliary capacitance lines forming an element;
A plurality of first contact holes and a plurality of gate electrodes formed on the plurality of storage capacitor electrodes, a plurality of semiconductor layers, a plurality of gate electrodes, and a plurality of storage capacitor lines, respectively, facing the source regions of the plurality of semiconductor layers. An interlayer insulating film having a plurality of opposing second contact holes;
Extending in the second direction, arranged at intervals in the first direction, intersecting the plurality of gate electrodes and the plurality of auxiliary capacitance lines via the interlayer insulating film, and at least the plurality of first contacts A plurality of signal lines electrically connected to source regions of the plurality of semiconductor layers through holes;
The gate electrodes adjacent to each other in the first direction are disposed opposite to the plurality of gate electrodes through the interlayer insulating film, electrically connected to the plurality of gate electrodes through at least the plurality of second contact holes. A plurality of connection electrodes extending in the first direction together with the plurality of gate electrodes and forming a plurality of scanning lines arranged at intervals in the second direction;
A plurality of pixel electrodes arranged in the first direction and the second direction and electrically connected to the plurality of auxiliary capacitance electrodes on a one-to-one basis,
The storage capacitor electrode connected to one pixel electrode adjacent in the first direction and the storage capacitor electrode connected to the other pixel electrode face each other across the scanning line. substrate. An array substrate;
A counter substrate disposed opposite to the array substrate with a gap;
A liquid crystal layer sandwiched between the array substrate and the counter substrate,
The array substrate is
A plurality of auxiliary capacitance electrodes;
A plurality of semiconductor layers each having a source region and a drain region connected to the storage capacitor electrode;
A plurality of gate electrodes intersecting with the plurality of semiconductor layers via a gate insulating film and forming a plurality of thin film transistors together with the plurality of semiconductor layers;
A plurality of auxiliary capacitance lines that are arranged opposite to the plurality of auxiliary capacitance electrodes via the gate insulating film and form a plurality of auxiliary capacitance elements together with the plurality of auxiliary capacitance electrodes;
A plurality of first contact holes and a plurality of gate electrodes formed on the plurality of storage capacitor electrodes, a plurality of semiconductor layers, a plurality of gate electrodes, and a plurality of storage capacitor lines, respectively, facing the source regions of the plurality of semiconductor layers. An interlayer insulating film having a plurality of opposing second contact holes;
A plurality of gate electrodes and a plurality of auxiliary capacitance lines that intersect with each other through the interlayer insulating film and are electrically connected to source regions of the plurality of semiconductor layers through at least the plurality of first contact holes. A signal line;
The plurality of gate electrodes are arranged to face each other through the interlayer insulating film, and are electrically connected to the plurality of gate electrodes through at least the plurality of second contact holes, and a plurality of scanning lines together with the plurality of gate electrodes. A plurality of connection electrodes forming
A plurality of pixel electrodes electrically connected to the plurality of auxiliary capacitance electrodes,
A liquid crystal display device, wherein an auxiliary capacitance electrode to which one adjacent pixel electrode is connected and an auxiliary capacitance electrode to which the other pixel electrode is connected face each other across the scanning line. A plurality of semiconductor layers having a plurality of storage capacitor electrodes, a plurality of semiconductor layers each having a source region and a drain region connected to the storage capacitor electrode, and a plurality of semiconductor layers intersecting the plurality of semiconductor layers through a gate insulating film And a plurality of gate electrodes that form a plurality of thin film transistors, and a plurality of storage capacitors that are disposed opposite to the plurality of storage capacitors via the gate insulating film and that form a plurality of storage capacitors together with the plurality of storage capacitors Prepare an array substrate under production in which lines are formed,
Forming an interlayer insulating film on the plurality of auxiliary capacitance electrodes, the plurality of semiconductor layers, the plurality of gate electrodes, and the plurality of auxiliary capacitance lines;
On the stage having an electrostatic chuck electrode and an inert gas cooling groove positioned away from the electrostatic chuck electrode, the array substrate on which the interlayer insulating film is formed is placed,
Applying a voltage to the electrostatic chuck electrode, fixing the array substrate to the stage,
In a state where the array substrate is fixed to the stage, the interlayer insulating film is etched, and the plurality of first contact holes and the plurality of gates facing the source regions of the plurality of semiconductor layers are formed in the interlayer insulating film. Forming a plurality of second contact holes facing the electrodes;
After the array substrate is lowered from the stage, the plurality of gate electrodes and the plurality of auxiliary capacitance lines are crossed through the interlayer insulating film, and at least through the plurality of first contact holes, the plurality of semiconductor layers. Forming a plurality of signal lines electrically connected to the source region;
The plurality of gate electrodes are arranged to face each other through the interlayer insulating film, and are electrically connected to the plurality of gate electrodes through at least the plurality of second contact holes, and a plurality of scanning lines together with the plurality of gate electrodes. Forming a plurality of connection electrodes to form
After forming the plurality of signal lines and the plurality of connection electrodes, forming a plurality of pixel electrodes electrically connected to the plurality of auxiliary capacitance electrodes,
When forming the plurality of pixel electrodes, an auxiliary capacitance electrode to which one adjacent pixel electrode is connected and an auxiliary capacitance electrode to which the other pixel electrode is connected face each other across the scanning line. A method for manufacturing an array substrate, comprising: forming an array substrate.

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