JP2015064638A - Computer device, interruption control method and computer program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the processing time of BIOS(Basic Input/Output System) processing while preventing the processing time of OS(Operating System) processing from becoming long in the case of executing the BIOS processing as interruption processing during the OS processing.SOLUTION: A computer device 1 includes: an OS processing part 2; a BIOS processing part 3; and a CPU group 4. The OS processing part 2 includes a function for controlling CPU 6, 6, through 6on the basis of an OS. The BIOS processing part 3 controls the CPU 6, 6, through 6on the basis of a BIOS. The BIOS processing part 3 puts the set number of CPU in the CPU group 4 in an OS resting state where it is excluded from the target of control based on the OS during OS processing in which the CPU group 4 is controlled by the OS processing part 2. Furthermore, the BIOS processing part 3 executes the BIOS processing based on the BIOS as interruption processing by controlling the CPU put in the OS resting state on the basis of the BIOS.

Description

  The present invention relates to a technique in which a computer device executing processing (OS processing) based on an OS (Operating System) executes processing (BIOS processing) based on BIOS (Basic Input / Output System) as interrupt processing. .

  For example, in order to realize a high RAS (Reliability, Availability, Serviceability (maintenability)) function required by a high-end server or the like, a CPU (Central Processing Unit) that is performing OS processing has its high RAS. The BIOS process related to the function may be performed intermittently. For example, when the CPU receives a notification of SMI (System management interrupts), the CPU transits to an operation mode called SMM (System Management Mode) (see, for example, Non-Patent Document 1). In this SMM, the CPU executes a process based on the BIOS (BIOS process). Then, the CPU executes the BIOS process for a number (milliseconds (ms)), and then returns to the OS process.

  By the way, the CPU in the SMM does not respond to a request (scheduling management control) by OS processing. For this reason, when a plurality of CPUs are executing OS processing in a computer device having a plurality of CPUs, for example, if only one CPU is transitioned to SMM, the CPU in the SMM responds to a request by OS processing. Stop responding. As a result, the computer apparatus determines that the CPU in the SMM has stalled (stopped), and may cause a kernel panic (OS panic).

  In order to prevent such a problem, when receiving the SMI, the computer device controls all the CPUs to transition to the SMM.

Intel Corporation, “Intel64 and IA-32 Architectures Software Developer Manuals”, [online], [searched September 6, 2013], Internet (URL: http://www.intel.com/content/www/us /en/processors/architectures-software-developer-manuals.html)

  However, when all the CPUs transition to SMM (mode in which processing is executed based on the BIOS) as described above, the OS processing is interrupted. For this reason, the bad effect that the processing time of OS processing becomes long will arise.

  Therefore, in order to avoid the adverse effects, the following processing can be considered. That is, a BIOS process executed as an interrupt process (for example, a process executed with SMM (SMM process)) is divided into a plurality of steps that can be completed in a short time. All the CPUs execute the BIOS process intermittently step by step during the OS process. However, in this case, since the number of times of returning from the BIOS processing (SMM processing) to the OS processing increases, there is a problem that the processing time of the BIOS processing (SMM processing) becomes longer by the increase in the number of processing times.

  The present invention has been made to solve the above problems. That is, the main object of the present invention is to shorten the processing time of the BIOS processing while preventing the processing time of the OS processing from becoming long when the BIOS processing is executed as the interrupt processing during the OS processing. It is to provide the technology that can.

In order to achieve the above object, the computer apparatus of the present invention provides:
A CPU group including a plurality of CPUs (Central Processing Units);
An OS processing unit for controlling the CPU based on an OS (Operating System);
A BIOS processing unit for controlling the CPU based on BIOS (Basic Input / Output System);
The BIOS processing unit is in an OS hibernation state in which a set number of CPUs in the CPU group are excluded from control targets based on the OS during the OS process in which the CPU group is controlled by the OS processing unit. And the BIOS processing based on the BIOS is executed as an interrupt processing by controlling the CPU in the OS dormant state based on the BIOS.

The interrupt control method of the present invention
A CPU group including a plurality of CPUs (Central Processing Units) is provided, and has a function of controlling the CPU based on an OS (Operating System) and a function of controlling the CPU based on a BIOS (Basic Input / Output System). Computer equipment
During the OS processing in which the CPU group is controlled by the OS processing unit, the set number of CPUs in the CPU group are put into an OS hibernation state that is excluded from the control target based on the OS,
The BIOS process based on the BIOS is executed as an interrupt process by controlling the CPU in the OS hibernation state based on the BIOS.

The computer program of the present invention is:
A CPU group including a plurality of CPUs (Central Processing Units) is provided, and has a function of controlling the CPU based on an OS (Operating System) and a function of controlling the CPU based on a BIOS (Basic Input / Output System). Computer equipment
A process of setting a set number of CPUs in the CPU group to an OS hibernation state that is excluded from a control target based on the OS during the OS process in which the CPU group is controlled based on the OS;
The processing procedure which performs the process which performs the BIOS process based on the said BIOS as an interruption process by controlling the said CPU of the said OS dormant state based on the said BIOS is represented.

  The object of the present invention is also achieved by the interrupt control method of the present invention corresponding to the computer apparatus of the present invention. The object of the present invention is also achieved by a computer program for realizing the computer apparatus and interrupt control method of the present invention, and a computer program storage medium for storing the computer program.

  According to the present invention, when BIOS processing is executed as interrupt processing during OS processing, it is possible to shorten the processing time of BIOS processing while preventing an increase in processing time of OS processing.

It is a block diagram which simplifies and represents the structure of the computer apparatus of 1st Embodiment which concerns on this invention. It is a block diagram which simplifies and represents the structure of the computer apparatus of 2nd Embodiment which concerns on this invention. It is a flowchart showing the operation example of the BIOS process part in 2nd Embodiment. It is a figure explaining the example of a state of CPU in 2nd Embodiment. It is a figure explaining the operation example of the table change part in 2nd Embodiment. It is a figure explaining an example of the storage state of the memory in 2nd Embodiment.

  Embodiments according to the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a simplified configuration of the computer apparatus according to the first embodiment of the present invention. The computer apparatus 1 according to the first embodiment includes an OS (Operating System) processing unit 2, a BIOS (Basic Input / Output System) processing unit 3, and a CPU (Central Processing Unit) group 4.

The CPU group 4 has a plurality of CPUs 6 ₁ , 6 ₂ ,..., 6 _n (n is an integer of 2 or more). The OS processing unit 2 has a function of controlling the CPUs 6 ₁ , 6 ₂ ,..., 6 _n based on the OS.

The BIOS processing unit 3 has a function of controlling the CPUs 6 ₁ , 6 ₂ ,..., 6 _n based on the BIOS. The BIOS processing unit 3 is configured so that during the OS processing in which the CPU group 4 is controlled by the OS processing unit 2, the set number of CPUs in the CPU group 4 are in an OS hibernation state in which they are excluded from the control targets based on the OS. It has a function to do. Further, the BIOS processing unit 3 has a function of executing a BIOS process based on the BIOS as an interrupt process by controlling the CPU in the OS inactive state based on the BIOS.

  In such a BIOS processing unit 3, for example, a CPU 8 as a controller for controlling the CPU group 4 reads and executes a computer program (program (BIOS)) 11 of the storage device 10 provided in the computer device 1. Realize. In other words, the program 11 represents a processing procedure for realizing the function of the BIOS processing unit 3 as described above. The same applies to the OS processing unit 2, which is realized by the CPU 8 executing a program (OS).

The computer device 1 according to the first embodiment has a configuration (function) in which some CPUs included in the CPU group 4 execute BIOS processing when the CPU group 4 executes OS processing. Therefore, the computer device 1 can execute the BIOS process without interrupting the OS process. Thus, for example, the computer apparatus 1 has a longer processing time for the OS process than when all the CPUs 6 ₁ , 6 ₂ ,..., 6 _n execute the BIOS process intermittently during the OS process. The processing time of the BIOS processing can be shortened while suppressing the above.

  In the first embodiment, the CPU that executes the BIOS process as the interrupt process during the OS process is put into the OS hibernation state by the function of the BIOS processing unit 3. For this reason, the OS processing unit 2 does not determine that there is an abnormality even if there is no response from the CPU in the OS hibernation state (in other words, during the BIOS processing). Can be prevented.

(Second Embodiment)
The second embodiment according to the present invention will be described below.

  FIG. 2 is a block diagram illustrating a simplified configuration of a computer device according to the second embodiment. The computer device 20 according to the second embodiment roughly includes a management device (controller) 21, a CPU (Central Processing Unit) group 23, a memory 24, and a storage device 25.

  The storage device 25 is constituted by a hard disk device, for example. The storage device 25 stores various data and a computer program (for example, an OS (Operating System)) 29 that controls the operation of the computer device 20.

The CPU group 23 includes a plurality of CPUs 44 _{1 to} 44 _n (n is an integer of 2 or more). The memory 24 is constituted by, for example, a RAM (Random Access Memory). In the second embodiment, the following storage areas are set in the memory 24. That is, the memory 24 includes an SMRAM (System Management Random Access Memory) 50, a handler unit 51, an IDT (Interrupt Descriptor Table) 52, an address unit 53, and a stack unit 54. .

  The SMRAM 50 is a storage area for storing information indicating the processing status (state status) of the CPU group 23 executing the OS processing when a notification called SMI (System management interrupts) is issued. Status storage unit).

  The handler unit 51 is a storage area (program storage unit) in which an interrupt handler, which is a computer program representing an interrupt processing procedure, is stored.

  The IDT 52 is a storage area (storage position storage unit) in which entry points of interrupt handlers are stored.

  The address unit 53 is a storage area for storing a storage position (address) of data written to the memory 24 by the OS process.

  In the second embodiment, the stack unit 54 is a storage area for storing an IP (Instruction Pointer) of a process to be executed next in the OS process.

  The management device 21 has a controller function for controlling the CPU group 23. The management device 21 includes a CPU (Central Processing Unit) 30 and a storage unit (nonvolatile memory) 32. The storage unit 32 stores a BIOS (Basic Input / Output System (computer program)) 42.

  The CPU 30 reads out a computer program (program) 29 including a BIOS (program) 42 stored in the storage unit 32 and an OS stored in the storage device 25, and executes these programs 29, 42, whereby the CPU group The function which controls 23 is provided.

  That is, the CPU 30 includes an OS processing unit 34 and a BIOS processing unit 35 as functional units. The OS processing unit 34 is a functional unit that controls the CPU group 23 based on the OS. There are various methods for OS processing based on the OS, and detailed description of the OS processing is omitted here.

  The BIOS processing unit 35 is a functional unit that controls the CPU group 23 based on the BIOS. The BIOS processing unit 35 has a function capable of interrupting the OS processing and executing SMM (System Management Mode) processing, which is BIOS processing, when the OS processing unit 34 is controlling the CPU group 23 (during OS processing). I have. Note that there are various types of BIOS processing, and detailed description regarding the BIOS processing other than the processing described below is omitted here.

  In the second embodiment, the BIOS processing unit 35 includes an interrupt procedure unit 37, a table changing unit 38, and a monitoring unit 39 as functional units. The interrupt procedure unit 37 has a function of executing a process from the start of the process interrupting the OS process to the start of the SMM process related to the high RAS function, for example. Each of the table changing unit 38 and the monitoring unit 39 has a function related to a process of removing the CPU during the SMM process from the control target by the BIOS and returning to the OS process when the SMM process is interrupted.

  Hereinafter, operation examples of the interrupt procedure unit 37, the table change unit 38, and the monitoring unit 39 will be described with reference to FIGS. 3 to 6, and the interrupt procedure unit 37 and the table change unit 38 will be described with the description of the operations. And the function (configuration) of the monitoring unit 39.

  FIG. 3 is a flowchart of interrupt processing executed by the BIOS processing unit 35 of the management device 21 in the computer device 20 according to the second embodiment. The flowchart of FIG. 3 shows the processing procedure of the BIOS computer program executed by the computer device 20 of the second embodiment.

  FIG. 4 is a diagram schematically illustrating an example of the state of the CPU during the procedure process executed by the CPU group 23 during the OS process to start the SMM process as the interrupt process. FIG. 5 is a diagram for explaining an operation example of the table changing unit 38. FIG. 6 is a diagram schematically illustrating an example of the storage state of the memory 24.

For example, when all the CPUs 44 _{1 to} 44 _n in the CPU group 23 are performing OS processing, when receiving a notification requesting SMM processing, the interrupt procedure unit 37 starts the following procedure to start SMM processing. The process is started (step S101 in FIG. 3).

First, the interrupt procedure unit 37 issues a command to the OS processing unit 34 so that all the CPUs 44 _{1 to} 44 _n are controlled by the BIOS processing unit 35 from being controlled by the OS processing unit 34 (step S102). . Then, the interrupt procedure processing unit 37 executes processing for analyzing the content of the requested SMM processing. Thus, when it is detected that the requested SMM process is a process related to the high RAS function, the interrupt procedure processing unit 37 executes an LPI (Logical Processor Ldling) function. The LPI function is a function defined by the ACPI (Advanced Configuration and Power Interface) standard, and is originally a function that reduces power consumption by transitioning the CPU to an idle (Idle) state. The CPU that has been in a dormant state by this LPI function is in a state of being excluded from the target of control by the OS processing unit 34.

  In the second embodiment, the interrupt procedure processing unit 37 outputs an instruction (request) for setting one CPU included in the CPU group 23 to a dormant state toward the OS processing unit 34 by the LPI function (step S103). . Here, for ease of explanation, a CPU that is in a hibernation state (OS hibernation state) by the LPI function is also referred to as CPU (A), and other CPUs in the CPU group 23 are also referred to as CPU (B). .

Thereafter, the interrupt procedure unit 37 reserves a timing for resuming the procedure process (step S104). Then, the interrupt procedure unit 37 excludes all the CPUs 44 _{1 to} 44 _n from being controlled by the BIOS processing unit 35. As a result, all the CPUs 44 _{1 to} 44 _n return to the targets of control by the OS processing unit 34. Then, the interrupt procedure unit 37 interrupts the procedure process (step S105). That is, as shown in FIG. 4, at time T <b> 1, all the CPUs in the CPU group 23 (CPU (A) and CPU (B) shown in FIG. 4) perform the processing of step S <b> 102 of the interrupt procedure unit 37 ( Transition from OS processing to BIOS processing. Thereafter, at a time T2 in FIG. 4 after issuing a command to put the CPU (A) in the dormant state, all the CPUs (A) and CPU (B) in the CPU group 23 transition from the BIOS process to the OS process. (Return). However, since the OS processing unit 34 has received a command from the BIOS processing unit 35 to put one CPU (A) in the CPU group 23 into the hibernation state, the CPU (A) is put into the OS hibernation state at time T3 in FIG. And

Thereafter, when the interrupt procedure unit 37 detects that it is a restart timing based on the reservation operation performed in step S104 (step S106), it restarts the procedure process. As a result, the interrupt procedure unit 37 causes all the CPUs 44 _{1 to} 44 _{n of} the CPU group 23 including the CPU (A) in the dormant state to be controlled by the BIOS processing unit 35 from being controlled by the OS processing unit 34. A command is issued to the OS processing unit 34 so as to become (step S107, time T4 in FIG. 4). At this time, information indicating the state of the CPUs 44 _{1 to} 44 _n immediately before being excluded from the control target of the OS processing unit 34 is written into the SMRAM 50 by the function of the BIOS processing unit 35.

Thereafter, the interrupt procedure unit 37 identifies the CPU (A) that has been in the OS hibernation state by the OS processing unit 34 among the CPUs 44 _{1 to} 44 _n (step S108). That is, the interrupt procedure unit 37 reads from the SMRAM 50 the information on the instruction address and the register value executed by the CPUs 44 _{1 to} 44 _n immediately before the OS processing unit 34 is excluded from the control target. Based on the read information, the interrupt procedure unit 37 identifies the CPU whose instruction being executed is a pause instruction and whose parameter (register value) is an instruction by the LPI function. , CPU (A) is specified.

Thereafter, the interrupt procedure unit 37 notifies the CPU (A) of IPI (Inter Processor Interrupt) so that only the identified CPU (A) executes the requested SMM processing. (Step S109). Subsequently, the interrupt procedure unit 37 interrupts the procedure process (step S110). Thereby, all the CPUs 44 _{1 to} 44 _n of the CPU group 23 including the CPU (A) are removed from the control target of the BIOS processing unit 35 and returned to the state before being the control target of the BIOS management unit 35. That is, the CPU (A) is in the OS hibernation state, and the other CPUs (B) in the CPU group 23 are in a state (OS processing) being controlled by the OS processing unit 34 (time T5 in FIG. 4). .

  As described above, the CPU (A) is in the OS hibernation state, but returns to the state controlled by the BIOS processing unit 35 (in the BIOS processing) because of the IPI notification (time T6 in FIG. 4). When the BIOS processing unit 35 detects that the CPU (A) has returned to the control target (transition to the BIOS processing) (step S111), the CPU (A) performs the SMM processing related to the high RAS function. Command to start (step S112).

In the second embodiment, as described above, when the CPU group 23 during OS processing executes SMM processing as interrupt processing, one of the CPUs 44 _{1 to} 44 _n in the CPU group 23 (CPU (CPU ( A)) executes the SMM process. In this case, the CPU (A) is in a dormant state when viewed from the OS processing unit 34 and is not managed by the OS processing 34. For this reason, the computer apparatus 20 of the second embodiment can prevent the following problems. That is, the problem is that when the CPU (A) is normal but the CPU (A) is stopped because there is no response from the CPU (A) to the OS processing unit 34, the OS processing is performed. This is a problem that the unit 34 determines and causes, for example, an OS panic (kernel panic). The computer apparatus 20 of the second embodiment executes the SMM process by the CPU (A) while preventing the problem, and executes the OS process by the CPU (B) together with the SMM process. Thereby, the computer apparatus 20 can obtain the effects of shortening the processing time of the SMM process and preventing the delay of the OS process.

  By the way, as described above, the CPU (A) during the SMM process is in a dormant state (OS dormant state) when viewed from the OS processing unit 34. The CPU (A) may return to the control target of the OS processing unit 34 from the OS hibernation state depending on the processing status of the OS processing unit 34. The table changing unit 38 and the monitoring unit 39 have a function related to a process for smoothly returning the CPU (A).

  In other words, the table changing unit 38 is related to a return process when the OS processing unit 34 executes an interrupt process (OS interrupt handler). That is, in preparation for such a return process, the table changing unit 38 first rewrites the IDT of the memory 24 when the BIOS processing unit 35 starts the SMM process by the CPU (A) (step S112 in FIG. 3). . As a specific example, in the example of FIG. 5, in the handler unit 51, the entry points of the interrupt handler (OS interrupt handler) in the OS process are 0x100, 0x300, and 0x500. The entry points of the interrupt handler (BIOS process interrupt handler) in the BIOS process are 0x200, 0x400, and 0x600. The table changing unit 38 uses the entry points (0x100, 0x300, 0x500) of the OS interrupt handler in the IDT 52 as shown in FIG. 5A, and the entry points (0x200, 0x400, BIOS interrupt handler) as shown in FIG. Rewrite (change) to 0x600).

  By rewriting the IDT 52 in this way, the CPU (A) operates as follows when the OS processing unit 34 executes the OS interrupt handler, which is the return timing for controlling the CPU (A). That is, the OS processing unit 34 attempts to execute an interrupt handler based on the entry point of the IDT 52 in order to execute the OS interrupt handler, but the entry point has been rewritten. For this reason, not the OS interrupt handler but the BIOS interrupt handler is executed. That is, if the BIOS processing unit 35 determines that it is time to return the CPU (A) to the control target of the OS processing unit 34 by the determination operation in step S113 of FIG. (BIOS interrupt handler) is executed (step S116).

  When starting the return process (BIOS interrupt handler), as shown in FIG. 6A, the entry point 0x200 of the BIOS interrupt handler is written in the IDT 52. In addition, the RIP (Relative Instruction-Pointer) register in the SMRAM 50 stores 0x1000, which is the IP output to the CPU (A) immediately before the CPU (A) is removed from the control target of the OS processing unit 34. .

  In the return process, the BIOS processing unit 35 stores the progress status of the SMM process being executed by the CPU (A). Then, the BIOS processing unit 35 rewrites the entry point (0x200) of the BIOS interrupt handler stored in the IDT 52 to the original OS interrupt handler entry point (0x100) as shown in FIG. 6C. Further, the BIOS processing unit 35 changes 0x1000, which is the IP of the pause instruction written in the RIP register in the SMRAM 50, to 0x100, which is the entry point of the OS interrupt handler as shown in FIG. 6C. Thereafter, the BIOS processing unit 35 stores IP (0x1003) in the storage position of the stack unit 54 stored in the RSP (Return Stack Pointer) register in the SMRAM 50. This IP (0x1003) is an IP corresponding to the processing content (command) that the CPU (A) executes after the pause command.

  Thereafter, the BIOS processing unit 35 suspends the SMM process as shown in step S117 of FIG. 3 by removing the CPU (A) from the control target. As a result, the CPU (A) becomes a control target of the OS processing unit 34. The OS processing unit 34 executes the OS interrupt handler of the entry point (0x100) to be executed stored in the RIP register in the SMRAM 50. In this state, 0x1003 which is the IP of the instruction next to the pause instruction is stored in the storage position of the stack unit 54 corresponding to the storage information of the RSP register. Therefore, the CPU (A) can return to the OS processing based on the IP (0x1003) after the OS interrupt handler ends.

As a result, all the CPUs 44 _{1 to} 44 _n in the CPU group 23 are in a state of executing OS processing. In this state, when the management device 21 receives a notification requesting the SMM process, the operations after step S101 in FIG. 3 are repeated.

  In the above example, a processing example in which the CPU (A) returns to the control target of the OS processing unit 34 when the OS processing unit 34 executes the OS interrupt handler is described. Further, the CPU (A) may return to the control target of the OS processing unit 34 when data is written by the OS processing unit 34 at the address specified in the address unit 53. In this case, the BIOS processing unit 35 executes the following process.

  For example, in step S112, the BIOS processing unit 35 refers to the SMRAM 50 before starting the SMM processing by the CPU (A), so that the register immediately before the CPU (A) is excluded from the control target of the OS processing unit 34. Get the value. Then, based on the register value, the BIOS processing unit 35 acquires the address of the address unit 53 (hereinafter referred to as a return trigger address) that triggers the CPU (A) to return to the control target of the OS processing unit.

  Thereafter, the BIOS processing unit 35 starts SMM processing by the CPU (A). During this SMM process, the BIOS processing unit 35 executes a polling function for the memory 24. That is, the BIOS processing unit 35 monitors (polls) the writing state in the memory 24 at a constant period during the SMM processing.

  Then, when the BIOS processing unit 35 detects that the return trigger address in the memory 24 has been changed by the OS processing unit 34, the CPU (A) causes the OS processing unit 34 to perform the determination operation in step S113 of FIG. It is determined that it is time to return to the control target. And the BIOS process part 35 memorize | stores the progress of the SMM process by CPU (A) as a return process in step S116, and removes CPU (A) from a control object. As a result, the CPU (A) returns to the control target of the OS processing unit 34, and the BIOS processing unit 35 interrupts the SMM processing (step S117 in FIG. 3).

  By the way, the maximum latency required for the CPU (A) to return to the control target of the OS processing unit 34 after the OS processing unit 34 instructs to write information to the return trigger address is the value from the hibernation state due to the performance of the CPU. This is the time obtained by adding the polling period to the return time. Since the maximum latency is determined in advance, the BIOS processing unit 35 notifies the OS processing unit 34 of the maximum latency information in advance (for example, when the OS is started up). By setting the time set by the OS processing unit 34 as the allowable return time of the CPU (A) to be equal to or greater than the maximum latency, the OS processing unit 34 performs the CPU recovery even though the CPU (A) is about to return normally. It can be prevented that the return of (A) is determined to be slow.

  If the BIOS processing unit 35 determines in step S113 in FIG. 3 that it has not received a return command from the CPU (A) due to the processing of the OS processing unit 34 during the SMM processing, in step S114, the SMM processing It is determined whether the processing is completed. If the BIOS processing unit 35 determines that the SMM processing has not been completed, the BIOS processing unit 35 continues the SMM processing using the CPU (A) (step S115), and repeats the operations after step S113. If the BIOS processing unit 35 determines in step S114 that the SMM processing has been completed, the BIOS processing unit 35 ends the SMM processing and removes the CPU (A) from the control target. As a result, the CPU (A) returns to the control target of the OS processing unit 34 and starts OS processing.

  Since the computer device 20 according to the second embodiment has the above-described configuration, it is possible to prevent the time required for the OS processing from becoming long when executing the interrupt processing by the BIOS during the OS processing. The time required for BIOS processing can be shortened.

  That is, the computer device 20 according to the second embodiment has a function of executing SMM processing by one CPU included in the CPU group 23 during OS processing, and therefore can execute SMM processing while continuing OS processing. . For this reason, since the computer apparatus 20 performs the SMM process without interrupting the OS process, the problem that the processing time of the OS process becomes long can be suppressed. In addition, the computer device 20 executes a process of setting the CPU that executes the SMM process to the OS hibernation state (a state in which the OS processing unit 34 looks like the hibernation state) before executing the SMM process during the OS process. Therefore, it is possible to avoid the occurrence of problems caused by the CPU during the SMM process not responding to the OS processing unit 34.

  Furthermore, the computer apparatus 20 of the second embodiment can smoothly return the CPU to the control target of the OS processing unit 34 by the operations of the table changing unit 38 and the monitoring unit 39.

(Other embodiments)
The present invention is not limited to the first and second embodiments, and various embodiments can be adopted. For example, in the second embodiment, the computer device 20 has a function in which one CPU included in the CPU group 23 executes a BIOS process as an interrupt process during the OS process. On the other hand, the number of CPUs that execute BIOS processing as interrupt processing during OS processing may be plural.

  Further, in the second embodiment, as an opportunity for the CPU (A) in the SMM process to return to the OS process, the case where the OS processing unit 34 executes the OS interrupt handler and the case where the data is written to the return opportunity address are exemplified. Are listed. However, the trigger conditions for the CPU (A) to return to the OS processing are not limited to them. For example, the return trigger condition may be one of the above two cases (conditions). Further, the trigger condition for return may include another condition in the above two cases (conditions).

1,20 Computer device 2,34 OS processing unit 3,35 BIOS processing unit 4,23 CPU group

Claims (8)

A CPU group including a plurality of CPUs (Central Processing Units);
An OS processing unit for controlling the CPU based on an OS (Operating System);
A BIOS processing unit for controlling the CPU based on BIOS (Basic Input / Output System);
The BIOS processing unit is in an OS hibernation state in which a set number of CPUs in the CPU group are excluded from control targets based on the OS during the OS process in which the CPU group is controlled by the OS processing unit. And a computer apparatus configured to execute the BIOS process based on the BIOS as an interrupt process by controlling the CPU in the OS dormant state based on the BIOS. A situation storage unit for storing information representing a processing status of the OS processing unit;
When executing the BIOS process as an interrupt process during the OS process, the BIOS processing unit outputs a sleep command for setting the set number of CPUs to the OS sleep state to the OS processing unit. The processing and the processing for specifying the CPU in the OS hibernation state by using the information stored in the status storage unit by the OS processing unit that has received the hibernation instruction, The computer apparatus according to claim 1, wherein the BIOS processing is executed using the CPU in the OS hibernation state. A program storage unit for storing the computer program; and a storage location storage unit for storing information on the storage location of the computer program to be executed;
The BIOS processing unit stores, in the storage location storage unit, a storage location of a computer program specified in the OS processing related to the timing at which the CPU in the OS hibernation state returns to the control target of the OS processing unit in the storage location storage unit. The information is changed to information on the storage location of the computer program for the return process for the CPU in the OS hibernation state, and the return process is executed before the process based on the prescribed computer program for the OS process is executed. The computer apparatus according to claim 1, further comprising a configuration.   The BIOS processing unit stores a process for storing information indicating a progress status of the BIOS process when the BIOS process using the CPU in the OS hibernation state is interrupted, and a memory for resuming the BIOS process. 4. The computer apparatus according to claim 1, further comprising a configuration for executing a process of restarting the BIOS process by using the progress information of the BIOS process.   The BIOS processing unit monitors the information writing status by the OS processing unit in a storage unit to which the OS processing unit reads and writes information, so that the CPU in the OS hibernation state returns to the control target of the OS processing unit. 5. The computer apparatus according to claim 1, further comprising a configuration in which the CPU in the OS hibernation state is excluded from a control target when it is detected that it is a timing to perform.   The BIOS processing unit periodically monitors the write status, and the recovery required for the CPU in the OS hibernation state to return to the state in which the OS processing can be executed is performed for one period of the monitoring. The computer apparatus according to claim 5, further comprising a configuration for notifying the OS processing unit of information of a total time obtained by adding the time. A CPU group including a plurality of CPUs (Central Processing Units) is provided, and has a function of controlling the CPU based on an OS (Operating System) and a function of controlling the CPU based on a BIOS (Basic Input / Output System). Computer equipment
During the OS processing in which the CPU group is controlled based on the OS, a set number of the CPUs in the CPU group are put into an OS hibernation state that is excluded from the control target based on the OS,
An interrupt control method for executing a BIOS process based on the BIOS as an interrupt process by controlling the CPU in the OS dormant state based on the BIOS. A CPU group including a plurality of CPUs (Central Processing Units) is provided, and has a function of controlling the CPU based on an OS (Operating System) and a function of controlling the CPU based on a BIOS (Basic Input / Output System). Computer equipment
A process of setting a set number of CPUs in the CPU group to an OS hibernation state that is excluded from a control target based on the OS during the OS process in which the CPU group is controlled based on the OS;
The computer program showing the process sequence which performs the process which performs the BIOS process based on the said BIOS as an interruption process by controlling the said CPU of the said OS dormant state based on the said BIOS.

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