JP3116215B2 - How to control double directory virtual cache - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates without performing address conversion operation, dual directory to allow direct access using a virtual address - relates to the control method of the virtual cache.

[0002]

2. Description of the Related Art Generally, a cache system is used as a means for improving the performance of a microprocessor. In particular, the importance of virtual caches has been gradually increased in translating virtual addresses into physical addresses and reducing the time required to access the cache using the translated physical addresses. Such a virtual cache can be used as an internal storage in high performance systems, especially high performance microprocessors.

Generally, a cache is used as a virtual cache used to improve the performance of a microprocessor and, in particular, to increase the efficiency of a data storage device. This virtual address is used internally but accesses an external memory. Must be translated to a physical address. Also, the internal and external caches are accessed using the translated physical addresses.

Generally, an external cache is accessed through a physical address. However, if the internal cache needs to be accessed using a physical address, an address translation operation must be performed, which increases the access time.

In order to solve such a problem, a virtual cache that can directly access an internal cache using a virtual address is used. In such a virtual cache, the internal data identity (consistent)
ncy) must be guaranteed and the internal cache must be monitored from the outside according to changes in the external cache or memory.

FIG. 1 shows a configuration diagram of a conventional microprocessor system. As shown, the conventional microprocessor system uses a two-level cache system having an internal cache (1) and an external cache (2) to improve performance. When the external cache (2) is used, the external memory has a relatively high capacity and low cost, but has a longer access time than the internal cache (1). When the internal cache (1) is used, the internal memory is expensive but performs high-speed operations that enable high-speed operation of the microprocessor.

FIG. 2 shows an example of a multiprocessor using the processor of FIG. As shown, the multiprocessor system must also consider the operation of the other processors of the bus master. To accomplish this, the multiprocessor system requires a monitoring operation on an external bus, which is referred to as bus snooping (bu).
ssnooping or simply snooping. This snooping is very important for data identity in multiprocessor systems.

FIG. 3 is a conceptual diagram of a virtual cache access using a virtual address and a physical address in a processor using a virtual cache such as an internal cache, and a virtual memory is used as shown in the drawing. When the virtual address (VA) is converted into the physical address (PA) and compared with the time for accessing the internal cache using the converted physical address, the virtual address (V) is used.
The time to access the internal cache directly using A) is significantly reduced.

However, when the internal cache is directly accessed using the virtual address, the bus snooping is performed because the operation is performed by the physical address (PA) on the external bus.
Ping occurs, and the access time in the system increases.

[0010]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention has been developed to reduce the micro access time and increase the performance of the processor while allowing the use of the physical cache of the related system. It is an object to provide a directory-virtual cache control method .

[0011]

SUMMARY OF THE INVENTION To achieve the above object, a method for controlling a dual directory virtual cache according to the present invention is provided. The method for controlling a virtual cache includes a virtual address in response to a request from a microprocessor having a bus monitoring logic circuit. a method of accessing a catcher Sshumemori, step virtual tag corresponding to the virtual address to generate a hit signal or a miss signal by checking whether the stored in the first memory; if said hit signal is generated, stored data Determining the state of the cache line in the second memory to be performed; performing the read or write operation if the state of the cache line is valid; and changing the virtual address to the physical address if the state of the cache line is invalid Converting to; the physics obtained in the above converting step Determining whether a physical tag corresponding to the address is stored in the third memory; if there is a physical tag corresponding to the physical address obtained in the converting step in the third memory, Performing a read or write operation by copying state information of a physical tag to the first memory; if the corresponding physical address does not exist in the third memory or a miss signal is generated, the first Selecting a replacement entry in the memory; determining whether an entry corresponding to the replacement entry in the first memory exists in the third memory; and the replacement in the third memory. if there is an entry corresponding with the entries, read the new cache line from the external memory, read or write operation to step; on If an entry corresponding to the replacement entry does not exist in the third memory, another replacement entry is re-selected in the third memory, and the replacement is performed in the first memory by the re-selected entry. Selecting a corresponding entry, reading a new cache line from the external memory, and performing a read or write operation.

[0012]

[0013]

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to FIGS. First, FIG. 4 is a configuration diagram of the dual directory virtual cache according to the present invention. As shown in the drawing, the internal cache according to the present invention is roughly divided into three. That is, the internal cache according to the present invention is a physical tag memory (hereinafter referred to as P
-A tag memory) (41), a virtual tag memory (hereinafter referred to as a V-tag memory) (42), and a data memory (43).

Normally, the CPU uses the virtual address to
-To access the tag memory (42) and perform the bus snooping operation, the bus monitoring logic in the CPU accesses the P-tag memory (41) using the physical address. The memory (43) with the available actual data is accessed by the CPU through virtual addresses in parallel with the V-tag memory (42).

The P-tag memory (41) responsible for bus snooping accesses the data by comparing the address in the internal cache with the address on the bus as soon as possible. CP
In order to respond quickly, the V-tag memory (42) is accessed by the CPU together with the data memory (43).

The P-tag memory (41) is a data memory (43)
(A cache line has the size of data that can be transmitted between the cache and the memory at one time, and the tag indicates whether or not the cache data corresponds to an address). Each tag has information that can uniquely correspond to data in the data memory (43). Since the P-tag memory (41) is composed of a pointer table for the data memory (43), the V-tag memory (42) and the data memory (43) have the same association ( asso
It is not necessary to have ciativity).

The true state of the data for each line of the cache is maintained in a P-tag memory (41). V-tag memory (42)
Also maintain some information for each line. However, if the valid data is invalid in the V-tag memory (42) (i
nvalid). This is a specific case, ie, taskswitch.
This is because the V-tag item must be invalidated when an event that causes the conversion of the page table or the page table occurs. This means that a virtual and physical address mapping relationship is invalidated, and the processor must go through a verification process before accessing data.

Therefore, two kinds of mistakes occur in the V-tag memory (42), one of which is "no matchmis" which occurs due to the absence of data.
s ", the other is an" invalidmiss "in which the data is valid but the virtual address must be newly mapped. Each tag memory (41 and 42) stores the virtual address in the physical address. It has pointer information to be linked to the target address.

The CPU according to the present invention comprises a V-tag memory (4
2) and request access to the data memory (43).
At this time, if an invalid miss occurs, address conversion from a virtual address to a physical address occurs. The converted physical address is stored in the P-tag memory (41). If it is determined that the corresponding data exists in the data memory (43), the status information in the P-tag memory (41) is copied to a specific position in the V-tag memory (42). In this way, an invalid miss is processed like a hit.

When a no match occurs, the physical address is obtained by address translation and cpu checks whether it is in the P-tag memory (41). If no physical address is present in the P-tag memory (41), the cpu selects a new item, replaces the previous item with the newly selected item, calls the new data from external memory, and then calls the tag memory. (41) and (42) are updated.

The snooping (monitoring) logic circuit stores all addresses on the bus in the P-tag memory (4).
If there is a corresponding address in the P-tag memory 41 compared to 1), the following various events can occur in the snooping logic. 1) Invalidate the data and invalidate the items in the P-tag memory (41) and the V-tag memory (42).

2) When data must be driven externally, the data is driven externally using the pointer of the P-tag memory (41), and the state of the cache line is related to the driving when necessary. To change. 3) Update the data memory while changing the state of the cache line from which the data on the external bus has been read.

The dual directory virtual cache according to the present invention will be described in detail with reference to FIGS. First, FIG. 5 illustrates the dual directory virtual cache of the present invention that operates in response to a processor request.

The cpu checks whether a virtual address is stored in the V-tag memory (42). That is, the hit / miss is checked using the virtual address (step (hereinafter referred to as “step”).
Floor)) 51) . If the virtual address corresponding to the request from the cpu is stored in the V-tag memory, a hit signal is generated and the state of the corresponding cache line is checked (step 52). If the state of the cache line is valid,
A conventional read or write operation is performed at the request of the cpu (steps 56 to 60). If the state of the cache line is invalid, the virtual address is TLB (translation look-asi
de buffer) to convert to a physical address (step 5
3) The translated physical address is checked in a P-tag memory (step 54). If the corresponding physical tag exists in the P-tag memory, the status information displayed by the corresponding P-tag is V
Copied to the tag entry (step 55) and the above read or write operation is performed (step 56).

If there is no corresponding physical tag in the P-tag memory (step 54) or a miss signal is generated (step 51), cpu selects an entry to be replaced in the V-tag memory (step 51). 61) determining whether there is a corresponding entry (associated with a pointer) in the P-tag memory (step 62); If the corresponding entry exists in the P-tag memory, cpu checks whether the cache line is invalid or the cache line has been changed (step 65). If the cache line is invalid and has been changed, cpu writes the corresponding cache line to the external memory (step 66).

If the corresponding entry does not exist in the P-tag memory, cpu selects an alternative entry again in the P-tag memory (step 63), and selects a V-tag entry corresponding to the selected P-tag entry. A selection is made in the V-tag memory (step 64), and the above steps (65 and 66) are performed for the selected V-tag entry. Thus, the cpu updates the V-tag and P-tag memories using the external data, and performs the read and write operations (steps 56 to 60).

FIG. 6 illustrates a dual directory virtual cache of the present invention that operates in response to a request from a bus monitoring logic circuit. As shown, the bus monitoring logic circuit checks whether a tag corresponding to the input physical address exists in the P-tag memory (step 81). If the corresponding tag exists, the bus monitoring logic circuit checks the bus operation (step 82).

In the case of a read operation, invalid (invalid
d; data stored in the cache memory are provided to an external bus according to the state of the cache line such as I), modification (M) and sharing (S: S), and the cache memory is read by a general monitoring logic circuit. When the operation is performed, the state of the provided cache line is changed. That is, if the requested state of the cache line is changed (M), the data is written to the external memory and the state of the requested cache line is shared (S) (steps 85 and 86).

In the case of a write operation, data stored in the cache memory must be invalid. However, depending on the state of the cache line, write back (write
-Back) operation is performed (step 83). In particular, when the state of the cache line is changed (M),
The corresponding data is written back to the external memory, and since the changed (M) state has updated information, the state changes to the invalid (I) state.

Further, when an entry in the P-tag memory becomes invalid, the corresponding entry in the V-tag memory also becomes P-tag.
It must be changed to the invalid (I) state using the tag pointer.

[0032]

As described above, the present invention provides a virtual address tag memory having a physical address tag memory in the internal cache memory, thereby minimizing the time required for address translation and improving the performance of the microprocessor.
Although the present invention has been described by way of example, modifications, additions and substitutions may be made by those of ordinary skill without departing from the scope and spirit of the invention, as set forth in the appended claims.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a conventional microprocessor system.

FIG. 2 is a diagram illustrating an example of a multiprocessor using the processor of FIG. 1;

FIG. 3 is a conceptual diagram of a virtual cache access using a virtual address and a physical address in a processor using a virtual cache such as an internal cache.

FIG. 4 is a configuration diagram of a dual directory virtual cache according to the present invention;

FIG. 5 illustrates a dual directory virtual cache of the present invention that operates in response to a processor request;

FIG. 6 illustrates a dual directory virtual cache of the present invention that operates in response to a request from a berth monitoring logic circuit.

[Explanation of symbols]

 41 P-tag memory 42 V-tag memory 43 Data memory

Continuation of the front page (56) References JP-A-62-266634 (JP, A) JP-A-2-150938 (JP, A) JP-A-2-234245 (JP, A) JP-A-5-216756 (JP) JP-A-2-21342 (JP, A) JP-A-5-204756 (JP, A) JP-A-4-328655 (JP, A) JP-A-4-235648 (JP, A) JP-A-1-288940 (JP, A) JP-A-62-214453 (JP, A) JP-A-61-246850 (JP, A) JP-A-50-72542 (JP, A) A) JP-A-4-322340 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 12/08-12/12

Claims (4)

(57) [Claims] 1. A method for accessing a key catcher Sshumemori by the virtual address in response to a request from the microprocessor provided with the bus monitoring logic circuit, or virtual tag corresponding to the virtual address is stored in the first memory Generating a hit signal or a miss signal by examining the data; if the hit signal is generated, storing a second data
Determining a state of a cache line in the memory; performing a read or write operation if the state of the cache line is valid; converting a virtual address to a physical address if the state of the cache line is invalid Determining whether the physical tag corresponding to the physical address obtained in the converting step is stored in a third memory; and storing the physical tag obtained in the converting step in the third memory. Copying the status information of the physical tag to the first memory if the physical tag corresponding to the address exists, and performing a read or write operation; if the physical address does not exist in the third memory; Selecting a replacement entry in the first memory when a miss signal or a miss signal is generated; Entry corresponding to an entry to be replaced in the memory step to determine present in the third memory; if there is an entry corresponding to an entry that is the alternative to and the third memory, an external memory Reading a new cache line and performing a read or write operation; if an entry corresponding to the replacement entry does not exist in the third memory, another replacement entry is reselected in the third memory. And a step of selecting a corresponding entry to be substituted in the first memory by the reselected entry, reading a new cache line from the external memory, and performing a read or write operation. How to control dual directory virtual caches. 2. The method according to claim 1, wherein the third memory is accessed by the bus monitoring logic circuit using a physical address on a bus . 3. The bus monitoring logic circuit according to claim 2, wherein the bus monitoring logic circuit changes state information of the physical tag, and the state information of the virtual tag is changed by the changed state information of the physical tag. Characteristic control method of double directory virtual cache. 4. The method of claim 2, wherein the third memory has pointer information that associates the physical tag with the virtual tag.