KR970029072A - Dual Directory Virtual Cache and Its Control Method - Google Patents

Abstract

The present invention provides a V-tack memory 42 for accessing data using a virtual address by an external processor (CPU); A P-tack memory 41 for accessing data using a physical address loaded on an external bus; And a data memory 43 for storing actual data, wherein the data memory 43 is configured to access data in parallel with the V-tack memory using the virtual address by an external processor. And a tag for each cache line in the baby data memory, wherein the tag of the P-tack memory 41 has information to enable correspondence with data in the data memory 43. It is a dual directory virtual cache that is characterized by reducing the cycles of cache access to improve the performance of microprocessors, and to give a performance advantage over systems using a physical cache. .

Description

Dual Directory Virtual Cache and Its Control Method

As this is a public information case, the full text was not included.

4 is a configuration diagram of a dual directory virtual cache according to an embodiment of the present invention;

5 is a flowchart illustrating an operation of the cache system in response to a request of a processor (CPU);

6 is an embodiment flow diagram illustrating the operation of the present cache system in response to a request of bus monitoring logic.

Claims (7)

A V-tack memory for accessing data using a virtual address by an external processor; A P-tack memory for accessing data using a physical address loaded on an external bus; And a data memory storing actual data, wherein data access is performed in parallel with the V-tack memory using the virtual address by an external processor, wherein each of the P-tack memories is located in the data memory. And a tag for a cache line, wherein said tag of said P-tag memory has information to enable correspondence with data in said data memory. 2. The dual directory virtual cache of claim 1 wherein the P-tack memory has a pointer table to the data memory, and does not need to have the same association as the V-tack memory and the data memory. 3. The dual directory virtual cache of claim 2 wherein the P-tack memory maintains a true state of data for each of the cache lines. 4. The dual directory virtual cache of claim 3 wherein each of the V-tag and P-tag memories has pointer information linking the virtual and physical address pairs. A method for controlling a dual directory virtual cache, comprising: a first step of, when requested by an external processor, checking whether a V-tack memory is hit / missed using a virtual address; In the first step, when a hit occurs, the operation is terminated by taking the operation according to whether the corresponding cache line is valid or copying state information of the P-tack memory to the V-tack memory, and then operating the corresponding operation line. Taking a second step and ending; In the first step, when a miss occurs in the V-tack memory, selecting an entry to be reflected in the V-tack memory and checking whether the entry exists in the P-tack memory; In the third step, if there is an entry in the P-tack memory, a second method of performing a reply or immediately performing a reply after the write-back is performed according to whether the corresponding line is valid and whether the corresponding line is changed. Step 4; In the third step, if the entry is not in the P-tack memory, after selecting another target to be reflected among the P-tack memories, the state of the V-tack memory, whether the corresponding line is valid, and whether the corresponding line is changed According to the fifth step of performing a reply after performing the write-back or immediately performing a reply; And a sixth step of taking the operation and ending the operation after performing the fourth and fifth steps of the reflection. When the external bus monitoring logic requests, the physical address is accepted to match the physical address. A seventh step of terminating immediately according to whether the P-tack memory exists or checking whether the operation occurring in the corresponding bus is 'read' or 'write'; In the seventh step, if the operation is 'read', the internal cache data is supplied to the external bus according to the state of the corresponding cache line, and the state of the cache line is changed or only the state of the cache line is changed. An eighth step of notifying after sharing; And in the seventh step, if the operation is 'write', the state of the cache line is changed to 'invalid' accordingly, and the state of the corresponding entry is 'invalid' in the V-tack memory using the P-tack pointer. And a ninth step of switching to a state. 6. The method of claim 5, wherein the second step comprises: a tenth step of, if a hit occurs, taking a corresponding operation if the corresponding cache line is valid; In the first step, when a hit occurs, if the corresponding cache line is invalid, the virtual address is converted into a physical address, and when there is a match in the P-tack memory, the state information of the P-tack memory is read. Copying to the V-tack memory; And performing a corresponding operation after performing the eleventh step, and controlling the dual directory virtual cache. The method of claim 6, wherein the taking of the corresponding operations in the second and sixth steps comprises: a thirteenth step of identifying an operation to be operated; In the thirteenth step, when the operation is 'read', a fourteenth step of reading the corresponding data and ending; In the thirteenth step, when the corresponding operation is 'write', a fifteenth step of performing data writing and terminating or changing the state information according to whether the corresponding line is changed includes writing and ending data writing. The control method of the dual directory virtual cache, characterized in that. ※ Note: The disclosure is based on the initial application.