JP3540643B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a group III-V nitride-based semiconductor layer (hereinafter referred to as a nitride semiconductor) of GaN (gallium nitride), AlN (aluminum nitride), InN (indium nitride), BN (boron nitride), or a mixed crystal thereof. The present invention relates to a method for manufacturing a semiconductor device having a compound semiconductor layer consisting of
[0002]
[Prior art]
In recent years, nitride semiconductor light emitting devices such as GaN, InGaN, AlGaN, and AlGaInN have been put into practical use as semiconductor light emitting devices capable of emitting light in a wavelength range over the ultraviolet region. The nitride-based semiconductor light emitting device as described above is expected to be applied as an environment-resistant electronic device used at high temperatures or a high-frequency high-power electronic device used in mobile communication and the like.
[0003]
When a GaN-based semiconductor light emitting device is manufactured, since a substrate made of GaN does not exist, an organic metal vapor phase epitaxy (hereinafter, referred to as GaN) is performed on an insulating substrate such as sapphire (Al ₂ O ₃ ) having the same hexagonal system as GaN. The GaN-based semiconductor layer is heteroepitaxially grown by MOVPE method, molecular beam epitaxial growth method (MBE method), or the like. In this case, the sapphire substrate and the GaN-based semiconductor layer have different lattice constants.
[0004]
In a conventional semiconductor light emitting device that emits infrared light or red light, since the crystal orientation of the substrate and each semiconductor layer on the substrate match, the wafer can be easily separated by cleaving the substrate on a surface that is easily cleaved. Can be separated.
[0005]
On the other hand, in the GaN-based semiconductor light-emitting device, both the sapphire substrate and the GaN-based semiconductor layer are easily cleaved on the (10-10) plane, but the sapphire substrate and the GaN-based semiconductor layer have different lattice constants as described above. The crystal orientations of the substrate and the GaN-based semiconductor layer are shifted. Therefore, both (10-10) planes are not the same plane. The sapphire substrate and the GaN-based semiconductor layer are both very hard materials and have a Mohs hardness of 9. As described above, in the GaN-based semiconductor light emitting device, it is difficult to separate the wafer into individual devices by cleavage.
[0006]
A method for manufacturing such a GaN-based or other nitride-based semiconductor device is disclosed in JP-A-7-1310069 and JP-A-9-167858.
[0007]
In the manufacturing method described in Japanese Patent Application Laid-Open No. Hei 7-1310069, first, an n-type nitride-based semiconductor layer, a light-emitting layer, and a p-type nitride-based semiconductor layer are sequentially formed on one surface of a sapphire substrate. Next, a part of the predetermined region from the p-type semiconductor layer to the n-type semiconductor layer is etched to simultaneously form the n-electrode formation region where the n-type semiconductor layer is exposed and the first split groove. Thus, the first split grooves are formed in a lattice on the wafer.
[0008]
Subsequently, a position corresponding to the first split groove on the back surface of the sapphire substrate is scribed to form a second split groove. In this case, the width of the second split groove is smaller than the width of the first split groove.
[0009]
Finally, the wafer is separated into individual devices along the first and second grooves.
On the other hand, in the manufacturing method disclosed in JP-A-9-167858, first, an n-type nitride-based semiconductor layer, a light-emitting layer, and a p-type nitride-based semiconductor layer are sequentially formed on one surface of a sapphire substrate. Next, a part of the predetermined region from the p-type semiconductor layer to the n-type semiconductor layer is etched to form a dicing line boundary region where the n-type semiconductor layer is exposed. Thus, convex dicing lines are formed on the wafer in a lattice pattern.
[0010]
Subsequently, the convex dicing line is used as a recognition pattern, and dicing is performed with a blade slightly wider than the width of the dicing line. Thus, the first split groove is formed.
[0011]
Finally, a second split groove is formed by scribing a position corresponding to the first split groove on the other surface of the sapphire substrate, and a load is applied along the first and second split grooves. Separate the wafer into individual devices.
[0012]
[Problems to be solved by the invention]
In the manufacturing method disclosed in Japanese Patent Application Laid-Open No. Hei 7-1310069, since the n-electrode formation region and the first split groove are formed simultaneously by etching, the width of the first split groove is increased. For this reason, it is difficult to separate the element at the center of the first split groove, and the separation surface is formed biased to one of the adjacent elements. Therefore, it becomes difficult to manufacture a uniform element, and the yield of the element decreases.
[0013]
On the other hand, in the manufacturing method disclosed in Japanese Patent Application Laid-Open No. 9-167858, it is necessary to etch a dicing line boundary region having a small width in order to form a dicing line serving as a recognition pattern at the time of dicing. In etching such a small width region, it is difficult to control the depth. For this reason, it is necessary to take measures such as increasing the distance between adjacent elements and increasing the width of the dicing line boundary region, and the productivity of the elements decreases.
[0014]
An object of the present invention is to provide a method of manufacturing a semiconductor device which is easy to separate and has a high yield.
[0015]
Means for Solving the Problems and Effects of the Invention
The method for manufacturing a semiconductor device according to the present invention includes a step of forming a first semiconductor layer made of a nitride-based semiconductor containing at least one of aluminum, indium, gallium and boron on a main surface of a substrate; Forming a second semiconductor layer made of a nitride-based semiconductor containing at least one of aluminum, indium, gallium and boron on the semiconductor layer, and forming a split groove extending from the second semiconductor layer to the substrate Etching the inner surface of the split groove from the second semiconductor layer to the first semiconductor layer to form exposed side surfaces of the first and second semiconductor layers and an exposed bottom surface of the first semiconductor layer; Forming an electrode on the exposed bottom surface of the first semiconductor layer, and dividing the substrate together with the first and second semiconductor layers along the dividing groove.
[0016]
In the method of manufacturing a semiconductor device according to the present invention, first and second semiconductor layers are sequentially formed on a substrate, and a dividing groove extending from the second semiconductor layer to the substrate is formed. Thereafter, the portion from the second semiconductor layer to the first semiconductor layer on the inner surface of the split groove is removed by etching, and an electrode is formed on the exposed bottom surface of the first semiconductor layer. Finally, the substrate is divided along with the formed groove along with the first and second semiconductor layers, and separated into individual elements.
[0017]
In the above-described method for manufacturing a semiconductor element, after forming the split groove, the region where the electrode is to be formed is exposed by etching. In this case, since the width of the split groove may be small, the element can be separated by a vertical separation surface along the split groove. Therefore, an element having a desired shape and size can be manufactured uniformly.
[0018]
In addition, since the first and second semiconductor layers damaged at the time of forming the split groove can be removed by etching, the characteristics and reliability of the device are reduced due to the damage at the time of forming the split groove. There is no.
[0019]
From the above points, it is possible to manufacture a uniform element with a high yield.
Further, since the split groove is formed before the electrode is formed, it is not necessary to position the split groove with high accuracy. Therefore, when forming the dividing groove, a recognition pattern for specifying the position of the dividing groove becomes unnecessary, so that the process of separating the elements becomes easy and the interval between adjacent elements can be reduced. Therefore, manufacturing efficiency and productivity are improved.
[0020]
It is preferable that the method further includes a step of forming a separation line at a position on the back surface of the substrate corresponding to the dividing groove before dividing the substrate. This makes it possible to easily and uniformly separate the elements on the vertical separation plane along the dividing groove and the separation line.
[0021]
Preferably, the method further includes a step of grinding the back surface of the substrate to a predetermined thickness after forming the electrodes. This makes it possible to make the substrate thinner, which further facilitates element separation.
[0022]
The split groove may be formed by dicing. This makes it possible to easily form a groove having a desired pattern. Further, since the first and second semiconductor layers on the inner surfaces of the split grooves damaged by the dicing are removed by etching, the characteristics and reliability of the element are not reduced by the dicing.
[0023]
Further, the separation line may be formed by scribe. Thus, the separation line can be easily formed, and the elements can be uniformly separated along the dividing groove and the separation line.
[0024]
The second semiconductor layer may include a light emitting layer. In this case, it is possible to manufacture a semiconductor light emitting device having a light emitting layer from which damage at the time of forming the split groove has been removed and having a uniform shape and size. Therefore, it is possible to manufacture a semiconductor light-emitting element with small variations and uniform characteristics and reliability at a high yield.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the case where the method for manufacturing a semiconductor device according to the present invention is applied to the manufacture of a GaN-based light emitting diode device (hereinafter, referred to as an LED chip) will be described.
[0026]
FIG. 1 is a cross-sectional view of an LED chip manufactured by the method for manufacturing a semiconductor device according to the present invention, and FIGS. 2 to 6 are cross-sectional views showing the manufacturing steps of the LED chip of FIG.
[0027]
As shown in FIG. 1, the LED chip has a low-temperature buffer layer 2 made of AlN, a first high-temperature buffer layer 3 made of undoped GaN, and a second layer made of undoped GaN on a (0001) plane of a sapphire substrate 1. Buffer layer 4, n-contact layer 5 made of n-GaN, multiple quantum well light emitting layer (hereinafter referred to as MQW light emitting layer) 6, protective layer 7 made of undoped GaN, p-Al _0.05 Ga _0.95 N A p-cladding layer 8 and a p-contact layer 9 made of p-GaN are sequentially formed.
[0028]
In the above semiconductor layers 2 to 9, the low-temperature buffer layer 2 is a non-single-crystal layer, and the other layers 3 to 9 are single-crystal layers.
[0029]
In the LED chip of FIG. 1, Si is used as an n-type dopant, and Mg is used as a p-type dopant.
[0030]
The MQW light emitting layer 6 has a multiple quantum well structure in which six quantum barrier layers 6a made of undoped GaN and five quantum well layers 6b made of undoped Ga _0.65 In _0.35 N are alternately stacked.
[0031]
In the above-mentioned LED chip, the n-contact layer 5 also functions as an n-cladding layer. Further, the protective layer 7 is a layer for preventing crystal deterioration of the MQW light emitting layer 6.
[0032]
On the p-contact layer 9, a p-side translucent electrode 10 formed by sequentially stacking a Ni film 10a and an Au film 10b is formed. Further, a p-side pad electrode 11 formed by laminating a Ti film 11a and an Au film 11b in a predetermined region on the p-side translucent electrode 10 is formed.
[0033]
On the other hand, a part of the region from the p-contact layer 9 to the n-contact layer 5 is etched, and the n-contact layer 5 is exposed.
[0034]
An n-side electrode 12 made of an Al film is formed on the exposed n-contact layer 5.
[0035]
Next, a method for manufacturing the LED chip of FIG. 1 will be described.
First, the sapphire substrate 1 is set in a MOVPE apparatus. Next, in this apparatus, as shown in FIG. 2, a low-temperature buffer layer 2 and a first high-temperature buffer layer 3 are formed on the (0001) plane of the sapphire substrate 1 by MOVPE (metal organic chemical vapor deposition). And a second high-temperature buffer layer 4 and an n-contact layer 5 are sequentially grown.
[0036]
During the growth of the low-temperature buffer layer 2, the substrate temperature is maintained at a temperature at which a non-single crystal grows, for example, 600 ° C. NH ₃ , trimethylaluminum (TMAl) and trimethylgallium (TMGa) are used as a source gas, and a gas composed of H ₂ and N ₂ and having a H ₂ content of about 50% is used as a carrier gas. .
[0037]
Thus, undoped AlN is grown to form the low-temperature buffer layer 2 having a thickness of 20 nm.
[0038]
During the growth of the first high-temperature buffer layer 3, the second high-temperature buffer layer 4, and the n-contact layer 5, the substrate temperature is maintained at a temperature at which a single crystal grows, for example, 1150 ° C. In this case, it is preferable to maintain the substrate temperature at 1000 to 1200 ° C. In addition, NH ₃ and TMGa are used as source gases for these layers 3 to 5, and the same gas as that used when growing the low-temperature buffer layer 2 is used as a carrier gas. Further, SiH ₄ is used as a dopant gas for the n-contact layer 5.
[0039]
Thus, the first high-temperature buffer layer 3 made of undoped GaN and having a thickness of 80 nm, the second high-temperature buffer layer 4 made of undoped GaN having a thickness of 0.4 μm, and the thickness 1. An n-contact layer 5 of 5 μm is formed in order. In this case, the growth rates of the layers 3, 4, and 5 are about 0.7 nm / s, about 3 μm / h, and about 3 μm / h, respectively.
[0040]
Next, an MQW light emitting layer 6 is formed by alternately growing six quantum barrier layers 6a and five quantum well layers 6b on the n-contact layer 5, and a protective layer 7 is formed on the MQW light emitting layer 6. Grow.
[0041]
During the growth of the MQW light emitting layer 6 and the protective layer 7, the substrate temperature is maintained at a temperature at which a single crystal grows, for example, 850 ° C. In this case, it is preferable to maintain the substrate temperature at 700 to 1000 ° C. NH ₃ , triethylgallium (TEGa) and trimethylindium (TMIN) are used as source gases for these layers 6 and 7. Further, as the carrier gas, a gas composed of H ₂ and N ₂ and having a H ₂ content of about 1 to 5% is used.
[0042]
In this manner, six 5 nm-thick quantum barrier layers 6a made of undoped GaN and five five-nm thick quantum well layers 6b made of undoped Ga _0.65 In _0.35 N are alternately grown to form the MQW light emitting layer 6. Is formed, and undoped GaN is grown to form a protective layer 7 having a thickness of 10 nm. In this case, the growth rates of the MQW light emitting layer 6 and the protective layer 7 are both about 0.4 nm / s.
[0043]
Further, a p-cladding layer 8 and a p-contact layer 9 are grown on the protective layer 7.
[0044]
During the growth of the p-cladding layer 8 and the p-contact layer 9, the substrate temperature is maintained at a temperature at which a single crystal grows, for example, 1150 ° C. In this case, it is preferable to maintain the substrate temperature at 1000 to 1200 ° C. NH ₃ , TMGa and TMAl are used as source gases for the p-cladding layer 8, and NH ₃ and TMGa are used as source gases for the p-contact layer 9. The carrier gas of the p-cladding layer 8 and the p-contact layer 9 is a gas composed of H ₂ and N ₂ and having a H ₂ content of about 1 to 3%, and a dopant gas of Cp ₂ Mg is used.
[0045]
During the growth of the p-cladding layer 8 and the p-contact layer 9, the p-type dopant can be activated by lowering the H ₂ composition in the carrier gas as described above. Therefore, in this case, the heat treatment in the N ₂ atmosphere for activating the p-type dopant as in the related art is not required.
[0046]
In this manner, p-Al _0.05 Ga _0.95 N and p-GaN are sequentially grown to form a p-cladding layer 8 having a thickness of 0.15 μm and a p-contact layer 9 having a thickness of 0.3 μm. In this case, the growth rates of p-cladding layer 8 and p-contact layer 9 are both about 3 μm / h.
[0047]
Subsequently, using a dicer device having a blade having a blade thickness of 25 μm, as shown in FIG. 3, a dividing groove 50 extending from the p-contact layer 9 to the sapphire substrate 1 is formed by dicing. As a result, the split grooves 50 are formed in a lattice on the wafer.
[0048]
In this case, the depth of the split groove 50 is preferably set to 20 to 30 μm in consideration of the wafer thickness, warpage, and the like so that the bottom of the split groove 50 reaches the sapphire substrate 1.
[0049]
During dicing, the layers 2 to 9 on the inner surface of the split groove 50 and the sapphire substrate 1 are damaged. For this reason, a chip 61 or a crack 60 occurs on the inner surface of the split groove 50.
[0050]
After the above dicing, as shown in FIG. 4, the inner surface of the split groove 50 is etched from the p-contact layer 9 to the n-contact layer 5 by a reactive ion beam etching method (RIBE method) or the like. Thereby, an n-side electrode formation region 51 in which the n-contact layer 5 is exposed is formed. Further, a region on the inner surface of the split groove 50 damaged during dicing is removed by etching.
[0051]
FIG. 5 is a view of the wafer of FIG. 4 having undergone the above manufacturing steps as viewed from the p-contact layer 9 side.
[0052]
As shown in FIG. 5, split grooves 50 are formed in a lattice shape on the wafer surface. The area 100 defined by the split grooves 50 is an individual LED chip area. Further, the n-side electrode forming region 51 has a shape in which one corner of the LED chip region is cut off in a semi-arc shape.
[0053]
After the formation of the n-side electrode formation region 51, as shown in FIG. 6, a Ni film 10a having a thickness of 2 nm and an Au film 10b having a thickness of 4 nm are sequentially stacked over substantially the entire surface of the p-contact layer 9, and The side translucent electrode 10 is formed. Further, a Ti film 11a having a thickness of 30 nm and an Au film 11b having a thickness of 500 nm are sequentially laminated on a predetermined region of the p-side translucent electrode 10 to form a p-side pad electrode 11. Further, the n-side electrode 12 made of an Al film having a thickness of 500 nm is formed on the n-side electrode formation region 51.
[0054]
The p-side translucent electrode 10, the p-side pad electrode 11, and the n-side electrode 12 are formed by a vacuum evaporation method or the like.
[0055]
The p-side translucent electrode 10 and the n-side electrode 12 thus formed are heat-treated at 500 ° C. to make ohmic contact with the p-contact layer 9 and the n-contact layer 5, respectively.
[0056]
Next, the back surface side of the sapphire substrate 1 is ground to make the thickness of the wafer 100 μm, and a position corresponding to the split groove 50 is scribed to form a separation line 52. Finally, the sapphire substrate 1 is separated into a plurality of LED chips by applying pressure along the separation line 52 using a breaker device.
[0057]
Preferably, the thickness of the wafer is reduced to about 100 μm by grinding. Thereby, it is possible to easily separate the LED chips along the split grooves 50 and the separation lines 52.
[0058]
In the above-described LED chip manufacturing method, the n-side electrode formation region 51 is formed by etching after the split groove 50 is formed by dicing. Therefore, it is not necessary to set the width of the first split groove 50 large. Therefore, the separation surface is not formed unevenly on any one of the LED chips, and can be separated evenly on the vertical separation surface along the dividing groove 50 and the separation line 52. As a result, LED chips having a uniform shape and size can be manufactured along the lattice-shaped split grooves 50.
[0059]
In addition, the layers 2 to 9 damaged by dicing, particularly, the regions of the MQW light emitting layer 6, the n-contact layer 5, and the p-cladding layer 8 which affect light emission are removed by etching. The characteristics and reliability of the LED chip do not decrease.
[0060]
Further, since the split groove 50 is formed before the electrode is formed, it is not necessary to position the split groove 50 with high accuracy. Therefore, the alignment at the time of dicing need only recognize the end face of the wafer, and there is no need to form a recognition pattern of the dicing position as described above. For this reason, the manufacturing efficiency is improved, and the interval between the adjacent LED chips can be reduced, so that the productivity is improved.
[0061]
As described above, according to the method for manufacturing an LED chip according to the present invention, an LED chip can be efficiently manufactured with a high yield.
[0062]
In the above description, the case where each layer is made of a nitride-based semiconductor containing Al, In, and Ga has been described. However, each layer may be made of a nitride-based semiconductor containing boron.
[0063]
In the above, the case where the method of manufacturing a semiconductor device according to the present invention is applied to the manufacture of an LED chip has been described. However, the method of manufacturing a semiconductor device according to the present invention is also applicable to the manufacture of a semiconductor laser device and other semiconductor devices. Applicable.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a light emitting diode device manufactured by a method of manufacturing a semiconductor device according to the present invention.
FIG. 2 is a cross-sectional view illustrating a manufacturing process of the light-emitting diode element of FIG.
FIG. 3 is a cross-sectional view illustrating a manufacturing process of the light-emitting diode element of FIG.
FIG. 4 is a cross-sectional view illustrating a process of manufacturing the light-emitting diode element of FIG.
FIG. 5 is a plan view of the wafer of FIG. 4;
FIG. 6 is a cross-sectional view showing a step of manufacturing the light-emitting diode element of FIG.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 sapphire substrate 2 low-temperature buffer layers 3 and 4 high-temperature buffer layer 5 n-contact layer 6 MQW light emitting layer 7 protective layer 8 p-cladding layer 9 p-contact layer 10 p-side translucent electrode 11 p-side pad electrode 12 n-side Electrode 50 Split groove 51 n-side electrode forming area 52 separation line

Claims (6)

Forming a first semiconductor layer made of a nitride-based semiconductor containing at least one of aluminum, indium, gallium and boron on a main surface of the substrate;
Forming a second semiconductor layer made of a nitride-based semiconductor containing at least one of aluminum, indium, gallium and boron on the first semiconductor layer;
Forming a split groove extending from the second semiconductor layer to the substrate;
Etching from the second semiconductor layer to the first semiconductor layer on the inner surface of the split groove to form exposed side surfaces of the first and second semiconductor layers and an exposed bottom surface of the first semiconductor layer The process of
Forming an electrode on the exposed bottom surface of the first semiconductor layer;
Dividing the substrate along with the first and second semiconductor layers along the split groove. 2. The method according to claim 1, further comprising forming a separation line at a position on the back surface of the substrate corresponding to the dividing groove before dividing the substrate. 3. The method according to claim 1, further comprising a step of grinding the back surface of the substrate to a predetermined thickness after the formation of the electrode. 4. The method according to claim 1, wherein the dividing groove is formed by dicing. The method according to claim 1, wherein the separation line is formed by scribe. The method according to claim 1, wherein the second semiconductor layer includes a light emitting layer.

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