JPH0438836A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, the following objects are provided: High-speed operation of an element by reducing parasitic capacitance and source resistance around a gate electrode, and reproducibility in the removal rate by recess etching. A method for manufacturing a semiconductor device includes, on a semiconductor substrate, an active layer, a first cap layer having an etching rate higher than that of the surface layer of the active layer, and an etching stopper layer having an etching rate different from that of the first cap layer. a second cap layer having an etching rate different from that of the etching stop layer and thicker than the first cap layer, and a mask layer having a first opening selectively in an electrode layer formation region. a step of sequentially laminating the layers, a step of removing the second cap layer exposed in the first opening by anisotropic etching using the mask layer as a mask, and stopping the etching at the surface of the etching stop layer; forming a metal mask layer having a second opening narrower than the first opening by depositing metal obliquely on the surface of the mask layer; removing the etching stop layer; removing the first cap layer exposed at the second opening by anisotropic etching and stopping at the surface of the active layer; in contact with the active layer and the first cap layer;
The process of forming an electrode layer that does not come into contact with the cap layer was adopted.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device.

Hereinafter, an enhancement type heterojunction FET (hereinafter referred to as ε-HEMT) having a recessed gate structure will be described as an example of a semiconductor device.

In heterojunction FETs, the threshold voltage V0 is determined by the depth of recess etching of the cap layer, or a cess gate structure is often used.In recent years, a cess gate structure has been proposed in which the cap layer around the gate electrode is partially removed. has been done.

Since the rate of removal greatly affects the performance of the device, recess etching is required to ensure reproducibility in the rate of removal.

[Conventional technology]

HEMT (High Electron Mobile)
Heterojunction field effect transistors (hereinafter referred to as heterojunction FETs), typified by the TY Transistor, are a new type of transistor that operates by controlling the concentration of a high electron mobility two-dimensional gas at the semiconductor heterojunction interface using a field effect. A group of high-speed devices. Among these, the high speed of enhancement type heterojunction FET is
This is important for increasing the speed of LSI.

A recessed gate structure is a structure in which the part of the active layer of the FET directly below the gate electrode is removed by etching to create a predetermined channel layer thickness, and the thickness of the Nl region between the source and gate and the train and gate is kept larger than the channel layer thickness. A structure that reduces parasitic resistance.

In a recessed gate structure, when the sidewalls of the cap layer and the gate electrode come into contact, parasitic capacitance around the gate electrode (hereinafter referred to as parasitic capacitance) increases and gate breakdown voltage decreases. Therefore, this structure was proposed in which a part of the cap layer around the gate electrode was removed, and for E-HEMT, a structure as shown in FIG. 3 was proposed (Japanese Patent Laid-Open No. 62-202564).

That is, on a semiconductor substrate 1, a channel layer 2, an electron supply layer 3, a first cap layer 4, an etching stop layer 5, and a second etching layer are formed.
A cap layer 6 is sequentially grown, and an ohmic electrode 8.9 is deposited and alloyed. Next, a photoresist is applied, the gate formation region is opened, and the second cap layer is selected for the etching stop layer 5 and isotropically etched (step 301).

The second etch stop layer 5 and the first cap layer 4 are anisotropically etched with a predominance perpendicular to the substrate (step 30).
2).

Finally, the gate electrode 11 is formed, and the A1 layer other than the gate electrode 11 is lifted off and removed together with the film resist (step 303).

Note that the above-mentioned problem is unlikely to occur in a depression mode heterojunction FET (so-called D-HEMT) even if it has a recessed gate structure. Here, D-
A cross-sectional view of the HEMT recess gate structure is shown in FIG. Similarly, the thickness of the cap layer is increased to reduce the source resistance, and since the cap layer has a side edge, it does not contact the gate electrode, and the parasitic capacitance is reduced. However, when an E-HEMT is structured as shown in Figure 4, a depletion layer extends from the gate edge, resulting in two-dimensional electron gas (two-dimensional electron gas).
DEC) channel is turned off and the FET stops working. Therefore, the structure shown in Figure 3 was adopted. That is, the first cap layer is provided to prevent the depletion layer from reaching the two-dimensional electron gas from the edge of the gate, the second cap layer is further thickened to reduce the source resistance, and the second cap layer is formed by side etching. This prevents the cap layer and the gate electrode from coming into contact with each other.

[Invention or problem to be solved]

■E-HE obtained by the above method or having a cessgate structure
In MT, since the second cap layer 6 around the gate electrode 11 is removed isotropically, the second cap layer 6 may be removed as shown in FIG. 5(b) depending on the degree of etching as described later. There is a possibility that it will be cut down more than necessary. Figure 5 (b
), the channel region between the source and drain is narrowed because the second cap layer is removed more than necessary. Therefore, in the structure shown in FIG. 5(b), the source resistance becomes large, which hinders high-speed operation of the device.

(2) Furthermore, among the above methods, the isotropic etching step 301 has a problem in that the removal rate is not reproducible.

That is, the amount of etching performed for a certain etching time under certain conditions is not constant. One reason for this is thought to be the oxidation of the gallium arsenide layer (n-GaAs) used as the second cap layer 6. The gallium arsenide layer is easily oxidized, and once oxidized, it is difficult to be etched. Although the gallium arsenide layer is oxidized during the step 301, the degree of oxidation is not constant. As a result, if the rate of removal by etching is small, the gate electrode 11 and the second cap layer 6 may come into contact as shown in FIG. 5(a). On the other hand, if the removal rate by etching is too high, as shown in FIG. 5(b), the channel for the source/drain current will be etched, leading to an increase in the source resistance as described above.

■Furthermore, in the conventional method using wet etching,
When the gate length is shortened, there is also the problem that some parts of the wafer are etched and some are not. This is because in wet etching, there are cases where the etching solution does not penetrate into the cap layer due to the influence of the etching solution or its surface tension.

In view of these problems, the present invention provides the following means for the purpose of reducing the parasitic capacitance and source resistance around the gate electrode and making the removal rate by recess etching reproducible.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor device, in which active layers (2, 3) are formed on a semiconductor substrate 1, and the etching rate is lower than that of the surface layer of the active layer. a different first cap layer 4; an etching stop layer 5 having a different etching rate than the first cap layer; and a second cap having a different etching rate than the first cap layer and being thicker than the first cap layer. layer 6 and a mask layer 7 selectively having a first opening in the electrode layer formation region; and using the mask layer as a mask, the second layer exposed in the first opening. By removing the cap layer by anisotropic etching and stopping at the surface of the etching stop layer, and depositing metal from an oblique direction on the surface of the mask layer, a first opening narrower than the first opening is formed. forming a metal mask layer 10 having two openings; removing the etching stop layer and removing the first cap layer exposed in the second opening by anisotropic etching; a step of stopping at the surface of the active layer;
After removing the mask layer and the metal mask layer, forming an electrode layer in contact with the exposed active layer and the first cap layer but not in contact with the second cap layer. .

[Effect]

(2) Since the second cap layer 6 has substantially vertical sidewalls located around the gate electrode 11,
The distance between the cap layer 6 and the cap layer 6 can be maintained approximately equal;
A large channel region can be secured without the second cap layer 6 coming into contact with the gate electrode 11.

■Also, at the gate opening, a second
By selectively and anisotropically etching the cap layer 6, the second cap layer 6 can be removed by the pattern width perpendicular to the substrate l.

Furthermore, a selective thin film 10 is deposited on the patterning mask 7 to narrow the pattern width to make the gate length, and selective anisotropic etching is performed on the first cap layer 4 from above the mask layer 7. By doing this, the first cap layer 4 can be removed by the gate length perpendicular to the substrate l.

Thereby, the gate electrode 11 and the second cap layer 6 are not brought into contact with each other, and the distance between them is kept constant.

〔Example〕

Embodiments of the present invention will be described using an E-HEMT having a recessed structure as an example.

FIG. 1 shows the E of a recessed gate structure according to an embodiment of the present invention.
- The steps of the HEMT manufacturing method are shown.

In step 102 in the figure, a semiconductor substrate is etched with a channel layer 2, an electron supply layer 3, a first cap layer 4, and an etching stop layer 5.
, a second cap layer 6 is sequentially grown and a patterning mask 7 is applied as a photoresist to a portion where a gate opening is planned.

Here, the substrate l is a semi-insulating GaAs substrate, the channel layer 2 is made of Andsoap GaAs with a thickness of 5000 nm, and the electron supply layer 3 is made of n-AI GaAs with a thickness of 350 nm.
A, the first cap layer 4 is made of n-GaAs with a thickness of 1
In the etching stop layer 5, n-AIGaA was used for 50 people.
The second cap layer 6 is made of n-Ga.
As is MBE or MO with a thickness of 700 people.
It was deposited by CVD method. Note that the cap layer is not limited to gallium arsenide, but may also be an indium compound or the like.

In this structure, the thickness of the first cap layer 4 and the etching stop layer 5 above the electron supply layer 3 that supplies the two-dimensional electron gas (20EG) is 150 and 5.
With this film thickness, the 2DEC has sufficient electron density, so the source resistance does not increase.

Ohmic electrode 8.9 is made of AuGe on the surface of the above layered structure.
/Au (200/2800 people) is vapor-deposited and alloyed so as to reach the channel layer 2, and then a patterning mask 7 is applied as a photoresist, and a pattern width longer than the gate length is opened in the area where the gate is to be formed. do. The width of the planned gate opening portion is approximately 0.5 to 0.6 μm.

During the transition from step 101 to step 102, dry etching is selectively and anisotropically applied to the second cap layer 6 from above the patterning mask. Since the pattern mask 7 and the second cap layer 6 are selective, the pattern mask 7 is not removed together with the second cap layer 6. Further, since the second cap layer 6 is etched anisotropically, the second cap layer 6 is removed in the etching direction along the pattern width. Therefore, a certain percentage is always removed, and the removal rate is reproducible. Furthermore, since trial etching is generally carried out under a constant pressure, the controllability of etching is also higher than that in wet etching.

For such etching, for example, reactive ion etching (RIE) using a mixed gas of CCl2F2 and He is used. This is because such etching causes relatively little surface damage peculiar to tri-etching and is highly selective and anisotropic. Ar is added to increase the etching rate, and H2 is added to increase the selectivity with the mask. CC1,F is made by etching GaAs and AlGaAs to form GaC
1*, C1 to generate volatile gases such as AsC1-, AlCl-, etc., and GaF, A to suppress etching.
It consists of F which generates non-volatile compounds such as IF. FIG. 2 shows an example of etching characteristics.

P[CCl2F,]/P[H2]=1. When the RF power is 0.18W/cm2, the etching speed is AlG.
aAs: 20 people/min, GaAs: 5200 people/min
The selection ratio is more than 200 times that of min. With this technique, the AlGaAs layer can be used as an etching stopper material, and any thickness can be controlled by dry etching. The type of etching is not limited to RIH; other methods include ion beam etching, and IBAE (
With ion-beam assist etching, a high etching rate of 3 to 5 μm/min can be obtained for GaAs.

Note that the etching stop layer 5 is removed after the dry etching. However, the width of the removal need not be the same as that of the second cap layer 6, and may be etched together with the first cap layer 4 after the metal thin film 10 is deposited as described below. In this case, the width of removal of the etching stop layer 5 becomes the gate length of the gate electrode II. This is because the purpose of the present invention can be achieved as long as the gate electrode 11 does not come into contact with the second cap layer 6. As mentioned above, the etching stop layer 5 is as thin as about 50 mm, so it can be easily removed by dry etching or wet etching. Etching stop layer 5 is suitable for wet etching.
This is because the isotropy of etching can be ignored due to the thickness. Therefore, for example, RIE using CC12Ft as an enchantment at a pressure of 2 Pa may be used, or a highly corrosive hydrofluoric acid or alkaline etching agent may be used.

Step 102 in FIG. 1 shows the deposition of a metal thin film 10 on top of the pattern mask. The metal thin film 0 has selectivity with the first cap layer 4, and the type is not limited as long as it is not removed by etching.

Moreover, it is not limited to metal, and may be any suitable insulator.

For example, when the first cap layer 4 is n-GaAs,
It is formed by vapor depositing SiO1, SiO, or the like. The thickness of the vapor deposition is, for example, about 500 to 1000, taking into consideration the distance between the gate electrode 11 and the second cap layer 6. This is because the gate electrode 11 and the second cap layer 6 are separated by the thickness of the top layer. Note that the vapor deposition must be performed anisotropically from the diagonal direction of the gate opening. Anisotropic deposition means that metal atoms are deposited directly onto the patterning mask 7 from the deposition source. This is because in vapor deposition such as sputtering, metal atoms wrap around other than the vapor deposition location, making it impossible to control minute thickness. Anisotropic vapor deposition is performed using, for example, a high vacuum resistance heating vapor deposition apparatus. Further, the reason why the vapor deposition is performed from an oblique direction as shown by the arrow shown in step 102 is to allow metal atoms to enter the planned gate opening area and form a width of the gate electrode narrower than that of the second cap layer 6. .

In particular, it has the role of almost uniformly depositing the vapor on the inner wall of the patterning mask 7.

Step 103 shows selective and anisotropic tri-etching performed on the first cap layer 4 from above the metal thin film 10, similar to that during the transition from the step lot to step 102. Since the first cap layer 4 is etched anisotropically, whether it is thicker or thinner than the second cap layer, the pressure is constant and may be the same as that during the transition from step 101 to step +02. Specifically, it is less than 10 Pa.

Step 104 shows the deposition of the gate electrode IJ in the gate opening of the etched first cap layer 4. The gate metal that is the material of the gate electrode 11 is, for example, A
I, the thickness is about 4000 people, and the convergence is 0.3 μm.
to a certain degree. After forming the gate electrode 11, the gate electrode 1
The A1 layers other than 1 are lifted on and removed together with the patterning mask 7.

The E-HEMT according to the embodiment of the present invention has a recessed gate structure in which the distance between the gate pole 11 and the second cap layer 6 is kept constant at all times, compared to the conventional E-HEMT shown in FIG. 3 which is formed by wet etching. It has become.

This ensures a large channel area between the ohmic electrodes. Therefore, the parasitic capacitance can be further reduced than that of the conventional E-)IEMT, and the response speed can be improved by as much as 50%, especially under high power.

Therefore, the improvement in performance is also dramatic. Note that the enhancement type heterojunction field effect transistor of the present invention is not limited to the manufacturing method according to the embodiments of the present invention.

〔Effect of the invention〕

■With the semiconductor device of the present invention, the distance between the gate pole and the second cap layer is always constant, and for example, even in the E mode of a heterojunction field effect transistor, the source resistance and parasitic capacitance are reduced in the recessed gate structure. A semiconductor device capable of high-speed operation can be obtained.

(2) Furthermore, by selectively and anisotropically etching the second cap layer according to the semiconductor device of the present invention, the removal rate by etching can be made reproducible. Furthermore, it is possible to always keep the distance between the gate electrode and the second cap layer constant.

[Brief explanation of the drawing]

FIG. 1 shows a recessed gate structure according to an embodiment of the present invention.
A diagram showing the steps of the HEMT manufacturing method, Figure 2 is CC1t
GaAs and AlGa by F2+He ion etching
Figure 3 is a diagram showing the process of manufacturing a conventional E-HEMT with a recessed gate structure. Figure 4 is a cross-sectional view of a D-HEMT with a recessed gate structure. Figure 5 is a diagram showing a comparison of the etching rates of As. It is a figure explaining the problem of E-HEMT of a gate structure. In the figure, l is a semiconductor substrate, 2 is a channel layer, 3 is an electron supply layer, 4 is a first cap layer, 4a is a cap layer, 5 is an etching stop layer, 6 is a second cap layer, and 7 is a pattern 8.9 is an ohmic electrode, 10 is a metal thin film, and 11 is a gate electrode. Figure (?/) 2) 1st [d(f/) 1) Niso Rei ν 2° Masu 翳 1 (S)

Claims (1)

[Scope of Claims] On a semiconductor substrate (1), active layers (2, 3), a first cap layer (4) having an etching rate different from that of the surface layer of the active layer, and etching with the first cap layer are provided. An etching stop layer (5) having a different etching rate, a second cap layer (6) having a different etching rate from the etching stop layer and being thicker than the first cap layer, and an electrode layer forming area selectively. A mask layer (7) having a first opening
), using the mask layer as a mask, removing the second cap layer exposed in the first opening by anisotropic etching, and stopping at the surface of the etching stop layer. , forming a metal mask layer (10) having a second opening narrower than the first opening by depositing metal from an oblique direction onto the surface of the mask layer; and the etching stop layer. is removed and the first cap layer exposed in the second opening is removed by anisotropic etching, stopping at the surface of the active layer; and after removing the mask layer and the metal mask layer. A method for manufacturing a semiconductor device, comprising: forming an electrode layer in contact with the exposed active layer and the first cap layer, but not in contact with the second cap layer.