WO2006033167A1

WO2006033167A1 - Semiconductor device

Info

Publication number: WO2006033167A1
Application number: PCT/JP2004/014435
Authority: WO
Inventors: Yoshitomo Sagae; Takao Noda; Yorito Kakiuchi; Tomohiro Nitta
Original assignee: Kabushiki Kaisha Toshiba
Priority date: 2004-09-24
Filing date: 2004-09-24
Publication date: 2006-03-30

Abstract

A semiconductor device comprises a channel layer (103), an ohmic contact layer (108) above the channel layer,the ohmic contact layer including two holes on its surface and opening between the holes, two source/drain electrodes (109) including metal, one of the electrodes contacting bottom surface of one of the holes and the other of the electrodes contacting bottom surface of the other of the holes, a gate electrode (111) in the opening, a multilayered compound semiconductor layer (106, 107) between the channel and ohmic contact layers and including first and second compound semiconductor layers, diffusion coefficient of the metal in one of the compound semiconductor layers being smaller than that of the metal in the ohmic contact layer, and an alloy layer (110) in a region reaching a surface of the channel layer from the surface of the ohmic contact layer under the electrodes and including the metal.

Description

D E S C R I P T I O N

SEMICONDUCTOR DEVICE

Technical Field

The present invention relates to a semiconductor device using a compound semiconductor material.

Background Art

A high electron mobility transistor (HEMT) has heretofore been known as one type of field effect transistor (FET) . The HEMT includes a semi-insulating substrate; a channel layer which is provided on the semi-insulating substrate and which includes a high- purity semiconductor layer; and an electron supply layer which is provided on the channel layer and whose electron affinity is smaller than that of the channel layer and which is doped with n-type impurities.

In general, InGaAs large in electron mobility has been used as a material of the channel layer. On the other hand, various compound semiconductors such as

AlGaAs, InAlAs, InGaAlAs, InGaP, and InGaAlP are used as the material of the electron supply layer.

In recent years, as the electron supply layer, especially multilayered compound semiconductor layers including an Al]___z__wIn_wGa_zP layer (0 < z, w < 1) and an Al_]___x_yInyGa_xP layer (0 < x, y < 1) have attracted attention. This is because it is possible to alternately and selectively etch the Al;i___z__wIn_wGa_zP layer and Al_]___x_yInyGa_xP layer by wet etching. As a result, high controllability is obtained with respect to recess etching. FIG. 24 shows a sectional view of a conventional HEMT. FIGS. 25 to 29 are sectional views showing manufacturing processes of the HEMT.

First, as shown in FIG. 25, on a semi-insulating GaAs substrate 901, a GaAs/AlGaAs superlattice buffer layer 902, non-doped Ing. lsGag.85-^s channel layer 903, non-doped AIQ _,2^^a0.8&-^s spacer layer 904, Si-doped n-type AIg.2^^a0.8-^-^s electron supply layer 905, non-doped Alo.2^^aO.8^^s Schottky contact layer 906, ^ⁿ0„48^^a0.52-P etching stopper layer 9.07, and Si-doped n-type GaAs ohmic contact layer 908 are successively grown by an MOCVD process. Thereafter, a silicon oxide film 920 is deposited on the Si-doped n-type GaAs ohmic contact layer 908.

Next, as shown in FIG. 26, a resist pattern 921 is formed on the silicon oxide film 920, and thereafter the resist pattern 921 is used as a mask to etch the silicon oxide film 920 by a wet process. As a result, the surface of the ohmic contact layer 908 on a source/drain region is exposed. Next, as shown in FIG. 27, on the resist pattern

921 and ohmic contact layer 908, a conductive layer 909 of a laminate structure including an AuGe layer, Ni layer, and Au layer is formed by an evaporation process. The AuGe layer is a lower-layer side of the conductive layer 909, and the Au layer is an upper- layer side of the conductive. Next, as shown in FIG. 28, the resist pattern 921 and the conductive layer 909 provided above it are removed (lift-off process) . The remaining two conductive layers 909 form source/drain electrodes, respectively. Thereafter, by a heating process (alloying process) at about 350 to 450°C, elements such as Au and Ge in the source/drain electrodes 909 are diffused in the ohmic contact layer 908, etching stopper layer 907, and Schottky contact layer 906. As a result, as shown in FIG. 28, an ohmic alloy layer 910 is formed in the ohmic contact layer 908, etching stopper layer 907, and Schottky contact layer 906.

Next, as shown in FIG. 29, a resist pattern 922 is formed on the ohmic contact layer 908 and source/drain electrodes 909. Thereafter, the resist pattern 922 is used as the mask to etch the ohmic contact layer 908 and etching stopper layer 907 by the wet process. As a result, the surface of the Schottky contact layer 906 on a gate region is exposed. Thereafter, in the same manner as in a process for forming the source/drain electrodes 909, the evaporation and lift-off processes are carried out to form a gate electrode 911 on the Schottky contact layer 906. Any metal which makes Schottky junction with the Schottky contact layer can be used as a material of the gate electrode formed by the evaporation process, for instance, a laminated layer structure including Ti layer/Pt layer/Au layer or a laminated layer structure including Ti layer/Al layer can be used. In this manner, the conventional HEMT shown in FIG. 24 is obtained. In the conventional HEMT of FIG. 24, the ohmic alloy layer 910 does not reach the channel layer 903. For enhancement of device characteristics, the ohmic alloy layer 910 preferably reaches the channel layer 903. However, it is difficult to form the ohmic alloy layer 910 extended into the channel layer 903. For example, even when the heating process (alloying process) for forming the ohmic alloy layer 910 is carried out at 400°C for five minutes, the ohmic alloy layer 910 extended into the channel layer 903 is not formed.

This is because, in general, diffusion coefficient of metals in Ali_χInχGaP (0 < X < 1) which is the material of the etching stopper layer 907 is remarkably small as compared with that of the metals in an

Al]__γInγGaAs layer (0 < Y < 1) which is the material of the A Schottky contact layer 906. Moreover, even if the ohmic alloy layer 910 extended into the channel layer 903 is formed, as shown in FIG. 30, only a part of the ohmic alloy layer 910 enters the channel layer 903. A shape and size of the part of the ohmic alloy layer 910 extended into the channel layer 903 differ with devices. Fluctuations of the shape and size of this ohmic alloy layer 910 cause those of source/drain resistances, and further cause those of the device characteristics such as a high-frequency characteristic and low noise capability.

This problem can be solved by increase of temperature of the heating process (alloying process) for forming the ohmic alloy layer 910. However, when the temperature of the heating process (alloying process) is high, As comes off the surfaces of the source/drain electrodes 909, and this causes problems such as an increase of contact resistance of the source/drain electrodes 909. An object of the present invention is to provide a semiconductor device using a compound semiconductor material, including a structure in which an ohmic alloy layer extended into a channel layer can easily be formed. Disclosure of Invention

According to an aspect of the present invention, there is provided a semiconductor device comprising: a semi-insulating substrate; a channel layer provided above the semi-insulating substrate and including an In_uGai__uAs layer (0 < u < 1) ; an ohmic contact layer provided above the channel layer and including an InγGa_]__γAs layer (0 < V < 1), the ohmic contact layer including two holes on its surface, the ohmic contact layer between the two holes including an opening; two source/drain electrodes including metal, one of the source/drain electrodes contacting a bottom surface of one of the two holes and the other of the source/drain electrodes contacting a bottom surface of the other of the two holes; a gate electrode provided in the opening; a multilayered compound semiconductor layer provided between the channel layer and the ohmic contact layer and including a first and second compound semiconductor layers, a diffusion coefficient of the metal in one of the first and second compound semiconductor layers being smaller than a diffusion coefficient of the metal in at least a part of the ohmic contact layer; and an alloy layer provided in a region reaching a surface of the channel layer from the surface of the ohmic contact layer under the source/drain electrodes and including the metal. Brief Description of Drawings FIG. 1 is a sectional view showing HEMT according to the first embodiment of the present invention;

FIG. 2 is a sectional view showing a manufacturing process of the HEMT according to the first embodiment of the present invention;

FIG. 3 is a sectional view, following FIG. 2, showing the manufacturing process of the HEMT according to the first embodiment;

FIG. 4 is a sectional view, following FIG. 3, showing the manufacturing process of the HEMT according to the first embodiment;

FIG. 5 is a sectional view, following FIG. 4, showing the manufacturing process of the HEMT according to the first embodiment;

FIG. 6 is a sectional view, following FIG. 5, showing the manufacturing process of the HEMT according to the first embodiment; FIG. 7 is a sectional view showing the HEMT according to the second embodiment of the present invention;

FIG. 8 is a sectional view showing the manufacturing process of the HEMT according to the second embodiment of the present invention;

FIG. 9 is a sectional view, following FIG. 8, showing the manufacturing process of the HEMT according to the second embodiment;

FIG. 10 is a sectional view showing the HEMT according to the third embodiment of the present invention;

FIG. 11 is a sectional view showing the manufacturing process of the HEMT according to the third embodiment of the present invention;

FIG. 12 is a sectional view, following FIG. 11, showing the manufacturing process of the HEMT according to the third embodiment;

FIG. 13 is a sectional view, following FIG. 12, showing the manufacturing process of the HEMT according to the third embodiment;

FIG. 14 is a sectional view, following FIG. 13, showing the manufacturing process of the HEMT according to the third embodiment;

FIG. 15 is a sectional view, following FIG. 14, showing the manufacturing process of the HEMT according to the third embodiment; FIG. 16 is a sectional view showing the HEMT according to the fourth embodiment of the present invention;

FIG. 17 is a sectional view showing the manufacturing process of the HEMT according to the fourth embodiment of the present invention;

FIG. 18 is a sectional view, following FIG. 17, showing the manufacturing process of the HEMT according to the fourth embodiment;

FIG. 19 is a sectional view, following FIG. 18, showing the manufacturing process of the HEMT according to the fourth embodiment;

FIG. 20 is a sectional view, following FIG. 19, showing the manufacturing process of the HEMT according to the fourth embodiment;

FIG. 21 is a sectional view, following FIG. 20, showing the manufacturing process of the HEMT according to the fourth embodiment;

FIG. 22 is a sectional view showing the HEMT according to the fifth embodiment of the present invention;

FIG. 23 is a diagram showing a relation between a contact resistance after forming an ohmic alloy layer and a thickness of an ohmic contact layer under source/drain electrodes;

FIG. 24 is a sectional view showing a conventional HEMT; FIG. 25 is a sectional view showing the manufacturing process of the conventional HEMT;

FIG. 26 is a sectional view, following FIG. 24, showing the manufacturing process of the conventional HEMT; FIG. 27 is a sectional view, following FIG. 25, showing the manufacturing process of the conventional HEMT;

FIG. 28 is a sectional view, following FIG. 26, showing the manufacturing process of the conventional HEMT;

FIG. 29 is a sectional view, following FIG. 27, showing the manufacturing process of the conventional HEMT ; and

FIG. 30 is a sectional view showing a problem of the conventional HEMT.

Best Mode for Carrying Out the Invention (First Embodiment)

FIG. 1 is a sectional view showing HEMT according to the first embodiment of the present invention. The HEMT of the present embodiment includes a semi-insulating GaAs substrate 101; a non-doped Ing_β i5Gag.85-^^s channel layer 103 provided above the semi-insulating GaAs substrate 101; a Si-doped n-type GaAs ohmic contact layer 108 provided above the channel layer 103; a multilayered compound semiconductor layer which is provided between the channel layer 103 and the ohmic contact layer 108 and which includes a Si-doped n-type Alo.2^^aO.8^-^s electron supply layer 105, a non-doped AIg .2^^a0.8^-^s Schottky contact layer 106, and an Ing.4gGag _#52? etching stopper layer 107; two source/drain electrodes 109; a gate electrode 111; and an ohmic alloy layer 110.

Two holes 122 are provided in the surface of the ohmic contact layer 108 on a source/drain region. Two source/drain electrodes 109 contact bottom surfaces of two holes 122, respectively. The surfaces of two source/drain electrodes 109 are substantially flat.

The ohmic contact layer 108 and etching stopper layer 107 on a gate region includes an opening 124. The gate electrode 111 is provided on the Schottky contact layer 106 in the opening 124.

The ohmic alloy layers 110 are formed in a region reaching the surface of the channel layer 103 from that of the ohmic contact layer 108 under the source/drain electrodes 109.

Details of the HEMT of the present embodiment will be described hereinafter with reference to sectional views of FIGS. 2 to 6 showing manufacturing processes. First, as shown in FIG. 2, on the semi-insulating

GaAs substrate 101, a GaAs/AlGaAs superlattice buffer layer 102, non-doped Ing . lsGag .85-^^s channel layer 103, non-doped AIQ.2^Ga0.8^As spacer layer 104, Si-doped n-type AIg.2^Ga0.8^As electron supply layer 105, non-doped AIQ .2^Ga0.8^-^s Schottky contact layer 106,

^In0.48^Ga0.52^p etching stopper layer 107, and Si-doped n-type GaAs ohmic contact layer 108 are successively grown by an MOCVD process. Thereafter, a silicon oxide film 120 is deposited on the ohmic contact layer 108. Moreover, a resist pattern 121 is formed on the silicon oxide film 120.

Here, a thickness of the ohmic contact layer 108 is 50 nm or more and 200 nm or less. The reason why the thickness of the ohmic contact layer 108 is 50 nm or more is that a sheet resistance be lowered. A HEMT has been requested to be low in a source/drain resistance. For that, as described above, it is necessary to lower the sheet resistance. On the other hand, the reason why the thickness of the ohmic contact layer 108 is set to 200 nm or less is that etching controllability of the ohmic contact layer 108 is remarkably deteriorated with the thickness exceeding 200 nm.

Additionally, as described later, the thickness of a portion left in etching the ohmic contact layer 108 (the thickness of the ohmic contact layer 108 under the source/drain electrodes 109) is 10 nm or more and 40 nm or less.

Next, as shown in FIG. 3, the resist pattern 121 is used as a mask to etch the silicon oxide film 120 by a wet process. Subsequently, the resist pattern 121 is used as the mask to etch the ohmic contact layer 108 by the wet process using a phosphoric-acid-based etching solution.

At this time, the holes 122 are formed in the surface of the ohmic contact layer 108 so that the surface of the etching stopper layer 107 under the ohmic contact layer 108 is not exposed. The ohmic contact layer 108 under the holes 122 (an etched but remaining portion in the ohmic contact layer 108) has a thickness of 10 nm or more and 40 nm or less. The reason why the thickness is set to 10 nm or more and 40 nm or less will be described later.

Next, on the resist pattern 121 and ohmic contact layer 108, a conductive layer of a laminate structure including an AuGe layer, Ni layer, and Au layer is formed by an evaporation process. Thereafter, the resist pattern 121 and the conductive layer on the pattern are removed (lift-off process) .

As a result, as shown in FIG. 4, the source/drain electrodes 109 including the conductive layer are formed on the holes 122 of the ohmic contact layer 108. The AuGe layer is a lower-layer side of the source/drain electrodes 109, and the Au layer is an upper-layer side.

Thereafter, by a heating process (alloying process) at 400°C for five minutes, elements such as Au and Ge in the source/drain electrodes 109 are diffused in the ohmic contact layer 108, etching stopper layer 107, Schottky contact layer 106, electron supply layer 105, spacer layer 104, and channel layer 103.

As a result, as shown in FIG. 5, in the ohmic contact layer 108, etching stopper layer 107, Schottky contact layer 106, electron supply layer 105, spacer layer 104, and channel layer 103, the ohmic alloy layers 110 are formed.

The source/drain electrodes 109 contain metals such as Au. A diffusion coefficient of metals in Al_]___z__wIn_wGa_zP (0 < z, w < 1) which is the material of the etching stopper layer 107 is smaller than that of the metals in GaAs which is the material of the ohmic contact layer 108.

A time of the alloying process is lengthened, or a temperature of the alloying process is raised. Accordingly, even if the thickness of the ohmic contact layer 108 under the source/drain electrodes 109 is not reduced, it is possible to form the ohmic alloy layer 110 reaching the inside of the channel layer 103.

However, when the temperature of the alloying process is raised at 450°C or more, As comes off the ohmic contact layer 108. When As is detached from the inside of the ohmic contact layer 108, crystallinity of the ohmic contact layer 108 of an unchanged portion in the ohmic alloy layer 110 is deteriorated. When the crystallinity of the ohmic contact layer 108 is deteriorated, the sheet resistance increases, and, as a result, a contact resistance increases. On the other hand, when the time of the alloying process is lengthened, a manufacturing process lengthens. Therefore, productivity is deteriorated. On the other hand, for the manufacturing process of the present embodiment, it is not necessary to lengthen the time for the alloying process or to raise the temperature of the alloying process. Therefore, according to the present embodiment, a source/drain electrode structure which is low in contact resistance is obtained in a short time.

Here, a relation between a contact resistance pc after forming the ohmic alloy layers 110 and a thickness d of the ohmic contact layer under the source/drain electrodes 109 (the thickness of the ohmic contact layer 108 under the holes 122) is shown in FIG. 23. The contact resistance is requested to be 1 X 10^~6 Ωcm² or less. Therefore, to satisfy the requirement, it is seen from FIG. 23 that the thickness d needs to be 10 nm or more and 40 nm or less. This is why the thickness of the ohmic contact layer 108 under the source/drain electrodes 109 is set to 10 nm or more and 40 nm or less.

Next, as shown in FIG. 6, a resist pattern 123 is formed on the ohmic contact layer 108 and source/drain electrodes 109. The resist pattern 123 is formed by a lithography process.

Next, the resist pattern 123 is used as the mask to etch the ohmic contact layer 108 and etching stopper layer 107. Accordingly, the opening 124 is formed in the ohmic contact layer 108 and etching stopper layer 107. ^•

The ohmic contact layer (GaAs-based compound) 108 is etched by the wet process using the phosphoric-acid- based etching solution.

Here, an etching rate of an InGaP-based compound is 1/40 of that of the GaAs-based compound. That is, the etching rate of the InGaP-based compound is sufficiently small as compared with that of the GaAs-based compound.

Therefore, the ohmic contact layer (GaAs-based compound) 108 is selectively etched, and the surface of the etching stopper layer (InGaP-based compound) 107 is exposed. That is, when the ohmic contact layer 108 is etched, the etching stopper layer 107 functions as an etching stopper.

On the other hand, the etching stopper layer 107 is etched by the wet process using hydrochloric acid. Here, an AlGaAs-based compound is hardly etched by hydrochloric acid. Therefore, the etching stopper layer (InGaP-based compound) 107 is selectively etched, and the surface of the Schottky contact layer

⁽AIg.2^Ga0.8^As) ¹⁰⁶ ^^Ξ exposed. Thereafter, in the same manner as in the process for forming the source/drain electrodes 109, the evaporation process and lift-off process are performed, and the gate electrode 111 is formed on the Schottky contact layer 106. Any metal which makes Schottky junction with the Schottky contact layer can be used as a material of the gate electrode formed by the evaporation process, for instance, a laminated layer structure including Ti layer/Pt layer/Au layer or a laminated layer structure including Ti layer/Al layer can be used. In the present embodiment, the formation method using the evaporation lift-off process is explained, but another formation method using metal deposition process such as sputter process or metal CVD process can be used. In this manner, the HEMT shown in FIG. 1 is obtained.

As a result of observation of a section of the HEMT of the present embodiment by electron microscopes such as SEM and TEM, it has been confirmed that the ohmic alloy layer 110 reaches the inside of the channel layer 103.

Moreover, electric characteristics of the HEMT of the present embodiment were compared with those of a conventional HEMT. As a result, a source resistance Rs and drain resistance Rd of the HEMT of the present embodiment were lower by 20% as compared with those of the conventional HEMT. A mutual conductance gm and current gain cutoff frequency fT of the HEMT of the present embodiment were higher by 12% as compared with those of the conventional HEMT. A minimum noise index NFmin of the HEMT of the present embodiment was lower by about 0.1 dB as compared with that of the conventional HEMT. The reason why the electric characteristics (gm, fT, and NFmin) of the HEMT of the present embodiment are superior to those of the conventional HEMT is that Rs and Rd of the HEMT of the present embodiment are lower than those of the conventional HEMT.

Furthermore, sizes of in-plane fluctuations of Rs and Rd of the HEMT of the present embodiment were largely improved as about 1/3, respectively, as compared with those of the conventional HEMT.

The sizes of the fluctuations of gm, fT, and NFmin of the HEMT of the present embodiment were also largely improved, respectively, as compared with those of the conventional HEMT.

It goes without saying that the same effect can be obtained even in a case that the gate electrode is formed on the InGaP etching stopper layer 107 without etching the InGaP etching stopper layer 107 when the gate electrode is formed in order to functionate the InGaP etching stopper layer of the present embodiment as the Schottky contact layer of the second electron supply layer. It goes without saying that the gate electrode has a cross section view of straight structure in the present embodiment, even a T shape structure allows same effect as the present embodiment. (Second Embodiment) FIG. 7 is a sectional view showing the HEMT according to the second embodiment of the present invention.

In the first embodiment, opening diameters of the holes 122 of the ohmic contact layer 108 were larger than widths of the source/drain electrodes 109, and the surfaces of the source/drain electrodes 109 of the first embodiment were substantially flat. On the other hand, in the present embodiment, the opening diameters of holes 222 of an ohmic contact layer 208 are larger than widths of source/drain electrodes 209, and the surfaces of the source/drain electrodes 209 include holes provided opposite to the holes 222.

The details of the HEMT of the present embodiment will hereinafter be described with reference to sectional views of FIGS. 8 and 9 showing the manufacturing process. First, as shown in FIG. 8, on a semi-insulating

GaAs substrate 201, a GaAs/AlGaAs superlattice buffer layer 202, non-doped IΠQ _#isGag_o 85^s channel layer 203, non-doped AIQ _^2^^a0.8-^^s spacer layer 204, Si-doped n-type AlQ.2^Ga0.8^As electron supply layer 205, non-doped Al_Q^Gag.sAs Schottky contact layer 206,

^In0.48^Ga0.52^P etching stopper layer 207, and Si-doped n-type GaAs ohmic contact layer 208 are successively grown by the MOCVD process.

The thickness of the ohmic contact layer 208 is 50 nm or more and 200 nm or less for the reason similar to that of the first embodiment.

Next, a silicon oxide film 220 is deposited on the Si-doped n-type GaAs ohmic contact layer 208, and thereafter a resist pattern 221 is formed on the silicon oxide film 220.

Here, in the first embodiment, the opening diameters of the resist pattern 112 were larger than the widths of the source/drain electrodes 109, but in the present embodiment, the opening diameters of the resist pattern 221 are smaller than the widths of the source/drain electrodes 209. Next, as shown in FIG. 9, the resist pattern 221 is used as the mask to etch the silicon oxide film 220 by the wet process, and subsequently the resist pattern 221 is used in the mask to etch the ohmic contact layer 208 by the wet process using the phosphoric-acid-based etching solution.

At this time, the ohmic contact layer 208 is etched so as to prevent the surface of the etching stopper layer 207 under the ohmic contact layer 208 from being exposed. That is, the holes 222 are formed in the surface of the ohmic contact layer 208. The thickness of the ohmic contact layer 208 under the holes 222 (the etched but remaining portion of the ohmic contact layer 208) is 10 nm or more and 40 nm or less for the reason similar to that of the first embodiment.

Next, the silicon oxide film 220 and resist pattern 221 are removed, the conductive layer of the laminate structure including an AuGe layer, Ni layer, and Au layer is formed on the whole surface by the evaporation process, and the conductive layer is processed by the photolithography and etching process to obtain the source/drain electrodes 209. The AuGe layer is the lower-layer side of the source/drain electrodes 209, and the Au layer is the upper-layer side.

Thereafter, through steps similar to those of and after FIG. 5 of the first embodiment, an ohmic alloy layer 210, opening 124, and gate electrode 211 are formed to obtain the HEMT shown in FIG. 7.

In the present embodiment, as described above, the opening diameters of the holes 222 of the ohmic contact layer 208 are smaller than the widths of the source/drain electrodes 209. This prevents a bore from being accidentally made in the ohmic contact layer 208 in peripheral edges of the source/drain electrodes 209 by a rinsing treatment performed after the step of forming the source/drain electrodes 209. This prevents an increase of the contact resistance by the rinsing treatment.

Moreover, in the same manner as in the first embodiment, the source/drain electrode structure which is low in the contact resistance is obtained in a short time.

As a result of the observation of the section of the HEMT of the present embodiment by the electron microscopes such as SEM and TEM, it has been confirmed that the ohmic alloy layer 210 reaches the inside of the channel layer 203.

Moreover, the electric characteristics of the HEMT of the present embodiment were compared with those of the conventional HEMT. As a result, Rs and Rd of the HEMT of the present embodiment were lower by 25%, respectively, as compared with those of the conventional HEMT.

The gm and fT of the HEMT of the present embodiment were higher by 15%, respectively, as compared with those of the conventional HEMT. The NFmin of the HEMT of the present embodiment was lower by about 0.1 dB as compared with that of the conventional HEMT. The reason why the electric characteristics (gm, fT, and NFmin) of the HEMT of the present embodiment are superior to those of the conventional HEMT is that Rs and Rd of the HEMT of the present embodiment are lower than those of the conventional HEMT.

Furthermore, the sizes of the in-plane fluctuations of Rs and Rd of the HEMT of the present embodiment were largely improved as about 1/3, respectively, as compared with those of the conventional HEMT.

It goes without saying that the same effect can be obtained even in a case that the gate electrode is formed on the InGaP etching stopper layer 207 without etching the InGaP etching stopper layer 207 when the gate electrode is formed in order to functionate the InGaP etching stopper layer of the present embodiment as the Schottky contact layer of the second electron supply layer.

It goes without saying that the gate electrode has a cross section view of straight structure in the present embodiment, even a T shape structure allows same effect as the present embodiment. (Third Embodiment)

FIG. 10 is a sectional view showing the HEMT according to the third embodiment of the present invention. The HEMT of the first and second embodiments was of a single hetero junction type, but the HEMT of the present embodiment is of a double hetero junctions type.

Moreover, in the first embodiment, the opening diameters of the holes 122 of the ohrαic contact layer 108 were larger than the widths of the source/drain electrodes 109, and the surfaces of the source/drain electrodes 109 of the first embodiment were substantially flat. On the other hand, in the present embodiment, the opening diameters of holes 322 of an ohmic contact layer 311 are smaller than the widths of source/drain electrodes 312, and the surfaces of the source/drain electrodes 312 include holes provided opposite to the through holes 322.

The details of the HEMT of the present embodiment will hereinafter be described with reference to the sectional views of FIGS. 11 and 15 showing the manufacturing process.

First, as shown in FIG. 11, on a semi-insulating GaAs substrate 301, a GaAs/AlGaAs superlattice buffer layer 302, Si-doped n-type AlQ.2^Ga0.8^As electron supply layer 303, non-doped AlQ.2^Ga0.8^As spacer layer 304, non-doped

channel layer 305, AIQ .2^Ga0.8-^-^s spacer layer 306, Si-doped n-type AIQ.2^Ga0.8-^-^s electron supply layer 307, non-doped Alo.2^GaO.8^As Schottky contact layer 308, Ing.48^Ga0.52^P etching stopper layer 309, Si-doped n-type GaAs layer 310, and Si-doped n-type GaAs ohmic contact layer 311 are successively grown by the MOCVD process.

The thickness of the ohmic contact layer 311 is 50 ran or more and 200 ran or less for the reason similar to that of the first embodiment.

The thickness of the n-type GaAs layer 310 corresponds to that of the etched but left portion of the ohmic contact layer 108 of the first embodiment. Therefore, the thickness of the n-type GaAs layer 310 is 10 nm or more and 40 nm or less for the reason similar to that of the first embodiment.

Next, as shown in FIG. 12, a resist pattern 320 is formed on the ohmic contact layer 311, and thereafter the resist pattern 320 is used as the mask to etch the ohmic contact layer 311 by the wet process using the phosphoric-acid-based etching solution. At this time, the ohmic contact layer 311 is etched so that through holes 321 are formed in the ohmic contact layer 311. The surface of the n-type GaAs layer 310 in the bottom of the through holes 321 is exposed. Next, the resist pattern 320 is removed, and the conductive layer of the laminate structure including the AuGe layer, Ni layer, and Au layer is formed on the ohmic contact layer 311 and the n-type GaAs layer 310 in the bottom of the through holes 321 by the evaporation process.

Next, the conductive layer is processed by the photolithography and etching process to form the source/drain electrodes 312 including the conductive layer as shown in FIG. 13. The AuGe layer is the lower-layer side of the source/drain electrodes 312, and the Au layer is the upper-layer side.

Thereafter, by the heating process (alloying process) at 400°C for five minutes, the elements such as Au and Ge in the source/drain electrodes 312 are diffused in the ohmic contact layer 311, n-type GaAs layer 310, etching stopper layer 309, Schottky contact layer 308, electron supply layer 307, spacer layer 306, and channel layer 305.

As a result, as shown in FIG. 14, in the ohiαic contact layer 311, n-type GaAs layer 310, etching stopper layer 309, Schottky contact layer 308, electron supply layer 307, spacer layer 306, and channel layer 305, an ohmic alloy layer 313 is formed. Also in the present embodiment, in the same manner as in the first embodiment, the source/drain electrode structure which is low in the contact resistance is obtained in the short time.

Next, as shown in FIG. 15, by the lithography and etching processes, a first opening is formed in the ohmic contact layer 311. The etching process is the wet process using the phosphoric-acid-based etching solution.

Next, by the lithography and etching processes, a second opening is formed in the n-type GaAs layer 310 and etching stopper layer 309 in the first opening. The opening diameter of the second opening is smaller than that of the first opening.

Here, the etching process for forming the second opening is the wet process using the phosphoric-acid- based etching solution, when etching the n-type GaAs layer 310. At this time, the etching rate of the InGaP-based compound is 1/40 of that of the GaAs-based compound, the n-type GaAs layer 310 is selectively etched to expose the surface of the etching stopper layer (InGaP-based compound) 309. That is, when the n-type GaAs layer 310 is etched, the etching stopper layer 309 functions as the etching stopper.

On the other hand, the etching process is the wet process using hydrochloric acid, when etching the etching stopper layer 309. At this time, the etching stopper layer 309 is selectively etched to expose the surface of the Schottky contact layer (AIQ.2^Ga0.8^As) ³⁰⁸- This is because the AlGaAs-based compound is hardly etched by hydrochloric acid.

Thereafter, the evaporation and lift-off processes are performed to form a gate electrode 314 on the Schottky contact layer 308. Any metal which makes Schottky junction with the Schottky contact layer can be used as a material of the gate electrode formed by the evaporation process, for instance, a laminated layer structure including Ti layer/Pt layer/Au layer or a laminated layer structure including Ti layer/Al layer can be used. In the present embodiment, the formation method using the evaporation lift-off process is explained, but another formation method using metal deposition process such as sputter process or metal CVD process can be used. In this manner, the HEMT shown in FIG. 10 is obtained. As a result of the observation of the section of the HEMT of the present embodiment by the electron microscopes such as SEM and TEM, it has been confirmed that the ohmic alloy layer 313 reaches the inside of the channel layer 305.

Moreover, the electric characteristics of the HEMT of the present embodiment were compared with those of the conventional HEMT. As a result, Rs and Rd of the HEMT of the present embodiment were lower by 30%, respectively, as compared with those of the conventional HEMT.

The gm and fT of the HEMT of the present embodiment were higher by 18%, respectively, as compared with those of the conventional HEMT. The NFmin of the HEMT of the present embodiment was lower by about 0.1 dB as compared with that of the conventional HEMT. The reason why the electric characteristics (gm, fT, and NFmin) of the HEMT of the present embodiment are superior to those of the conventional HEMT is that Rs and Rd of the HEMT of the present embodiment are lower than those of the conventional HEMT. Furthermore, the sizes of the in-plane fluctuations of Rs and Rd of the HEMT of the present embodiment were largely improved as about 1/2, respectively, as compared with those of the conventional HEMT. The sizes of the fluctuations of gm, fT, and NFmin of the HEMT of the present embodiment were also largely improved, respectively, as compared with those of the conventional HEMT.

It goes without saying that the same effect can be obtained even in a case that the gate electrode is formed on the InGaP etching stopper layer 309 without etching the InGaP etching stopper layer 309 when the gate electrode is formed in order to functionate the InGaP etching stopper layer of the present embodiment as the Schottky contact layer of the second electron supply layer. It goes without saying that the gate electrode has a cross section view of straight structure in the present embodiment, even a T shape structure allows same effect as the present embodiment. (Fourth Embodiment) FIG. 16 is a sectional view showing the HEMT according to the fourth embodiment of the present invention.

The HEMT of the first and second embodiments was of the single hetero junction type, but the HEMT of the present embodiment is of the double hetero junctions type.

Moreover, in the first embodiment, the opening diameters of the holes 122 of the ohmic contact layer 108 were larger than the widths of the source/drain electrodes 109, and the surfaces of the source/drain electrodes 109 of the first embodiment were substantially flat. On the other hand, in the present embodiment, the opening diameters of through holes 421 of an ohmic contact layer 412 are smaller than the widths of source/drain electrodes 413, and the surfaces of the source/drain electrodes 413 include holes provided opposite to the through holes 421.

Furthermore, the etching stopper layer was not provided on the n-type GaAs layer 310 in the HEMT of the third embodiment, but an etching stopper layer 411 is also provided on an ohmic contact layer 410. The details of the HEMT of the present embodiment will hereinafter be described with reference to the sectional views of FIGS. 17 to 21 showing the manufacturing process.

First, as shown in FIG. 17, on a semi-insulating GaAs substrate 401, a GaAs/AlGaAs superlattice buffer layer 402, Si-doped n-type AIQ.2^^a0.8-^^s electron supply layer 403, non-doped AIQ.2^aQ. sAs spacer layer 404, non-doped Ing_#

channel layer 405, non-doped AIg.2^aQ.8^^s spacer layer 406, Si-doped n-type AIQ _#2^^a0.8-^^s electron supply layer 407, non-doped

AIQ .2^^a0.8^-^s Schottky contact layer 408, Ing.48Gag.52? etching stopper layer 409, Si-doped n-type GaAs layer 410, Ing .48^Ga0.52^p etching stopper layer 411, and Si-doped n-type GaAs ohmic contact layer 412 are successively grown by the MOCVD process.

The thickness of the ohmic contact layer 412 is 50 nm or more and 200 nm or less for the reason similar to that of the first embodiment.

The thickness of the n-type GaAs layer 410 corresponds to that of the etched but left portion of the ohmic contact layer 108 of the first embodiment. Therefore, the thickness of the n-type GaAs layer 410 is 10 nm or more and 40 nm or less for the reason similar to that of the first embodiment.

Next, as shown in FIG. 18, a resist pattern 420 is formed on the ohmic contact layer 412, thereafter the resist pattern 420 is used as the mask to etch the ohmic contact layer 412 and etching stopper layer 411 by the wet process, and the through holes 421 are formed.

Here, the etching process is the wet process using the phosphoric-acid-based etching solution, when etching the ohmic contact layer 412. At this time, the etching rate of the InGaP-based compound is 1/40 of that of the GaAs-based compound, the ohmic contact layer 412 is selectively etched to expose the surface of the etching stopper layer (InGaP-based compound) 411. That is, when the ohmic contact layer 412 is etched, the etching stopper layer 411 functions as the etching stopper.

On the other hand, the etching process is the wet process using concentrated hydrochloric acid, when etching the etching stopper layer 411. At this time, the etching stopper layer 411 is selectively etched to expose the surface of the n-type GaAs layer 410. This is because the GaAs-based compound is hardly etched by hydrochloric acid.

Next, the resist pattern 420 is removed, and the conductive layer of the laminate structure including the AuGe layer, Ni layer, and Au layer is formed on the ohmic contact layer 412 and the n-type GaAs layer 410 in the bottoms of the through holes 421 by the evaporation process. Next, the conductive layer is processed by the photolithography and etching process to form the source/drain electrodes 413 including the conductive layer as shown in FIG. 19. The AuGe layer is the lower-layer side of the source/drain electrodes 312, and the Au layer is the upper-layer side.

Thereafter, by the heating process (alloying process) at 400°C for five minutes, the elements such as Au and Ge in the source/drain electrodes 413 are diffused in the ohmic contact layer 412, etching stopper layer 411, n-type GaAs layer 410, etching stopper layer 409, Schottky contact layer 408, electron supply layer 407, spacer layer 406, and channel layer 405.

As a result, as shown in FIG. 20, in the ohmic contact layer 412, etching stopper layer 411, n-type GaAs layer 410, etching stopper layer 409, Schottky contact layer 408, electron supply layer 407, spacer layer 406, and channel layer 405, ohmic alloy layers 414 are formed. Also in the present embodiment, in the same manner as in the first embodiment, the source/drain electrode structure which is low in the contact resistance is obtained in the short time.

Next, as shown in FIG. 21, by the lithography and etching processes, an opening is formed in the n-type GaAs layer 410 and etching stopper layer 409 in a region between two source/drain electrodes 413. Moreover, the etching process is the wet process using the phosphoric-acid-based etching solution, when etching the n-type GaAs layer 410. At this time, since the etching rate of the InGaP-based compound is 1/40 of that of the GaAs-based compound, the n-type GaAs layer 410 is selectively etched to expose the surface of the etching stopper layer (InGaP-based compound) 409. That is, when the n-type GaAs layer 410 is etched, the etching stopper layer 409 functions as the etching stopper. On the other hand, the etching process is the wet process using hydrochloric acid, when etching the etching stopper layer 409. At this time, the etching stopper layer 409 is selectively etched to expose the surface of the Schottky contact layer 408. This is because the AlGaAs-based compound is hardly etched by hydrochloric acid.

Thereafter, the evaporation and lift-off processes are performed to form a gate electrode 415 on the Schottky contact layer 408. Any metal which makes Schottky junction with the Schottky contact layer can be used as a material of the gate electrode formed by the evaporation process, for instance, a laminated layer structure including Ti layer/Pt layer/Au layer or a laminated layer structure including Ti layer/Al layer can be used. In the present embodiment, the formation method using the evaporation lift-off process is explained, but another formation method using metal deposition process such as sputter process or metal CVD process can be used. In this manner, the HEMT shown in FIG. 16 is obtained.

As a result of the observation of the section of the HEMT of the present embodiment by the electron microscopes such as SEM and TEM, it has been confirmed that the ohmic alloy layer 413 reaches the inside of the channel layer 405.

Moreover, the electric characteristics of the HEMT of the present embodiment were compared with those of the conventional HEMT. As a result, Rs and Rd of the HEMT of the present embodiment were lower by 30%, respectively, as compared with those of the conventional HEMT. The gm and fT of the HEMT of the present embodiment were higher by 18%, respectively, as compared with those of 'the conventional HEMT. The NFmin of the HEMT of the present embodiment was lower by about 0.1 dB as compared with that of the conventional HEMT. The reason why the electric characteristics (gm, fT, and NFmin) of the HEMT of the present embodiment are superior to those of the conventional HEMT is that Rs and Rd of the HEMT of the present embodiment are lower than those of the conventional HEMT.

^• It goes without saying that the same effect can be obtained even in a case that the gate electrode is formed on the InGaP etching stopper layer 409 without etching the InGaP etching stopper layer 409 when the gate electrode is formed in order to functionate the InGaP etching stopper layer of the present embodiment as the Schottky contact layer of the second electron supply layer.

(Fifth Embodiment)

FIG. 22 is a sectional view showing the HEMT according to a fourth embodiment of the present invention. The manufacturing process of the HEMT of the present embodiment is as follows.

First, on a semi-insulating GaAs substrate 501, a GaAs/AlGaAs superlattice buffer layer 502, Si-doped n-type Alo.2^GaO.8^As electron supply layer 503, non-doped AIQ .2^^a0.8-^^s spacer layer 504, non-doped -^ⁿ0.15^Ga0.85^^s channel layer 505, non-doped AI_{Q ^}2^a_Q. δAs spacer layer 506, Si-doped n-type AIg.2^^a0.8^^s electron supply layer 507, non-doped

-^ⁿ0.48^Ga0.52-P Schottky contact layer 508, and Si-doped n-type GaAs ohmic contact layer 509 are successively grown by the MOCVD process.

The thickness of the ohmic contact layer 509 is 50 nm or more and 200 nm or less for the reason similar to that of the first embodiment.

Next, by a process similar to that of FIGS. 2 to 4 of the first embodiment, holes 520 are formed in the surface of the ohmic contact layer 509, and further source/drain electrodes 510 are formed in the holes 520. The lower layer of the source/drain electrodes 510 is the AuGe layer, and the upper layer is the Au layer.

The thickness of the ohmic contact layer 509 under the source/drain electrodes 510 (under the holes 521) is 10 nm or more and 40 nm or less for the reason similar to that of the first embodiment. Next, by the heating process (alloying process) at 400°C for five minutes, ohmic alloy layers 5.11 are formed in the ohmic contact layer 509, Schottky contact layer 508, electron supply layer 507, spacer layer 506, and channel layer 505. Also in the present embodiment, in the same manner as in the first embodiment, the source/drain electrode structure which is low in the contact resistance is obtained in the short time.

Next, by the lithography and etching processes, an opening 521 is formed in the ohmic contact layer 509 in a region between two source/drain electrodes 510.

Moreover, the etching process is the wet process using the phosphoric-acid-based etching solution. At this time, since the etching rate of the InGaP-based compound is 1/40 of that of the GaAs-based compound, the ohmic contact layer (GaAs-based compound) 509 is selectively etched to expose the surface of the Schottky contact layer (InGaP-based compound) 508.

Thereafter, the evaporation and lift-off processes are performed to form a gate electrode 512 on the

Schottky contact layer 508 in the opening 521. Any metal which makes Schottky junction with the Schottky contact layer can be used as a material of the gate electrode formed by the evaporation process, for instance, a laminated layer structure including Ti layer/Pt layer/Au layer or a laminated layer structure including Ti layer/Al layer can be used. In the present embodiment, the formation method using the evaporation lift-off process is explained, but another formation method using metal deposition process such as sputter process or metal CVD process can be used. In this manner, the HEMT shown in FIG. 16 is obtained.

As a result of the observation of the section of the HEMT of the present embodiment by the electron microscopes such as SEM and TEM, it has been confirmed that the ohmic alloy layer 511 reaches the inside of the channel layer 505.

The gm and fT of the HEMT of the present embodiment were higher by 18%, respectively, as compared with those of the conventional HEMT. The NFmin of the HEMT of the present embodiment was lower by about 0.1 dB as compared with that of the conventional HEMT. The reason why the electric characteristics (gm, fT, and NFmin) of the HEMT of the present embodiment are superior to those of the conventional HEMT is that Rs and Rd of the HEMT of the present embodiment are lower than those of the conventional HEMT. Furthermore, the sizes of the in-plane fluctuations of Rs and Rd of the HEMT of the present embodiment were largely improved as about 1/3, respectively, as compared with those of the conventional HEMT.

The sizes of the fluctuations of gm, fT, and NFmin of the HEMT of the present embodiment were also largely improved, respectively, as compared with those of the conventional HEMT. It is to be noted that in the above-described embodiments, the present invention applied to the HEMT has been described, but the present invention can also be applied to another field effect transistor such as a hetero junction FET. Moreover, the Ali___z__wIn_wGa_zP layer and Al_]___x_yIn_xGaAs layer for use in the device can appropriately be changed in a range of 0 < Z, w < 1 and 0 < x, Y < 1. Additionally, the present invention can variously be modified and carried out without departing from the scope. Industrial Applicability

According to the present invention, a semicon¬ ductor device using a compound semiconductor material can be obtained including a structure in which an ohmic alloy layer extended into a channel layer can easily be formed.

Claims

C L A I M S

1. A semiconductor device comprising: a semi-insulating substrate; a channel layer provided above the semi-insulating substrate and including an In_uGa_]___uAs layer (0 < u < 1) ; an ohmic contact layer provided above the channel layer and including an InyGai-yAs layer (0 < V < 1), the ohmic contact layer including two holes on its surface, the ohmic contact layer between the two holes including an opening; two source/drain electrodes including metal, one of the source/drain electrodes contacting a bottom surface of one of the two holes and the other of the source/drain electrodes contacting a bottom surface of the other of the two holes; a gate electrode provided in the opening; a multilayered compound semiconductor layer provided between the channel layer and the ohmic contact layer and including a first and second compound semiconductor layers, a diffusion coefficient of the metal in one of the first and second compound semiconductor layers being smaller than a diffusion coefficient of the metal in at least a part of the ohmic contact layer; and an alloy layer provided in a region reaching a surface of the channel layer from the surface of the ohmic contact layer under the source/drain electrodes and including the metal.

2. The semiconductor device according to claim 1, wherein the second compound semiconductor layer is closer to the ohmic contact layer than the first compound semiconductor layer, and a diffusion coefficient of the metal in the second compound semiconductor layer is smaller than a diffusion coefficient of the metal in a compound semiconductor layer contacting one of the first and second compound semiconductor layer in the ohmic contact layer.

3. The semiconductor device according to claim 1, wherein the first compound semiconductor layer is an electron supply layer provided between the channel layer and the ohmic contact layer.

4. The semiconductor device according to claim 3, wherein the first compound semiconductor layer includes an Al_]___x_yInyGa_xAs layer (0 < x, y < 1) .

5. The semiconductor device according to claim 4, wherein the ohmic contact layer under the holes has a thickness of 10 to 40 nm, and the ohmic contact layer excluding the holes and the opening has a thickness of 50 to 200 nm.

6. The semiconductor device according to claim 3, wherein the second compound semiconductor layer is an etching stopper layer provided between the electron supply layer and the ohmic contact layer.

7. The semiconductor device according to claim 6, wherein the second compound semiconductor layer includes an Al_]___z__wIn_wGa_zP layer (0 < z, w ≤ 1) .

8. The semiconductor device according to claim 7, wherein the ohmic contact layer under the holes has a thickness of 10 to 40 nm, and the ohmic contact layer excluding the holes and the opening has a thickness of 50 to 200 nm.

9. The semiconductor device according to claim 2, wherein the first compound semiconductor layer is an electron supply layer provided between the channel layer and the ohmic contact layer, the second compound semiconductor layer is an etching stopper layer provided between the electron supply layer and the ohmic contact layer.

10. The semiconductor device according to claim 9, wherein the first compound semiconductor layer includes an Ali__x_yInyGa_xAs layer (0 < x, y < 1), the second compound semiconductor layer includes an Al₁__z__wIn_wGa_zP layer (0 < z, w < 1) .

11. The semiconductor device according to claim 10, wherein the ohmic contact layer under the holes has a thickness of 10 to 40 nm, and the ohmic contact layer excluding the holes and the opening has a thickness of 50 to 200 nm.

12. The semiconductor device according to claim 1, wherein the first compound semiconductor layer is an electron supply layer provided between the channel layer and the ohmic contact layer.

13. The semiconductor device according to claim 12, wherein the first compound semiconductor layer includes an Al_]___x_yInyGa_xAs layer (0 < x, y < 1) .

14. The semiconductor device according to claim 13, wherein the ohmic contact layer under the holes has a thickness of 10 to 40 nm, and the ohmic contact layer excluding the holes and the opening has a thickness of 50 to 200 nm.

15. The semiconductor device according to claim 1, wherein the second compound semiconductor layer is an etching stopper layer having a function of an electron supply layer provided between the electron supply layer and the ohmic contact layer.

16. The semiconductor device according to claim 15, wherein the second compound semiconductor layer includes an Al]___z__wIn_wGa_zP layer (0 < z, w < 1) .

17. The semiconductor device according to claim 16, wherein the ohmic contact layer under the holes has a thickness of 10 to 40 nm, and the ohmic contact layer excluding the holes and the opening has a thickness of 50 to 200 nm.

18. The semiconductor device according to claim 1, wherein the first compound semiconductor layer is an electron supply layer provided between the channel layer and the ohmic contact layer, the second compound semiconductor layer is an etching stopper layer provided between the electron supply layer and the ohmic contact layer.

19. The semiconductor device according to claim 18, wherein an Ali__x_yIn.yGa_xAs layer (0 < x, y < 1) , the second compound semiconductor layer includes an Ali_[___z__wIn_wGa_zP layer (0 < z, w < 1) .

20. The semiconductor device according to claim 19, wherein the ohmic contact layer under the holes has a thickness of 10 to 40 nm, and the ohmic contact layer excluding the holes and the opening has a thickness of 50 to 200 nm.