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WO2006033167A1 - Title: dispositif a semi-conducteur - Google Patents

Title: dispositif a semi-conducteur

Info

Publication number
WO2006033167A1
WO2006033167A1 PCT/JP2004/014435 JP2004014435W WO2006033167A1 WO 2006033167 A1 WO2006033167 A1 WO 2006033167A1 JP 2004014435 W JP2004014435 W JP 2004014435W WO 2006033167 A1 WO2006033167 A1 WO 2006033167A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
ohmic contact
contact layer
holes
hemt
Prior art date
Application number
PCT/JP2004/014435
Other languages
English (en)
Inventor
Yoshitomo Sagae
Takao Noda
Yorito Kakiuchi
Tomohiro Nitta
Original Assignee
Kabushiki Kaisha Toshiba
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kabushiki Kaisha Toshiba filed Critical Kabushiki Kaisha Toshiba
Priority to PCT/JP2004/014435 priority Critical patent/WO2006033167A1/fr
Publication of WO2006033167A1 publication Critical patent/WO2006033167A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices

Definitions

  • the present invention relates to a semiconductor device using a compound semiconductor material.
  • a high electron mobility transistor has heretofore been known as one type of field effect transistor (FET) .
  • the HEMT includes a semi-insulating substrate; a channel layer which is provided on the semi-insulating substrate and which includes a high- purity semiconductor layer; and an electron supply layer which is provided on the channel layer and whose electron affinity is smaller than that of the channel layer and which is doped with n-type impurities.
  • various compound semiconductors such as
  • AlGaAs, InAlAs, InGaAlAs, InGaP, and InGaAlP are used as the material of the electron supply layer.
  • FIG. 24 shows a sectional view of a conventional HEMT.
  • FIGS. 25 to 29 are sectional views showing manufacturing processes of the HEMT.
  • a GaAs/AlGaAs superlattice buffer layer 902 non-doped Ing. lsGag.85- ⁇ s channel layer 903, non-doped AIQ , 2 ⁇ a 0.8&- s spacer layer 904, Si-doped n-type AIg.2 ⁇ a 0.8- ⁇ - s electron supply layer 905, non-doped Alo.2 ⁇ a O.8 ⁇ s Schottky contact layer 906, ⁇ n 0 cuisine48 ⁇ a 0.52-P etching stopper layer 9.07, and Si-doped n-type GaAs ohmic contact layer 908 are successively grown by an MOCVD process. Thereafter, a silicon oxide film 920 is deposited on the Si-doped n-type GaAs ohmic contact layer 908.
  • a resist pattern 921 is formed on the silicon oxide film 920, and thereafter the resist pattern 921 is used as a mask to etch the silicon oxide film 920 by a wet process. As a result, the surface of the ohmic contact layer 908 on a source/drain region is exposed.
  • FIG. 27 on the resist pattern
  • a conductive layer 909 of a laminate structure including an AuGe layer, Ni layer, and Au layer is formed by an evaporation process.
  • the AuGe layer is a lower-layer side of the conductive layer 909, and the Au layer is an upper- layer side of the conductive.
  • the resist pattern 921 and the conductive layer 909 provided above it are removed (lift-off process) .
  • the remaining two conductive layers 909 form source/drain electrodes, respectively.
  • a heating process (alloying process) at about 350 to 450°C, elements such as Au and Ge in the source/drain electrodes 909 are diffused in the ohmic contact layer 908, etching stopper layer 907, and Schottky contact layer 906.
  • elements such as Au and Ge in the source/drain electrodes 909 are diffused in the ohmic contact layer 908, etching stopper layer 907, and Schottky contact layer 906.
  • an ohmic alloy layer 910 is formed in the ohmic contact layer 908, etching stopper layer 907, and Schottky contact layer 906.
  • a resist pattern 922 is formed on the ohmic contact layer 908 and source/drain electrodes 909. Thereafter, the resist pattern 922 is used as the mask to etch the ohmic contact layer 908 and etching stopper layer 907 by the wet process. As a result, the surface of the Schottky contact layer 906 on a gate region is exposed. Thereafter, in the same manner as in a process for forming the source/drain electrodes 909, the evaporation and lift-off processes are carried out to form a gate electrode 911 on the Schottky contact layer 906.
  • any metal which makes Schottky junction with the Schottky contact layer can be used as a material of the gate electrode formed by the evaporation process, for instance, a laminated layer structure including Ti layer/Pt layer/Au layer or a laminated layer structure including Ti layer/Al layer can be used.
  • the conventional HEMT shown in FIG. 24 is obtained.
  • the ohmic alloy layer 910 does not reach the channel layer 903.
  • the ohmic alloy layer 910 preferably reaches the channel layer 903.
  • the ohmic alloy layer 910 extended into the channel layer 903 is formed, as shown in FIG. 30, only a part of the ohmic alloy layer 910 enters the channel layer 903.
  • a shape and size of the part of the ohmic alloy layer 910 extended into the channel layer 903 differ with devices. Fluctuations of the shape and size of this ohmic alloy layer 910 cause those of source/drain resistances, and further cause those of the device characteristics such as a high-frequency characteristic and low noise capability.
  • An object of the present invention is to provide a semiconductor device using a compound semiconductor material, including a structure in which an ohmic alloy layer extended into a channel layer can easily be formed. Disclosure of Invention
  • a semiconductor device comprising: a semi-insulating substrate; a channel layer provided above the semi-insulating substrate and including an In u Gai_ u As layer (0 ⁇ u ⁇ 1) ; an ohmic contact layer provided above the channel layer and including an In ⁇ Ga ] __ ⁇ As layer (0 ⁇ V ⁇ 1), the ohmic contact layer including two holes on its surface, the ohmic contact layer between the two holes including an opening; two source/drain electrodes including metal, one of the source/drain electrodes contacting a bottom surface of one of the two holes and the other of the source/drain electrodes contacting a bottom surface of the other of the two holes; a gate electrode provided in the opening; a multilayered compound semiconductor layer provided between the channel layer and the ohmic contact layer and including a first and second compound semiconductor layers, a diffusion coefficient of the metal in one of the first and second compound semiconductor layers being smaller than a diffusion coefficient of the metal in at least a
  • FIG. 2 is a sectional view showing a manufacturing process of the HEMT according to the first embodiment of the present invention
  • FIG. 3 is a sectional view, following FIG. 2, showing the manufacturing process of the HEMT according to the first embodiment
  • FIG. 4 is a sectional view, following FIG. 3, showing the manufacturing process of the HEMT according to the first embodiment
  • FIG. 5 is a sectional view, following FIG. 4, showing the manufacturing process of the HEMT according to the first embodiment
  • FIG. 6 is a sectional view, following FIG. 5, showing the manufacturing process of the HEMT according to the first embodiment
  • FIG. 7 is a sectional view showing the HEMT according to the second embodiment of the present invention
  • FIG. 8 is a sectional view showing the manufacturing process of the HEMT according to the second embodiment of the present invention.
  • FIG. 9 is a sectional view, following FIG. 8, showing the manufacturing process of the HEMT according to the second embodiment
  • FIG. 10 is a sectional view showing the HEMT according to the third embodiment of the present invention.
  • FIG. 11 is a sectional view showing the manufacturing process of the HEMT according to the third embodiment of the present invention.
  • FIG. 12 is a sectional view, following FIG. 11, showing the manufacturing process of the HEMT according to the third embodiment
  • FIG. 13 is a sectional view, following FIG. 12, showing the manufacturing process of the HEMT according to the third embodiment
  • FIG. 14 is a sectional view, following FIG. 13, showing the manufacturing process of the HEMT according to the third embodiment
  • FIG. 15 is a sectional view, following FIG. 14, showing the manufacturing process of the HEMT according to the third embodiment;
  • FIG. 16 is a sectional view showing the HEMT according to the fourth embodiment of the present invention.
  • FIG. 17 is a sectional view showing the manufacturing process of the HEMT according to the fourth embodiment of the present invention.
  • FIG. 18 is a sectional view, following FIG. 17, showing the manufacturing process of the HEMT according to the fourth embodiment
  • FIG. 19 is a sectional view, following FIG. 18, showing the manufacturing process of the HEMT according to the fourth embodiment
  • FIG. 20 is a sectional view, following FIG. 19, showing the manufacturing process of the HEMT according to the fourth embodiment
  • FIG. 21 is a sectional view, following FIG. 20, showing the manufacturing process of the HEMT according to the fourth embodiment
  • FIG. 22 is a sectional view showing the HEMT according to the fifth embodiment of the present invention.
  • FIG. 23 is a diagram showing a relation between a contact resistance after forming an ohmic alloy layer and a thickness of an ohmic contact layer under source/drain electrodes;
  • FIG. 24 is a sectional view showing a conventional HEMT
  • FIG. 25 is a sectional view showing the manufacturing process of the conventional HEMT
  • FIG. 26 is a sectional view, following FIG. 24, showing the manufacturing process of the conventional HEMT
  • FIG. 27 is a sectional view, following FIG. 25, showing the manufacturing process of the conventional HEMT
  • FIG. 28 is a sectional view, following FIG. 26, showing the manufacturing process of the conventional HEMT
  • FIG. 29 is a sectional view, following FIG. 27, showing the manufacturing process of the conventional HEMT .
  • FIG. 30 is a sectional view showing a problem of the conventional HEMT.
  • FIG. 1 is a sectional view showing HEMT according to the first embodiment of the present invention.
  • the HEMT of the present embodiment includes a semi-insulating GaAs substrate 101; a non-doped Ing ⁇ i5Gag.85- ⁇ s channel layer 103 provided above the semi-insulating GaAs substrate 101; a Si-doped n-type GaAs ohmic contact layer 108 provided above the channel layer 103; a multilayered compound semiconductor layer which is provided between the channel layer 103 and the ohmic contact layer 108 and which includes a Si-doped n-type Alo.2 ⁇ a O.8 ⁇ - s electron supply layer 105, a non-doped AIg .2 ⁇ a 0.8 ⁇ - s Schottky contact layer 106, and an Ing.4gGag # 52? etching stopper layer 107; two source/drain electrodes 109; a gate electrode 111; and an ohmic alloy layer 110
  • Two holes 122 are provided in the surface of the ohmic contact layer 108 on a source/drain region.
  • Two source/drain electrodes 109 contact bottom surfaces of two holes 122, respectively.
  • the surfaces of two source/drain electrodes 109 are substantially flat.
  • the ohmic contact layer 108 and etching stopper layer 107 on a gate region includes an opening 124.
  • the gate electrode 111 is provided on the Schottky contact layer 106 in the opening 124.
  • the ohmic alloy layers 110 are formed in a region reaching the surface of the channel layer 103 from that of the ohmic contact layer 108 under the source/drain electrodes 109.
  • GaAs substrate 101 a GaAs/AlGaAs superlattice buffer layer 102, non-doped Ing . lsGag .85- ⁇ s channel layer 103, non-doped AIQ.2 Ga 0.8 As spacer layer 104, Si-doped n-type AIg.2 Ga 0.8 As electron supply layer 105, non-doped AIQ .2 Ga 0.8 ⁇ - s Schottky contact layer 106,
  • n-type GaAs ohmic contact layer 108 are successively grown by an MOCVD process. Thereafter, a silicon oxide film 120 is deposited on the ohmic contact layer 108. Moreover, a resist pattern 121 is formed on the silicon oxide film 120.
  • a thickness of the ohmic contact layer 108 is 50 nm or more and 200 nm or less.
  • the reason why the thickness of the ohmic contact layer 108 is 50 nm or more is that a sheet resistance be lowered.
  • a HEMT has been requested to be low in a source/drain resistance. For that, as described above, it is necessary to lower the sheet resistance.
  • the reason why the thickness of the ohmic contact layer 108 is set to 200 nm or less is that etching controllability of the ohmic contact layer 108 is remarkably deteriorated with the thickness exceeding 200 nm.
  • the thickness of a portion left in etching the ohmic contact layer 108 (the thickness of the ohmic contact layer 108 under the source/drain electrodes 109) is 10 nm or more and 40 nm or less.
  • the resist pattern 121 is used as a mask to etch the silicon oxide film 120 by a wet process. Subsequently, the resist pattern 121 is used as the mask to etch the ohmic contact layer 108 by the wet process using a phosphoric-acid-based etching solution.
  • the holes 122 are formed in the surface of the ohmic contact layer 108 so that the surface of the etching stopper layer 107 under the ohmic contact layer 108 is not exposed.
  • the ohmic contact layer 108 under the holes 122 (an etched but remaining portion in the ohmic contact layer 108) has a thickness of 10 nm or more and 40 nm or less. The reason why the thickness is set to 10 nm or more and 40 nm or less will be described later.
  • a conductive layer of a laminate structure including an AuGe layer, Ni layer, and Au layer is formed by an evaporation process. Thereafter, the resist pattern 121 and the conductive layer on the pattern are removed (lift-off process) .
  • the source/drain electrodes 109 including the conductive layer are formed on the holes 122 of the ohmic contact layer 108.
  • the AuGe layer is a lower-layer side of the source/drain electrodes 109, and the Au layer is an upper-layer side.
  • the ohmic alloy layers 110 are formed.
  • the source/drain electrodes 109 contain metals such as Au.
  • a diffusion coefficient of metals in Al ] __ z _ w In w Ga z P (0 ⁇ z, w ⁇ 1) which is the material of the etching stopper layer 107 is smaller than that of the metals in GaAs which is the material of the ohmic contact layer 108.
  • a time of the alloying process is lengthened, or a temperature of the alloying process is raised. Accordingly, even if the thickness of the ohmic contact layer 108 under the source/drain electrodes 109 is not reduced, it is possible to form the ohmic alloy layer 110 reaching the inside of the channel layer 103.
  • FIG. 23 a relation between a contact resistance pc after forming the ohmic alloy layers 110 and a thickness d of the ohmic contact layer under the source/drain electrodes 109 (the thickness of the ohmic contact layer 108 under the holes 122) is shown in FIG. 23.
  • the contact resistance is requested to be 1 X 10 ⁇ 6 ⁇ cm 2 or less. Therefore, to satisfy the requirement, it is seen from FIG. 23 that the thickness d needs to be 10 nm or more and 40 nm or less. This is why the thickness of the ohmic contact layer 108 under the source/drain electrodes 109 is set to 10 nm or more and 40 nm or less.
  • a resist pattern 123 is formed on the ohmic contact layer 108 and source/drain electrodes 109.
  • the resist pattern 123 is formed by a lithography process.
  • the resist pattern 123 is used as the mask to etch the ohmic contact layer 108 and etching stopper layer 107. Accordingly, the opening 124 is formed in the ohmic contact layer 108 and etching stopper layer 107.
  • the ohmic contact layer (GaAs-based compound) 108 is etched by the wet process using the phosphoric-acid- based etching solution.
  • an etching rate of an InGaP-based compound is 1/40 of that of the GaAs-based compound. That is, the etching rate of the InGaP-based compound is sufficiently small as compared with that of the GaAs-based compound.
  • the ohmic contact layer (GaAs-based compound) 108 is selectively etched, and the surface of the etching stopper layer (InGaP-based compound) 107 is exposed. That is, when the ohmic contact layer 108 is etched, the etching stopper layer 107 functions as an etching stopper.
  • the etching stopper layer 107 is etched by the wet process using hydrochloric acid.
  • an AlGaAs-based compound is hardly etched by hydrochloric acid. Therefore, the etching stopper layer (InGaP-based compound) 107 is selectively etched, and the surface of the Schottky contact layer
  • the evaporation process and lift-off process are performed, and the gate electrode 111 is formed on the Schottky contact layer 106.
  • Any metal which makes Schottky junction with the Schottky contact layer can be used as a material of the gate electrode formed by the evaporation process, for instance, a laminated layer structure including Ti layer/Pt layer/Au layer or a laminated layer structure including Ti layer/Al layer can be used.
  • the formation method using the evaporation lift-off process is explained, but another formation method using metal deposition process such as sputter process or metal CVD process can be used. In this manner, the HEMT shown in FIG. 1 is obtained.
  • electric characteristics of the HEMT of the present embodiment were compared with those of a conventional HEMT.
  • a source resistance Rs and drain resistance Rd of the HEMT of the present embodiment were lower by 20% as compared with those of the conventional HEMT.
  • a mutual conductance gm and current gain cutoff frequency fT of the HEMT of the present embodiment were higher by 12% as compared with those of the conventional HEMT.
  • a minimum noise index NFmin of the HEMT of the present embodiment was lower by about 0.1 dB as compared with that of the conventional HEMT.
  • the reason why the electric characteristics (gm, fT, and NFmin) of the HEMT of the present embodiment are superior to those of the conventional HEMT is that Rs and Rd of the HEMT of the present embodiment are lower than those of the conventional HEMT.
  • the sizes of the fluctuations of gm, fT, and NFmin of the HEMT of the present embodiment were also largely improved, respectively, as compared with those of the conventional HEMT.
  • FIG. 7 is a sectional view showing the HEMT according to the second embodiment of the present invention.
  • opening diameters of the holes 122 of the ohmic contact layer 108 were larger than widths of the source/drain electrodes 109, and the surfaces of the source/drain electrodes 109 of the first embodiment were substantially flat.
  • the opening diameters of holes 222 of an ohmic contact layer 208 are larger than widths of source/drain electrodes 209, and the surfaces of the source/drain electrodes 209 include holes provided opposite to the holes 222.
  • GaAs substrate 201 a GaAs/AlGaAs superlattice buffer layer 202, non-doped I ⁇ Q # isGag o 85 ⁇ s channel layer 203, non-doped AIQ ⁇ 2 ⁇ a 0.8- ⁇ s spacer layer 204, Si-doped n-type AlQ.2 Ga 0.8 As electron supply layer 205, non-doped Al Q ⁇ Gag.sAs Schottky contact layer 206,
  • the thickness of the ohmic contact layer 208 is 50 nm or more and 200 nm or less for the reason similar to that of the first embodiment.
  • a silicon oxide film 220 is deposited on the Si-doped n-type GaAs ohmic contact layer 208, and thereafter a resist pattern 221 is formed on the silicon oxide film 220.
  • the opening diameters of the resist pattern 112 were larger than the widths of the source/drain electrodes 109, but in the present embodiment, the opening diameters of the resist pattern 221 are smaller than the widths of the source/drain electrodes 209.
  • the resist pattern 221 is used as the mask to etch the silicon oxide film 220 by the wet process, and subsequently the resist pattern 221 is used in the mask to etch the ohmic contact layer 208 by the wet process using the phosphoric-acid-based etching solution.
  • the ohmic contact layer 208 is etched so as to prevent the surface of the etching stopper layer 207 under the ohmic contact layer 208 from being exposed. That is, the holes 222 are formed in the surface of the ohmic contact layer 208.
  • the thickness of the ohmic contact layer 208 under the holes 222 is 10 nm or more and 40 nm or less for the reason similar to that of the first embodiment.
  • the silicon oxide film 220 and resist pattern 221 are removed, the conductive layer of the laminate structure including an AuGe layer, Ni layer, and Au layer is formed on the whole surface by the evaporation process, and the conductive layer is processed by the photolithography and etching process to obtain the source/drain electrodes 209.
  • the AuGe layer is the lower-layer side of the source/drain electrodes 209, and the Au layer is the upper-layer side.
  • an ohmic alloy layer 210, opening 124, and gate electrode 211 are formed to obtain the HEMT shown in FIG. 7.
  • the opening diameters of the holes 222 of the ohmic contact layer 208 are smaller than the widths of the source/drain electrodes 209. This prevents a bore from being accidentally made in the ohmic contact layer 208 in peripheral edges of the source/drain electrodes 209 by a rinsing treatment performed after the step of forming the source/drain electrodes 209. This prevents an increase of the contact resistance by the rinsing treatment.
  • the source/drain electrode structure which is low in the contact resistance is obtained in a short time.
  • the electric characteristics of the HEMT of the present embodiment were compared with those of the conventional HEMT.
  • Rs and Rd of the HEMT of the present embodiment were lower by 25%, respectively, as compared with those of the conventional HEMT.
  • the gm and fT of the HEMT of the present embodiment were higher by 15%, respectively, as compared with those of the conventional HEMT.
  • the NFmin of the HEMT of the present embodiment was lower by about 0.1 dB as compared with that of the conventional HEMT.
  • the reason why the electric characteristics (gm, fT, and NFmin) of the HEMT of the present embodiment are superior to those of the conventional HEMT is that Rs and Rd of the HEMT of the present embodiment are lower than those of the conventional HEMT.
  • the sizes of the fluctuations of gm, fT, and NFmin of the HEMT of the present embodiment were also largely improved, respectively, as compared with those of the conventional HEMT.
  • the gate electrode has a cross section view of straight structure in the present embodiment, even a T shape structure allows same effect as the present embodiment.
  • FIG. 10 is a sectional view showing the HEMT according to the third embodiment of the present invention.
  • the HEMT of the first and second embodiments was of a single hetero junction type, but the HEMT of the present embodiment is of a double hetero junctions type.
  • the opening diameters of the holes 122 of the ohr ⁇ ic contact layer 108 were larger than the widths of the source/drain electrodes 109, and the surfaces of the source/drain electrodes 109 of the first embodiment were substantially flat.
  • the opening diameters of holes 322 of an ohmic contact layer 311 are smaller than the widths of source/drain electrodes 312, and the surfaces of the source/drain electrodes 312 include holes provided opposite to the through holes 322.
  • a GaAs/AlGaAs superlattice buffer layer 302 Si-doped n-type AlQ.2 Ga 0.8 As electron supply layer 303, non-doped AlQ.2 Ga 0.8 As spacer layer 304, non-doped channel layer 305, AIQ .2 Ga 0.8- ⁇ - s spacer layer 306, Si-doped n-type AIQ.2 Ga 0.8- ⁇ - s electron supply layer 307, non-doped Alo.2 Ga O.8 As Schottky contact layer 308, Ing.48 Ga 0.52 P etching stopper layer 309, Si-doped n-type GaAs layer 310, and Si-doped n-type GaAs ohmic contact layer 311 are successively grown by the MOCVD process.
  • the thickness of the ohmic contact layer 311 is 50 ran or more and 200 ran or less for the reason similar to that of the first embodiment.
  • the thickness of the n-type GaAs layer 310 corresponds to that of the etched but left portion of the ohmic contact layer 108 of the first embodiment. Therefore, the thickness of the n-type GaAs layer 310 is 10 nm or more and 40 nm or less for the reason similar to that of the first embodiment.
  • a resist pattern 320 is formed on the ohmic contact layer 311, and thereafter the resist pattern 320 is used as the mask to etch the ohmic contact layer 311 by the wet process using the phosphoric-acid-based etching solution.
  • the ohmic contact layer 311 is etched so that through holes 321 are formed in the ohmic contact layer 311. The surface of the n-type GaAs layer 310 in the bottom of the through holes 321 is exposed.
  • the resist pattern 320 is removed, and the conductive layer of the laminate structure including the AuGe layer, Ni layer, and Au layer is formed on the ohmic contact layer 311 and the n-type GaAs layer 310 in the bottom of the through holes 321 by the evaporation process.
  • the conductive layer is processed by the photolithography and etching process to form the source/drain electrodes 312 including the conductive layer as shown in FIG. 13.
  • the AuGe layer is the lower-layer side of the source/drain electrodes 312, and the Au layer is the upper-layer side.
  • the elements such as Au and Ge in the source/drain electrodes 312 are diffused in the ohmic contact layer 311, n-type GaAs layer 310, etching stopper layer 309, Schottky contact layer 308, electron supply layer 307, spacer layer 306, and channel layer 305.
  • an ohmic alloy layer 313 is formed in the ohi ⁇ ic contact layer 311, n-type GaAs layer 310, etching stopper layer 309, Schottky contact layer 308, electron supply layer 307, spacer layer 306, and channel layer 305. Also in the present embodiment, in the same manner as in the first embodiment, the source/drain electrode structure which is low in the contact resistance is obtained in the short time.
  • a first opening is formed in the ohmic contact layer 311.
  • the etching process is the wet process using the phosphoric-acid-based etching solution.
  • a second opening is formed in the n-type GaAs layer 310 and etching stopper layer 309 in the first opening.
  • the opening diameter of the second opening is smaller than that of the first opening.
  • the etching process for forming the second opening is the wet process using the phosphoric-acid- based etching solution, when etching the n-type GaAs layer 310.
  • the etching rate of the InGaP-based compound is 1/40 of that of the GaAs-based compound
  • the n-type GaAs layer 310 is selectively etched to expose the surface of the etching stopper layer (InGaP-based compound) 309. That is, when the n-type GaAs layer 310 is etched, the etching stopper layer 309 functions as the etching stopper.
  • the etching process is the wet process using hydrochloric acid, when etching the etching stopper layer 309.
  • the etching stopper layer 309 is selectively etched to expose the surface of the Schottky contact layer (AIQ.2 Ga 0.8 As ) 308 - This is because the AlGaAs-based compound is hardly etched by hydrochloric acid.
  • the evaporation and lift-off processes are performed to form a gate electrode 314 on the Schottky contact layer 308.
  • Any metal which makes Schottky junction with the Schottky contact layer can be used as a material of the gate electrode formed by the evaporation process, for instance, a laminated layer structure including Ti layer/Pt layer/Au layer or a laminated layer structure including Ti layer/Al layer can be used.
  • the formation method using the evaporation lift-off process is explained, but another formation method using metal deposition process such as sputter process or metal CVD process can be used. In this manner, the HEMT shown in FIG. 10 is obtained.
  • the electron microscopes such as SEM and TEM
  • the electric characteristics of the HEMT of the present embodiment were compared with those of the conventional HEMT.
  • Rs and Rd of the HEMT of the present embodiment were lower by 30%, respectively, as compared with those of the conventional HEMT.
  • the gm and fT of the HEMT of the present embodiment were higher by 18%, respectively, as compared with those of the conventional HEMT.
  • the NFmin of the HEMT of the present embodiment was lower by about 0.1 dB as compared with that of the conventional HEMT.
  • the reason why the electric characteristics (gm, fT, and NFmin) of the HEMT of the present embodiment are superior to those of the conventional HEMT is that Rs and Rd of the HEMT of the present embodiment are lower than those of the conventional HEMT.
  • the sizes of the in-plane fluctuations of Rs and Rd of the HEMT of the present embodiment were largely improved as about 1/2, respectively, as compared with those of the conventional HEMT.
  • the sizes of the fluctuations of gm, fT, and NFmin of the HEMT of the present embodiment were also largely improved, respectively, as compared with those of the conventional HEMT.
  • FIG. 16 is a sectional view showing the HEMT according to the fourth embodiment of the present invention.
  • the HEMT of the first and second embodiments was of the single hetero junction type, but the HEMT of the present embodiment is of the double hetero junctions type.
  • the opening diameters of the holes 122 of the ohmic contact layer 108 were larger than the widths of the source/drain electrodes 109, and the surfaces of the source/drain electrodes 109 of the first embodiment were substantially flat.
  • the opening diameters of through holes 421 of an ohmic contact layer 412 are smaller than the widths of source/drain electrodes 413, and the surfaces of the source/drain electrodes 413 include holes provided opposite to the through holes 421.
  • the etching stopper layer was not provided on the n-type GaAs layer 310 in the HEMT of the third embodiment, but an etching stopper layer 411 is also provided on an ohmic contact layer 410.
  • the details of the HEMT of the present embodiment will hereinafter be described with reference to the sectional views of FIGS. 17 to 21 showing the manufacturing process.
  • a GaAs/AlGaAs superlattice buffer layer 402 Si-doped n-type AIQ.2 ⁇ a 0.8- ⁇ s electron supply layer 403, non-doped AIQ.2 ⁇ aQ. sAs spacer layer 404, non-doped Ing # channel layer 405, non-doped AIg.2 ⁇ aQ.8 ⁇ s spacer layer 406, Si-doped n-type AIQ # 2 ⁇ a 0.8- ⁇ s electron supply layer 407, non-doped
  • AIQ .2 ⁇ a 0.8 ⁇ - s Schottky contact layer 408, Ing.48Gag.52? etching stopper layer 409, Si-doped n-type GaAs layer 410, Ing .48 Ga 0.52 p etching stopper layer 411, and Si-doped n-type GaAs ohmic contact layer 412 are successively grown by the MOCVD process.
  • the thickness of the ohmic contact layer 412 is 50 nm or more and 200 nm or less for the reason similar to that of the first embodiment.
  • the thickness of the n-type GaAs layer 410 corresponds to that of the etched but left portion of the ohmic contact layer 108 of the first embodiment. Therefore, the thickness of the n-type GaAs layer 410 is 10 nm or more and 40 nm or less for the reason similar to that of the first embodiment.
  • a resist pattern 420 is formed on the ohmic contact layer 412, thereafter the resist pattern 420 is used as the mask to etch the ohmic contact layer 412 and etching stopper layer 411 by the wet process, and the through holes 421 are formed.
  • the etching process is the wet process using the phosphoric-acid-based etching solution, when etching the ohmic contact layer 412.
  • the etching rate of the InGaP-based compound is 1/40 of that of the GaAs-based compound
  • the ohmic contact layer 412 is selectively etched to expose the surface of the etching stopper layer (InGaP-based compound) 411. That is, when the ohmic contact layer 412 is etched, the etching stopper layer 411 functions as the etching stopper.
  • the etching process is the wet process using concentrated hydrochloric acid, when etching the etching stopper layer 411.
  • the etching stopper layer 411 is selectively etched to expose the surface of the n-type GaAs layer 410. This is because the GaAs-based compound is hardly etched by hydrochloric acid.
  • the resist pattern 420 is removed, and the conductive layer of the laminate structure including the AuGe layer, Ni layer, and Au layer is formed on the ohmic contact layer 412 and the n-type GaAs layer 410 in the bottoms of the through holes 421 by the evaporation process.
  • the conductive layer is processed by the photolithography and etching process to form the source/drain electrodes 413 including the conductive layer as shown in FIG. 19.
  • the AuGe layer is the lower-layer side of the source/drain electrodes 312, and the Au layer is the upper-layer side.
  • the elements such as Au and Ge in the source/drain electrodes 413 are diffused in the ohmic contact layer 412, etching stopper layer 411, n-type GaAs layer 410, etching stopper layer 409, Schottky contact layer 408, electron supply layer 407, spacer layer 406, and channel layer 405.
  • ohmic contact layer 412 As a result, as shown in FIG. 20, in the ohmic contact layer 412, etching stopper layer 411, n-type GaAs layer 410, etching stopper layer 409, Schottky contact layer 408, electron supply layer 407, spacer layer 406, and channel layer 405, ohmic alloy layers 414 are formed. Also in the present embodiment, in the same manner as in the first embodiment, the source/drain electrode structure which is low in the contact resistance is obtained in the short time.
  • the etching process is the wet process using the phosphoric-acid-based etching solution, when etching the n-type GaAs layer 410.
  • the n-type GaAs layer 410 is selectively etched to expose the surface of the etching stopper layer (InGaP-based compound) 409.
  • the etching stopper layer 409 functions as the etching stopper.
  • the etching process is the wet process using hydrochloric acid, when etching the etching stopper layer 409. At this time, the etching stopper layer 409 is selectively etched to expose the surface of the Schottky contact layer 408. This is because the AlGaAs-based compound is hardly etched by hydrochloric acid.
  • the evaporation and lift-off processes are performed to form a gate electrode 415 on the Schottky contact layer 408.
  • Any metal which makes Schottky junction with the Schottky contact layer can be used as a material of the gate electrode formed by the evaporation process, for instance, a laminated layer structure including Ti layer/Pt layer/Au layer or a laminated layer structure including Ti layer/Al layer can be used.
  • the formation method using the evaporation lift-off process is explained, but another formation method using metal deposition process such as sputter process or metal CVD process can be used. In this manner, the HEMT shown in FIG. 16 is obtained.
  • the electric characteristics of the HEMT of the present embodiment were compared with those of the conventional HEMT.
  • Rs and Rd of the HEMT of the present embodiment were lower by 30%, respectively, as compared with those of the conventional HEMT.
  • the gm and fT of the HEMT of the present embodiment were higher by 18%, respectively, as compared with those of 'the conventional HEMT.
  • the NFmin of the HEMT of the present embodiment was lower by about 0.1 dB as compared with that of the conventional HEMT.
  • the reason why the electric characteristics (gm, fT, and NFmin) of the HEMT of the present embodiment are superior to those of the conventional HEMT is that Rs and Rd of the HEMT of the present embodiment are lower than those of the conventional HEMT.
  • the sizes of the fluctuations of gm, fT, and NFmin of the HEMT of the present embodiment were also largely improved, respectively, as compared with those of the conventional HEMT.
  • FIG. 22 is a sectional view showing the HEMT according to a fourth embodiment of the present invention.
  • the manufacturing process of the HEMT of the present embodiment is as follows.
  • a GaAs/AlGaAs superlattice buffer layer 502 Si-doped n-type Alo.2 Ga O.8 As electron supply layer 503, non-doped AIQ .2 ⁇ a 0.8- ⁇ s spacer layer 504, non-doped - ⁇ n 0.15 Ga 0.85 ⁇ s channel layer 505, non-doped AI Q ⁇ 2 ⁇ a Q . ⁇ As spacer layer 506, Si-doped n-type AIg.2 ⁇ a 0.8 ⁇ s electron supply layer 507, non-doped
  • Ga 0.52-P Schottky contact layer 508, and Si-doped n-type GaAs ohmic contact layer 509 are successively grown by the MOCVD process.
  • the thickness of the ohmic contact layer 509 is 50 nm or more and 200 nm or less for the reason similar to that of the first embodiment.
  • holes 520 are formed in the surface of the ohmic contact layer 509, and further source/drain electrodes 510 are formed in the holes 520.
  • the lower layer of the source/drain electrodes 510 is the AuGe layer, and the upper layer is the Au layer.
  • the thickness of the ohmic contact layer 509 under the source/drain electrodes 510 (under the holes 521) is 10 nm or more and 40 nm or less for the reason similar to that of the first embodiment.
  • ohmic alloy layers 5.11 are formed in the ohmic contact layer 509, Schottky contact layer 508, electron supply layer 507, spacer layer 506, and channel layer 505.
  • the source/drain electrode structure which is low in the contact resistance is obtained in the short time.
  • an opening 521 is formed in the ohmic contact layer 509 in a region between two source/drain electrodes 510.
  • the etching process is the wet process using the phosphoric-acid-based etching solution.
  • the etching rate of the InGaP-based compound is 1/40 of that of the GaAs-based compound
  • the ohmic contact layer (GaAs-based compound) 509 is selectively etched to expose the surface of the Schottky contact layer (InGaP-based compound) 508.
  • any metal which makes Schottky junction with the Schottky contact layer can be used as a material of the gate electrode formed by the evaporation process, for instance, a laminated layer structure including Ti layer/Pt layer/Au layer or a laminated layer structure including Ti layer/Al layer can be used.
  • the formation method using the evaporation lift-off process is explained, but another formation method using metal deposition process such as sputter process or metal CVD process can be used. In this manner, the HEMT shown in FIG. 16 is obtained.
  • the electric characteristics of the HEMT of the present embodiment were compared with those of the conventional HEMT.
  • Rs and Rd of the HEMT of the present embodiment were lower by 30%, respectively, as compared with those of the conventional HEMT.
  • the gm and fT of the HEMT of the present embodiment were higher by 18%, respectively, as compared with those of the conventional HEMT.
  • the NFmin of the HEMT of the present embodiment was lower by about 0.1 dB as compared with that of the conventional HEMT.
  • the reason why the electric characteristics (gm, fT, and NFmin) of the HEMT of the present embodiment are superior to those of the conventional HEMT is that Rs and Rd of the HEMT of the present embodiment are lower than those of the conventional HEMT.
  • the sizes of the in-plane fluctuations of Rs and Rd of the HEMT of the present embodiment were largely improved as about 1/3, respectively, as compared with those of the conventional HEMT.
  • the sizes of the fluctuations of gm, fT, and NFmin of the HEMT of the present embodiment were also largely improved, respectively, as compared with those of the conventional HEMT.
  • the present invention applied to the HEMT has been described, but the present invention can also be applied to another field effect transistor such as a hetero junction FET.
  • the Ali__ z _ w In w Ga z P layer and Al ] __ x _yIn x GaAs layer for use in the device can appropriately be changed in a range of 0 ⁇ Z, w ⁇ 1 and 0 ⁇ x, Y ⁇ 1.
  • the present invention can variously be modified and carried out without departing from the scope.
  • a semicon ⁇ ductor device using a compound semiconductor material can be obtained including a structure in which an ohmic alloy layer extended into a channel layer can easily be formed.

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  • Junction Field-Effect Transistors (AREA)

Abstract

Dispositif à semi-conducteur comprenant une couche de canal (103), une couche de contact ohmique (108) au-dessus de la couche de canal, la couche de contact ohmique comprenant deux orifices sur sa surface et une ouverture entre les orifices, deux électrodes de source/drain (109) comprenant un métal, une des électrodes entrant en contact avec la surface inférieure d’un des orifices et l’autre des électrodes entrant en contact avec la surface inférieure de l’autre des orifices, une électrode grille (111) dans l’ouverture, une couche à semi-conducteur de composés multicouches (106, 107) entre les couches de canal et de contact ohmique et comprenant des première et seconde couches à semi-conducteur de composés, un coefficient de diffusion du métal dans une des couches à semi-conducteur de composés étant inférieur à celui du métal dans la couche de contact ohmique, et une couche d’alliage (110) dans une région atteignant une surface de la couche de canal depuis la surface de la couche de contact ohmique sous les électrodes et comprenant le métal.
PCT/JP2004/014435 2004-09-24 2004-09-24 Title: dispositif a semi-conducteur WO2006033167A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2914500A1 (fr) * 2007-03-30 2008-10-03 Picogiga Internat Soc Par Acti Dispositif electronique a contact ohmique ameliore

Citations (5)

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Publication number Priority date Publication date Assignee Title
JPH0438836A (ja) * 1990-06-04 1992-02-10 Fujitsu Ltd 半導体装置の製造方法
JPH05315368A (ja) * 1992-05-13 1993-11-26 Sony Corp 電界効果トランジスタ
JPH11177079A (ja) * 1997-12-15 1999-07-02 Nec Corp 電界効果トランジスタ
JP2003100778A (ja) * 2001-09-26 2003-04-04 Toshiba Corp 半導体装置
JP2003197558A (ja) * 2001-12-28 2003-07-11 New Japan Radio Co Ltd 半導体装置およびその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0438836A (ja) * 1990-06-04 1992-02-10 Fujitsu Ltd 半導体装置の製造方法
JPH05315368A (ja) * 1992-05-13 1993-11-26 Sony Corp 電界効果トランジスタ
JPH11177079A (ja) * 1997-12-15 1999-07-02 Nec Corp 電界効果トランジスタ
JP2003100778A (ja) * 2001-09-26 2003-04-04 Toshiba Corp 半導体装置
JP2003197558A (ja) * 2001-12-28 2003-07-11 New Japan Radio Co Ltd 半導体装置およびその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2914500A1 (fr) * 2007-03-30 2008-10-03 Picogiga Internat Soc Par Acti Dispositif electronique a contact ohmique ameliore
WO2008120094A3 (fr) * 2007-03-30 2008-12-04 Picogiga Internat Dispositif électronique avec contact ohmique optimisé
US7968390B2 (en) 2007-03-30 2011-06-28 S.O.I.Tec Silicon On Insulator Technologies Electronic devices with improved ohmic contact
US8253170B2 (en) 2007-03-30 2012-08-28 Soitec SA & Soitec USA, Inc. Electronic devices with improved OHMIC contact

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