JPH0475350A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To make it possible to manufacture a thin film transistor merely at a singe coat of image reversal photoresist by providing a first pattern formation process which processes a channel protection film based on the application of a first resist pattern shaped in conformity with a gate electrode, a second resist pattern formation process which carries out exposure development based on a photolitho mask, and a third resist pattern formation process which eliminates the resist on the channel protection film and forms a resist pattern. CONSTITUTION:This is a thin film transistor manufacture process based on the application of image reversal photoresist characteristic capable of etching each layer comprising an ITO layer 40, an n<+>a-Si:H layer 28', and an a-Si:H layer 27' at a time. Therefore, in a process after the formation of a channel protection film 29, a thin film transistor can be manufacture by coating the resist at a single coat of image reversal photoresist, which makes it possible to simplify the manufacture process.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a thin film transistor, and particularly to a method for manufacturing a thin film transistor that can simplify the manufacturing process.

(Prior Art) Conventional thin film transistors are used in various electronic devices, but in particular, they are used in image sensors such as facsimiles and scanners, and in liquid crystal displays (1quid C).
It is sometimes used as a switching element for crystal display "" L CD>.

The structure of a conventional thin film transistor will be described with reference to FIG. 4, which is an explanatory cross-sectional view.

Conventional thin film transistors use an insulating substrate 2 made of glass or the like.
1, a chromium (Cr) layer as a gate electrode 25, a silicon nitride (SiNxl) layer as a gate insulating film 26,
Hydrogenated amorphous silicon (a-5i:H) layer as semiconductor active layer 27, silicon nitride (SiNx2) layer as channel protective film 29, ohmic contact layer 2
8 as n+hydrogenated amorphous silicon (n+a−
8t:H) layer, drain electrode 41 part and source electrode 42
This transistor has an inverted staggered structure in which indium tin oxide (ITO) layers made of a transparent conductive material are sequentially laminated.

Here, the ohmic contact layer 28 is the drain electrode 4
The portion 28a layer that contacts the source electrode 1 and the portion 28b layer that contacts the source electrode 42 are formed separately. Further, the ITO layer serving as the drain electrode 41 portion and the source electrode 42 portion is formed to cover the ohmic contact layers 28a and 28b.

Next, a conventional method for manufacturing a thin film transistor will be explained using the manufacturing process diagram of a thin film transistor shown in FIG.

First, as a first step, a chromium (Cr) layer for the gate electrode 25 of the thin film transistor is deposited on the substrate 21 to a thickness of about 750 Å by DC sputtering.

Next, as a second step, the Cr is patterned by a photolithography process to form a pattern for the gate electrode 25 of the thin film transistor.

As a third step, the gate insulating film 26 of the thin film transistor is formed on the Cr pattern, and the semiconductor active Jl! 2
7 and a channel protective film 29 thereon, a SiNx1 layer 26' is formed to a thickness of about 3000A.
-3t: The H layer 27' is made of SiN with a thickness of about 1000A.
Plasma CVD (P-CVD) to sequentially break the vacuum of x2 layer 29' with a thickness of about 2000A? , : The film is deposited more (see FIG. 2(a)).

Next, as a fourth step, a positive resist (first resist) 51 is applied on the gate insulating film 26 in order to form a pattern of the channel protection H29 in a shape corresponding to the gate electrode 25. Then, back side exposure is performed from the back side of the substrate 21 by self-alignment using the shape pattern of the gate electrode 25 as a mask (see FIG. 2(b)).

As a result, it is divided into an exposed portion 51a that is exposed to light and an unexposed portion 51b that is not exposed above the channel protective film 29.

Then, as a fifth step, the exposed area 5 is
1a is dissolved to form a first resist pattern in which the resist of the unexposed portion 51b on the upper part of the channel protective film 29 remains. Then, according to the first resist pattern, a 3iNx2 layer 29 is formed using a mixed solution of HF, NH, and F.
' etching is performed and the resist is removed. As a result, a pattern of the channel protective film 29 is formed (see FIG. 2(C)).

On top of that, as a sixth step, an n medium-sized a-5i:H (n”a-8t:H) is formed as an ohmic contact layer 28.
Layer 28' is deposited by P-CVD to a thickness of approximately 1000 Å. Next, the drain electrode 41 of the thin film transistor,
An ITO layer 40, which will become the source electrode 42, is deposited to a thickness of about 600 Å by DC magnetron sputtering (see FIG. 2(d)).

Next, as a seventh step, a 0-top di-type resist (second resist) 52 is applied on the four ITO layers.

As an eighth step, a second resist pattern 52a is formed by exposure and development using a photolithographic mask to define the outer edge shapes of the drain electrode 41 and source electrode 42 of the thin film transistor (see FIG. 2(e)). reference).

As a ninth step, the second resist pattern 52a is
170 layers 40 were etched according to the method, and further n”a
-5i: Etching the H layer 28' and a-3
i: Etching the H layer 27'. As a result, the outer edge shapes of the drain electrode 41, the sos electrode 42, the ohmic contact layer 28, and the semiconductor active layer 27 are formed. As a result, the outer edge shapes of the 170 layer 40 and the n"a-3i:H layer 28' are defined, and the ITO layer 40' and the n"a-3i:
i: H layer 28'.

As a tenth step, the drain electrode 41 and the sos electrode 42 are
The resist remaining on the top of the ITO layer 40 is removed (see FIG. 2(f)).

As an eleventh step, a negative resist (third resist) 53 is applied.

As the twelfth step, 170 layers 4 with a defined outer edge shape
0' and n"a-8t: In the H layer 28', the ITO layer 40'a and n"a-3i on the upper part of the channel protective film 29:
In order to remove the H layer 28'a, backside exposure is performed from the back side of the substrate 21 by self-alignment using the shape pattern of the gate electrode 25 as a mask (see FIG. 2(g)). As a result, it is divided into an exposed portion 53a that has been exposed and an unexposed portion 53b that has not been exposed.

As a thirteenth step, an unexposed portion 53b of the third resist (negative resist) 53 is not exposed using a developer.
Development is performed to dissolve the resist in the unexposed area 53b on the upper part of the channel protective film 29, thereby forming a third resist pattern consisting of the exposed area 53a (see FIG. 2(h)).

As a fourteenth step, 170 layers 40' are etched according to the third resist pattern.

As a result, the upper 170 layer 40 of the channel protective film 29
'a is removed.

As a fifteenth step, the n''a-3i:H layer 28' is further etched according to the third resist pattern.
i: H layer 28'a is removed.

As a sixteenth step, the remaining resist 53a is removed (see FIG. 2(i)).

In this way, a thin film transistor is manufactured.

Although the conventional thin film transistor manufacturing method described above is a general manufacturing method, there is also a thin film transistor manufacturing method using a lift-off method.

Next, a thin film transistor manufacturing method using the lift-off method will be explained using the thin film transistor manufacturing process diagram shown in FIG. 3, while comparing it with the above-mentioned general manufacturing method.

In the case of the thin film transistor manufacturing method using the lift-off method, the first to fourth steps of the conventional manufacturing method described above are used to insulate the gate electrode 25, gate insulating film 26, semiconductor active layer 27, and channel protective film 29 on the substrate. layer (SiNx2 layer 2
9'), and a positive resist 54 is further deposited thereon,
Then, backside exposure is performed by self-alignment using the shape of the gate electrode 25 as a mask.

Then, as a fifth step, the exposed portion is dissolved using a developer to form a first resist pattern 54a such that the resist in the upper unexposed portion of the channel protective film 29 remains. H according to the resist pattern 54a of
The SiNx two layer 29' is etched using a mixed solution of F, NH, and F (see FIG. 3(a)). However, the resist is not removed here and will be used in the subsequent process.

While leaving the first resist pattern 54a, an ohmic contact layer 28 is formed thereon as a sixth step.
As n-type a-3i:H (n''a-3i:H) layer 2
8' is deposited using P-CVDJ to a thickness of about 1000A. Next, the drain electrode 41 of the thin film transistor,
D
A film is deposited to a thickness of about 600 Å by C magnetron sputtering (see FIG. 3(b)). In this case, since the SiNx2 layer 29' has a certain sufficient thickness and the positive resist 54 is formed on top of it to a certain degree of thickness, n"a-8t:H layer 2
8' and the ITO layer 4o are not deposited up to the upper side surfaces of the channel protective film 29 and the first resist pattern 54a.

Next, in the seventh step, the resist at 548 portions is dissolved and removed using a developer (see FIG. 3(C)).

In this case, the n"a-3i:8 layer 28'b and the ITO layer 40b formed on the resist pattern at the same time as the resist 54a are also washed away (lift-off). In this way, the pattern of the channel protective film 29 and A pattern of an n''a-8i:H layer 28' and a 170 layer 40 around it is formed.

Then, as an eighth step, a positive resist (second resist) 55 is applied to the entire surface.

As a ninth step, a second resist pattern 55a is formed by exposure and development using a photolithographic mask to define the outer edge shapes of the drain electrode 41 and source electrode 42 of the thin film transistor (FIG. 3(d)). reference).

As a tenth step, the resist button 55a of the section 2 is
The ITO layer 4o is etched according to the etching process, and further n”a
-5i: Etching the H layer 28' and a-3
i: Etching the H layer 27' and removing the drain electrode 41
Then, the outer edge shapes of the source electrode 42, the ohmic contact layer 28, and the semiconductor active layer 27 are formed (see FIG. 3(e)).

As an eleventh step, the drain electrode 41 and the sos electrode 42 are
The resist 55a remaining on the top of the ITO layer 40 is removed.

In this way, a thin film transistor is manufactured by the lift-off method.

As a prior art related to the above-mentioned lift-off method for manufacturing thin film transistors, Japanese Patent Application Laid-Open No. 59-27574
There is a technology described in the publication.

(Problems to be Solved by the Invention) However, in the conventional general thin film transistor manufacturing method as described above, there are many photolithography and etching steps, and mask alignment is difficult and complicated.
In particular, it is necessary to deposit the resist at least three times, and the etching of the ITO layer and n''a-3i:H layer is also necessary when forming the outer edge shape of the thin film transistor and when forming the ITO layer 40 on the channel protective film 29. ’a part and n”a
-3i: When removing the H layer 28''a portion, this process must be performed twice (instead of removing the H layer 28''a portion), which has the problem of increasing the manufacturing cost due to the complexity of the manufacturing process.

In addition, in the thin film transistor manufacturing method using the lift-off method, the developer used in the seventh step is used to resist the resist 54a.
(see FIGS. 3(b) and (C)), the n"a-3i:H layer 28'b and cFI formed on the first resist pattern at the same time as the resist 54a.
The To layer 40b is also tried to be removed by washing away, but although the resist itself dissolves, the n''a-3i:8 layer 28'b and the ITO layer 40b do not, so their fragments remain on the substrate. As a result, there was a problem in that the product lacked reliability.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a thin film transistor manufacturing method that can simplify the manufacturing process and manufacture highly reliable thin film transistors.

(Means for Solving the Problems) The present invention for solving the problems of the above conventional example provides a gate electrode, a gate insulating film, a semiconductor active layer, and a channel protective film made of a non-transparent conductive material on a substrate. In the method for manufacturing a thin film transistor, in which a source electrode and a drain electrode made of a transparent conductive material are formed on the stacked ohmic contact layer by dividing the ohmic contact layer with the channel protective film in between, the channel protective film is a film deposition step of depositing the ohmic contact layer and the transparent conductive material after forming a first resist pattern in a shape corresponding to the electrode; a resist deposition step of depositing an image reversal photoresist; and a resist deposition step of depositing an image reversal photoresist; a second resist pattern forming step of performing exposure and development using a photolithographic mask to form a second resist pattern on the upper part of the electrode and the drain electrode; an exposure step of exposing the back side of the substrate to light; and a step of exposing the second resist pattern to light using a photolithographic mask. a baking step of baking the image rehearsal photoresist on which a pattern has been formed, an exposure step of exposing the substrate surface to light, and a third step of developing the image reversal photoresist to remove the resist on the channel protective film. and an etching step of etching away the ohmic contact layer, the transparent conductive material, and the semiconductor active layer using the third resist pattern. .

(Function) According to the present invention, after forming a channel protective film pattern of a thin film transistor using a first resist pattern, an ohmic contact layer and a transparent conductive material are deposited, and an image reversal photoresist is further applied thereon. A film is deposited, and the outer edges of the drain and source electrodes are defined using a photolithographic mask, and exposed and developed so that a second resist pattern is formed above the channel protective film pattern. A second resist pattern is formed, backside exposure is performed by self-alignment using the shape of the gate electrode as a mask, the edges of the image reversal photoresist are formed, and the entire surface of the image reversal photoresist is exposed from the surface of the substrate.
When development is performed, the resist on the upper part of the channel protective film is dissolved and a third resist pattern is formed, and the transparent conductive material, the ohmic contact layer, and the semiconductor active layer can be etched using the resist pattern in the box 3. A thin film transistor manufacturing method that utilizes the characteristics of reversal photoresist (if the exposed area is baked, it will not dissolve in the etching solution, but if the unexposed area is baked and then exposed to become the exposed area, it will dissolve in the etching solution). Therefore, in the step after forming the channel protective film, a thin film transistor can be manufactured by simply depositing the image reversal photoresist once, thereby simplifying the manufacturing process.

(Example) An example of the present invention will be described with reference to the drawings.

The thin film transistor according to this embodiment is used as a switching element for an image sensor or a liquid crystal display (LCD).

The structure of the thin film transistor according to this embodiment is the same as the conventional structure shown in the cross-sectional explanatory diagram of FIG. Therefore, the reference numerals in FIG. 4 will be used for each component of the thin film transistor described below.

The method for manufacturing the thin film transistor of this embodiment will be explained using FIGS. 1(a) to 1(j), which are cross-sectional explanatory views of the thin film transistor showing the manufacturing process.

First, as a first step, a chromium (C'') layer for the gate electrode 25 of the thin film transistor is deposited to a thickness of about 750 mm on the inspected and cleaned substrate 21, such as glass, by DC sputtering.

Next, as a second step, the Cr is patterned by a photolithography process and an etching process using a mixed solution of cerium ammonium nitrate, perchloric acid, and water to form a pattern for the gate electrode 25 of the thin film transistor. .

As a third step, a gate insulating film 26 of a thin film transistor is formed on the Cr pattern, a semiconductor active layer 27 is formed thereon,
Further, in order to form a channel protective film 29 thereon, S
iNx1 layer 26' with a thickness of about 3000A, a-8i
: Plasma CVD (P-CVD) is performed on the H layer 27' to a thickness of about 1000A and the SiNx 2 layer 29' to a thickness of about 2000A without breaking the vacuum! , : more deposited (see Figure 1(a)). Continuous deposition of films after breaking the vacuum can prevent contamination of each interface and stabilize the properties of the film.

The insulating layer (SiNx1 layer 26') of the gate insulating film 26 is made of P.
-The conditions for forming by CVD are that the substrate temperature is 300 to 400.
℃, and the gas pressure of SiH and NH is 0. 1-1.
At 0 Torr, SiH, gas flow rate is 10 to 50 SCCI
11, the gas flow rate of NH3 is 100 to 300 sec
The RF power is 50 to 200W.

The conditions for forming the a-3i:H layer 27' of the semiconductor active layer 27 by PCVD are that the substrate temperature is 200 to 300°C, and the Si
H, gas pressure is 0. At 1~1°QTorr, S i
H, gas flow rate is 100-300scCIIl, RF
The power is 50-200W.

The conditions for forming the insulating layer (SiNx2 layer 29') of the channel protective film 29 by P-CVD are that the substrate temperature is 200 to 30°C.
At 0°C, the gas pressure of S i H, and NH3 is 0. 1~
1. At 0 Torr, SiH, gas flow rate is 10 to 50 seconds
ccIIl, NH3 gas flow rate is 100 to 300 s
ec+n, and the RF power is 50 to 200W.

Next, as a fourth step, a positive resist (first resist) 51 is applied on the gate insulating film 26 in order to form a pattern of the channel protective film 29 in a shape corresponding to the gate electrode 25. , and from the back side of the board 21,
- Back side exposure is performed by self-alignment using the shape pattern of the top electrode 25 as a mask (FIG. 1(b))
reference).

As a result, it is divided into an exposed portion 51a that has been exposed and an unexposed portion 51b that has not been exposed.

Then, as a fifth step, the exposed portion 51a exposed to light is dissolved using a developer, and the unexposed portion 51a above the channel protective film 29 is dissolved. A first resist pattern is formed in which the resist of b remains, and a 5iNx2 layer 2 is formed using a mixed solution of HF, NH, and F according to the resist pattern of section 1.
9' is etched and the resist is removed. As a result, a pattern of the channel protective film 29 is formed (first
(See figure (c)).

As a sixth step, a BHF process is further performed, and an n0a-3t:H layer 28' is formed as an ohmic contact layer 28 by P-CV using a mixed gas of 5iHj and PH.
A film is deposited to a thickness of about 100 OA by D. Next, BH
After performing the F treatment, an ITO layer 40 that will become the drain electrode 41 and source electrode 42 of the thin film transistor is deposited to a thickness of about 600A by DC magnetron sputtering (
(See Figure 1(d)). At this time, alkaline cleaning is performed before each film deposition.

The conditions for forming the ITO layer 40 by DC sputtering are the substrate temperature or room temperature, and the Ar and O2 gas pressures of 1. 5x
At 10-3 Torr, A "gas flow rate is 100 to 150
secm, 0. When the gas flow rate is 1 to 2 sc, the DC power is 200 to 400 W.

Next, as a seventh step, an image reversal photoresist (second resist) 56 is applied on the 170 layer 40. The characteristic of the image reversal photoresist 56 is that it does not dissolve in the etching solution when the exposed portion is baked, but it dissolves in the etching solution when the unexposed portion is baked and then exposed to become the exposed portion. In other words, even after baking, the unexposed areas do not lose their positive resist properties. As an image reversal photoresist, for example, AZ-5200 manufactured by Hoechst Co., Ltd. is famous.

As an eighth step, a second resist pattern 56a is formed by exposure and development using a photolithographic mask to define the outer edge shapes of the drain electrode 41 and source electrode 42 of the thin film transistor (see FIG. 1(e)). reference).

As a ninth step, the gate electrode 25 is
Back side exposure is performed by self-alignment using the shape pattern as a mask (see FIG. 1(f)). By backside exposure, it is divided into an exposed portion 56b and an unexposed portion 56c on the channel protective film 29, which is not exposed to light.

As a tenth step, the resist pattern 56a of the image reversal photoresist 56 is baked (reversal baking). As a result, the exposed portion 56b of the image reversal photoresist 56 becomes insoluble in the developer.

As an eleventh step, the entire surface of the substrate 21 is exposed from the front side (see FIG. 1(g)). As a result, during backside exposure, the unexposed portion 56C that was not exposed to light is exposed and turns into an exposed portion 56d. Although the exposed area 56d has been baked, it has not lost its positive resist properties and will be dissolved in the developer. In addition, the exposed portion 56
b is also exposed again to become an exposed portion 56b'. but,
The exposed portion 56b' is insoluble in the developer as described above.

As a twelfth step, development is performed with a developer to dissolve the exposed portion 56d on the channel protective film 29, and the exposed portion 56d is dissolved.
A third resist button consisting of b' is formed (see FIG. 1(h)).

As a thirteenth step, the ITO layer 40 is etched using a hydrochloric acid solution according to the third resist pattern. As a result, the ITO layer 4 above the channel protective film 29
0, the ITO layer 40 at the outer edge portions of the drain electrode 41 and source electrode 42 is etched to form a pattern of the drain electrode 41 and source electrode 42 portions.

As a fourteenth step, the n''a-3i:H layer 28' is similarly coated with hydrofluoric acid (HF) according to the third resist pattern.
Etching is performed using a mixed solution of and nitric acid (HNO,). As a result, n"a-3i on the upper part of the channel protection film 29
:H layer 28' and the n''aSi:H layer 28' at the outer edge of the ohmic contact layer 28 are etched to form a layer 28a connected to the drain electrode 41 of the ohmic contact layer 28 and a layer 28b connected to the source electrode 42 of the ohmic contact layer 28. At the same time, the a-5iH layer 27' is also etched to form the pattern of the semiconductor active layer 27 (see FIG. 1(i)).

As a fifteenth step, the drain electrode 41 and the sos electrode 42 are
The resist 56b' remaining on the ITO layer is removed (see FIG. 1(j)).

In this way, a thin film transistor as a switching element for an image sensor or a liquid crystal display (LCD) is manufactured.

According to this embodiment, after forming the pattern of the channel protection film 29 of the thin film transistor using the first resist batten, the n"a-3
i: The H layer 28' and the ITO layer 40, which is a transparent conductive material, are deposited, and an image reversal photoresist 56 is deposited thereon, and the outer edge portions of the drain electrode 41 and the source electrode 42 are formed using a photolithographic mask. A second resist pattern is formed by exposure and development so that a second resist pattern is formed on top of the channel protective film 29, using the shape of the gate electrode 25 as a mask. When back exposure is performed by self-alignment, the image reversal photoresist 56 is baked, and the image reversal photoresist 56 is exposed from the surface of the substrate 21 over the entire surface and developed, the resist 56d on the upper part of the channel protective film 29 is removed. A third resist baton consisting of the exposed portion 56b' is melted, and
The ITO layer 40,n is formed by the third resist pattern.
Since the thin film transistor manufacturing method utilizes the characteristics of an image reversal photoresist that allows each layer of the "a-Si:H layer 28' and the a-8t:H layer 27' to be etched at the same time," after forming the channel protective film 29, In the process, thin film transistors can be manufactured by simply depositing the image reversal photoresist 56 once, which simplifies the manufacturing process and reduces manufacturing costs. ,
Compared to the lift-off method, this method does not leave debris such as ITO on the substrate, and has the effect of manufacturing highly reliable thin film transistors.

In this embodiment, ITO (indium tin oxide) is used as the transparent conductive material, but it is also possible to use silicide instead of ITO. Silicide is a film of chromium (Cr) deposited on the n-type a-5f:H layer 8',
When r is selectively etched and Cr is removed, n”a-
8i: A thin layer (Cr-5i) is formed on the H layer 8'.Tantalum (Ta) or molybdenum (Mo) is used instead of the above Cr0, and Ta or Mo is selectively etched to form Ta. -8i or Mo-3i silicide can also be used.The 170 layer has higher wiring resistance than Cr, so it is necessary to make the film thicker.If you want to make the film thinner, use silicide. It is valid.

(Effects of the Invention) According to the present invention, after forming a pattern of a channel protective film of a thin film transistor using a first resist pattern, an ohmic contact layer and a transparent conductive material are deposited, and an image reversal photo is further deposited thereon. A resist film is deposited, and the outer edges of the drain electrode and source electrode are defined using a photolithographic mask, and exposed and developed to form a shape in which a second resist pattern is formed above the channel protective film pattern. to form a second resist pattern, perform backside exposure by self-alignment using the shape of the gate electrode as a mask, apply the image reversal photoresist, and then fully expose the image reversal photoresist from the surface of the substrate.
When development is performed, the resist on the upper part of the channel protective film is dissolved and a third resist pattern is formed, and the transparent conductive material, the ohmic contact layer, and the semiconductor active layer can be etched using the resist pattern in the box 3. A thin film transistor manufacturing method that utilizes the characteristics of reversal photoresist (if the exposed area is baked, it will not dissolve in the etching solution, but if the unexposed area is baked and then exposed to become the exposed area, it will dissolve in the etching solution). Therefore, in the process after forming the channel protective film, thin film transistors can be manufactured by simply depositing the image rehearsal photoresist once, which simplifies the manufacturing process and reduces manufacturing costs. It has the effect of reducing the amount of oxidation, and also has the effect of manufacturing a thin film transistor with higher reliability than the lift-off method.

[Brief explanation of drawings]

Figures 1 (Jl) to (j) are cross-sectional explanatory diagrams illustrating the manufacturing process of a thin film transistor part according to an embodiment of the present invention, and Figures 2 (a) to (i) are sectional views illustrating the manufacturing process of a conventional thin film transistor part. Cross-sectional explanatory diagram to explain, FIG. 3(a) ~
(e) is a cross-sectional explanatory view illustrating the manufacturing process of a thin film transistor portion by a conventional left-off method, and FIG. 4 is a cross-sectional explanatory view of the conventional thin film transistor portion. 21...Substrate 25...Gate electrode 26...Gate insulating film 27...Semiconductor active layer 28...Ohmic contact layer 29...・
...Channel protective film 40...170 layer 41...Drain electrode 42...Source electrode 51.52.53.54.55...Resist 5
6...Image reversal photoresist 1st
Figure 1 Figure 2 Figure 1 Figure 2 Figure 2 Figure 3 Section

Claims (1)

[Claims] A gate electrode made of a non-transparent conductive material, a gate insulating film, a semiconductor active layer, and a channel protective film are laminated on a substrate, and an ohmic contact layer is divided and laminated with the channel protective film in between. In the method for manufacturing a thin film transistor in which a source electrode and a drain electrode made of a transparent conductive material are formed on the ohmic contact layer, after forming the channel protective film in a shape corresponding to the gate electrode using a first resist pattern. a film deposition step of depositing the ohmic contact layer and the transparent conductive material; a resist deposition step of depositing an image reversal photoresist; and forming a second resist pattern on the source electrode and the drain electrode. a second resist pattern forming step in which exposure and development is performed using a photolithographic mask; an exposure step in which exposure is performed from the back side of the substrate; and a baking step in which the image reversal photoresist on which the second resist pattern is formed is baked. an exposure step of exposing the substrate surface to light; a third resist pattern forming step of developing the image reversal photoresist and removing the resist on the channel protective film to form a third resist pattern; A method for manufacturing a thin film transistor, comprising an etching step of etching away the ohmic contact layer, the transparent conductive material, and the semiconductor active layer using a third resist pattern.