JPH06118928A - Information processing device capable of multicolor display - Google Patents

Abstract

(57) [Summary] [Purpose] In an information processing device using a battery,
Ensure a longer operating time. A display device 23 in which the number of colors is increased by increasing the screen scanning frequency, a frequency control circuit 21 for setting the operating frequency of the display control circuit 6, and a color number control circuit 22 for setting the number of colors of the display device 23. Is provided so that a mode in which the number of colors is small and operates at a low frequency and a mode in which a number of colors is large and operates at a high frequency can be selected and used. [Effect] The operation mode can be selected according to the user's purpose. In the mode operating at a low frequency, the power consumption is reduced and the operation time when the battery is used is long.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a workstation,
The present invention relates to an information processing apparatus including a display device such as a personal computer, and more particularly to an information processing apparatus including a display device capable of multicolor display and capable of selecting the number of display colors and operating frequency.

[0002]

2. Description of the Related Art In recent years, information processing apparatuses such as workstations and personal computers have been remarkably miniaturized. As a result, usage patterns are diversifying. That is, in addition to the conventional desktop type, a laptop type capable of saving the installation area and a notebook type which is small and has excellent portability can be roughly classified into three types. Among them, the notebook type information processing device is desired to be light in weight and operable for a long time in order to realize portability. Therefore, it is an important issue to efficiently use the electric power that can charge the built-in battery. Various inventions have been devised to solve this problem. One of them is JP-A-3-27.
"Personal computer" disclosed in Japanese Patent Publication No. 420
Is.

This computer can stop the power supply from the power supply circuit to the display device when the input device such as the keyboard is not operated for a predetermined time. That is, when there is no key input for a certain period of time, it is determined that the user is not in the idle state, and the power of the display device that consumes relatively large power is turned off.
To prevent unnecessary power consumption.

As described above, by detecting the idle state and preventing excessive power consumption, it is possible to lengthen the operable time when the battery is used.

[0005]

As described above, in the method of utilizing the idle state, if the data is input or the document is created for a long time, the frequency of the idle state decreases, so that the power consumption is reduced. The operation will not be executed. Therefore, there may be a case where a sufficient operable time cannot be secured. Therefore, it is an important issue to secure a longer operable time even when the user is always using it.

An object of the present invention is to provide an information processing apparatus capable of multicolor display by selecting the number of display colors and operating frequency in a display apparatus capable of multicolor display.

Another object of the present invention is to provide an information processing apparatus capable of reducing power consumption in use and ensuring a long operable time when a battery is used.

[0008]

In order to solve the above-mentioned problems, the present invention adopts a display adopting a technique capable of increasing the number of colors to be generated while ensuring the image quality by increasing the scanning frequency of the display screen. In an information processing apparatus including the apparatus, the number of colors produced and the scanning frequency can be changed.

That is, according to one aspect of the present invention, in an information processing apparatus capable of multicolor display, a CPU (central processing unit), a display memory for storing display information, and the display information are determined. The display device for displaying multi-colors among the number of colors and the transfer of information between the CPU and the display memory are controlled, and the display information stored in the display memory is periodically read out to the display device. A display control circuit for sending, a first mode in which the number of colors is small and operates at a low frequency, and a second mode in which a number of colors is large and operates at a high frequency, at least two modes are selected. And a clock signal generating unit for generating a plurality of clock signals having different frequencies, and receives the selection information and outputs from the clock signal generating unit. Among the plurality of clock signals,
The selection information indicates a clock selection circuit which selects a clock signal having a frequency corresponding to the mode indicated by the selection information and outputs it to at least the display control circuit, and the number of colors to be displayed on the display device upon receiving the selection information. An information processing apparatus, comprising: a color number control unit for controlling a number corresponding to a mode; and the CPU having a unit for instructing a mode selecting unit which mode to select. To be done.

The selecting circuit is provided with a switching circuit having a hazard preventing function, which switches the clock signal currently selected and the newly selected clock signal in synchronization when the clock signal is selected. be able to.

The information processing apparatus of the present invention may further include a battery for supplying electric power and a power remaining amount detecting circuit for detecting the power remaining amount of the battery. In this case, the CPU monitors the detection result of the power remaining amount detection circuit, and when the power remaining amount of the battery becomes lower than the preset power remaining amount value, the CPU issues an instruction to select the first mode. The mode can be automatically changed by performing the selection on the selection unit.

An input device that allows a user to input an instruction can be further provided. In this case, the CP
The U can accept an instruction from the input device and give a mode selection instruction.

Further, the above CPU displays on the screen of the display device,
It is possible to further include means for generating a control window, displaying a mode selection area on the window, and accepting a user's selection operation.

The mode selection section has a storage section for storing the selection information, and stores selection information indicating which mode is selected in the storage section in response to a selection instruction from the CPU. can do.

Further, in the present invention, the above display device is
A display unit capable of displaying N colors and N displayable by the display unit by receiving display information including up to (N + M) colors
A data conversion circuit for outputting display information of a corresponding color from colors and M combinations of two colors selected from N colors for displaying an intermediate color, which are alternately displayed at a specific timing. And a configuration including

Further, the display device replaces the input display information up to (N + M) colors with one of the N colors if the input display information is an arbitrary intermediate color of the M colors. In addition, it is possible to further include N colorization means for generating display information in which the maximum number of colors is N.

The maximum color number selection means includes display information up to (N + M) colors output from the data conversion circuit,
Any of the display information up to N colors output from the N colorization unit may be selected according to the mode selection information from the mode selection unit. The maximum color number selecting means can be provided in the display device or the display control circuit, for example.

Further, the display memory can be composed of a first memory and a second memory. In this case, the first memory has a memory capacity capable of storing at least the display information of the number of colors required for display in the first mode, and the second memory is used together with the first memory. As a result, in the second mode, it is possible to have a configuration having a memory capacity capable of storing at least display information of the number of colors that is necessary for display.

Furthermore, the present invention can further comprise power consumption control means for controlling the power consumption of the second memory. The power consumption control means controls the power supply to the second memory such that the power supply is stopped in the first mode and the power is supplied in the second mode.

A memory operation control means for controlling the operation of the second memory can be further provided. The memory operation control means controls the address information and the control information so as to put the second memory in the standby state in the first mode.

Further, according to the present invention, in the display device for displaying the display information in multiple colors within the determined number of colors, N
A display unit capable of displaying colors and display information including colors up to (N + M) colors are received, and N colors that can be displayed by the display unit are alternately displayed at a specific timing to display an intermediate color. A data conversion circuit that outputs display information of a corresponding color from M combinations of two colors selected from N colors and input display information of up to (N + M) colors. If the information is an arbitrary intermediate color of the M colors, it is replaced with one of the N colors to generate display information in which the maximum number of colors is N, and the data conversion circuit. An instruction to select any one of the display information up to (N + M) colors output from the display unit and the display information up to N colors output from the N colorization unit according to the selection information input from the rotating unit. There is provided a display device having means for outputting

[0022]

According to the present invention, the mode selection unit selects one of at least two modes, a mode in which the number of colors is small but operates at a low frequency and a mode in which a number of colors is large and operates at a high frequency. You can choose. The clock selection circuit receives the selection information, and among the plurality of clock signals output from the clock signal generation means,
A clock signal having a frequency corresponding to the mode indicated by the selection information is selected and output to at least the display control circuit.
Also, the maximum color number selection means selects the maximum color number of the display device according to the mode indicated by the selection information.

The frequency can be lowered to a level at which the image quality does not deteriorate by reducing the number of colors to be generated by the maximum number of colors to be selected. In this case, the number of colors is, for example,
Regarding the input video information up to (N + M) colors, if the input video information is an arbitrary intermediate color of M colors, it can be replaced with one of the above N colors to obtain the maximum number of colors N. .

The power consumption control means controls the power supply to the second memory such that the power supply is stopped in the first mode and the power is supplied in the second mode.
Further, the memory operation control means, in the first mode,
The address information and the control information are controlled so that the second memory is in the standby state. As a result, when used with a small number of colors, only the first memory required for the number of colors operates, and the unnecessary second memory can be in the power supply stop state or the standby state.

When the frequency can be lowered in this way, the display control circuit can be operated at a low frequency. This reduces not only the display control circuit but also the power consumption of the display memory and the display device.

Further, since the display memory unnecessary for display is put in the power supply stop state or the standby state, the power can be reduced accordingly.

In such an operation mode, although the number of colors that can be used by the user is reduced, the power consumption of the circuit section related to the display control is reduced, and the operable time when the battery is used is secured for a long time. it can.

Of course, it can also be used in an operation mode in which the number of colors is large.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of an information processing apparatus to which the present invention is applied.

In FIG. 1, an information processing apparatus according to this embodiment includes a central processing unit (hereinafter abbreviated as CPU) 1,
Address bus 2, data bus 3, random access memory (hereinafter abbreviated as RAM) 4, read-only memory for storing programs (hereinafter abbreviated as ROM)
5, a display memory 8 for storing display information, and an LCD (Liquid Crystal) capable of multicolor display within a predetermined number of colors.
A display device 23 such as a display) and a clock generation unit 7a that functions as a means for generating a clock of a different frequency.
A mode selection section 9 for selecting an operation mode, a display control circuit 6 for reading the display information stored in the display memory 8 and displaying it on the display device 23, and receiving the selection information, the selection information indicates A selection circuit 20 for selecting a clock signal of a frequency corresponding to the mode, a keyboard 11 for inputting data, instructions, etc., and a keyboard controller 10 for controlling the operation of the keyboard 11, an information processing unit for executing information processing. Have as.

In the present embodiment, the display memory 8 is V
RAM (Video Random Access Memory) is used.
Of course, the present invention is not limited to this.

The clock generator 7a includes oscillators 7 and 1
Have 9. These generate clocks of different frequencies.

The mode selecting section 9 selects one of at least two modes, namely, a mode in which the number of colors is small but operates at a low frequency, and a mode in which a number of colors is large and operates at a high frequency, and which mode is selected. It functions as a mode selection unit that outputs selection information to be selected.

The display control circuit 6 includes the CPU 1 and the V
The transfer of information in the RAM 8 is controlled and the V
The display information stored in the RAM 8 is read out periodically to generate a video signal. Then, this video signal is displayed on the display device 23.
Send to.

The selection circuit 20 receives the above selection information and
It functions as a means for selecting a clock signal having a frequency corresponding to the mode indicated by the selection information from the clock signals output from the oscillator 7 and the oscillator 19 and outputting it to at least the display control circuit 6.

Further, the information processing apparatus of the present embodiment generates, as a power supply section, an external DC input terminal 13 for inputting DC (direct current) power, a battery 14, and a power supply voltage required by the information processing section. A power supply circuit 12 for supplying power, a power supply line 18 for supplying power from the power supply circuit 12 to the display device 23, and a power supply line 17 for supplying power to a circuit unit other than the display device 23. . Further, the power supply circuit 12 has an external DC input terminal 13 which is an external D
When it is connected to the C power source, it has a function of supplying power with the power of an external power source and charging the battery 14. Electric power from the external DC input terminal 13 is sent to the power supply circuit 12 via the power supply line 15. Further, the power from the built-in battery 14 is sent to the power supply circuit 12 via the power supply line 16.

In the present embodiment, when the battery 14 is used as a power source without connecting an external DC power source, as another means for ensuring a longer operable time, the non-use state A power saving function is added. This function is used when there is no external operation for a certain period of time.
The CPU 1 uses the address bus 2 and the data bus 3 to
A command is sent to the power supply circuit 12 to stop the power supply to the display device 23. The function of stopping only the power supply to the display device 23 may be omitted.

The mode selection unit 9 has a frequency control circuit 21 for designating a clock to be selected to the selection circuit 20.
And a color number control circuit 22 for designating a color number to be selected for the display device 23. This mode selector 9
Selects either a low power mode using a low frequency clock or a normal mode with a high frequency. This selection instruction is given by the CPU 1 in this embodiment.

In FIG. 1, reference numeral 24 is a signal line for the color number control circuit 22 to transfer information to the display device 23.
Reference numeral 25 is a signal line for transferring information from the display control circuit 6 to the display device 23.

The selection circuit 20 operates according to the selection information stored in the frequency control circuit 21. The frequency control circuit 21 receives the C signal via the address bus 2 and the data bus 3.
Selection information is stored by the write operation of PU1.
In short, the frequency of the clock supplied from the CPU 1 to the display control circuit 6 can be set.

The color number control circuit 22 is controlled by the CPU 1.
Selection information is set via the address bus 2 and the data bus 3. The color formation number control circuit 22 sends this selection information to the display device 23 through the signal line 24, and specifies the color formation number of either 4096 colors or 512 colors. When 512 colors are specified, the display device 23 displays 60 Hz.
It is possible to display only 512 colors whose image quality does not deteriorate at the scanning frequency of, and it is not possible to display a larger number of colors. In other words, when the color information of 3584 colors is to be displayed, the color information is converted into arbitrary color information of 512 colors and displayed. In short, the CPU 1 is the display device 2
It is possible to set the color development number of 3.

The display device 23 employs a technique capable of increasing the number of colors while ensuring image quality by increasing the scanning frequency of the display screen. That is, FRC
(Frame Rate Control) method is used. That is, the display device 23 is capable of displaying N colors, displays M intermediate colors in a method of alternately displaying any two of N colors at a specific timing, and displays the maximum number of colors (N + M). Display information can be displayed. As will be described later, a data conversion circuit therefor, a means for inputting display information capable of displaying up to (N + M) colors, and a means for selecting whether the maximum number of colors is N or (N + M) colors. And a display unit that displays the display information.

Specifically, in this embodiment, the display device 23
When the scanning frequency of the display screen is 80 Hz, a maximum of 4096 colors can be displayed, and when it is used at 60 Hz, a maximum of 512 colors can be displayed. This limitation on the number of colors is premised on ensuring an image quality that the user is satisfied with. Of course, it is possible to display 4096 colors at 60 Hz, but in that case, flickering occurs and the image quality deteriorates.

In order to cope with two kinds of scanning frequencies, the oscillator 7 outputs a clock having a frequency corresponding to a scanning frequency of 80 Hz, and the oscillator 19 outputs a clock having a frequency corresponding to a scanning frequency of 60 Hz. Things are used. These clocks are used by the selection circuit 20.
, Either one is selected and supplied to the display control circuit 6.

Next, an outline of the operation of the information processing apparatus configured as described above will be described.

The CPU 1 can read / write information from / to each section of the information processing apparatus via the address bus 2 and the data bus 3. When the power is turned on, the CPU 1
The program stored in the ROM 5 is read. Normally, the initialization of each circuit unit in the apparatus is started according to the program. After that, various application programs stored in the RAM 4, such as document creation and
Read and execute editing programs, spreadsheet programs, etc. Here, the CPU 1 uses, for example, the keyboard 11
In response to the input of the mode selection instruction from the above, the selection instruction as described above is issued to the mode selection unit 9 accordingly. Note that this selection can be made at startup. Of course, the instruction may be accepted and the mode may be selected at any time thereafter.

The program being executed is the display device 2
In the case of processing for displaying information on 3, the CPU 1
Display control circuit 6 via address bus 2 and data bus 3
Write the display information to. The display control circuit 6 stores the received display information in the VRAM 8. Further, the display control circuit 6 periodically adjusts the V voltage according to the clock supplied by the oscillator 7 or 19 selected by the selection circuit 20.
The display information stored in the RAM 8 is read and the display device 23
Transfer to. As a result, the display device 23 displays the VRAM 8
The display information stored in can be displayed.

Here, the mode is set by the CPU 1 setting predetermined information in the frequency control circuit 21 and the color formation number control circuit 22. That is, the scanning frequency of the display screen is set to either the normal mode in which 4096 colors can be displayed at 80 Hz or the low power mode in which 512 colors are displayed at 60 Hz. When a mode different from the current one is set, the mode is switched to.
For example, the normal mode is selected when an external DC power source is connected to the external DC input terminal 13 to supply power, and the low power mode is selected when the battery 14 is supplying power. You can Such selection can be specified by the user by starting a selection program.

A flow chart showing the procedure of this selection program is shown in FIG. According to the procedure shown in FIG.
1 determines whether to set to the low power mode (step 401). If the instruction is not the low power mode, selection information for selecting 4096 colors is set in the color number control circuit 22 (step 402). Then, the selection information for selecting the oscillator 7 is set in the frequency control circuit 21 (step 403). On the other hand, if the instruction is for the low power mode, selection information for selecting 512 colors is set in the color number control circuit 22 (step 404). Then, the selection information for selecting the oscillator 19 is set in the frequency control circuit 21 (step 405).

In the low power mode, since the operating frequency of the display control circuit 6 is low, it is possible to suppress not only the power consumption of the display control circuit 6 but also the power consumption of the VRAM 8 and the display device 23 that operate in a dependent manner. As a result, the power load on the battery 14 is reduced, and a relatively long operable time can be secured. On the other hand, in the normal power mode, display in many colors is possible.

Information input by the user using the keyboard 11 is transferred to the keyboard controller 10. The keyboard controller 10 sends the input information to the CP
It is converted into information in a format that U1 can read. According to the program stored in the RAM 4, the CPU 1 receives the input information from the keyboard controller 10 via the address bus 2 and the data bus 3 and executes a predetermined process.

The power of each circuit section described above is supplied from the power supply circuit 12. The power supply circuit 12 inputs power from an external DC power supply connected to the external DC input terminal 13 and a built-in battery 14. The power input by the power supply circuit 12 is supplied to the display device 23 via the power supply line 18, and to the circuit parts other than the display device 23 via the power supply line 17.

Next, the power saving function when not in use, which is added to the information processing apparatus of this embodiment, will be described with reference to FIG. FIG. 3 is a flowchart showing the operation of the power saving function added in this embodiment. This power saving function, when there is no key input for a certain period of time, determines that the user is in an idle state not in use and turns off the power of the display device 23 that consumes a relatively large amount of power to prevent wasteful power consumption. To do. The details of the operation are shown below. It should be noted that this function can be added to other embodiments described later.

When the power of the apparatus is turned on, the system is started according to the programs stored in the ROM 5 and the RAM 4 (step 301). First, the count value stored in a specific area of the RAM 4 is set to 0 (step 302). Next, the keyboard controller 1
From the information read from 0, it is determined whether or not there is a key input (step 303). If there is, a predetermined process is executed according to the program, and then the count value is set to 0 to judge the presence / absence of key input (steps 304 and 302). When there is no key input, the count value is incremented by 1 and it is determined whether or not a predetermined value n has been reached (steps 305, 306). If it has not reached n, the process returns to step 303 to determine whether or not there is a key input. When it reaches n, the information is transferred to the power supply circuit 12 and the power supplied to the display device 23 is stopped (step 307). After that, when there is a key input, the display device 2
The power supply to No. 3 is started and a predetermined process is executed (steps 308 and 309).

As described above, by detecting the idle state and preventing extra power consumption, it is possible to lengthen the operable time when the battery is used.

Next, details of the frequency control circuit 21, the color number control circuit 22 and the display device 23 will be described.

FIG. 5 is a block diagram of the color number control circuit 22. In the figure, circuit blocks and signal lines having the same functions as those of the components shown in FIG. 1 are designated by the same reference numerals. In the figure, 30 is an address line of the address bus 2 and 3
1 is a valid signal line indicating that the address line 30 is valid, 32 is a decoder circuit, 33 is a NAND circuit, and 34 is a latch circuit which holds a signal of d (data) input at a rising edge of a ck (clock) input. is there. The address line 30 has 20 signal lines if the address space that the CPU 1 can handle is 1 MB.

A time chart showing the operation of the color number control circuit 22 is shown in FIG. The decoder circuit 32 outputs "H" when the address line 30 is in the state indicating the address of the latch circuit 34, and outputs "L" in other states. The valid signal line 31 is in the “H” state when the address line 30 is valid, and is in the “L” state when the address line 30 is invalid. Therefore, NA
The ND circuit 33 is normally in the "H" state, but when the access to the latch circuit 34 occurs, it becomes the "L" state. Then, the latch circuit 34 takes in the information of the data bus 3 at the rising edge of the output signal of the NAND circuit 33 and outputs it to the signal line 24. As a result, the latch circuit 34 can hold the state of the least significant bit of the data bus 3. If the signal line 24 shows 512 colors in the “H” state and 4096 colors in the “L” state, when the CPU 1 writes 1 to the address assigned to the latch circuit 34, 512 colors and 0 are obtained. You can set it to 4096 colors by writing.

The frequency control circuit 21 can be realized by the same configuration as that shown in FIG. However, the decoder circuit 32 needs to be changed so as to indicate the address assigned to the frequency control circuit 21. The writing to the circuit corresponding to the latch circuit 34 is set corresponding to the color number control circuit 22 such that when 1 is written, the low frequency is selected and when 0 is written, the high frequency is selected.

Next, the details of the display device 23 will be described below, taking a liquid crystal display as an example.

FIG. 6 is an internal block diagram of the display device 23. In the figure, circuit blocks and signal lines having the same functions as those of the components shown in FIG. 1 are designated by the same reference numerals.

The display device 23 used in this embodiment is an FRC (Frame Rate Control) for increasing the number of colors of the display device.
The circuit 44, the signal drive drivers 48 and 49 for fetching the display data for one line, the scan drive driver 50 for designating the line to be scanned, and the signal drive drivers 48 and 49 and the scan drive driver 50 to actually display an image. And a liquid crystal display section 51, and a liquid crystal display section 51.
A back light unit (not shown) that illuminates from the back side of, and a back light inverter 52 that drives this back light unit. In the figure, 40 is a signal line 25.
, 41 is a clock signal line for latching information of the display data line 40, 42 is a horizontal synchronizing signal, 43 is a vertical synchronizing signal, 45 is an FRC display signal line, 4
Reference numeral 6 is a horizontal clock for latching information on the FRC display signal line 45, and 47 is a vertical clock whose cycle is one display line.

The display data line 40 has 40 dots per dot.
It has a 12-bit information amount for displaying 96 colors. Normally, a color is represented by three components of red (R) green (G) and blue (B), so that each component of 4 bits constitutes 12-bit information. On the other hand, the FRC display signal line 45 is composed of 3 bits for each RGB component due to the limitation of the signal driving drivers 48 and 49. Therefore, the liquid crystal display unit 51
Basically displays 512 colors with 9 (= 3 × 3 × 3) bits. FRC is a technique for displaying 4096 colors on the liquid crystal display unit 51. Details of the FRC circuit 44 will be described later.

The liquid crystal display unit 51 has a horizontal direction (1120 ×
3) x resolution of 1120 x 780 dots in 780 pixels in the vertical direction, and 3 pixels of RGB form 1 dot.
The liquid crystal display unit 51 can display each pixel with three levels of luminance by driving the respective pixels with the potentials of three levels by the signal driving drivers 48 and 49. Based on this principle, 512 colors are displayed per dot.

The signal driving drivers 48 and 49 are arranged in the horizontal direction 1.
16 which is half of the line data (1120 x 3 bits)
It is configured to hold 80 bits, and when one line of data is collected, one line is simultaneously driven. Therefore, the signal driving drivers 48 and 49 are connected to the liquid crystal display section 51 by 1680 signal lines. This one
It is the scan drive driver 50 that instructs which line of the liquid crystal display unit 51 to display the data for a line.
The scan driving driver 50 is connected to the liquid crystal display unit 51 by 780 signal lines, and when scanning the first line, activates only the signal lines corresponding thereto. Sequentially, 78
By scanning up to the 0th line, an image is displayed on the liquid crystal display unit 51.

The horizontal clock line 46 transmits a clock signal for the signal driving drivers 48 and 49 to take in the data of the FRC display signal line 45. On the other hand, the vertical clock line 47 is used to notify the scan drive driver 50 of the fact that the data for the next one line is held in the signal drive drivers 48 and 49 by a clock signal. The scan drive driver 50 activates the signal line of the next line according to the clock signal. The clock signals on the horizontal clock line 46 and the vertical clock line 47 are
The C circuit 44 is generated from the clock signal line 41, the horizontal synchronizing signal 42, and the vertical synchronizing signal 43.

Next, details of the FRC circuit 44 will be described.

FIG. 7 is an internal block diagram of the FRC circuit 44. In the figure, circuit blocks and signal lines having the same functions as those of the components shown in FIG. 6 are designated by the same reference numerals.

The FRC circuit 44 shown in FIG. 7 includes a 12-bit latch circuit 60, R (red), G (green) and B.
FRC data generation circuit 62 provided corresponding to (blue), and a random signal generation circuit 64 that generates a switching signal for realizing FRC display without flicker, 9
It has a bit latch circuit 66, a frequency dividing circuit 67 for doubling the clock cycle, and a timing adjusting circuit 68 for adjusting the phase of the horizontal synchronizing signal 42. In the figure, 61
Is a display data line consisting of 12 signal lines, 63 is an FRC data line consisting of 9 signal lines, and 65 is a random signal line.

The latch circuit 60 takes in the information of the display data line 40 at the timing of the clock signal line 41 and outputs it to the display data line 61. The display data line 61 is 409
R3 to R0, G3 to G0, B for transmitting information of 6 colors
It is composed of a total of 12 signal lines for transmitting the respective signals of 3 to B0. Among them, the signal line for transmitting R3 to R0 is F
It is connected to the RC data generation circuit 62. Similarly, G3 ~
The signal line for transmitting G0 and the signal line for transmitting B3 to B0 are also connected to the corresponding FRC data generation circuit 62, respectively. Further, the signal line 24 and the random signal line 65 are connected as inputs to each FRC data generation circuit 62.

Based on these inputs, each FRC data generation circuit 62 sends the signals FR2 to FR2 to the FRC data line 63.
Generate FR0, FG2-FG0 and FB2-FB0. FRC display is a method of displaying an intermediate gradation level by switching and displaying two different gradation levels for each screen scanning. For example, the R FRC data generation circuit 62 for R can generate FR2 to FR0 capable of displaying 16 levels of gradation by performing the processing required for FRC display. The information on the FRC data line 63 composed of FR2 to FR0, FG2 to FG0 and FB2 to FB0 includes the amount of information capable of displaying 4096 colors in 9 bits. Details of the FRC data generation circuit 62 will be described later.
The information on the FRC data line 63 is output to the FRC display signal line 45 with the timing of each signal aligned by the latch circuit 66.

The frequency dividing circuit 67 divides the frequency of the clock signal on the clock signal line 41 by a factor of 2 and outputs it to the horizontal clock line 46. The signal driving driver 48 in FIG. 6 fetches the information of the FRC display signal line 45 at the rising edge of the clock and the signal driving driver 49 at the falling edge. In short, the information of the FRC display signal line 45 is alternately fetched in units of one dot. The timing adjustment circuit 68 is F
In order to match the phase with the RC display signal line 45, the signal of the horizontal synchronizing signal 42 is delayed by two clock cycles of the clock signal line 41 and output to the vertical clock line 47.

The random signal generation circuit 64 generates the random signal line 65. The above FRC display causes flickering when the response speed of the display is fast. Therefore, in order to reduce this flicker, it is necessary to devise a gradation switching method and increase the screen scanning frequency. The former is a system in which not only two gradation levels are switched in one screen scanning unit, but also one line display unit is switched and line and gradation level allocation is switched in one screen scanning unit. The random signal generation circuit 64 performs this control, and if the even line is displayed at a high gradation level and the odd line is displayed at a low gradation level during one screen scanning, the random signal generation circuit 64 When scanning the screen, the correspondence between lines and gradations is reversed. Specifically, when the random signal line 6 becomes "H" on an even line and "L" on an odd line during a screen scan, it becomes "L" on an even line and "H" at an odd line during the next screen scan. . On the other hand, it is also essential to increase the screen frequency, and when the signal line 24 specifies 512 colors, FRC display is not performed, so there is no flicker at a screen frequency of 60 Hz, but if 4096 colors are specified, FRC display is performed. Therefore, it is necessary to set the frequency to 80 Hz.

FIG. 8 is an internal block diagram of the FRC data generation circuit 62. In the figure, circuit blocks and signal lines having the same functions as those of the components shown in FIG. 7 are designated by the same reference numerals.

The FRC data generation circuit 62 shown in FIG.
It has a data conversion circuit 70 and a selection circuit 72. In the figure, 71 is an FRC display data line.

The data conversion circuit 70 is composed of, for example, a programmable logic array or the like. That is, it is configured by combining and connecting the logic circuit element groups so as to realize a truth table described later. Then, the information of the display data line 61 and the random signal line 65 is input to the data conversion circuit 70, and the FRC display data is output to the FRC display data line 71 according to the combination of the logic circuit element groups.

The selection circuit 72 selects one of R3 to R1 in the FRC display data line 71 and the display data line 61 according to the information of the signal line 24, and the FRC data line 6
Output to 3. In short, the display data line 61 is selected when the signal line 24 indicates the 512 color mode, and the FRC display data line 71 is selected when the 4096 color mode is selected. In this way, the selection circuit 72 can switch the mode of the number of colors.

Next, the function of the data conversion circuit 70 will be described with reference to FIG. FIG. 9 is a truth table of the data conversion circuit 70. The input is the display data line 61 and the random signal line 65, and the output is the FRC display data line 71. The truth table shown in the figure shows that in order to realize gradation display of 16 levels, gradation levels 14, 12, 10, 8, 6, 4,
2 and 1 are displayed using FRC. For example, the level 14 is displayed by switching "111" and "110" of the FRC display data line 71 according to the information of the random signal line 65. Therefore, the actual brightness level is an intermediate level between the brightness of "111" and "110". On the other hand, in the gradation levels other than these, in which the FRC is not used, it is not necessary to switch the display of the two luminance levels, and therefore the information of the random signal line 65 has no meaning. In the figure, it is indicated by "x".

In the above embodiment, the oscillators 7 and 9 are provided as means for generating a plurality of clock signals, but the means is not limited to this. For example, 1
The clock of the oscillator may be divided to generate a plurality of clock signals. This also applies to other embodiments described later.

As described above, according to this embodiment, 4
A 096 color mode and a 512 color mode can be selected. Further, when the 512-color mode is selected and used, the circuit unit related to display control operates at 60 Hz, so that it is possible to reduce power consumption and ensure a long operation time when the battery is used. However, the present invention is not limited to this example. For example, there are the following examples.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 10 is a block diagram of an information processing apparatus showing the second embodiment. In the figure, the same components and signals as those of the embodiment shown in FIG. 1 are designated by the same reference numerals, and duplicated description will be omitted.

In the figure, reference numeral 80 is a display control circuit capable of controlling the number of colors, 81 is a clock line for supplying a clock to the display control circuit 80, 82 is an address line of the VRAM 8, and 83 is V.
It is a data line of the RAM 8. In addition, the display device 23 is 40
It is fixed in 96-color mode. The display control circuit 80 receives information from the color number control circuit 22 through the signal line 24 and can select 4096 color mode or 512 color mode. In short, this example is different from the first embodiment in that the color development mode is switched not by the display device 23 but by the display control circuit 80. The other configurations and operations are the same as those in the first embodiment. Therefore, duplicate description will be omitted. Therefore, details of the display control circuit 80, which is the point, will be described below.

FIG. 11 is a block diagram of the display control circuit 80. In the figure, circuit blocks and signal lines having the same functions as the components shown in FIG. 10 are designated by the same reference numerals.

The display control circuit 80 shown in FIG. 11 has a display controller 93, a selection circuit 90, a data path controller 92, and a color number selection circuit 95. In addition,
In the figure, 91 is a display timing signal line, 94 is a display data line, and 96 is a timing signal line for controlling the color number selection circuit 95.

The display controller 93 generates address information for sequentially reading information from the VRAM 8 for display scanning, and displays the display timing information indicating that the address information is in a valid period to the display timing signal line 91. Output. Further, it also generates a timing signal to be applied to the data path controller 92 and the color number selection circuit 95.

The selection circuit 90 uses the display timing signal line 9
According to the information of 1, the address information output by the display controller 93 is selected during the valid period, and the address information of the address bus 2 is selected during the period other than the valid period. Therefore, the CPU 1 shown in FIG.
You can access 8.

The data path controller 92 controls the flow of information read from the VRAM 8 via the data line 83. In the data path controller 92, the CP
The information accessed by U1 is distributed to the data bus 3, and the display information read at the address generated by the display controller 93 is distributed to the display data line 94. 409 is sent to the color number selection circuit 95 via the display data line 94.
It is information of 6 colors.

The color number selection circuit 95 converts the information of 4096 colors and the information of 512 colors not displayed by FRC on the display device 23 according to the information of the signal line 24 and outputs the information to the display data line 25. That is, the color number selection circuit 95
Has a function as a maximum color number selection means for receiving the selection information from the color number control circuit 22 and selecting the maximum color number displayed on the display device 23 in accordance with the mode indicated by the selection information.

Next, details of the color number selection circuit 95 will be described.

FIG. 12 is a block diagram of the color number selection circuit 95. In the figure, circuit blocks and signal lines having the same functions as those of the components shown in FIG. 11 are designated by the same reference numerals.

The color number selection circuit 95 shown in FIG. 12 includes latch circuits 101 and 106 for latching information at the timing of the timing signal line 96, and FRC data removal circuit 1.
03 and a selection circuit 105. In the figure, 10
Reference numeral 2 is a 4096 color display data line, and 104 is a 512 color display data line.

The information latched by the latch circuit 101 is 4
It is sent to the FRC data removing circuit 103 via the 096 color display data line 102. The information of the FRC data removing circuit 103 is 12 bits, and this is distributed to the three FRC data removing circuits 103 by 4 bits.

The FRC data removing circuit 103 is, for example,
It consists of a programmable logic array. That is, it is configured by combining and connecting the logic circuit element groups so as to realize a truth table described later. Then, the FRC data removal circuit 103 sets the information displayed in the FRC on the display device 23 among the information of 16 gradations to F
Convert to appropriate information that is not RC-displayed. Therefore, 5
Although the information sent to the 12-color display data line 104 has a 4-bit structure, it actually becomes information of 8 gradations, and the output of the three FRC data removing circuits is combined to form 512-color display information. . For details of the FRC data removal circuit 103,
It will be described later.

The selection circuit 105 selects the display information of the 4096 color display data line 102 and the 512 color display data line 104 according to the signal line 24, and supplies it to the latch circuit 106. The latch circuit 106 latches this selected information and outputs it to the display data line 25. With such a configuration, the display device 23 does not need to have a mode switching function for the number of colors.

The function of the FRC data removal circuit 103 is shown in FIG.
3 will be used for the explanation. FIG. 13 is a truth table describing the operation of the FRC data removing circuit 103. Input 40
The 96-color display data line 102 and the output are 512-color display data line 104. Similar to FIG. 9, the FRC display is
The gradation levels 14, 12, 10, 8, 6, 4, 2, 1. Therefore, these pieces of information are converted into the nearest gradation level. As shown in the figure, gradation level 14 goes to level 15, 12 goes to 13, 10 goes to 11, 8 goes to 9,
Converts 6 to 7, 4 to 5, 2 to 3, and 1 to 0. Levels other than these are not converted. By such conversion, 16-level information becomes 8-level information.

As described above, in the second embodiment, even in an information processing apparatus using a display device that does not have a mode for changing the number of color developments, the display control circuit 80 is provided with means for switching the number of color developments. The function of setting the color display mode can be realized. Therefore, it is possible to reduce the power consumption of the circuit unit related to display control.

Next, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 14 is a block diagram of an information processing apparatus showing a third embodiment. In the figure, circuit blocks and signal lines having the same functions as those of the components shown in FIG. 1 are designated by the same reference numerals.

The present embodiment differs from the embodiment shown in FIG. 1 in the configuration of the mode selection unit 9. That is, the mode selection unit 9 of the present embodiment omits the frequency control circuit 21 used in FIG.
The information of the signal line 24 output from the control circuit controls the clock selection of the selection circuit 20. Except for this point, it has the same configuration and operation as the embodiment of FIG. Therefore, the description will be omitted here, and the different points will be mainly described.

In the third embodiment, when the color number control circuit 22 is set to the 4096 color mode, the selection circuit 20
When the clock signal (80 MHz) of the oscillator 7 is in the 512 color mode, the clock signal (60 MH) of the oscillator 19
z). In short, the operation of switching the clock and the operation of switching the number of colors can be controlled together. Therefore, the oscillator 19 and the 4096 color mode are not selected at the same time. If both are selected at the same time, as described above, F
Flickering of RC display occurs, resulting in deterioration of image quality. Therefore, in this embodiment, it is possible to prevent the software from mistakenly setting the information in the hardware so as to cause the deterioration of the image quality.

In this embodiment, in the mode selection section 9, the frequency control circuit 21 is omitted and the information of the signal line 24 output from the color number control circuit 22 is the selection circuit 20.
However, the present invention is not limited to this. On the contrary, the color number control circuit 22 may be omitted, and the color number may be controlled based on the information output from the frequency control circuit 21. This is not limited to this embodiment, and the same applies to other embodiments.

Next, a fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 15 is a block diagram of an information processing apparatus showing the fourth embodiment. In the figure, circuit blocks and signal lines having the same functions as those of the components shown in FIG. 1 are designated by the same reference numerals.

The present embodiment is different from the embodiment shown in FIG. 1 in that a selection circuit 110 is provided as a selection circuit for selecting the clocks of the oscillators 7 and 19, and the power remaining of the battery 14 remains in the power supply section. It is provided with a power remaining amount detection circuit 115 for detecting the amount. Other than these points,
It has the same configuration and operation as the embodiment of FIG. Therefore,
Here, a duplicate description will be avoided and the description will focus on the differences.

The selection circuit 110 shown in FIG. 15 is a selection circuit having a function of preventing the occurrence of hazards when switching clock signals. In the figure, 111 is a clock signal line of the oscillator 7, 112 is a clock signal line of the oscillator 19,
13 is a selection signal line output from the frequency control circuit 21, 11
Reference numeral 4 denotes a clock signal line supplied to the display control circuit 6, 116
Is a battery use signal line.

By the way, a hazard may occur when the clock is switched. Therefore, the display control circuit 6 may malfunction and destroy the contents of the VRAM 8. Therefore, the setting to the frequency control circuit 21 is
It is limited to system startup, and it is not preferable to dynamically switch in the program used by the user. In order to avoid this problem, in the fourth embodiment, the selection circuit 110 is constructed so that no hazard occurs during switching. As a result, the CPU1
Can set information in the frequency control circuit 21 at an arbitrary timing. Details of the configuration of the selection circuit 110 will be described later. The selection circuit 110 used in this embodiment is
It goes without saying that it can also be used in other embodiments.

FIG. 17 is a block diagram of the selection circuit 110. In the figure, the same reference numerals are given to the circuit blocks and the same signal lines having the same functions as those of the constituent elements shown in FIG.

In the figure, the selection circuit 110 has inverting circuits 120 to 122, latch circuits 123 to 126 having the same function as the latch circuit 34 of FIG. 5, and an AND / OR circuit 127.

Since the inverting circuit 121 inverts the information on the clock signal line 111, the latch circuits 123 and 124 hold the information at the fall of the clock signal line 111. Similarly, since the inverting circuit 122 inverts the information on the clock signal line 112, the latch circuits 125 and 126 hold the information at the fall of the clock signal line 112. Latch circuits 123 and 124 and latch circuits 125 and 126
Has a two-stage latch configuration for synchronization processing. The latch circuit 124 synchronizes the information on the selection signal line 113 and outputs it to the AND / OR circuit 127. Similarly, the latch circuit 126 synchronizes the information inverted by the inverting circuit 120 on the selection signal line 113 and outputs the synchronized information to the AND / OR circuit 127.

In the AND / OR circuit 127, since the clock signal on the clock signal line 111 is switched at the falling edge, no hazard is generated on the clock signal line 114. Similarly, since the clock signal on the clock signal line 112 switches at the falling edge, the clock signal line 1
There is no hazard in 14.

As described above, according to this embodiment, the selection circuit 110 capable of preventing the occurrence of hazard can be constructed with a simple circuit.

Further, the power remaining amount detecting circuit 115 can detect the residual power in the battery 14. C
By reading the detection information, the PU 1 monitors the remaining amount of electric power stored in the battery 14, and as a result, when it recognizes that the amount of electric power has dropped to a specific remaining amount, it enables low power operation in the 512-color mode. Moreover, information can be set in the color number control circuit 22 and the frequency control circuit 21. RA
If the above function is incorporated into the system program resident in M4, when the power of the battery 14 becomes low,
The user can automatically shift to the low power consumption mode without being aware of it and secure a longer operable time.

FIG. 18 is a block diagram of the power remaining amount detecting circuit 115. In the figure, the circuit blocks and the same signal lines having the same functions as those of the components shown in FIG. 15 are designated by the same reference numerals.

In the figure, the remaining power level detection circuit 115
Has a decoder circuit 132, an AND circuit 133, a timer 134 for measuring time, and a buffer circuit 136. In the figure, 130 is an address line, 131 is a valid signal line, and 135 is a signal line from which the timer 134 outputs time information. The address bus 2 is composed of an address line 130 and an effective signal line 131, like the color number control circuit 22 shown in FIG.

The timer 134 is the battery use signal line 1
By inputting 16 pieces of information, it is possible to detect a period during which the battery 14 is supplying power (discharge period) and a period during which the battery 14 is supplying power (charge period). During the charging period, the timer 134 counts up the time information during that period, and during the discharging period, counts down the time information during that period. Therefore, the fact that the time information of the timer 134 is large indicates that the remaining amount of power of the battery 14 is large. Here, the timer 134 is provided with an upper limit value. This upper limit value is determined on the assumption that the battery is fully charged for the capacity. This state can be set, for example, by performing experiments in advance or by calculation.

The decoder circuit 132 is the buffer circuit 13
The address signal assigned to 6 is output to the AND circuit 133. The AND circuit 133 notifies the buffer circuit 136 that the address line 130 indicates the address of the buffer circuit 136 and that the valid signal line 131 indicates a valid read cycle. At this time, the buffer circuit 136 outputs the information on the digital output line 135 to the data bus 3. On the other hand, at other times, the data bus 3 is in a high impedance state. By such a read operation, the CPU 1 can take in the time information of the timer 134, that is, the power remaining amount information of the battery 14.

The power remaining amount detecting circuit 115 can be realized with the configuration as described above. According to the fourth embodiment, when the power of the battery 14 is low, the user automatically shifts to the low power consumption mode without being aware of it, and a longer operable time can be secured. Here, the automatic shift to the low power consumption mode can be realized by relatively simple software as shown in FIG. 16, for example.

FIG. 16 shows a flow chart when incorporated in a timer interrupt routine as an example of a program for this purpose.

When there is a predetermined timer interrupt, the CPU 1 carries out this interrupt processing (step 1601). Then, the remaining power amount information of the remaining power amount detection circuit 115 is read (step 1602). The read power remaining amount information is compared with a predetermined power remaining amount value set as a reference in advance (step 1603). When the read remaining power information is lower than the predetermined remaining power value, the color number control circuit 22 is set with 512 color selection information (step 16).
04). Then, the selection information of the oscillator 19 is set in the frequency control circuit 21 (step 1605). On the other hand, when the read power remaining amount information is not lower than the predetermined power remaining amount value, the normal mode is continued as it is.

Here, the above-mentioned predetermined power remaining amount value is, for example, the relationship between the power remaining amount value and the count value when the power is supplied from the battery 14 to all loads,
It is set by obtaining it by experiments, calculations, etc. in advance. The determination may be made based on the electric power supplied to the main load instead of the full load.

In this embodiment, an example in which the remaining amount of power of the battery 14 is detected by checking the charging period and the discharging period has been shown, but the present invention is not limited to this. For example, the remaining power detection circuit 115 may be configured to measure the charging current and the discharging current and integrate the measurement results thereof to obtain the remaining power of the battery 14. When a battery having a structure in which the terminal voltage of the battery 14 decreases as the remaining amount of power decreases, the same mode selection control can be performed by monitoring the terminal voltage of the battery 14. You can

FIG. 23 shows an example of the configuration of the voltage detection circuit in the latter case. The voltage detection circuit shown in FIG. 18 includes a timer 134 in the remaining power detection circuit 115 shown in FIG.
Replace the A / D conversion circuit 134a with the battery 14
The voltage of the electric power supply line 16 is taken in and the terminal voltage of the battery 14 is detected. In this case, the flowchart shown in FIG.
In step 2, the voltage level of the power supply line 16 is read, and in step 1603, the contents of both steps may be changed so that the read voltage value is compared with a predetermined voltage level set as a reference in advance. .

Next, a fifth embodiment of the present invention will be described with reference to the drawings.

FIG. 19 is a block diagram of an information processing apparatus showing the fifth embodiment. In the figure, the circuit blocks and the same signal lines having the same functions as those of the components shown in FIG. 10 and FIG. 14 are designated by the same reference numerals.

In this embodiment, as in the second embodiment, the display control circuit 80 selects the number of colors.
The difference from the second embodiment is that the information of the signal line 24 output from the color number control circuit 22 is used as the selection information of the selection circuit 20. As a result, similarly to the third embodiment, it is possible to prevent the software from mistakenly setting the information in the hardware so as to cause the deterioration of the image quality.
The other configurations are similar to those of the above-described embodiment, and therefore the description thereof is omitted here.

Next, a sixth embodiment of the present invention will be described with reference to the drawings.

FIG. 20 is a block diagram of an information processing apparatus showing the sixth embodiment. In the figure, the same reference numerals are given to the circuit blocks and the same signal lines having the same functions as those of the components shown in FIGS.

In this embodiment, the display control circuit 80 selects the number of colors, as in the second embodiment. Also,
Similar to the fourth embodiment, a selection circuit 110 having a hazard prevention function and a power remaining amount detection circuit 115 are provided.

In the present embodiment, similarly to the fourth embodiment, since the hazard does not occur at the time of switching in the selection circuit 110, the CPU 1 can set the information in the frequency control circuit 21 at an arbitrary timing.

The remaining power detection circuit 115 can detect the remaining power of the battery 14. That is, the CPU 1 regularly monitors the remaining power level of the battery 14 via the remaining power level detection circuit 115. And C
The PU 1 can set information in the color number control circuit 22 and the frequency control circuit 21 so that the PU 1 can operate at low power in the 512 color mode when it recognizes that the remaining amount of power has dropped to a specific level. If the above functions are incorporated into the system program resident in RAM4, the battery 14
When the remaining electric power becomes low, the user automatically shifts to the low power consumption mode without being aware of it, and a longer operable time can be secured.

Next, a seventh embodiment of the present invention will be described with reference to the drawings.

FIG. 21 is a block diagram of a video processing apparatus showing the seventh embodiment. In the figure, circuit blocks and signal lines having the same functions as those of the components shown in FIG. 20 are designated by the same reference numerals. This embodiment has the same configuration as the embodiment shown in FIG. 20 except that the video signal input circuit 140 is provided. The keyboard controller 10 and the keyboard 11 are not shown. However, an apparatus in which these are omitted may be used. Specifically, it can be a video reproducing device.

The video signal input circuit 140 is, for example, a video signal (NTSC, PAL, etc.) 1 from a video tape recorder, a television tuner, a video disc reproducing device, or the like.
The input of 41 is accepted, and the image information of the video signal 141 is transferred to the VRAM 8. At this time, the video signal input circuit 140 has a function of outputting address information to the address bus 2 and directly transferring the video information to the VRAM 8 without passing through the CPU 1 in order to realize real-time processing. The video information transferred to the VRAM 8 is transferred to the display device 23 by the display control circuit 80. Thereby, the video information of the video signal 141 can be displayed on the display device 23.

Also in this embodiment, as in the above-described embodiments, the power remaining amount detecting circuit 115 is the battery 1
The remaining power level of 4 is detected. That is, the CPU 1 monitors the remaining power level of the battery 14 via the remaining power level detection circuit 115. Then, when the remaining power level of the battery 14 becomes lower than a predetermined value, the CPU 1, as described above,
Switch the operating mode to low power mode. This allows
It is possible to secure a longer reproduction time of the video signal.

Next, an eighth embodiment of the present invention will be described with reference to the drawings.

FIG. 22 shows an example of a display screen for guiding the operation to be executed in the eighth embodiment. The information processing apparatus of this embodiment is applicable to each of the above-described embodiments and each of the embodiments described later. Therefore, although the hardware configuration is not particularly illustrated, here, description will be made assuming that the hardware shown in FIG. 1 is used.

The present embodiment is an example having a multi-window function as shown in FIG. In the figure, CPU1
Thus, three windows of the control panel 231, application (1) 232, and application (2) 233 are opened on the screen 230 of the display device 23.

The control panel 231 is usually for setting the brightness of the screen of the display device 23, the volume of a warning sound such as a miss touch of the keyboard 11, and the like. In the present embodiment, in addition to this, an area for setting the low power consumption mode is defined.

Thus, the user can easily set the mode manually. Also,
Even when the application is being executed, the mode can be switched by opening the control panel 231.

Further, the control panel 231 may be provided with an area for defining the stop of the automatic mode switching so that the automatic mode change is not performed.

In the case of the present embodiment, the input device may be further provided with a position indicating device such as a mouse.

Next, a ninth embodiment will be described with reference to the drawings.

FIG. 24 is a block diagram of an information processing apparatus showing the ninth embodiment. In the figure, the same reference numerals are given to the circuit blocks and the same signal lines having the same functions as the constituent elements shown in FIG.

The present embodiment is different from the first embodiment in that the VRAM 8 is replaced by a two-block configuration of VRAM 150 and VRAM 151, which are connected to separate power supply lines, and that power is supplied to the VRAM 151. A VRAM power supply control circuit 154 for controlling is provided. Therefore, the description will be omitted here, and the different points will be mainly described.

The VRAM 150 shown in FIG. 24 has a memory capacity necessary for N-color display described in the first embodiment. On the other hand, the VRAM 151 has a memory capacity capable of displaying (N + M) colors when used in combination with the VRAM 150. These VRAMs 150 and 151
Is connected to the display control circuit 6 using a common signal line,
Pass display information. The common signal line is a signal line 152 for transmitting address information and control information and a signal line 153 for transmitting data information.

Further, the VRAM 150 has a power supply line 17
Power is supplied from the power supply circuit 12 via the. On the other hand, the VRAM 151 is connected to the V line via the power line 155.
Power is supplied from the RAM power supply control circuit 154. VR
The AM power supply control circuit 154 controls power supply to the VRAM 151 according to the selection information of the signal line 24. When the information on the signal line 24 indicates the N-color mode, power supply is stopped, and conversely, when the (N + M) -color mode is indicated, power is supplied. Such a VRAM power supply control circuit 154 can be easily realized by using a relay circuit.

Therefore, when used in the N color mode, the power consumption of the VRAM 151 becomes 0, and the power consumption can be reduced.

The detailed structure of the VRAMs 150 and 151 will be described below with reference to the drawings. Especially, the resolution is 8
An example will be described in which 00 * 600 dots are used, the number of colors N is 512, and the number of colors (N + M) is 4096.

FIG. 25 is a block diagram showing details of the VRAM 150. In the figure, circuit blocks and signal lines having the same functions as those of the components shown in FIG. 24 are designated by the same reference numerals. Here, the memory element is 6
Hitachi's "HM53461 series" with 4k words x 4 bits is used. By using two of these memory elements, binary display information can be stored with a resolution of 800 × 600 dots. This binary display information is defined as one plane.

According to this definition, the VRAM 150 has 8
In order to store display information of 512 colors at a resolution of 00 × 600 dots, a 9-plane configuration (plane # 0 in the figure
8). Address information (A7 to A0) given to each memory element and RAS (row address strobe),
Six pieces of control information such as CAS (column address strobe) are supplied through the signal line 152. Further, as shown in the figure, the two memory elements in one plane have an 8-bit data bus configuration (D7 to D0 and SD7 to SD).
It can be 0). Display information is transferred via the signal line 153 configured as described above. Like this, 8
VRAM15 that can display 512 colors with 00x600 dots
0 can be configured.

Similarly, FIG. 26 is a block diagram showing details of the VRAM 151. In the figure, circuit blocks and signal lines having the same functions as those of the components shown in FIG. 24 are designated by the same reference numerals. Basically, VRA
It has the same configuration as M150, but is different in that it has three plane configurations (planes # 9 to 11). By using such VRAM 151 and VRAM 150 together, display information capable of storing 4096 colors with 800 × 600 dots can be stored.

As described above, according to this embodiment, 5
When the 12-color mode is selected and used, the power consumption of the VRAM 151 is reduced to 0 in addition to the effect of the first embodiment.
Therefore, it is possible to reduce power consumption and secure a long operable time when the battery is used.

Next, a tenth embodiment will be described with reference to the drawings.

FIG. 27 is a block diagram of an information processing apparatus showing the tenth embodiment. In the figure, circuit blocks and signal lines having the same functions as those of the components shown in FIG. 24 are designated by the same reference numerals.

The present embodiment differs from the ninth embodiment in that the VRAM power supply control circuit 154 is deleted and the VRAM is removed.
150 and 151 both receive power supply from the power supply circuit 12 via the power supply line 17, and a new VRA
The M control circuit 160 is provided. Further, as an effect of this embodiment, when the N color mode is selected, the VRAM
The aim of reducing the power consumption of 151 is the same as that of the ninth embodiment. Therefore, the description will be omitted here, and the different points will be mainly described.

The VRAM control circuit 160 shown in FIG.
It has a function of masking address information and control information of the signal line 152. As a specific operation, when the information of the signal line 24 indicates the (N + M) color mode, the address information and the control information of the signal line 152 are directly output to the signal line 161. On the other hand, when the information on the signal line 24 indicates the N-color mode, the address information and the control information on the signal line 152 are ignored, the signal on the signal line 161 becomes a fixed level, and all the memories in the VRAM 151. The element goes into the standby state.

In the standby state, the power consumption of the memory element is considerably low. As a specific example, Hitachi "HM5
In the case of "3461 series", the maximum power consumption per element is 600 mW during normal operation.
Maximum 40 mW in standby. In this way, the power consumption can be suppressed by one digit or more, so that the effect of reducing the power consumption is great.

The detailed structure of the VRAM control circuit 160 will be described below with reference to the drawings.

FIG. 28 is a block diagram showing details of the VRAM 216. In the figure, the same reference numerals are given to the circuit blocks and the same signal lines having the same functions as those of the constituent elements shown in FIG. In the figure, 170 is a logic circuit, which outputs the logic information of the information of the signal line 152 and the information of the signal line 24 to the signal line 161.

When the information on the signal line 24 indicates the N color mode, the signal level becomes 1, and when the information of the (N + M) color mode indicates, the signal level becomes 0. Therefore, in the N-color mode, all the signal levels of the signal line 161 are 1, and all the memory elements connected to the signal line 161 are in the standby state. Conversely, in the (N + M) color mode, the information on the signal line 152 can be transmitted to the signal line 161 at the same signal level. As described above, the VRAM control circuit 160 puts the VRAM 151 in the standby state in the N-color mode and VRA in the (N + M) color mode.
The M151 can be put into a normal operation state.

As described above, according to this embodiment, N
When the color mode is selected and used, in addition to the effect of the first embodiment, the power consumption of the VRAM 151 can be expected to be reduced by, for example, one digit or more. Therefore, the power consumption is reduced and the battery is used. It is possible to secure a long operable time of the information processing device.

In each of the above-described embodiments, an example of the display device is shown using liquid crystal, but the present invention is not limited to this.
The present invention can be widely applied to display devices that change the clock frequency to change the number of display colors.

[0165]

As described above, according to the present invention,
When a display device having a mode for changing the number of colors is used, the number of colors to be displayed and the operating frequency can be selected for multicolor display.

Further, according to the present invention, it is possible to reduce power consumption and secure a long operable time when the battery is used in the use state.

By changing a part of the constituent elements or adding a constituent element to a part of the constituent elements,
The following effects can be expected.

When the display control circuit is provided with a means for switching the number of colors, an information processing apparatus using a display device without a mode switching function of the number of colors can be set to a display mode with a small number of colors. Therefore, it is possible to reduce the power consumption of the circuit unit related to display control.

Further, if the clock switching operation and the color number switching operation are controlled in conjunction with each other, the low frequency oscillator and the multicolor mode are not simultaneously selected. Therefore, it is possible to prevent flickering of the FRC display and deterioration of the image quality caused by the software setting the wrong information in the hardware.

Further, when the remaining power detection circuit is provided, when the remaining battery power is low, the low power consumption mode is automatically entered without the user's awareness, and a longer operable time can be secured.

Furthermore, it is possible to prevent malfunction of the display control circuit by selecting a selection circuit that does not cause a hazard when the clock is switched.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of an information processing apparatus of the present invention.

FIG. 2 is a time chart showing an operation of a color number control circuit used in an embodiment of the present invention.

FIG. 3 is a flowchart showing an operation procedure of a power saving function when not in use, which can be added to the embodiment of the present invention.

FIG. 4 is a flowchart showing a procedure for determining a selection program for determining an operation mode in the first embodiment.

FIG. 5 is a block diagram showing details of a color number control circuit that can be used in an embodiment of the present invention.

FIG. 6 is a block diagram showing details of a display device that can be used in an embodiment of the present invention.

7 is a block diagram showing details of an FRC circuit which is a constituent element of the display device shown in FIG.

8 is a block diagram showing details of an FRC data generation circuit which is a component of the FRC circuit shown in FIG.

9 is an explanatory diagram showing a truth table of a data conversion circuit which is a constituent element of the FRC data generation circuit shown in FIG.

FIG. 10 is a block diagram showing the configuration of a second embodiment of the information processing apparatus of the present invention.

11 is a block diagram showing details of a display control circuit used in the embodiment shown in FIG.

FIG. 12 is a block diagram showing details of a color number selection circuit which is a component of the display control circuit shown in FIG.

13 is an explanatory diagram showing a truth table of an FRC data removing circuit which is a constituent element of the color development number selection circuit shown in FIG. 12;

FIG. 14 is a block diagram showing the configuration of a third embodiment of the information processing apparatus of the present invention.

FIG. 15 is a block diagram showing the configuration of a fourth embodiment of the information processing apparatus of the present invention.

FIG. 16 is a flowchart showing a selection procedure of an automatic mode selection function used in the fourth embodiment.

FIG. 17 is a block diagram showing details of the selection circuit shown in FIG. 15.

18 is a block diagram showing details of the power remaining amount detection circuit shown in FIG.

FIG. 19 is a block diagram showing a configuration of a fifth embodiment of the information processing system of the invention.

FIG. 20 is a block diagram showing the configuration of a sixth embodiment of the information processing apparatus of the present invention.

FIG. 21 is a block diagram showing the configuration of a seventh embodiment of the information processing system of the invention.

FIG. 22 is an explanatory diagram showing an example of a display screen for guiding an operation to be executed in the eighth embodiment of the information processing apparatus of the invention.

FIG. 23 is a block diagram showing an example of a voltage detection circuit that detects a terminal voltage of a battery.

FIG. 24 is a block diagram showing a configuration of a ninth embodiment of the information processing system of the invention.

FIG. 25 shows V used in the ninth embodiment.
It is a block diagram which shows the structure of RAM.

FIG. 26 is a diagram showing V used in the ninth embodiment.
It is a block diagram which shows the detailed structure of RAM.

FIG. 27 is a block diagram showing the configuration of the tenth embodiment of the information processing apparatus of the present invention.

FIG. 28 is a block diagram showing a detailed structure of a VRAM used in the tenth embodiment.

[Explanation of symbols] [Explanation of symbols]

1 ... CPU, 6 ... Display control circuit, 8 ... VRAM, 10 ...
Keyboard controller, 11 ... Keyboard, 12 ... Power supply circuit, 14 ... Battery, 21 ... Frequency control circuit, 2
2 ... Color development number control circuit, 23 ... Display device, 44 ... FRC circuit, 62 ... FRC data generation circuit, 70 ... Data conversion circuit, 80 ... Display control circuit, 95 ... Color development number selection circuit, 10
3 ... FRC data removal circuit, 110 ... Selection circuit, 115
... power remaining amount detection circuit, 150 ... VRAM, 151 ... VR
AM, 154 ... VRAM power supply control circuit, 160 ... VRA
M control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tsutomu Furuhashi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Microelectronics Equipment Development Laboratory, Hitachi, Ltd. (72) Inventor Koji Takahashi 3300 Hayano, Mobara-shi, Chiba Address: Hitachi, Ltd., Electronic Devices Division (72) Inventor, Fumikazu Fujimaki, 810 Shimoimaizumi, Ebina, Kanagawa Prefecture, Ltd., Office Systems Division, Hitachi, Ltd. (72) Koichi Isaji, 810, Shimoimaizumi, Ebina, Kanagawa Hitachi Systems Office Systems Division

Claims (22)

[Claims] 1. An information processing apparatus capable of multicolor display, comprising: a CPU (central processing unit); a display memory for storing display information; and the display information in multicolor within a predetermined number of colors. A display control circuit that controls information exchange between the display device, the CPU and the display memory, periodically reads out display information stored in the display memory and sends the display information to the display device, and Mode selection for selecting any one of at least two modes, a first mode that operates at low frequency and low frequency and a second mode that operates at high frequency with large number of colors and output selection information And a clock signal generator that generates a plurality of clock signals having different frequencies, and receives the selection information and outputs a plurality of clock signals output from the clock signal generator. Then, a clock signal having a frequency corresponding to the mode indicated by the selection information is selected and at least a clock selection circuit to be output to the display control circuit, and a maximum color number to be displayed on the display device upon receiving the selection information, And a maximum color number selecting means for selecting a mode corresponding to the mode indicated by the information, wherein the CPU has means for instructing the mode selecting section which mode to select. apparatus. 2. The information processing apparatus according to claim 1, wherein the clock selection circuit, when selecting a clock signal, synchronously switches the currently selected clock signal and the newly selected clock signal. , A switching circuit having a hazard prevention function. 3. The information processing apparatus according to claim 2, further comprising a battery for supplying electric power and a power remaining amount detection circuit for detecting a power remaining amount of the battery, wherein the CPU has a power remaining amount. The detection result of the detection circuit is monitored, and when the remaining power level of the battery becomes lower than a preset remaining power level value, the mode selection unit is instructed to select the first mode. . 4. The information processing apparatus according to claim 3, further comprising an input device through which a user can input an instruction, wherein the CPU receives an instruction from the input device and gives a mode selection instruction. Is something that can be done. 5. The information processing apparatus according to claim 4, wherein the CPU generates a control window on the screen of the display device, displays a mode selection area on the window, and performs a user's selection operation. Is further provided. 6. The information processing apparatus according to claim 1, further comprising a battery for supplying electric power, and a power remaining amount detection circuit for detecting a power remaining amount of the battery, wherein the CPU has a power remaining amount. The detection result of the detection circuit is monitored, and when the remaining power level of the battery becomes lower than a preset remaining power level value, the mode selection unit is instructed to select the first mode. . 7. The information processing apparatus according to claim 6, further comprising an input device through which a user can input an instruction, wherein the CPU receives an instruction from the input device and gives a mode selection instruction. Is something that can be done. 8. The information processing apparatus according to claim 7, wherein the CPU generates a control window on the screen of the display device, displays a mode selection area on the window, and performs a user's selection operation. Is further provided. 9. The information processing apparatus according to claim 1, further comprising an input device through which a user can input an instruction, wherein the CPU receives an instruction from the input device and issues a mode selection instruction. Is something that can be done. 10. The information processing apparatus according to claim 9,
The CPU further includes means for generating a control window on the screen of the display device, displaying a mode selection area on the window, and accepting a user's selection operation. 11. The information processing apparatus according to claim 1,
The display device receives a display section capable of displaying N colors and display information including up to (N + M) colors, and alternately displays the N colors displayable by the display section at a specific timing. And a data conversion circuit for outputting display information of a corresponding color from M combinations of two colors selected from N colors for displaying the intermediate color. 12. The information processing apparatus according to claim 11, wherein the display device, for input display information up to (N + M) colors, if the input display information is an arbitrary intermediate color of M colors, It further has N-coloring means for substituting one of the N colors for generating display information whose maximum number of colors is N. 13. The information processing apparatus according to claim 12, wherein the maximum color number selection means outputs the display information up to (N + M) colors output from the data conversion circuit and the N colorization means. Any of the display information up to N colors is selected according to the mode selection information from the mode selection unit. 14. The information processing apparatus according to claim 13, wherein the maximum color number selecting means is provided in the display device. 15. The information processing apparatus according to claim 11, wherein the maximum color number selection means is input intermediate information of M colors among the input display information up to (N + M) colors. If so, it has one of the above N colors, has N colorization means for generating display information whose maximum number of colors is N, and outputs (N + M) colors from the above data conversion circuit. Of the display information up to and the display information of up to N colors output from the N-colorization unit, and has a unit that outputs an instruction to select one of them in accordance with the mode selection information from the mode selection unit. It is a thing. 16. The information processing apparatus according to claim 15, wherein the maximum color number selecting means is provided in the display control circuit. 17. The information processing apparatus according to claim 15, wherein the display section is a liquid crystal display section. 18. The information processing apparatus according to claim 11, wherein the display section is a liquid crystal display section. 19. The information processing apparatus according to claim 1,
The display memory is composed of a first memory and a second memory, and the first memory has a memory capacity capable of storing at least display information of the number of colors required for display in the first mode. The second memory, when used in combination with the first memory, has a memory capacity capable of storing at least display information of the number of colors required for display in the second mode. 20. The information processing apparatus according to claim 19, further comprising power consumption control means for controlling the power consumption of the second memory, wherein the power consumption control means supplies power to the second memory. The supply is stopped in the first mode, and the supply is controlled in the second mode. 21. The information processing apparatus according to claim 19, further comprising a memory operation control means for controlling an operation of the second memory, wherein the memory operation control means stores the second memory in the first mode. The address information and the control information are controlled so that the standby state is established. 22. In a display device for displaying display information in multiple colors within a predetermined number of colors, a display unit capable of displaying N colors and display information including colors of up to (N + M) colors are accepted. And a corresponding color is selected from N colors that can be displayed on the display unit and M combinations of 2 colors selected from N colors for displaying intermediate colors by alternately displaying at a specific timing. With respect to the data conversion circuit for outputting the display information and the input display information up to (N + M) colors, if the input display information is an arbitrary intermediate color of the M colors, one of the above N colors is displayed. Instead, N-colorization means for generating display information whose maximum number of colors is N, display information up to (N + M) colors output from the data conversion circuit, and N output from the N-colorization means. One of the display information up to the color is input from the rotating part. It has means for outputting a selection instruction according to the selection information.