JPH06188429A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a semiconductor storage device capable of write and erase operation, using an FN current, by accomplishing the high breakdown strength of the drain of a memory transistor which has a floating gate. CONSTITUTION:This is a semiconductor storage device, where, on a semiconductor substrate, drain regions 4, source regions 3, channel regions caught between the drain regions 4 and the source regions 3, and, through a tunnel insulating film 5, on the surface of the semiconductor substrate, above the channel region, memory cells each consisting of a floating gate 6, a layer insulating film 7, and a control gate 8 are disposed in matrix shape, and the drain region 4 of each memory cell is made of a double diffusion layer consisting of a high- concentration area 4a and a low-concentration area 4b surrounding it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. More specifically, by increasing the breakdown voltage of the drain region,
The present invention relates to a semiconductor memory device capable of both writing and erasing with an FN current.

[0002]

2. Description of the Related Art EEPROMs, which are electrically rewritable and can hold data even in a non-powered state, are widely used. This EEPROM has a flash memory type in which hot electrons are injected into a floating gate, and a metal-oxide film-nitride film-oxide film-semiconductor structure MONOS (metal) which injects electrons by FN tunneling or direct tunneling in an insulating film. oxide nitr
ide oxide semiconductor) type or MNOS (metal nitride oxide semicon) of metal-nitride film-oxide film-semiconductor structure
ductor) type.

A memory cell of a semiconductor memory device having a floating gate has, for example, as shown in FIG.
A channel region 22 is formed on a p-type semiconductor substrate 21 made of silicon.
N ⁻ with impurities such as phosphorus introduced on both sides of the n ⁻
Type low concentration region 23a and n ⁺ type high concentration region 23b into which arsenic or the like is introduced, and a source region 23 and n such as arsenic
A drain region 24 in which a ⁺ type impurity is introduced is formed,
A tunnel insulating film 25 made of silicon oxide or the like is provided on the upper surface of the channel region 22 by an oxidation method or the like, and then a floating gate 26, an interlayer insulating film 27 and a control gate 28 are sequentially provided by a CVD method or the like,
The source region 23 and the drain region 24 are connected to the source line 29 and the bit line 30, respectively, to form a memory cell. The reason why the source region 23 has the double diffusion structure is
Since a high voltage is applied to the source during erasing, the low concentration region 23a is provided for the purpose of improving the breakdown voltage.

Writing and erasing of this semiconductor memory device are performed in the following procedure.

When writing, first the source electrode 29
In the state in which is grounded, a relatively high voltage of about 12V is applied to the control gate 28 and about 6 to 7V is applied to the bit line 30. As a result, a current flows between the source region 23 and the drain region 24, and high-energy hot electrons are generated in the high electric field portion near the drain region 24. Since the hot electrons exceed the energy level of the tunnel insulating film 25, they pass through the tunnel insulating film 25 and are injected into the floating gate 26. In this way, hot electrons are injected only into the floating gate 26 of a desired cell to perform writing.

On the other hand, when erasing, hot electrons are floated by applying a high voltage of about 12 V to the source electrode 29 with the control gate 28 grounded and the bit line 30 side floated. Gate
It is done by pulling out from 26.

[0007]

However, in the above semiconductor memory device, hot electrons are used when writing data. Therefore, hot electrons having high energy account for less than 1% of the current flowing between the source and the drain, most of the current is wasted, the injection efficiency is very poor, and the current consumption increases. Moreover,
Since hot electrons having high energy pass through the tunnel insulating film, stress is generated in the tunnel insulating film and the number of times of writing is limited.

In order to solve this problem, the inventor of the present invention uses a FN current to inject electrons into the floating gate as an erasing state as a driving method of a memory cell having a floating gate, and pulls out the electrons to enter a writing state. Figured out a scheme. Although this method can significantly improve the injection efficiency,
Since a high voltage (about 12 V) is applied to the drain side when a write operation is performed by generating a current, the drain region 24
There is a problem that the withstand voltage is not high. Therefore, in order to write in the memory cell having the conventional floating gate by the FN current, it is indispensable to increase the breakdown voltage of the drain region.

On the other hand, when the gate length is shortened to 1 μm or less as the density of the MOSIC becomes higher, the electric field strength near the drain increases, and the characteristics and reliability of the transistor such as trapping of electrons in the gate insulating film are increased. LDD type M having a double diffusion structure in the drain region because it is not preferable
OS transistors have been put to practical use. However, this structure is adopted for the purpose of preventing the generation of hot carriers in a MOS transistor having a particularly short gate length, and the end of the low concentration region of the drain region is located below the end of the gate electrode. However, the end of the high-concentration region exists far outside the gate electrode.

The present invention has been made in order to solve such a problem, and achieves a high breakdown voltage of the drain of a semiconductor memory device having a floating gate, and uses a FN current for both writing and erasing. The purpose is to provide.

[0011]

A semiconductor memory device according to the present invention is sandwiched between (a) a drain region, (b) a source region, and (c) a drain region and a source region provided on a semiconductor substrate. A channel region, and (b) a tunnel insulating film, (e) a floating gate, (f) an interlayer insulating film, and (g) a control gate, which are sequentially provided on the surface of the semiconductor substrate on the channel region. In a semiconductor memory device in which memory cells are arranged in a matrix, the drain region of each memory cell is composed of a high concentration region and a double diffusion layer of a low concentration region provided around the high concentration region, It is characterized in that the end portion of the high concentration region is formed below the floating gate of each memory cell.

[0012]

According to the semiconductor memory device of the present invention, since the diffusion layer having a concentration lower than that of the drain region is provided around the drain region of each memory cell, the drain electrode has a high potential when the control gate is grounded during writing. Even if a voltage is applied, a sufficiently high breakdown voltage can be obtained with the substrate. Moreover, since the high-concentration region of the gate region extends below the end of the floating gate, electrons can be efficiently extracted from the floating gate during writing.

Thus, by injecting electrons into the floating gate by the FN current, the memory is erased, and by setting the drain to a high potential with respect to the control gate, electrons can be extracted from the floating gate to be in the writing state. Therefore, in both writing and erasing, the FN in which electrons move based on the voltage applied between both electrodes
It is performed by an electric current, and electrons corresponding to the electric current are injected and extracted, so that a wasteful consumption current is drastically reduced. In addition, since the use of hot electrons for injecting electrons having high energy is not used, deterioration of the tunnel insulating film between the semiconductor substrate and the floating gate is small, and the number of times of rewriting can be significantly increased.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a semiconductor memory device of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing a planar arrangement of respective memory elements showing an embodiment of a semiconductor memory device of the present invention, FIG. 2 is a sectional view taken along line II-II of FIG. 1, and FIG. FIG. 4 is an enlarged cross-sectional view of a portion, FIG. 4 is a diagram for explaining a method of erasing and writing in the semiconductor memory device of the present invention. FIG. FIG. 9 is an equivalent circuit diagram of a stack type semiconductor memory device in which memory transistors having gates are arranged in a matrix.

1 to 3, field insulating films 2 are formed in a matrix on a semiconductor substrate 1 to separate memory cells arranged in the vertical direction in FIG. As shown in FIG. 2, the memory cell has a floating gate 6 made of a first polysilicon layer and an interlayer insulating film on a surface on a channel region 11 between a source region 3 and a drain region 4 via a tunnel insulating film 5. A control gate 8 composed of a film 7 and a second polysilicon layer is laminated, a bit contact 10 is provided in a contact hole provided in an interlayer film 9 covering the surface thereof, and each drain region 4 of cells arranged in the lateral direction is formed.
A bit line B is provided for electrically connecting the. The drain region 4 of each memory cell is formed of a double diffusion layer composed of a high concentration region 4a and a low concentration region 4b.
The end portion of a also extends below the floating gate 6. This is from floating gate 6 to drain region 4
This is because the electron is pulled out.

With such a structure, the concentration gradient in the drain region 4 becomes gentle, the electric field is relaxed when a reverse bias is applied, and a high breakdown voltage is achieved.

To manufacture this semiconductor memory device, first, as shown in the plan view of FIG. 1, a field insulating film 2 is provided on the surface of a semiconductor substrate 1 by an oxidation method or the like, and then, as shown in FIGS.
, A tunnel insulating film 5 made of, for example, a silicon oxide film is provided on the active region with a thickness of 80 to 120 Å.

Next, for example, the first polysilicon to be the floating gate 6 is formed by CVD, for example.
Deposited to a thickness of 00 to 2000Å, and an interlayer insulating film 7 with an ONO three-layered insulating film composed of silicon oxide, silicon nitride, and silicon oxide is also formed so as to have a total thickness of 200 to 300Å.
It is deposited by the VD method or the like. Further, a second polysilicon layer to be the control gate 8 is similarly provided with a thickness of 3000 to 4000 Å and then patterned to provide the floating gate 6, the interlayer insulating film 7 and the control gate 8 of each memory cell. After that, in order to form the low-concentration region 4b of the drain region, it is masked with a resist film or the like and phosphorus ions, for example, are dosed at 1E14 to 5E14 / cm ² , 50 to 150.
Implanted with the energy of keV, the impurity concentration is 1E18 to 1E19
/ Cm ³ of low concentration region. Next, using the control gate 8 as a mask, arsenic ions and the like are exposed to 5E14 to 5E15.
By ion-implanting with a dose amount of 50/100 keV with a dose amount of / cm ² , the high-concentration regions 4a of the source region 3 and the drain region respectively have impurity concentrations.
It is formed at 1E20 to 5E20 / cm ³ . Further, an insulating film made of silicon oxide or the like is entirely coated, and a bit line 11 connecting the drain regions of the cells arranged in the horizontal direction and a word line (not shown) connecting the control gates of the memory cells arranged in the vertical direction are formed of Al. -Si or Al-Si-Cu etc. 10
Provide a thickness of about 000 Å.

The interlayer insulating film between the floating gate 6 and the control gate 8 has a three-layer structure of ONO in order to enhance the insulating property, but it is constituted by any one layer or two layers. Good. Although the drain region has been described as an example of a low-concentration region of phosphorus and a high-concentration region of arsenic, the phosphorus impurity is easily diffused to the surroundings and the arsenic impurity is difficult to diffuse to maintain a high concentration, which is preferable, but not limited thereto. Furthermore, although the n-type source and drain regions have been described as an example on the p-type semiconductor substrate, they may have opposite conductivity types.

Next, a method of driving the semiconductor memory device of the present invention will be described.

In a conventional flash memory having a floating gate, writing is performed by injecting hot electrons into the floating gate and erasing is performed by drawing out electrons, but in the present invention, electrons are injected into the floating gate. Is erased, and electrons are extracted from each cell to be written, whereby electrons are moved by an FN current based on a voltage applied between both electrodes.

First, the method of erasing the storage state will be described with reference to FIG.
As in (a), a voltage is applied so that the control gate has a high potential with respect to the semiconductor substrate 1, and electrons are injected from the substrate into the floating gate. For example, when the control gate 8 is set to 18V and the source region 3 and the semiconductor substrate 1 are grounded (0V), an FN current flows from the semiconductor substrate 1 to the control gate 8.
Electrons are injected into the floating gate 6 through the tunnel insulating film 5. The drain region 4 is left floating. This erase is collectively performed for each word line. Therefore, other word lines (control gates of memory transistors in other columns) are set to 0V.

Next, write grounded control gate 1 of the selected cell P ₁ as shown in FIG. 4 (b), the drain region 4 by applying a voltage V _PP to be the high potential of about 12V floating gates 6 This is done by pulling out electrons from. At this time, the control gate 8 of the non-selected cell
Is applied with a prohibiting potential V _{i of} about 6 V to prevent writing.

The applied state of the potential at the time of writing is not limited to this example. For example, a low potential of about 5V is applied to the drain region 4 by applying a negative potential of about -7V instead of grounding the control gate 8. It can also be applied. As a result, the potential difference between the drain region 4 and the substrate 1 is reduced, the leak current is reduced, and the breakdown voltage is improved.

The cells of this memory transistor are arranged in a matrix as shown in FIG. 5, the control gates of the cells in each column are connected to form word lines W ₁ , W _2, ... And the drains of the cells in each row are connected. Connect and connect bit lines B ₁ , B
₂ ... Is formed, and the sources of the respective memory transistors are connected to form a source line to form a stacked semiconductor memory device.

A method of erasing, writing, and reading the selected cell P ₁ among the cells formed in a matrix of this semiconductor memory device will be described.

First, for erasing, a high potential (about 18 V) is applied to the word line W _{3 in} which the selected cell P ₁ is present, and the word lines W ₁ , W ₂ , W ₄ , the source line and the substrate of the other columns are applied. By applying 0V or a low potential close thereto to each bit line in a floating state F, electrons are injected by FN tunneling and erased in word line units. As a method of applying this potential, 11 V is applied to the word line W ₃ , -7 V is applied to the substrate, and the other word lines W ₁ , W ₂ ,
Similarly, by setting W ₄ ... To 0V and setting the bit lines B ₁ , B ₂ ...

Next, when writing to the memory transistor of the cell P ₁ , the word line W ₃ is grounded, and the word lines W ₁ , W ₂ , W _4, ...
V) is applied. Further, the bit line B ₁ cell P ₁ applies a high potential (about 12V), the bit line B ₂ ...... other than rows of cells P ₁ is the float F. The source of each cell and the substrate are set to 0V. Then, the drain of the transistor of the cell P _{1 has} a high potential with respect to the control gate, and electrons are extracted from the floating gate to the drain side to perform writing. On the other hand, other cells is different columns inhibit potential of about 6V cells to all the word lines of the applied, low voltage between the drain, the write is not performed, in the same column as the cell P _1, cell P ₁ Bit lines B ₂ ... Are in a floating state F and no current flows in each cell in the lower row except that no writing is performed. Thus, writing is not performed in the cell other than the cell P ₁ is, writing is performed only in the cell P _1. In addition, when a negative potential is applied to the control gate, the word line W ₃ is -7
V, 5V is applied to the bit line B ₁ , other word lines W ₁ ,
Writing can be performed in the same manner by setting W ₂ , W _4, ... And the substrate to 0V, and setting the bit line B ₂ ... And the source line to float.

Further, regarding reading, for example, when reading the cell P _1, a potential (about 5 V) lower than the high voltage for writing is applied to the word line W ₃ , and the bit line B ₃ is applied.
Applying about ₁ V to 1 and applying word lines W ₁ , W ₂ , and
W ₄ ...... and other bit line B ₂ ...... and source line and the substrate row can be read by a 0V. That is, only the cell P ₁ is in a state where the drain potential is higher than the source potential by about 1 V and a current can flow through this transistor, and it depends on the voltage applied to the control gate and the state of electrons injected to the floating gate. The state of "1" or "0" can be read by turning on or off according to the threshold voltage.

Table 1 summarizes these relationships.

[0032]

[Table 1]

Table 2 shows the voltage relationship when a negative voltage is used.

[0034]

[Table 2]

[0035]

According to the present invention, since the breakdown voltage of the drain region can be increased, the memory transistor having the floating gate is erased by injecting electrons into the floating gate, and writing is performed from the floating gate. It can be performed by extracting electrons, and both writing and erasing can be performed with an FN current. As a result, the injection efficiency of electrons is almost 100%, and there is no wasted current, so low power consumption can be achieved, and battery replacement or charging can be greatly reduced even in a battery-operated personal computer. Furthermore, since electrons are injected and extracted by FN current and hot electrons having high energy are not injected, deterioration of the tunnel insulating film is small,
The number of rewrites is also greatly improved.

[Brief description of drawings]

FIG. 1 is an explanatory plan view showing an embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a sectional view taken along line II-II in FIG.

FIG. 3 is an enlarged cross-sectional view of a main part of FIG.

4A and 4B are diagrams illustrating an erasing / writing method of a semiconductor memory device of the present invention, FIG. 4A is an explanatory diagram of an erasing method, and FIG. 4B is an explanatory diagram of a writing method.

FIG. 5 is an equivalent circuit diagram of a stack type semiconductor memory device in which memory transistors having floating gates are arranged in a matrix.

FIG. 6 is a sectional view of a conventional semiconductor memory device.

[Explanation of symbols]

 1 semiconductor substrate 3 source region 4 drain region 4a high concentration region 4b low concentration region 5 tunnel insulating film 6 floating gate 7 interlayer insulating film 8 control gate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G11C 16/04 H01L 27/115 7210-4M H01L 27/10 434

Claims (1)

[Claims] 1. (a) a drain region, (b) a source region, and (c) a channel region sandwiched between the drain region and the source region, which are provided on a semiconductor substrate, and (b) on the channel region. A semiconductor memory in which memory cells each including (d) a tunnel insulating film, (e) a floating gate, (f) an interlayer insulating film, and (g) a control gate, which are sequentially provided on the surface of the semiconductor substrate, are arranged in a matrix. In the device, the drain region of each memory cell comprises a high-concentration region and a double-diffusion layer of a low-concentration region provided on the periphery thereof, and an end portion of the high-concentration region of the drain region of each memory cell is A semiconductor memory device formed so as to be located below a floating gate.