JPH08255880A - Capacitor manufacturing method - Google Patents
Capacitor manufacturing methodInfo
- Publication number
- JPH08255880A JPH08255880A JP7332726A JP33272695A JPH08255880A JP H08255880 A JPH08255880 A JP H08255880A JP 7332726 A JP7332726 A JP 7332726A JP 33272695 A JP33272695 A JP 33272695A JP H08255880 A JPH08255880 A JP H08255880A
- Authority
- JP
- Japan
- Prior art keywords
- charge storage
- storage electrode
- oxide
- manufacturing
- amorphous silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体メモリ素子の
キャパシタの製造方法に関し、特に、制限された面積の
下でキャパシタの電荷貯蔵電極の有効面積を増大させる
ためのキャパシタの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor memory device, and more particularly, to a method of manufacturing a capacitor for increasing an effective area of a charge storage electrode of the capacitor under a limited area.
【0002】[0002]
【従来の技術】従来、キャパシタの形成方法は、シリコ
ン基板上にフィールド酸化膜、接合領域、ワードライン
及びビットラインを形成した後、全体構造上部を平坦化
絶縁膜で平坦化し、電荷貯蔵電極を接合領域にコンタク
トさせる方法を用いている。即ち、ビットライン上にキ
ャパシタが形成されるようにする積層型キャパシタを形
成することにより、電荷貯蔵電極の有効面積を大きくし
ている。2. Description of the Related Art Conventionally, a method of forming a capacitor is to form a field oxide film, a junction region, a word line and a bit line on a silicon substrate, then flatten the upper part of the entire structure with a flattening insulating film to form a charge storing electrode The method of contacting the junction region is used. That is, the effective area of the charge storage electrode is increased by forming a multilayer capacitor that allows the capacitor to be formed on the bit line.
【0003】[0003]
【発明が解決しようとする課題】しかし、半導体素子が
より高集積化されるに従って、上記従来技術によっては
制限された領域内で十分な電荷貯蔵電極の有効面積を得
ることが難しくなった。上記の如き従来技術の問題点を
解決するために案出した本発明は、制限された面積の下
で電荷貯蔵電極の有効面積を増大させるためのキャパシ
タの製造方法を提供することを目的とする。However, as semiconductor devices have become more highly integrated, it has become difficult to obtain a sufficient effective area of the charge storage electrode within the limited area according to the above conventional technique. SUMMARY OF THE INVENTION The present invention devised to solve the above-mentioned problems of the prior art aims to provide a method of manufacturing a capacitor for increasing the effective area of a charge storage electrode under a limited area. .
【0004】[0004]
【課題を解決するための手段】上記目的を達成するため
に本発明は、半導体素子のキャパシタの製造方法におい
て;キャパシタの電荷貯蔵電極コンタクトホールを形成
する段階;酸素が内包された非晶質シリコン膜を蒸着す
る段階;熱処理して上記酸素が内包された非晶質シリコ
ン膜を結晶化しながら、酸化副産物を形成する段階;及
び上記酸化副産物を除去する段階を含み、上記酸化副産
物が除去された結晶化されたシリコン膜で電荷貯蔵電極
を形成することを特徴とする。In order to achieve the above object, the present invention provides a method of manufacturing a capacitor for a semiconductor device; a step of forming a charge storage electrode contact hole of the capacitor; oxygen-containing amorphous silicon. A step of depositing a film; a step of forming an oxidation byproduct while crystallizing the oxygen-containing amorphous silicon film by heat treatment; and a step of removing the oxidation byproduct, wherein the oxidation byproduct is removed. The charge storage electrode is formed of a crystallized silicon film.
【0005】[0005]
【発明の実施の形態】以下に、添付された図を参照して
本発明の一実施例を詳細に説明する。図1乃至図3は、
本発明の一実施例に係り、コンタクトホール内に電荷貯
蔵電極用ポリシリコン膜を形成する方法を示す断面図で
あって、図1はシリコン基板(1)上にフィールド酸化
膜(2)、ワードライン(4)、接合領域(3)、層間
酸化膜(5)及びビットライン(6)を順次に形成した
後、全体構造上部を平坦化絶縁膜(7)で平坦化し、電
荷貯蔵電極コンタクトホールを形成した状態で、酸素が
内包された非晶質シリコン膜(8)を電荷貯蔵電極用伝
導層で蒸着した断面図である。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. 1 to 3 are
FIG. 1 is a cross-sectional view showing a method of forming a polysilicon film for a charge storage electrode in a contact hole according to an embodiment of the present invention. FIG. 1 shows a field oxide film (2) and a word on a silicon substrate (1). After the line (4), the junction region (3), the interlayer oxide film (5) and the bit line (6) are sequentially formed, the upper surface of the entire structure is flattened by the flattening insulating film (7), and the charge storage electrode contact hole is formed. FIG. 3 is a cross-sectional view of an amorphous silicon film (8) in which oxygen is included, which is vapor-deposited on a conductive layer for a charge storage electrode in a state in which is formed.
【0006】この際、酸素が内包された非晶質シリコン
膜(8)の蒸着はサイレン(Silane) ガスであるSiH
4 とN2 Oガスを用いて550℃乃至700℃の低温で
蒸着し、酸素の密度(Oxygen Concentration) は非晶質
シリコン分子に比べて10%乃至30%ほどの部分を占
めるようにする。At this time, the deposition of the amorphous silicon film (8) containing oxygen is performed by using SiH which is a Silane gas.
4 and N 2 O gas are used to deposit at a low temperature of 550 ° C. to 700 ° C., and the oxygen density (Oxygen Concentration) occupies about 10% to 30% of amorphous silicon molecules.
【0007】次いで、図2は850℃乃至1150℃の
温度下で5時間熱処理すると、非晶質状態のシリコン膜
を結晶化(ポリシリコン化)されながら、結晶化された
シリコン(9)間の結晶格子間にSiO2 又はSiOx
形態の酸化副産物(10)が形成される。この際、熱処
理はN2 ガス雰囲気下で実施する。Then, as shown in FIG. 2, when a heat treatment is performed at a temperature of 850 ° C. to 1150 ° C. for 5 hours, the amorphous silicon film is crystallized (polysiliconized) while the crystallized silicon (9) is removed. SiO 2 or SiO x between crystal lattices
A form of oxidation by-product (10) is formed. At this time, the heat treatment is performed in an N 2 gas atmosphere.
【0008】最後に、図3は上記酸化副産物(10)を
HF溶液で湿式除去して多孔質ポリシリコン形態の結晶
化されたシリコン(9)のみで電荷貯蔵電極(9)を完
成する。Finally, referring to FIG. 3, the oxidation by-product (10) is wet-removed with an HF solution to complete the charge storage electrode (9) only with the crystallized silicon (9) in the form of porous polysilicon.
【0009】[0009]
【発明の効果】上記の通りなる本発明は、コンタクトホ
ール内部に酸化副産物が形成されたポリシリコン膜(結
晶化されたシリコン)を形成した後、酸化副産物を除去
して多孔質ポリシリコン膜で電荷貯蔵電極を形成するこ
とにより、素子の高集積化に因り制限された狭い面積で
電荷貯蔵電極の有効表面積を増大させ、それによりキャ
パシタンス増大をもたらす効果がある。According to the present invention as described above, after forming a polysilicon film (crystallized silicon) in which an oxidation byproduct is formed inside a contact hole, the oxidation byproduct is removed to form a porous polysilicon film. The formation of the charge storage electrode has an effect of increasing the effective surface area of the charge storage electrode in a small area limited due to high integration of the device, thereby increasing the capacitance.
【図1】本発明の一実施例に係るコンタクトホール内に
電荷貯蔵電極用ポリシリコン膜を形成する方法を示す断
面図である。FIG. 1 is a cross-sectional view showing a method of forming a polysilicon film for a charge storage electrode in a contact hole according to an embodiment of the present invention.
【図2】図1の次の工程の断面図である。FIG. 2 is a sectional view of a step subsequent to that of FIG.
【図3】最終工程の断面図である。FIG. 3 is a sectional view of a final step.
1 シリコン基板 2 フィールド酸化膜 3 接合領域 4 ワードライン 5 層間酸化膜 6 ビットライン 7 平坦化絶縁膜 8 酸素が内包された非晶質シリコン膜 9 結晶化されたシリコン 1 Silicon Substrate 2 Field Oxide Film 3 Junction Area 4 Wordline 5 Interlayer Oxide Film 6 Bitline 7 Planarization Insulating Film 8 Amorphous Silicon Film 9 Including Oxygen 9 Crystallized Silicon
Claims (6)
いて;キャパシタの電荷貯蔵電極コンタクトホールを形
成する段階;酸素が内包された非晶質シリコン膜を蒸着
する段階;熱処理して上記酸素が内包された非晶質シリ
コン膜を結晶化しながら酸化副産物を形成する段階;及
び上記酸化副産物を除去する段階を含み、 上記酸化副産物が除去された結晶化されたシリコン膜で
電荷貯蔵電極を形成することを特徴とするキャパシタの
製造方法。1. A method of manufacturing a capacitor of a semiconductor device; a step of forming a charge storage electrode contact hole of a capacitor; a step of depositing an oxygen-containing amorphous silicon film; a heat treatment in which the oxygen is included. Forming an oxidation byproduct while crystallizing the amorphous silicon film; and removing the oxidation byproduct, wherein the charge storage electrode is formed of the crystallized silicon film from which the oxidation byproduct is removed. Manufacturing method of capacitor.
の蒸着はサイレンガスとN2 Oガスを用いることを特徴
とする請求項1記載のキャパシタの製造方法。2. The method of manufacturing a capacitor according to claim 1, wherein the vapor deposition of the oxygen-containing amorphous silicon film uses a siren gas and an N 2 O gas.
の蒸着は、550℃乃至700℃の低温でなることを特
徴とする請求項2記載のキャパシタの製造方法。3. The method for manufacturing a capacitor according to claim 2, wherein the vapor deposition of the amorphous silicon film containing oxygen is performed at a low temperature of 550 ° C. to 700 ° C.
温度下で成ることを特徴とする請求項3記載のキャパシ
タの製造方法。4. The method of manufacturing a capacitor according to claim 3, wherein the heat treatment is performed at a temperature of 850 ° C. to 1150 ° C.
の酸素密度は、10%乃至30%であることを特徴とす
る請求項1記載のキャパシタの製造方法。5. The method of manufacturing a capacitor according to claim 1, wherein the oxygen density of the amorphous silicon film containing oxygen is 10% to 30%.
ことを特徴とする請求項1記載のキャパシタの製造方
法。6. The method of manufacturing a capacitor according to claim 1, wherein the removal of the oxidation byproducts is performed by wet etching.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940035431A KR960026821A (en) | 1994-12-20 | 1994-12-20 | Capacitor Manufacturing Method |
| KR1994P35431 | 1994-12-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08255880A true JPH08255880A (en) | 1996-10-01 |
| JP2727434B2 JP2727434B2 (en) | 1998-03-11 |
Family
ID=19402524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7332726A Expired - Lifetime JP2727434B2 (en) | 1994-12-20 | 1995-11-28 | Method for manufacturing capacitor |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2727434B2 (en) |
| KR (1) | KR960026821A (en) |
| CN (1) | CN1135655A (en) |
| GB (1) | GB2296380A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6462369B1 (en) | 1999-05-12 | 2002-10-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory cell with porous cylindrical electrode |
| US7109081B2 (en) | 2003-11-29 | 2006-09-19 | Samsung Electronics Co., Ltd. | Capacitor for semiconductor device and method of forming the same |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2817645B2 (en) * | 1995-01-25 | 1998-10-30 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| KR100537193B1 (en) * | 2000-08-31 | 2005-12-16 | 주식회사 하이닉스반도체 | Method for manufacturing capacitor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2130009B (en) * | 1982-11-12 | 1986-04-03 | Rca Corp | Polycrystalline silicon layers for semiconductor devices |
| JP2679433B2 (en) * | 1991-03-14 | 1997-11-19 | 日本電気株式会社 | Method for forming polycrystalline silicon film |
| JPH04286152A (en) * | 1991-03-14 | 1992-10-12 | Sony Corp | Manufacture of semiconductor memory |
| JP2508948B2 (en) * | 1991-06-21 | 1996-06-19 | 日本電気株式会社 | Method for manufacturing semiconductor device |
-
1994
- 1994-12-20 KR KR1019940035431A patent/KR960026821A/en not_active Ceased
-
1995
- 1995-11-28 JP JP7332726A patent/JP2727434B2/en not_active Expired - Lifetime
- 1995-12-15 GB GB9525651A patent/GB2296380A/en not_active Withdrawn
- 1995-12-20 CN CN95120366A patent/CN1135655A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6462369B1 (en) | 1999-05-12 | 2002-10-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory cell with porous cylindrical electrode |
| US6541337B2 (en) | 1999-05-12 | 2003-04-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device and manufacturing method thereof |
| US7109081B2 (en) | 2003-11-29 | 2006-09-19 | Samsung Electronics Co., Ltd. | Capacitor for semiconductor device and method of forming the same |
| US7358557B2 (en) | 2003-11-29 | 2008-04-15 | Samsung Electronics Co., Ltd. | Capacitor for semiconductor device and method of forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2296380A (en) | 1996-06-26 |
| JP2727434B2 (en) | 1998-03-11 |
| CN1135655A (en) | 1996-11-13 |
| KR960026821A (en) | 1996-07-22 |
| GB9525651D0 (en) | 1996-02-14 |
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