JPH08316374A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08316374A JPH08316374A JP7116805A JP11680595A JPH08316374A JP H08316374 A JPH08316374 A JP H08316374A JP 7116805 A JP7116805 A JP 7116805A JP 11680595 A JP11680595 A JP 11680595A JP H08316374 A JPH08316374 A JP H08316374A
- Authority
- JP
- Japan
- Prior art keywords
- mounting surface
- semiconductor element
- resin composition
- wiring board
- molding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
(57)【要約】
【構成】半導体素子搭載面を有するプリント配線基板3
の搭載面裏面に、はんだボール4をグリッド状に配した
実装面を有し、実装面と電気的に接続されている半導体
素子搭載面に半導体素子を搭載固着し、半導体素子電極
部分と多層プリント配線基板とが電気的に接続されてお
り、半導体素子と電気接続部を含む半導体素子搭載面の
少なくとも一部分が樹脂組成物6で成形かつ封止されて
いる構造を有する半導体装置において、封止層の成形を
封止樹脂組成物6のガラス転移温度以下の温度で行う。
【効果】成形温度以上のガラス転移温度を有する樹脂組
成物で封止されているため成形時の収縮率が小さく、パ
ッケージの反り量が小さく、はんだボール搭載面の平坦
性に優れる。
(57) [Abstract] [Structure] Printed wiring board 3 having semiconductor element mounting surface
Has a mounting surface on which solder balls 4 are arranged in a grid pattern on the back surface of the mounting surface, and the semiconductor element is mounted and fixed on the mounting surface of the semiconductor element electrically connected to the mounting surface. In a semiconductor device having a structure in which a wiring board is electrically connected and at least a part of a semiconductor element mounting surface including a semiconductor element and an electrical connection portion is molded and sealed with a resin composition 6, a sealing layer Is molded at a temperature not higher than the glass transition temperature of the encapsulating resin composition 6. [Effect] Since the resin composition is sealed with a resin composition having a glass transition temperature equal to or higher than the molding temperature, the shrinkage rate during molding is small, the amount of package warpage is small, and the solder ball mounting surface is excellent in flatness.
Description
【0001】[0001]
【産業上の利用分野】本発明は実装面にはんだバンプを
有し半導体素子の搭載面を樹脂封止したボール・グリッ
ド・アレイ(BGA)型半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ball grid array (BGA) type semiconductor device having a solder bump on a mounting surface and a resin mounting surface for mounting a semiconductor element.
【0002】[0002]
【従来の技術】近年の電子機器の小型化,高性能化にと
もない、電子機器を構成する半導体装置及びそれを実装
する多層プリント配線基板には、小型薄型化,高性能
化,高速化,高信頼性化が求められている。例えば、半
導体装置は、小型薄型化の要求からピン挿入型のパッケ
ージから表面実装型のパッケージへの移行が進み、半導
体素子をプリント基板へ直接実装するような、ベアチッ
プ実装と呼ばれる実装方法も研究されている。またこれ
らの実装密度を向上するための手法として、COB(Ch
ip on board),FC(Flip chip),TCP(Tape carrie
r package)などが知られている。2. Description of the Related Art With the recent trend toward miniaturization and high performance of electronic equipment, semiconductor devices constituting electronic equipment and multilayer printed wiring boards for mounting the same have been made smaller, thinner, higher performance, higher speed and higher performance. Reliability is required. For example, semiconductor devices are shifting from pin-insertion packages to surface-mount packages due to the demand for smaller and thinner semiconductor devices, and a mounting method called bare chip mounting, in which semiconductor elements are directly mounted on a printed circuit board, has also been studied. ing. Also, as a method for improving the packaging density of these, COB (Ch
ip on board), FC (Flip chip), TCP (Tape carrie)
r package) is known.
【0003】高密度実装化,多ピン化,高速化の要請か
ら、リード間隔の狭ピッチ化しパッケージの四方向にリ
ードを有するクアッド・フラット・パッケージ(QFP
パッケージ),パッケージの実装面全体に接続端子を設
けたピン・グリッド・アレイ型パッケージ(PGAパッ
ケージ)及びはんだボール・グリッド・アレイ型パッケ
ージ(BGAパッケージ)などが開発されている。Due to demands for high-density mounting, high pin count, and high speed, the quad flat package (QFP) has a narrow lead pitch and has leads in four directions.
Package), a pin grid array type package (PGA package) in which connection terminals are provided on the entire mounting surface of the package, and a solder ball grid array type package (BGA package).
【0004】BGAパッケージの基本的な構造は、USP5
216278 ,特開平6−202955号,特願平4−508695号,特
開昭62−277753 号公報に開示されている。BGAでは
キャリア基板に半導体素子を直接搭載し、この裏面には
んだボールをグリッド状に配し、半導体搭載面を封止樹
脂組成物により片面モールドした構造である。The basic structure of the BGA package is USP5
216278, JP-A-6-202955, Japanese Patent Application No. 4-508695, and JP-A-62-177753. The BGA has a structure in which a semiconductor element is directly mounted on a carrier substrate, solder balls are arranged in a grid on the back surface, and the semiconductor mounting surface is molded on one side with a sealing resin composition.
【0005】封止材により片面モールドされている構造
を有するBGAパッケージにおいては、キャリア基板と
呼ばれる多層プリント配線基板上に半導体素子が直接搭
載されるため、半導体素子と多層プリント配線基板、さ
らに封止樹脂との間の熱膨張係数のミスマッチにより成
形時にパッケージが反る問題があった。この反り量は実
装基板へのはんだリフロー時に大きくなり、実装性が問
題となる。パッケージの反り量は成形時でも全体で60
μm以下に抑えることが望ましい。In a BGA package having a structure in which one side is molded with a sealing material, semiconductor elements are mounted directly on a multilayer printed wiring board called a carrier substrate, so that the semiconductor element, the multilayer printed wiring board, and further sealing. There was a problem that the package warps during molding due to a mismatch in the coefficient of thermal expansion with the resin. This amount of warpage becomes large during solder reflow on the mounting board, and mountability becomes a problem. The total warpage of the package is 60 even during molding.
It is desirable to keep the thickness below μm.
【0006】これを防止するためには、半導体素子と熱
膨張係数が等しいキャリア基板を用いることが有効と考
えられるが、この場合、キャリア基板とそれを実装する
プリント配線基板の間のはんだボール部に応力が集中す
るようになるため、はんだ接合部の接続信頼性が低下す
る。In order to prevent this, it is considered effective to use a carrier substrate having the same coefficient of thermal expansion as that of the semiconductor element. In this case, the solder ball portion between the carrier substrate and the printed wiring board on which it is mounted is used. Since stress concentrates on the solder joint, the connection reliability of the solder joint is reduced.
【0007】BGAパッケージは、上記のように異なる
熱膨張係数を有する部材から構成されているため、パッ
ケージ成形時の反りの問題,実装後のはんだボール部の
接続信頼性の問題があった。Since the BGA package is composed of members having different thermal expansion coefficients as described above, there are problems of warpage during molding of the package and connection reliability of the solder ball portion after mounting.
【0008】[0008]
【発明が解決しようとする課題】本発明の目的は、片面
モールドされたBGAパッケージの反り量を低減するこ
とにある。SUMMARY OF THE INVENTION It is an object of the present invention to reduce the amount of warpage of a single sided BGA package.
【0009】[0009]
【課題を解決するための手段】BGAパッケージの反り
量は、封止材やキャリア基板の物性値の他、封止材層や
キャリア基板の厚さなどパッケージ外形により影響を受
ける。このためBGAの開発にはこれらの点を十分に考
慮し設計が行われている。The amount of warpage of a BGA package is affected not only by the physical properties of the encapsulant and carrier substrate, but also by the package outline such as the thickness of the encapsulant layer and the carrier substrate. For this reason, these points are fully taken into consideration when designing the BGA.
【0010】本発明者は、鋭意検討を重ねた結果、片面
モールドされたBGAパッケージにおいて、反り量を低
減する為の方法を見いだした。以下にその方法を詳細に
説明する。As a result of intensive studies, the present inventor has found a method for reducing the amount of warpage in a single-sided molded BGA package. The method will be described in detail below.
【0011】BGAパッケージの反りは、パッケージ成
形時の降温過程において半導体搭載面に形成された封止
層とキャリア基板との間の熱収縮量の差が大きな原因で
ある。封止層やキャリア基板の弾性率も影響するが、大
部分は熱収縮量の差が原因となっている。The warp of the BGA package is largely due to the difference in the amount of heat shrinkage between the sealing layer formed on the semiconductor mounting surface and the carrier substrate during the temperature reduction process during the molding of the package. The elastic modulus of the sealing layer and the carrier substrate also influences, but most of them are caused by the difference in the amount of heat shrinkage.
【0012】一般に封止材料に用いられる樹脂組成物で
は、低熱収縮率化に対し低熱膨張成分であるシリカフィ
ラを高充填する方法がとられる。この方法はとても効果
が大きく、BGAパッケージでもパッケージ外形が小さ
な場合にはフィラの配合量を調整することにより反り量
を低減することができる。しかし、パッケージのピン数
が300ピン以上の大型パッケージになるとフィラの高
配合では限界がある。また、フィラの高充填は成形時の
粘度上昇,封止層の弾性率上昇を招き、パッケージ成形
に不都合である。In general, for a resin composition used as a sealing material, a method of filling a silica filler, which is a low thermal expansion component, with a high degree of filling is used in order to reduce the thermal shrinkage. This method is very effective, and even in the case of a BGA package, when the package outer shape is small, the warp amount can be reduced by adjusting the compounding amount of the filler. However, there is a limit to the high content of filler in a large package with 300 or more pins. Further, high filling of the filler causes an increase in viscosity during molding and an increase in elastic modulus of the sealing layer, which is inconvenient for package molding.
【0013】本発明者は鋭意検討を重ねた結果、封止層
のガラス転移温度をパッケージ成形温度以上に高めるこ
とにより反りを低減できることを見いだした。封止層の
熱収縮率は、成形温度からガラス転移温度までとガラス
転移温度から室温まででは異なり、一般的な有機材料を
ベースとして用いた場合、ガラス転移温度以上での収縮
率はガラス転移温度以下のものに比較し、3倍から5倍
大きくなる。このためガラス転移温度を成形温度程度ま
で高めるか、またはそれ以上にすることにより熱収縮量
を小さくすることができる。この場合、フィラの配合量
は、全体の熱収縮量を調整するために用いることが望ま
しい。As a result of intensive studies, the present inventor has found that the warp can be reduced by increasing the glass transition temperature of the sealing layer to the package molding temperature or higher. The heat shrinkage rate of the sealing layer differs from the molding temperature to the glass transition temperature and from the glass transition temperature to room temperature.When using a general organic material as a base, the shrinkage rate at the glass transition temperature or higher is the glass transition temperature. 3 to 5 times larger than the following: Therefore, the amount of heat shrinkage can be reduced by raising the glass transition temperature to about the molding temperature or higher. In this case, it is desirable to use the amount of the filler to adjust the total amount of heat shrinkage.
【0014】その他、本発明の封止樹脂組成物で用いら
れるエポキシ樹脂は、ガラス転移温度を成形温度以上に
高める事ができて、かつ一分子中にエポキシ樹脂を複数
個もち、半導体封止用樹脂として一般的に使用されるも
のであればいかなるものであってもよい。このようなエ
ポキシ樹脂は、ビスフェノールA,FまたはS型エポキ
シ樹脂,フェノールノボラック型エポキシ樹脂,クレゾ
ールノボラック型エポキシ樹脂、また分子中にビフェニ
ル骨格やナフタレン骨格,ジシクロペンタジエン骨格を
有する二官能以上のエポキシ樹脂,脂環式エポキシ樹
脂、また以上のエポキシ樹脂を臭素化したエポキシ樹脂
などが挙げられる。本発明では、これらを単独あるいは
数種類混合して使用される。In addition, the epoxy resin used in the encapsulating resin composition of the present invention is capable of increasing the glass transition temperature above the molding temperature and has a plurality of epoxy resins in one molecule, and is used for encapsulating semiconductors. Any resin may be used as long as it is generally used as a resin. Such epoxy resins include bisphenol A, F or S type epoxy resins, phenol novolac type epoxy resins, cresol novolac type epoxy resins, and bifunctional or higher functional epoxy having a biphenyl skeleton, a naphthalene skeleton, or a dicyclopentadiene skeleton in the molecule. Examples thereof include resins, alicyclic epoxy resins, and epoxy resins obtained by brominated the above epoxy resins. In the present invention, these are used alone or as a mixture of several kinds.
【0015】本発明において、フェノール性水酸基を有
する硬化剤は、一分子中にフェノール性の水酸基を複数
個もち、半導体封止用樹脂として一般的に使用されるも
のであればいかなるものであってもよい。このような硬
化剤として、ビスフェノールA,FまたはS,フェノー
ルノボラック,クレゾールノボラック、また、分子中に
ビフェニル骨格をもつビフェノール,ナフタレン骨格を
有するもの、ジシクロペンタジエン骨格を有するもの、
また以上の樹脂の共重合体、または数種類の混合物が使
用される。これらは樹脂の反応性,流動性などの成形性
と硬化物の吸湿率,力学物性などの諸物性に応じて使用
される。In the present invention, the curing agent having a phenolic hydroxyl group is any one as long as it has a plurality of phenolic hydroxyl groups in one molecule and is generally used as a semiconductor encapsulating resin. Good. As such a curing agent, bisphenol A, F or S, phenol novolac, cresol novolac, biphenol having a biphenyl skeleton in the molecule, those having a naphthalene skeleton, those having a dicyclopentadiene skeleton,
Further, copolymers of the above resins or a mixture of several kinds are used. These are used according to various properties such as resin moldability such as reactivity and fluidity, and moisture absorption rate and mechanical properties of the cured product.
【0016】本発明に用いられる封止樹脂組成物には、
硬化反応を促進させるため硬化促進剤が添加される。本
発明で用いられる硬化促進剤はエポキシ樹脂と硬化剤の
硬化反応を促進するものなら特に限定されるものではな
い。通常は、エポキシ樹脂組成物の保存安定性や成形
性,硬化後の電気特性などが良好な、トリフェニルフォ
スフィン,トリフェニルフォスフォニウム−トリフェニ
ルボレート,テトラフェニルフォスフォニウム−テトラ
フェニルボレート、及びこれらの誘導体などの分子中に
燐を含有するもの、またトリエチレンジアミン,ジアミ
ノジフェニルメタン、1,8−ジアザビシクロ(5,
4,0)−ウンデセン,イミダゾール及びその誘導体な
どのアミン系のもの、BF3,スルホニウム塩などが、
一種類、あるいは二種類以上をエポキシ樹脂に添加され
用いられる。添加量はエポキシ樹脂組成物の成形性や硬
化物の物性にあわせ任意に決めることができる。ガラス
転移温度を高める目的ではアミン系、特にイミダゾール
系の硬化促進剤が好適である。本発明のエポキシ樹脂成
形材料では上記の素材の他必要に応じ、充填剤,離型
剤,着色剤,カップリング剤,可とう化剤,難燃剤など
を添加して用いる。充填剤はエポキシ成形材料の熱膨張
係数を小さくする目的で、また、強度を高めるために用
いられ、タルク,クレー,シリカ,炭酸カルシウム,水
酸化アルミニウム,水酸化マグネシウム,ガラス繊維,
セラミック繊維などの無機質充填剤全般を用いることが
できる。The encapsulating resin composition used in the present invention includes
A curing accelerator is added to accelerate the curing reaction. The curing accelerator used in the present invention is not particularly limited as long as it accelerates the curing reaction between the epoxy resin and the curing agent. Usually, storage stability and moldability of an epoxy resin composition, good electrical properties after curing, triphenylphosphine, triphenylphosphonium-triphenylborate, tetraphenylphosphonium-tetraphenylborate, And those containing phosphorus in the molecule such as derivatives thereof, triethylenediamine, diaminodiphenylmethane, 1,8-diazabicyclo (5,5)
Amine compounds such as 4,0) -undecene, imidazole and their derivatives, BF3, sulfonium salts, etc.
One kind or two or more kinds are used by adding to the epoxy resin. The addition amount can be arbitrarily determined according to the moldability of the epoxy resin composition and the physical properties of the cured product. For the purpose of increasing the glass transition temperature, amine-based, particularly imidazole-based curing accelerators are suitable. In the epoxy resin molding material of the present invention, in addition to the above-mentioned materials, a filler, a release agent, a coloring agent, a coupling agent, a softening agent, a flame retardant and the like are added and used as necessary. The filler is used for the purpose of reducing the thermal expansion coefficient of the epoxy molding material and for increasing the strength, and includes talc, clay, silica, calcium carbonate, aluminum hydroxide, magnesium hydroxide, glass fiber,
All inorganic fillers such as ceramic fibers can be used.
【0017】充填剤の配合量は50重量%〜95重量%
が適当で、50重量%未満では熱膨張係数の低減,強度
の向上に対して十分な効果が得られない。また、95重
量%を越えて配合すると、充填剤の最密充填密度がエポ
キシ樹脂マトリックスの配合量を下回る為、成形材料の
調製が困難となり、また調製後の粘度が非常に高くな
り、成形性が低下する。熱収縮率を調整するためには8
0〜90重量%が適当である。The blending amount of the filler is 50% by weight to 95% by weight.
However, if it is less than 50% by weight, a sufficient effect cannot be obtained for reducing the thermal expansion coefficient and improving the strength. Also, if the content exceeds 95% by weight, the closest packing density of the filler will be less than the content of the epoxy resin matrix, making it difficult to prepare a molding material, and the viscosity after preparation will be extremely high, resulting in moldability. Is reduced. 8 to adjust the heat shrinkage
0 to 90% by weight is suitable.
【0018】離型剤は成形金型からの離型を容易にする
もので、カルナバワックス,モンタン酸系ワックス,ポ
リオレフィン系ワックスを単独で用いるか、これらを併
用して用いる。添加量は、全量の0.01〜5重量%が
好ましい。すなわち0.01%未満では離型性に効果が
なく、また5%をこえるとリードフレームやシリコンチ
ップとの接着性が低下するからである。着色剤はカーボ
ンブラックを用いることが望ましい。硬化物の強靭化,
低弾性率化のため配合される、可とう化剤はエポキシ樹
脂と非相溶のアミノ基またはエポキシ基,カルボキシル
基末端のブタジエン・アクリロニトリル系共重合体、ま
た、末端または側鎖アミノ基,水酸基,エポキシ基,カ
ルボキシル基変性シリコーン樹脂系可とう化剤などが用
いられる。上記材料を配合,混合,混練,粉砕しさらに
必要に応じ造粒しエポキシ樹脂成形材料を得る。混練は
一般的には、熱ロールや押し出し機などによって行う。
本発明の半導体装置は、このように得られたエポキシ樹
脂組成物を用いてキャリア基板上の半導体チップを封止
することにより得られる。その製造方法は、低圧トラン
スファ成形が、通常、用いられるが、場合によっては、
圧縮成形,注型などの方法によっても可能である。ま
た、半導体装置の信頼性を向上するため、エポキシ樹脂
組成物による成形後、150℃以上の温度で所定時間ア
フタキュアを行うことが望ましい。The release agent facilitates release from the molding die, and carnauba wax, montanic acid type wax, polyolefin type wax may be used alone or in combination. The addition amount is preferably 0.01 to 5% by weight of the total amount. That is, if it is less than 0.01%, the releasability is not effective, and if it exceeds 5%, the adhesion to the lead frame or the silicon chip is deteriorated. It is desirable to use carbon black as the colorant. Toughened cured products,
The softening agent that is blended to lower the elastic modulus is an amino group or epoxy group that is incompatible with the epoxy resin, a butadiene-acrylonitrile copolymer having a carboxyl group terminal, or an amino group or hydroxyl group at the terminal or side chain. An epoxy group- or carboxyl group-modified silicone resin-based flexible agent is used. The above materials are blended, mixed, kneaded and pulverized, and further granulated as necessary to obtain an epoxy resin molding material. The kneading is generally performed with a hot roll or an extruder.
The semiconductor device of the present invention can be obtained by sealing a semiconductor chip on a carrier substrate with the epoxy resin composition thus obtained. Low pressure transfer molding is usually used as the manufacturing method, but in some cases,
It is also possible by methods such as compression molding and casting. Further, in order to improve the reliability of the semiconductor device, it is desirable to perform aftercure at a temperature of 150 ° C. or higher for a predetermined time after molding with the epoxy resin composition.
【0019】本発明のキャリア基板であるプリント配線
基板の構成材料は、有機物と無機物の混合物または無機
物が単独で用いることができる。有機物はエポキシ樹
脂,マレイミド樹脂,ポリイミド樹脂,シアネート樹
脂,フェノール樹脂などの熱硬化性樹脂が適している。
また、これらとともに用いる充填材は、アラミド繊維,
フッソ系樹脂,紙などの有機物の他、Sガラスクロス,
Eガラスクロス,Dガラスクロス,Hガラスクロス,A
ガラスクロス,Cガラスクロス,ARガラスクロス,L
ガラスクロス,石英繊維などの繊維状の無機材料、また
シリカ,アルミナ、などの粉末状の充填材料も併用して
用いることができる。無機材料マトリックスはアルミナ
セラミック,セラミック−エポキシ樹脂複合体,窒化ア
ルミニウム,低融点ガラスなどが適している。無機物の
充填材は主にプリント配線基板の熱膨張係数を調整する
ために用いられる為、ガラスクロス単独か、または熱膨
張係数の小さなシリカとガラスクロスとの併用が好適で
ある。この時、マトリックスの有機材料は成形性,電気
特性のバランスからエポキシ樹脂が好適である。しかし
これらの組成は上記の材料に限定されるものではない。As the constituent material of the printed wiring board which is the carrier substrate of the present invention, a mixture of an organic substance and an inorganic substance or an inorganic substance can be used alone. Suitable organic materials are thermosetting resins such as epoxy resin, maleimide resin, polyimide resin, cyanate resin, and phenol resin.
In addition, the filler used with these is aramid fiber,
In addition to fluorine resin, organic materials such as paper, S glass cloth,
E glass cloth, D glass cloth, H glass cloth, A
Glass cloth, C glass cloth, AR glass cloth, L
Fibrous inorganic materials such as glass cloth and quartz fibers, and powdery filling materials such as silica and alumina can also be used together. As the inorganic material matrix, alumina ceramic, ceramic-epoxy resin composite, aluminum nitride, low melting point glass, etc. are suitable. Since the inorganic filler is mainly used to adjust the thermal expansion coefficient of the printed wiring board, it is preferable to use glass cloth alone or to use silica and glass cloth having a small thermal expansion coefficient in combination. At this time, as the organic material of the matrix, epoxy resin is preferable from the viewpoint of balance between moldability and electric characteristics. However, these compositions are not limited to the above materials.
【0020】本発明における半導体装置の成形には、ま
ずキャリア基板のシリコンチップ搭載面にシリコンチッ
プをダイアタッチメントを介して接着し、その後、チリ
コンチップとキャリア基板との間を金ワイヤボンディン
グにより電気的に接続する。シリコンチップを搭載した
キャリア基板は、チップ搭載面を所定の温度で低圧トラ
ンスファー成形により封止した後、成形温度以上の温度
で数時間後硬化する事が望ましい。後硬化後のキャリア
基板の実装面にはんだボールを取付け半導体装置を得る
ことができる。In the molding of the semiconductor device according to the present invention, first, a silicon chip is bonded to the silicon chip mounting surface of the carrier substrate through a die attachment, and then the chilicon chip and the carrier substrate are electrically bonded by gold wire bonding. Connect to. It is desirable that the carrier substrate on which the silicon chip is mounted is sealed on the chip mounting surface by low-pressure transfer molding at a predetermined temperature and then post-cured at a temperature higher than the molding temperature for several hours. Solder balls can be attached to the mounting surface of the carrier substrate after post-curing to obtain a semiconductor device.
【0021】量産性,作業性を高める目的で、キャリア
基板を支持するためのリードフレームを設けたものも用
いることができる。For the purpose of improving mass productivity and workability, a lead frame for supporting a carrier substrate may be used.
【0022】[0022]
【作用】封止層のガラス転移温度をパッケージ成形温度
以上に高めることや、成形温度を低くすることにより反
り量を低減することができる。これは、反り量は熱収縮
率の差と温度差(成形温度−室温)の積に対応するた
め、成形温度を室温に近付ける事により温度差を低減し
反り量を小さくすることが可能である。The amount of warpage can be reduced by raising the glass transition temperature of the sealing layer to the package molding temperature or higher or by lowering the molding temperature. This is because the amount of warp corresponds to the product of the difference in thermal shrinkage and the temperature difference (molding temperature-room temperature), so that it is possible to reduce the temperature difference and decrease the amount of warp by bringing the molding temperature close to room temperature. .
【0023】本発明における、化1で示すナフタレン型
多官能エポキシ樹脂や化3に示すトリスヒドロキシフェ
ニルメタン型多官能エポキシ樹脂と化4に示すフェノー
ルノボラック,化5に示すトリスヒドロキシフェニルメ
タン型多官能フェノール硬化剤を封止樹脂組成物のベー
ス樹脂として用いることにより、100〜150℃での
低温での成形が可能である。In the present invention, the naphthalene-type polyfunctional epoxy resin shown in Chemical formula 1, the trishydroxyphenylmethane-type polyfunctional epoxy resin shown in Chemical formula 3, the phenol novolac shown in Chemical formula 4, and the trishydroxyphenylmethane-type polyfunctional resin shown in Chemical formula 5 are used. By using the phenol curing agent as the base resin of the encapsulating resin composition, molding at a low temperature of 100 to 150 ° C. is possible.
【0024】[0024]
【化5】 Embedded image
【0025】また、これらの樹脂系では通常の成形温度
で成形した場合ガラス転移温度が高くなるため熱収縮量
が減少し、反り量を大幅に低下させることができる。Further, in these resin systems, when molded at a normal molding temperature, the glass transition temperature becomes high, so that the amount of heat shrinkage decreases, and the amount of warpage can be greatly reduced.
【0026】プリント配線基板の熱膨張係数を変えるた
めにはガラスクロス樹脂に対する樹脂の含量を変えた
り、樹脂成分に可とう性の粒子を導入し、ガラス成分の
寄与を大きくすることにより熱膨張係数を調整する方法
を適用することができる。樹脂成分のガラス転移温度は
好ましくは、パッケージ成形温度以上であることが望ま
しい。In order to change the coefficient of thermal expansion of the printed wiring board, the coefficient of thermal expansion can be increased by changing the resin content relative to the glass cloth resin or introducing flexible particles into the resin component to increase the contribution of the glass component. A method of adjusting can be applied. The glass transition temperature of the resin component is preferably the package molding temperature or higher.
【0027】[0027]
【実施例】以下、本発明について実施例に従い具体的に
説明する。EXAMPLES The present invention will be specifically described below with reference to examples.
【0028】<実施例1〜6,比較例1〜2>下記に示
すエポキシ樹脂並びにフェノール樹脂硬化剤、及び硬化
促進剤としてトリフェニルフォスフィン,充填剤として
平均粒径8μmの溶融シリカの破砕粉と平均粒径28μ
mの球形溶融シリカをそれぞれ3/7の割合で混合した
ものを用い、難燃助剤として三酸化アンチモン,カップ
リング剤としてエポキシシラン,離型剤としてモンタン
酸エステル,着色剤としてカーボンブラックを用い、表
1に示す配合組成でエポキシ樹脂成形材料を作製した。Examples 1 to 6 and Comparative Examples 1 to 2 Epoxy resin and phenol resin curing agents shown below, triphenylphosphine as a curing accelerator, and crushed powder of fused silica having an average particle size of 8 μm as a filler. And average particle size 28μ
m spherical sphere fused silica mixed at a ratio of 3/7, antimony trioxide as a flame retardant aid, epoxysilane as a coupling agent, montanic acid ester as a release agent, carbon black as a colorant An epoxy resin molding material was prepared with the composition shown in Table 1.
【0029】[0029]
【表1】 [Table 1]
【0030】素材の混練は二軸の熱ロール(65〜85
℃)を用い、10分間行った。The materials are kneaded by using a biaxial hot roll (65-85
C.) for 10 minutes.
【0031】エポキシ樹脂 (a)エポキシ当量:163g/eqEpoxy resin (a) Epoxy equivalent: 163 g / eq
【0032】[0032]
【化6】 [Chemical 6]
【0033】(b)エポキシ当量:176g/eq(B) Epoxy equivalent: 176 g / eq
【0034】[0034]
【化7】 [Chemical 7]
【0035】(c)エポキシ当量:195g/eq(C) Epoxy equivalent: 195 g / eq
【0036】[0036]
【化8】 Embedded image
【0037】フェノール樹脂硬化剤 (d)水酸基当量:106g/eqPhenolic resin curing agent (d) Hydroxyl equivalent: 106 g / eq
【0038】[0038]
【化9】 [Chemical 9]
【0039】(e)水酸基当量:98g/eq(E) Hydroxyl equivalent: 98 g / eq
【0040】[0040]
【化10】 [Chemical 10]
【0041】次に、本発明を適用した半導体装置の構造
を図面を用いて説明する。Next, the structure of the semiconductor device to which the present invention is applied will be described with reference to the drawings.
【0042】図1は半導体素子であるシリコンチップ1
をダイアタッチメント2を介してキャリア基板3に固着
した後、素子上の電極部とキャリア基板3を金ワイヤ7
で電気的に接続した後、素子側のキャリア基板面を封止
樹脂組成物6で封止したBGA型の半導体装置である。FIG. 1 shows a silicon chip 1 which is a semiconductor element.
After being fixed to the carrier substrate 3 via the die attachment 2, the electrode portion on the element and the carrier substrate 3 are connected to the gold wire 7
Is a BGA type semiconductor device in which the surface of the carrier substrate on the element side is sealed with the sealing resin composition 6 after being electrically connected.
【0043】図2は半導体素子であるシリコンチップ1
をダイアタッチメント2とリードフレーム9を介してキ
ャリア基板3に固着し、素子上の電極部とキャリア基板
3を金ワイヤ7で電気的に接続した後、素子側のキャリ
ア基板面を封止樹脂組成物6で封止したBGA型の半導
体装置である。FIG. 2 shows a silicon chip 1 which is a semiconductor element.
Is fixed to the carrier substrate 3 via the die attachment 2 and the lead frame 9, and the electrode portion on the element and the carrier substrate 3 are electrically connected by the gold wire 7. Then, the carrier substrate surface on the element side is sealed with a resin composition. It is a BGA type semiconductor device sealed with an object 6.
【0044】図3はパッケージが反った場合の様子と、
反り量の測定点11,反り量10を示した図である。FIG. 3 shows how the package is warped,
It is the figure which showed the measurement point 11 of the amount of curvatures, and the amount 10 of curvatures.
【0045】表中の特性測定は以下の方法で行った。The characteristics in the table were measured by the following methods.
【0046】(1)ガラス転移温度並びに線膨張係数:
熱物理試験機を用い、昇温速度5℃/min で測定した。(1) Glass transition temperature and linear expansion coefficient:
Using a thermophysical tester, measurement was performed at a temperature rising rate of 5 ° C / min.
【0047】(2)パッケージ反り量:成形後のパッケ
ージの実装面の反り量を焦点深度計を用いて測定した。
反り量は、パッケージ中心を基準としたときの対角方向
のパッケージ端部の変位量で表した。(2) Package warp amount: The warp amount of the mounting surface of the package after molding was measured using a depth of focus meter.
The amount of warpage is represented by the amount of displacement of the package end portion in the diagonal direction with respect to the center of the package.
【0048】BGAパッケージの成形は、9mm角のシリ
コンチップを32mm角の4層プリント配線基板であるキ
ャリア基板上にダイアタッチメントを介して接着し、シ
リコンチップの電極とキャリア基板の電極とを金ワイヤ
ボンディングした。その後、表2に示す実施例の組成の
封止樹脂を用い、成形温度150,180℃,成形圧力
7MPaの条件でトランスファー成形を行い、トータル
でパッケージ厚2.4mmの半導体樹脂を成形した。はん
だボールの数は18×18=324pinとした。ボー
ルの間隔は1.2 mmとした。In forming a BGA package, a 9 mm square silicon chip is bonded onto a carrier substrate, which is a 32 mm square 4-layer printed wiring board, through a die attachment, and the silicon chip electrode and the carrier substrate electrode are gold wires. Bonded. After that, transfer molding was performed under the conditions of a molding temperature of 150, 180 ° C. and a molding pressure of 7 MPa using the sealing resin having the composition of the example shown in Table 2 to mold a semiconductor resin having a total package thickness of 2.4 mm. The number of solder balls was 18 × 18 = 324 pins. The distance between the balls was 1.2 mm.
【0049】[0049]
【表2】 [Table 2]
【0050】[0050]
【表3】 [Table 3]
【0051】<実施例1,2,3,4,比較例1>実施
例1,2,3,4,比較例1はともにフィラ配合量は8
5重量%でガラス転移温度以下での熱膨張係数は10pp
m /℃であるが、実施例1,2,3,4ではガラス転移
温度が高いため成形温度から室温までの熱収縮量が小さ
く比較例1に比べ反り量は小さな値となった。実施例2
ではキャリア基板の熱収縮量よりも熱収縮率が小さな値
となるため他の実施例とは逆の方向に反りが生じる。<Examples 1, 2, 3, 4 and Comparative Example 1> In each of Examples 1, 2, 3, 4 and Comparative Example 1, the filler content was 8
Coefficient of thermal expansion below glass transition temperature at 5 wt% is 10 pp
Although m / ° C., in Examples 1, 2, 3 and 4, the glass transition temperature was high, so the amount of heat shrinkage from the molding temperature to room temperature was small and the amount of warpage was smaller than that in Comparative Example 1. Example 2
In this case, since the heat shrinkage ratio is smaller than the heat shrinkage amount of the carrier substrate, warpage occurs in the opposite direction to the other examples.
【0052】<実施例1,5>実施例1と実施例5はフ
ィラの配合量が異なる。フィラの配合量の小さい実施例
5では熱膨張係数が実施例1よりも大きくなるため、反
り量も大きくなった。 <実施例1,6,比較例1,2>実施例1,6と比較例
1,2は成形温度を比較したものである。実施例1と実
施例6を比較すると150℃で成形した実施例6の反り
量は非常に小さくなった。比較例2は150℃/90秒
でベースエポキシ樹脂が未硬化の為、成形不能であっ
た。<Examples 1 and 5> Example 1 and Example 5 are different from each other in the amount of filler. In Example 5 in which the filler content was small, the coefficient of thermal expansion was larger than that in Example 1, so the amount of warpage was also large. <Examples 1, 6 and Comparative Examples 1 and 2> Examples 1, 6 and Comparative Examples 1 and 2 compare molding temperatures. Comparing Example 1 and Example 6, the warpage amount of Example 6 molded at 150 ° C. was extremely small. Comparative Example 2 could not be molded at 150 ° C./90 seconds because the base epoxy resin was uncured.
【0053】<実施例7,8,比較例3,4>実施例
7,8,比較例3,4は本発明の樹脂組成物の硬化性を
比較したものである。180℃での成形では、実施例
7,8,比較例3では硬度80以上,スパイラルフロー
25inch以上を満足しパッケージの成形が可能である。
150℃の低温成形では硬化促進剤であるTPP量の少
ない実施例7では硬度が17と小さくパッケージの成形
は不可能である。また比較例3,4でも、硬度が0であ
るためパッケージの成形が出来ない。これに対し実施例
8ではスパイラルフローが25inch以上,硬度80以上
を満足しパッケージ成形に好適である。実施例7,比較
例3ではスパイラルフローは25inch以上であるので、
成形時間を長くすることにより80以上の硬度を得るこ
とも可能であるが、パッケージの量産性を考慮した場合
適しているのは本発明における実施例8である。<Examples 7 and 8, Comparative Examples 3 and 4> Examples 7 and 8 and Comparative Examples 3 and 4 compare the curability of the resin compositions of the present invention. In molding at 180 ° C., in Examples 7 and 8 and Comparative Example 3, hardness of 80 or more and spiral flow of 25 inch or more are satisfied, and the molding of the package is possible.
In the low temperature molding at 150 ° C., the hardness is as small as 17 in Example 7 in which the amount of TPP which is the curing accelerator is small, and molding of the package is impossible. Also in Comparative Examples 3 and 4, the hardness is 0, so that the package cannot be molded. On the other hand, in Example 8, the spiral flow is 25 inches or more and the hardness is 80 or more, which is suitable for package molding. In Example 7 and Comparative Example 3, since the spiral flow is 25 inches or more,
Although it is possible to obtain a hardness of 80 or more by lengthening the molding time, Example 8 of the present invention is suitable when considering the mass productivity of the package.
【0054】[0054]
【発明の効果】本発明の樹脂組成物を用いることによ
り、また、封止樹脂組成物のガラス転移温度以下の温度
で成形することにより反り量が低減する。EFFECT OF THE INVENTION By using the resin composition of the present invention, and by molding at a temperature not higher than the glass transition temperature of the encapsulating resin composition, the amount of warpage can be reduced.
【図1】本発明におけるボール・グリッド・アレイ・パ
ッケージの断面図。FIG. 1 is a sectional view of a ball grid array package according to the present invention.
【図2】BGAの量産性を高めるため、シリコンチップ
とキャリア基板の間にリードフレームを導入したパッケ
ージの断面図。FIG. 2 is a cross-sectional view of a package in which a lead frame is introduced between a silicon chip and a carrier substrate in order to improve mass productivity of BGA.
【図3】BGA成形後の反りの様子と反り量の測定部位
を示すパッケージ断面図。FIG. 3 is a package cross-sectional view showing the state of warpage after BGA molding and the measurement site of the warpage amount.
1…シリコンチップ、2…ダイアタッチメント、3…プ
リント配線基板、4…はんだボール、5…内層配線、6
…封止樹脂組成物、7…金ワイヤ、8…リードフレーム
を有するBGA、9…リードフレーム、10…反り量、
11…反り測定部位、12…反り量基準点。1 ... Silicon chip, 2 ... Die attachment, 3 ... Printed wiring board, 4 ... Solder ball, 5 ... Inner layer wiring, 6
... Encapsulating resin composition, 7 ... Gold wire, 8 ... BGA having lead frame, 9 ... Lead frame, 10 ... Warpage amount,
11 ... Warp measurement site, 12 ... Warp amount reference point.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 瀬川 正則 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 (72)発明者 小角 博義 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 (72)発明者 荻野 雅彦 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 (72)発明者 茂木 亮 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masanori Segawa, 7-1, 1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi, Ltd. Hitachi Research Laboratory, Ltd. (72) Hiroyoshi Ogaku, 7-chome, Omika-cho, Hitachi, Ibaraki No. 1 Hitachi Ltd., Hitachi Research Laboratory (72) Inventor Masahiko Ogino 7-1-1 Omika-cho, Hitachi City, Hitachi City, Ibaraki Prefecture 72 Hitachi Ltd. Hitachi Research Laboratory (72) Inventor, Ryo Mogi Omi Mika, Hitachi City, Ibaraki Prefecture 7-1-1, Machi, Hitachi Co., Ltd. Hitachi Research Laboratory
Claims (5)
基板の搭載面の裏面に、はんだボールをグリッド状に配
した実装面を有し、前記実装面と電気的に接続されてい
る前記半導体素子の搭載面に前記半導体素子を搭載固着
し、前記半導体素子の電極部分と前記プリント配線基板
とが電気的に接続されており、前記半導体素子と電気接
続部を含む前記半導体素子の搭載面の少なくとも一部分
が樹脂組成物で成形かつ封止されている構造を有する半
導体装置において、前記樹脂組成物による封止成形が、
樹脂組成物硬化物のガラス転移温度以下の温度で行われ
ることを特徴とする半導体装置。1. A semiconductor element having a mounting surface on which solder balls are arranged in a grid pattern on the back surface of the mounting surface of a printed wiring board having a mounting surface for the semiconductor element, and being electrically connected to the mounting surface. The semiconductor element is mounted and fixed on the mounting surface of, and the electrode portion of the semiconductor element and the printed wiring board are electrically connected to each other, and at least the mounting surface of the semiconductor element including the semiconductor element and the electrical connection portion. In a semiconductor device having a structure in which a part is molded and sealed with a resin composition, sealing molding with the resin composition,
A semiconductor device, which is performed at a temperature not higher than the glass transition temperature of a cured product of a resin composition.
基板の搭載面の裏面に、はんだボールをグリッド状に配
した実装面を有し、前記実装面と電気的に接続されてい
る前記半導体素子の搭載面に前記半導体素子を搭載固着
し、前記半導体素子の電極部分と前記プリント配線基板
とが電気的に接続されており、前記半導体素子と電気接
続部を含む前記半導体素子の搭載面の少なくとも一部分
が樹脂組成物で成形かつ封止されている構造を有する半
導体装置において、前記樹脂組成物が化1で示されるエ
ポキシ樹脂と化2で示される硬化剤を必須成分とし、か
つシリカ充填材を50〜95重量%含んでいることを特
徴とする半導体装置。 【化1】 【化2】 2. A semiconductor element having a mounting surface on which solder balls are arranged in a grid pattern on the back surface of the mounting surface of a printed wiring board having a mounting surface for the semiconductor element, and being electrically connected to the mounting surface. The semiconductor element is mounted and fixed on the mounting surface of, and the electrode portion of the semiconductor element and the printed wiring board are electrically connected to each other, and at least the mounting surface of the semiconductor element including the semiconductor element and the electrical connection portion. In a semiconductor device having a structure in which a part is molded and sealed with a resin composition, the resin composition contains an epoxy resin represented by Chemical formula 1 and a curing agent represented by Chemical formula 2 as essential components, and a silica filler. A semiconductor device containing 50 to 95% by weight. Embedded image Embedded image
基板の搭載面の裏面に、はんだボールをグリッド状に配
した実装面を有し、前記実装面と電気的に接続されてい
る前記半導体素子の搭載面に前記半導体素子を搭載固着
し、前記半導体素子の電極部分と前記プリント配線基板
とが電気的に接続されており、前記半導体素子と電気接
続部を含む前記半導体素子の搭載面の少なくとも一部分
が樹脂組成物で成形かつ封止されている構造を有する半
導体装置において、前記樹脂組成物が化3で示されるエ
ポキシ樹脂と化4で示される硬化剤を必須成分とし、か
つシリカ充填材を50〜95重量%含んでいることを特
徴とする半導体装置。 【化3】 【化4】 3. A semiconductor element, which has a mounting surface having solder balls arranged in a grid pattern on the back surface of the mounting surface of a printed wiring board having a mounting surface of the semiconductor element, and is electrically connected to the mounting surface. The semiconductor element is mounted and fixed on the mounting surface of, and the electrode portion of the semiconductor element and the printed wiring board are electrically connected to each other, and at least the mounting surface of the semiconductor element including the semiconductor element and the electrical connection portion. In a semiconductor device having a structure in which a part is molded and sealed with a resin composition, the resin composition contains an epoxy resin represented by Chemical formula 3 and a curing agent represented by Chemical formula 4 as essential components, and a silica filler. A semiconductor device containing 50 to 95% by weight. Embedded image [Chemical 4]
により支持されている半導体装置。4. The semiconductor device according to claim 1, wherein the printed wiring board and the silicon chip are supported by a lead frame.
0℃の温度範囲で行われている半導体装置。5. The method according to claim 1, 2, 3 or 4, wherein the molding with the molding resin composition is 100 to 15
A semiconductor device operated in a temperature range of 0 ° C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7116805A JPH08316374A (en) | 1995-05-16 | 1995-05-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7116805A JPH08316374A (en) | 1995-05-16 | 1995-05-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08316374A true JPH08316374A (en) | 1996-11-29 |
Family
ID=14696105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7116805A Pending JPH08316374A (en) | 1995-05-16 | 1995-05-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08316374A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6166433A (en) * | 1998-03-26 | 2000-12-26 | Fujitsu Limited | Resin molded semiconductor device and method of manufacturing semiconductor package |
| US6282781B1 (en) | 1997-12-18 | 2001-09-04 | Tdk Corporation | Resin package fabrication process |
| JP2011077199A (en) * | 2009-09-29 | 2011-04-14 | Sumitomo Bakelite Co Ltd | Semiconductor package and semiconductor device |
| JP2011129717A (en) * | 2009-12-17 | 2011-06-30 | Sumitomo Bakelite Co Ltd | Semiconductor package and semiconductor device |
-
1995
- 1995-05-16 JP JP7116805A patent/JPH08316374A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6282781B1 (en) | 1997-12-18 | 2001-09-04 | Tdk Corporation | Resin package fabrication process |
| US6166433A (en) * | 1998-03-26 | 2000-12-26 | Fujitsu Limited | Resin molded semiconductor device and method of manufacturing semiconductor package |
| JP2011077199A (en) * | 2009-09-29 | 2011-04-14 | Sumitomo Bakelite Co Ltd | Semiconductor package and semiconductor device |
| JP2011129717A (en) * | 2009-12-17 | 2011-06-30 | Sumitomo Bakelite Co Ltd | Semiconductor package and semiconductor device |
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