JPH0898140A - Digital signal reproducing apparatus and recording / reproducing apparatus - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the circuit scale of a special reproduction circuit in a digital VTR adopting an encoding method represented by MPEG2. A data separation means for separating intra-frame data, a special reproduction packet generation means for generating a special reproduction transport packet using the intra frame data separated by the data separation means, and the special reproduction packet generation means. It has a special reproduction block constructing unit that composes a special reproduction block by collecting a plurality of special reproduction transport packets output from the reproduction packet generating unit, and when the special reproduction block is generated, data of the same slice is generated. So that the special reproduction block does not straddle a plurality of special reproduction blocks, and the data output from the special reproduction block forming means is recorded in a predetermined area on the recording medium. To configure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal recording / reproducing apparatus (digital VTR, digital disc player or the like), or a digital VTR for recording a bit stream of a digital video signal and a digital audio signal represented by MPEG2 or the like. The present invention relates to a digital signal reproducing apparatus and a recording / reproducing apparatus such as the above, and particularly to interface control during special reproduction.

[0002]

2. Description of the Related Art FIG. 25 shows a general home digital VT.
It is a track pattern figure of R. In the figure, a diagonal track is formed on the magnetic tape, and one track is divided into two areas: a video area for recording a digital video signal and an audio area for recording a digital audio signal.

There are two methods for recording video and audio signals on such a home digital VTR. One is a so-called baseband recording method in which an analog video signal and an audio signal are input and recorded using a high-efficiency encoder for video and audio. The other is a so-called transparent recording system for recording a digitally transmitted bit stream.

ATV being discussed in the United States
The latter transparent recording method is suitable for recording the (Advanced Television) signal. The reason is that the ATV signal is already a digitally compressed signal and a high-efficiency encoder or decoder is not necessary, and since it is recorded as it is, there is no deterioration in image quality. On the other hand, the disadvantage is the image quality during high-speed reproduction, special reproduction such as still and slow reproduction. Particularly, if the bit stream is recorded on the diagonal track as it is, almost no image can be reproduced at the time of high speed reproduction.

As a method of the digital VTR for recording the above-mentioned ATV signal, "Intern" held in Ottawa, Canada from October 26 to 28, 1993.
national Workshop on HDTV '
"A Recording" in the technical announcement in "93"
Method of ATV data on aC
There is an "Digital Summarization VCR". Hereinafter, this content will be described as a conventional example.

As a basic specification of a home digital VTR prototype, SD (Standard Define) is used.
mode), the recording rate of the digital video signal is 25 Mbps, and the field frequency is 60 Hz.
In some cases, one frame of video is recorded in a video area of 10 tracks. Here, when the data rate of the ATV signal is set to 17-18 Mbps, transparent recording of the ATV signal becomes possible in this SD mode.

FIG. 26 is a diagram showing the head scanning loci of the rotary head during normal reproduction and high-speed reproduction of the conventional digital VTR. In the figure, adjacent tracks are alternately recorded obliquely by heads having different azimuth angles. During normal reproduction, the tape feed speed is the same as during recording, so the head moves along the recording track as shown in FIG.
It can be traced as in (a). However, during high speed reproduction, the tape speeds are different, so that it is possible to trace across several tracks and reproduce only the fragments of each same azimuth track. FIG. 26B shows the case of fast-forwarding at 5 times speed.

In the MPEG2 bit stream (ATV
The bit stream of the signal substantially conforms to the MPEG2 bit stream. ), Only intra-coded blocks can be independently decoded without reference to other frames. If the MPEG2 bit stream is recorded on each track in sequence, the reproduction data at the time of high-speed reproduction separates the intra-coded data from the reproduction data intermittently reproduced, and the separated intra-code The image is reconstructed using only the converted data. At this time, the reproduced area is not continuous on the screen, and the block fragments spread on the screen. Moreover, since the bitstream is variable length coded, there is no guarantee that all of the screen will be updated periodically, and some may not be updated for a long time. As a result, the image quality during high-speed playback is not sufficient,
It would be unacceptable for home digital VTRs.

FIG. 27 is a block diagram of a conventional bit stream recording apparatus capable of high speed reproduction. here,
The video area of each track is divided into a main area for recording a bit stream of all ATV signals and a copy area for recording an important part (HP data) of the bit stream used for image reconstruction during high speed reproduction. During high-speed playback, only the intra-coded block is effective, so this is recorded in the copy area. However, in order to further reduce the data, the low-frequency components are extracted from all intra-coded blocks and the HP data To record as. In FIG. 27, 1 is an input terminal of a bit stream, 2 is an output terminal of a bit stream, 3 is an output terminal of HP data, 4 is a variable length decoder, 5 is a counter, 6 is a data extracting circuit, and 7 is EOB (End). of Blo
ck) is an additional circuit.

The MPEG2 bit stream is input from the input terminal 1 and output from the output terminal 2 as it is,
It is sequentially recorded in the main area. On the other hand, the bit stream from the input terminal 1 is also input to the variable length decoder 4,
The syntax of the MPEG2 bit stream is analyzed, an intra image is detected, timing is generated by a counter 5, a low frequency component of all blocks of the intra image is extracted by a data extracting circuit 6, and E
The OB adding circuit 7 adds EOB to form HP data and records it in the copy area.

FIG. 28 shows a conceptual diagram of a system when a normal digital VTR is used for normal reproduction and high-speed reproduction. During normal reproduction, all bit streams recorded in the main area are reproduced and sent to an MPEG2 decoder outside the digital VTR. HP data is discarded. On the other hand, during high speed reproduction, only HP data in the copy area is collected and sent to the decoder, and the bit stream in the main area is discarded.

Next, the arrangement of the main area and the copy area on one track will be described. FIG. 29 shows an example of the head scanning locus during high speed reproduction. If the tape speed is an integral multiple speed and phase lock control is performed, head scanning is synchronized with the same azimuth track. Therefore, the position of the reproduced data is fixed. In FIG. 29, if it is assumed that a portion where the output level of the reproduction signal is higher than −6 dB is reproduced, a shaded area is reproduced by one head. FIG. 29 shows an example of 9 times speed,
At 9 × speed, signal reading in this shaded area is guaranteed. Therefore, HP data may be recorded in this area. However, at other speeds, signal reading is not guaranteed and this area must be chosen for reading at some tape speeds.

FIG. 30 shows an example of three tape speed scan areas in which the heads are synchronized with the same azimuth track.
The area scanned at each tape speed has some overlapping areas. Select a copy area from these areas,
Guarantees the reading of HP data at different tape speeds. Although FIG. 30 shows the cases of fast-forwarding at 4 times, 9 times, and 17 times, these scan areas are -2 times, -7
It becomes the same as the case of fast forward of double or -15 times.

At some tape speeds it is not possible for the head to trace the exact same area. This is because the number of tracks traversed by the head differs depending on the tape speed. In addition, it should be possible to trace from any one of the same azimuth tracks. FIG. 31 shows examples of head scanning loci at different tape speeds. In FIG. 31, areas 1, 2, and 3 are selected from the overlapping area of 5 × speed and 9 × speed. By repeatedly recording the same HP data on 9 tracks, the HP data can be read at either 5 × speed or 9 × speed.

FIG. 32 is a diagram showing two head scanning loci at the time of 5 × speed reproduction in the conventional digital VTR. As you can see, the same HP for the same number of tracks as the tape speed
By repeatedly recording data, HP data is
Reading can be performed by the head synchronized with the same azimuth track. Therefore, by duplicating the HP data for the same number of tracks as the maximum tape speed for high-speed reproduction, the duplicate HP data can be guaranteed to be read at both the forward and backward directions at some tape speeds. You can

The structure of the error correction code in the video signal area and audio signal area in one track of the digital VTR defined in the SD mode (hereinafter referred to as SD standard) will be briefly described below. FIG. 34 shows the arrangement of video signals, audio signals, etc. within one track defined by the SD standard. According to the SD standard, a Reed-Solomon code of (85, 77, 9) (hereinafter referred to as C1 check code) in the recording direction and an error correction code of the video signal area in the vertical direction of (149, 138, 12). The Reed-Solomon code (hereinafter referred to as C2 check code) is used. Further, as an error correction code in the audio signal area, a Reed-Solomon code (C1 check code) of (85, 77, 9) similar to the video signal in the recording direction is used in the vertical direction (14, 9,
The Reed-Solomon code (6) (hereinafter referred to as C3 check code) is used. Further, FIG. 35 shows one sync block (C1 block) which is a recording unit in the recording direction. As shown in FIG. 35, one sync block is composed of 90 bytes, of which the sync pattern and the ID signal are recorded in the first 5 bytes, and the error correction code (C1 detection code) in the last 8 bytes. ) Is recorded.

FIG. 33 is a track layout diagram in a conventional digital VTR, showing an example of a main area and a copy area. In the home digital VTR, the video area of each track is composed of 135 sync blocks, the main area is 97 sync blocks, and the copy area is 32 sync blocks. This copy area is shown in FIG.
The overlapping area corresponding to 4, 7, and 17 times speed shown by is selected. In this case, the main area data rate is about 1
Since the same data is recorded in the copy area 17 times at 7.46 Mbps, it becomes about 338.8 kbps.

During special reproduction (high speed reproduction, slow reproduction, still reproduction, etc.), since the rotary head crosses the recording track diagonally, the reproduction signal is intermittently reproduced from each track. Therefore, the error correction block (video data) as shown in FIG. 34 (a) cannot be constructed during special reproduction. Therefore, during the special reproduction, only the error correction by the C1 check code is applied to the reproduced data.

[0019]

The conventional home-use digital VTR is constructed as described above, and as described above, special reproduction data is repeatedly recorded in the copy area. However, there is a problem that the recording rate of the special reproduction data is extremely low, and particularly in slow reproduction or high speed reproduction, the reproduction image quality cannot be sufficiently obtained. For example, if there are 2 intraframes per second,
The amount of data only for intra encoding of the ATV signal is about 3 Mb
It is estimated to be about ps, but in the conventional example it is about 340 kbps.
Only the recorded data can be recorded, and the reproduced image quality is extremely deteriorated.

Further, when outputting the bit stream (transport packet) of the ATV signal formed by using the data recorded in the special reproduction area at the time of special reproduction, only the intra-coded data is outputted.
For example, when the amount of data in the intra frame is large, a memory for transport packet storage provided in the ATV decoder may overflow during the transport packet transmission, causing a system failure in the ATV decoder. There is a problem. There is also a problem that the memory capacity of the special reproduction memory on the reproduction side becomes larger than necessary.

Further, when outputting the bit stream (transport packet) of the ATV signal formed by using the data stored in the special reproduction area at the time of special reproduction, only the intra-coded data is outputted.
For example, when the data amount of the intra frame is large, the transport packet for a predetermined number of frames cannot be transmitted to the ATV decoder, and the system may fail in the ATV decoder. Have.

The present invention has been made to solve the above problems, and particularly improves the playback image quality during slow playback or high speed playback, and also during special playback (high speed playback, slow playback, and The purpose is to perform interface control so that the control on the ATV decoder side during still reproduction) does not change at all during normal reproduction.

Further, according to the present invention, the above-mentioned transport packet is efficiently generated at the time of recording so that the data control of the reproducing system at the time of high-speed reproduction can be performed relatively easily. The purpose is to perform high-speed playback well.

Another object of the present invention is to reduce the memory capacity of the reproducing system during high speed reproduction and to perform high speed reproduction efficiently.

[0025]

According to a first aspect of the present invention, there is provided a digital signal reproducing / reproducing apparatus and a recording / reproducing apparatus in which a frame or field is input in a transport packet state, or a frame or field is inter-field. In a digital signal recording / reproducing apparatus in which an encoded digital video signal and a digital audio signal are transparently recorded, a data separating means for separating the frame- or field-encoded digital video signal from the transport packet. A special reproduction packet generating means for reconstructing the frame or field-encoded digital video signal separated by the data separating means to generate a special reproduction transport packet, and the special reproduction packet Living The special reproduction block forming means for collecting a plurality of special reproduction transport packets output from the means to form the special reproduction block is provided, and when the special reproduction block is generated, the data of the same slice is plural. The special reproduction block is configured so as not to extend over the special reproduction block, and the data output from the special reproduction block forming means is recorded in a predetermined area on the recording medium.

According to a second aspect of the present invention, when the special reproduction transport packet is generated, the special reproduction packet generating means is provided so that the data in the same slice does not straddle a plurality of the special reproduction transport packets. Make up.

Further, in claim 3, when the special reproduction transport packet is generated, the special reproduction packet generating means is constituted so that the slice data is composed of all macroblocks belonging to the same macroblock row. .

Further, in claim 4, when the special reproduction block is constructed, the special reproduction block constructing means is constituted so that the data in the special reproduction block is composed of all macroblocks belonging to the same macroblock row. Make up.

According to a fifth aspect of the present invention, the special reproduction block is arranged on the recording medium so that the special reproduction block can be constructed in one scanning period of the rotary head when the special reproduction is performed at a predetermined speed. To configure.

According to a sixth aspect of the present invention, the special reproduction block configuring means is configured such that the special reproduction block is composed of two special reproduction transport packets.

According to a seventh aspect of the present invention, the special reproduction block configuring means is configured such that the special reproduction block is composed of one error correction block to which an error correction code in a direction different from the recording direction is added. .

Further, in claim 8, the trick play packet generating means is configured such that the data of the head macro block of the trick play transport packet is composed of a macro block on the left side of the screen.

According to a ninth aspect of the present invention, a digital video signal, which is input in the form of a transport packet and is encoded within a frame or field, or between frames or fields, and a digital audio signal are transparently recorded. Data for special reproduction used for special reproduction is generated from the digital video signal encoded in the frame or in the field from the transport packet, and the generated special reproduction data is recorded at a predetermined position. In a digital signal reproducing apparatus for reproducing a recording medium, data separation means for separating the special reproduction data from the reproduction signal during special reproduction, data storage means for storing the separated special reproduction data, and digital signal reproduction The data output from the device Specific area fixed packet generation means for generating a transport packet for stopping the signal in a specific area on the screen and decoding the special reproduction transport packet data when reproducing the reproduced image data. When the reproduced image is formed by using the data reproduced intermittently, the output timing signal is output from the data output control unit at a predetermined timing. When output, the special area fixed packet generating means and the special reproduction data stored in the data storage means are used to generate and transmit one frame of the special reproduction data.

In the tenth aspect, the output timing signal output from the data output control means is generated in synchronization with the number of scanning times of the rotary drum head.

In the eleventh aspect, the output timing signal output from the data output control means is generated in synchronization with the frame frequency of the display device connected to the outside.

In the twelfth aspect of the invention, the transport packet output from the specific area fixed packet generating means is composed of data of all macroblocks in the packet having a motion vector of 0 and a prediction error of 0. In addition, the transmission mode of all image data during special reproduction is set to an interframe mode, and only the special reproduction data is transmitted as a forced intra mode in an interframe image.

[0037]

A digital signal reproducing apparatus and a recording / reproducing apparatus according to the present invention are characterized in that, in claim 1, a digital image coded in a frame or field, or in a frame or field is encoded in a transport packet state. In a digital signal recording / reproducing apparatus in which a signal and a digital audio signal are transparently recorded, data is separated from the transport packet to separate a frame or field-encoded digital video signal, and the separated frame or A special reproduction transport packet is generated by reconstructing the intra-field encoded digital video signal, and a plurality of special reproduction transport packets thus generated are combined to form a special reproduction block.
At this time, the special reproduction block is configured so that the slice data does not straddle the plurality of special reproduction blocks, and the data output from the special reproduction block configuring means is predetermined on the recording medium. Recorded in the area.

According to a second aspect of the present invention, when the trick play transport packet is generated, the trick play transport packet is stored so that the data in the same slice does not straddle a plurality of the trick play transport packets. Generate a packet.

Further, in claim 3, when the transport packet for special reproduction is generated, the special reproduction packet is generated so that the slice data is composed of all macroblocks belonging to the same macroblock row.

Further, in claim 4, when the special reproduction block is formed, the special reproduction block is formed so that the data in the special reproduction block is composed of all macroblocks belonging to the same macroblock row. To generate.

According to a fifth aspect of the present invention, when performing special reproduction at a predetermined speed, the special reproduction block is formed on the recording medium so that the special reproduction block can be formed in one scanning period of the rotary head. Deploy.

Further, in the sixth aspect, the special reproduction block configuring means is controlled so that the special reproduction block is composed of two special reproduction transport packets.

Further, in claim 7, a plurality of the special reproduction transport packets are collected, and the special reproduction block is composed of one error correction block data to which an error correction code in a direction different from the recording direction is added. The special reproduction block forming means is controlled so as to form the structure.

Further, in claim 8, the trick play transport packet is generated so that the data of the head macro block of the trick play transport packet is composed of a macro block on the left side of the screen.

Further, in claim 9, a digital video signal, which is input in the form of a transport packet and is encoded in a frame or a field or between frames or a field, and a digital audio signal are transparently recorded. At the same time, special reproduction data used in special reproduction is generated from the transport packet by the frame or field encoded digital video signal, and the generated special reproduction data is recorded at a predetermined position. In a digital signal reproducing apparatus for reproducing a recording medium, a data separation means for separating the special reproduction data from the reproduction signal at the time of special reproduction, a data storage means for storing the separated special reproduction data, and a digital signal Output from playback device Specific area fixed packet generating means for generating a transport packet for stopping the signal in a specific area on the screen when decoding the reproduced data and the reproduced image data, and outputting the special reproduction transport packet data of one frame When having a data output control means for generating an output timing control signal in the case of forming a reproduced image using the data reproduced intermittently,
The data output control means outputs the output timing signal at a predetermined timing. When the output timing signal is output, the data storage means detects the position of the special reproduction data stored on the screen, and outputs the detected position information to the specific area fixed packet generation means. The specific area fixed packet generation means outputs a transport packet for stopping the image data portion of one frame which is not yet constructed in the data storage means. Then, these signals are configured to be combined and output.

In the tenth aspect, the output timing signal output from the data output control means is generated at a predetermined timing by counting the number of times of scanning of the rotary drum head.

In the eleventh aspect of the invention, the output timing signal output from the data output control means is generated in synchronization with the frame frequency of the display device connected to the outside by separating the frame frequency from the reproduced data. To configure.

In the twelfth aspect of the invention, the motion vector of the data of all macroblocks in the transport packet is 0 by the specific area fixed packet generating means.
In addition to constructing data having a prediction error of 0, when transmitting image data, a picture header is generated and changed so that the transmission mode of all image data becomes the interframe mode, and the special reproduction data is also changed. Only the header information is changed so as to be decoded as the forced intra mode in the inter-frame image and transmitted.

[0049]

【Example】

Example 1. FIG. 1 shows a digital V which is an embodiment of the present invention.
It is a block configuration diagram of a recording system of TR. In the figure, 1
Is an input terminal for inputting a digital video signal and a digital audio signal as a bit stream, 11 is a packet detection circuit for detecting packets such as video signals and audio signals from the transmitted bit stream, and 12 is a first bit stream storing bit stream. 1 is a memory, 13 is an intra detection circuit that detects intra-coded data in a bitstream, 14 is a second memory that stores the intra-coded data output from the intra detection circuit 13, and 15 is a second memory 14 A first error correction coder for adding an error correction code to the data output from the first, and a first error correction code encoder 16 for combining the data output from the first memory 12 and the second memory 15 to generate a recording data stream. 1 is a data composition circuit, 17 is a recording data stream output from the first data composition circuit 16. Second error correction encoder for adding an error correction code defined by SD standards streams, the recording amplifier 18, 19 is a rotary drum, 20a, and 20b are rotary heads.

FIG. 2 is a block diagram of the intra detection circuit 13 which is an embodiment of the present invention. In the figure, reference numeral 4 has the same configuration and operation as those shown in FIG. In the figure, 40 is an input terminal, 41 is an output terminal, 42 is an intra packet header detection circuit for detecting an intra packet header and generating a write control signal for writing the detected intra frame data in the memory 43, 43 Is a memory, and 44 is a code amount calculated from the code length of the variable length code word output from the variable length decoder 4 and the run length length, and controls the code amount of the special reproduction transport packet based on the calculation result. A code amount control circuit 45, a slice generation circuit 45 for synthesizing bit streams output from the memory 43 to generate a slice, and 46 an input terminal for a format generation control signal.

FIG. 3 is a block diagram of a slice generation circuit 45 which is an embodiment of the present invention. In the figure, reference numeral 4 has the same configuration and operation as those shown in FIG. In the figure, 50 and 51 are input terminals, 52 is a data output terminal, 53 is a transport header addition circuit, 54 is a slice header addition circuit, and 55.
Is a slice generation control circuit, 56 is an input terminal for a format generation control signal, and 57 is an output terminal.

FIG. 4 is a block diagram of a DCT block and a macro block in the ATV signal. Figure 5 is SD
It is a figure which shows the arrangement | positioning of the data in 1 track which is one Example of this invention based on a standard. 6A to 6C show the arrangement of rotary heads 20 (a) and 20 (b) on a typical rotary drum 19 used in the SD mode. FIG. 7 shows a data packet according to an embodiment of the present invention. 7A is a transport packet diagram included in the input bit stream, and FIG. 7B is a record data packet diagram recorded on the magnetic tape. FIG. 8 shows the code structure of the error correction code added to the special reproduction data in the first embodiment (hereinafter referred to as one error correction block). FIG. 9 shows the number of sync blocks that can be obtained from one track at each high speed reproduction speed. FIG. 10 shows the data recording area for special reproduction on the magnetic tape according to one embodiment of the present invention.
The recording area of the ATV signal is shown. FIG. 11 shows a method of dividing one error correction block of 16x speed (-14x speed) data of a digital VTR which is an embodiment of the present invention. FIG. 12 shows a digital VTR which is an embodiment of the present invention.
Shows the track format of. FIG. 13 shows a method of forming a macroblock of an ATV signal.

FIG. 14 is a block diagram of a reproducing system of a digital VTR which is an embodiment of the present invention. In the figure, 19 and 20 have the same configuration and operation as those shown in FIG. Reference numeral 21 is a head amplifier, 22 is a signal detection circuit for detecting digital data from the reproduced signal, 23 is a digital demodulation circuit for performing digital demodulation on the reproduced digital data output from the signal detection circuit 22, and 24 is an ID signal from the digital demodulated signal. Is an ID detection circuit for detecting the error, 25 is a first error correction decoding circuit for error correction or error detection of an error included in the reproduced signal subjected to digital demodulation using the C1 check code, and 26 is for normal reproduction. A second error correction decoding circuit for performing error correction or error detection on data that has not been error-corrected by the C1 check code (data for which an error has been detected or data for which an error has been missed) using the C2 check code,
27 is a third memory, and 28 is an error correction code added to the special reproduction data (hereinafter referred to as C4 check code).
A third error correction decoding circuit for performing error correction or error detection using 29, 29 is a fourth memory, 30 is a still image based on a control signal output from the third memory 27 or the fourth memory 29. A still image packet generation circuit for generating a packet, 31 and 32 are switches, 33 is a data output terminal, and 34 is a header replacement circuit.

FIG. 15 is a block diagram of the still image packet generation circuit 30 which is an embodiment of the present invention. In the figure, reference numerals 60 and 61 are input terminals, 62, 63 and 64 are output terminals, 65 is a slice header generation circuit for generating a slice header, 66 is a macroblock address generation circuit, and 67 is a still picture macroblock data generation circuit. 68 is a timing control circuit, 69 is a packet generation control circuit, 70 is a no-data packet generation circuit, 71 is a switch, and 72 is an input terminal.

FIG. 16 is a block diagram of the header changing circuit 34 which is an embodiment of the present invention. In the figure, 75 is an input terminal, 76 is an output terminal, 77 is a picture header generation circuit, 78 is a special reproduction slice detection circuit,
Reference numeral 79 is a forced intra flag addition circuit.

FIG. 17 shows the rotary head 20 (a) in the case of performing 2 × speed, 4 × speed, 8 × speed reproduction, and 16 × speed reproduction.
The scanning locus of is shown. FIG. 18 shows the tracking control points at each speed. FIG. 19 shows the scanning locus of 20 (a) of the rotary head and the output order of the special reproduction data when the −2 × speed reproduction is performed. FIG. 20 shows an output state of reproduction transport packets during special reproduction during forward special reproduction. FIG. 21 shows a partial refresh state on the screen during special playback in the forward direction. FIG. 22 shows the output state of the reproduction transport packet during the special reproduction during the special reproduction in the reverse direction. FIG. 23 shows a partial refresh state on the screen during special playback in the reverse direction. FIG. 24 shows the structure of a still image slice and a transport packet composed of the still image slice.

Before explaining the operation of the first embodiment, M
The image data encoding method (video packet configuration method) defined by PEG2 will be briefly described. MPEG
2 (the ATV signal also employs the same encoding method as MPEG2), an intra encoding method for encoding input image data within a frame or a field,
Image data of each frame or field is transmitted by combining an inter coding method (motion compensation prediction) for coding between frames or fields.

Further, as shown in FIG. 4A, the data in each frame or field is divided into blocks of 8 lines × 8 pixels adjacent to each other (hereinafter, this block will be referred to as a DCT block). There is. In MPEG2, high efficiency coding is performed with this DCT block as the minimum unit. Note that the intra-frame (field) data is subjected to discrete cosine transform (hereinafter referred to as DCT) in the DCT block during high-efficiency coding. DC
Since the power spectrum of the coefficient after T conversion (hereinafter referred to as a sequence) is concentrated on the low frequency side, the above sequence is sequentially transmitted from the data on the low frequency side where the power spectrum is concentrated by a method called zigzag scanning. Figure 4
The order of scanning is shown in (c). In the figure, the sequence in the upper left where the transmission order is fast is called the low-frequency sequence,
The lower right sequence is called the high frequency sequence.

Then, a plurality of adjacent DCT blocks are collected to form a macro block. The inter-frame (or field) data is subjected to motion vector detection and coding for each macro block. Regarding the structure of macroblocks, MPE
Several cases are defined in G2. The ATV signal is constructed as shown in FIG. Figure 4
As shown in (b), the macroblock in the ATV signal is a DCT block of four adjacent luminance signals (Y in the figure).
It is shown by 0 to Y3. It is composed of 16 lines × 16 pixels. ), And two DCT blocks (8 lines × 8 pixels) of color difference signals at the same position on the screen (C in the figure
Notated as R and CB. ) Each is composed of one.

Then, a plurality of macro blocks are collected to form a slice. Incidentally, in MPEG2, it is necessary to satisfy some conditions in constructing a slice. Some of the conditions are shown below. (Please refer to the MPEG2 standard for details.)
It is a series of arbitrary macroblocks, and the number of macroblocks contained in it is not limited. Also, the slice must include at least one macroblock. Also, the first and last macroblocks in a slice cannot be skipped. The first and last macroblocks in a slice belong to the same horizontal macroblock row (hereinafter referred to as the same macroblock row). The position of the slice can change from screen to screen. Also, the slices must appear in the bitstream starting from the top left of the screen, in raster scan order from left to right, and from top to bottom.

Next, a method of transmitting a 1-frame video packet will be described. A picture header is added to the beginning of each frame, and image coding information is added. (Specifically, information indicating intra coding or inter coding, or a quantization table, etc.)
One frame of image data is transmitted following the picture header. The image data of one frame is composed of the above-mentioned plurality of slice data, and each slice is added with a slice header at the head. Information such as an address (slice start code) in the row direction of the slice is added to the slice header. Also, a macroblock address is added to the head of each macroblock in the slice, and the presence or absence of skipping of the macroblock is determined based on this continuity. The macroblock skip will be described later. The macroblock address defined in MPEG2 is a relative address in the row direction with respect to the macroblock transmitted immediately before.

Next, the recording format of the first embodiment will be described with reference to FIGS. FIG. 9 is a diagram showing the number of sync blocks capable of collecting data during high speed reproduction. In the figure, the 9000 rpm system is shown in FIG.
(A) and FIG. 6 (b) show the head arrangement system, and the 4500 rpm system means the head arrangement system shown in FIG. 6 (c). Each value in the figure is the number of sync blocks that can be reproduced from one track at each reproduction speed when special reproduction is performed using a rotary head having a diameter of 10 μm (the track pitch in the SD standard is 10 μm). Is shown. The calculation is performed assuming that the number of sync blocks in one track (corresponding to 180 degrees) is 186 sync blocks, and that a portion where the output level of the reproduction signal is higher than -6 dB can be obtained as in the conventional example.

Considering the number of sync blocks capable of acquiring data shown in FIG. 9, FIG. 10A shows the arrangement of the special reproduction data recording area in the track of the digital VTR in the first embodiment. In this recording format, the special reproduction data recording area is repeated at a 4-track cycle, and the special reproduction data recording area corresponding to each double speed number is provided on the four tracks. In addition, a in the figure
1 and a2 are areas for recording special reproduction data for 2 × speed, 4 × speed, and −2 × speed, and b1 and b2 record special reproduction data for 8 × speed and −6 × speed. As an area, and c1 and c2 are 16
It is provided as an area for recording special reproduction data for double speed and -14 speed. Also, the input ATV
The bit stream of the signal shall be recorded in another area (hereinafter referred to as an ATV data recording area).

FIG. 10B shows the data (the number of sync blocks) recorded in each special reproduction data recording area. In the figure, the same signal is recorded in the areas marked with the same reference numerals. (For example, the data of 1 in a1 is also recorded in the portion of 1 in a2.) Further, the same data is repeatedly recorded twice in the areas a1 and a2, and the same in the areas b1 and b2. Data is recorded 4 times repeatedly. Also, c1 and c2
Regarding the area, the special reproduction data (1 error correction block) to which the above error correction code is added is divided into 4 units of 5 sync blocks as shown in FIG. 11, and the upper two blocks are repeatedly recorded 8 times. Record the bottom two blocks eight times. FIG. 12 shows the detailed arrangement of the data recording areas for special reproduction on the magnetic tape. In the figure, areas (A1, A1 ',
The same trick play data is recorded in B1, B1 ', C1, C1', etc.).

Next, the operation during special reproduction will be briefly described with reference to FIG. In the 9000 rpm system, 4 from Fig. 9
At the double speed, 62 sync block data can be reproduced from one track, whereas in the 4500 rpm system, only 31 sync blocks can be reproduced. That is, in this recording format, at the time of 4 × speed reproduction,
In the system of 9000 rpm, all the special reproduction data recorded in the track a1 can be reproduced (that is, 1, 2, 3, and 4 shown in FIG. 10B).
It is possible to reproduce all the signals (including ECC) of. However, in the 4500 rpm system, about 9 sync blocks have not been reproduced, so that one error correction block shown in FIG. 8 cannot be constructed. That is, the number sync block data at the beginning of the portion 1 and the sync block data at the end of the portion 4 in FIG. 10B are not reproduced. Therefore,
In the first embodiment, the auxiliary data used in the 4500 rpm system is recorded in the portion a2. (4
Regarding the construction method of one error correction block at the time of special reproduction in the 500 rpm system, the sync block which cannot be reproduced by the rotary head of 19 (a) is reproduced by the rotary head of 19 (b) arranged adjacently. The sync block is used to configure the one error correction block.
Details are omitted because they are different from the gist of the present invention. )

Here, the refresh time of the reproduced image at the time of 4 × speed reproduction, 8 × speed reproduction and 16 × speed reproduction in the recording format shown in FIG. 10 (recorded in the special reproduction data recording area at the aforementioned reproduction speed). When the special reproduction image is constructed using the data, the minimum time for updating the special reproduction image) is set to 0.5 seconds. At this time, the code amount of the special reproduction image forming one frame is about 1.32 Mbit in the 4 × speed reproduction, about 0.66 Mbit in the 8 × speed reproduction, and about 0.33 Mbit in the 16 × speed reproduction. Therefore, the reproduction image quality during special reproduction can be significantly improved. It should be noted that in the first embodiment, the special reproduction data is generated from the different intra frames at the preset speed number.

Next, a method of constructing one error correction block of special reproduction data will be described with reference to FIGS. 7 and 8.
The intra-coded image data of one frame separated from the input bit stream is subjected to variable length decoding, and the data amount is reduced so that the code amount of one frame is as described above. Then, the data whose data amount has been reduced is reconstructed in the form of transport packets shown in FIG. Then, the two reconstructed transport packets are collected to form a recording data block shown in FIG. Then, the three recording data blocks are collected to form one error correction block, and the C4 check code shown in FIG. 8 is added, and then the C1 check code is added. The details of the method for generating the transport packet of the special reproduction data will be described later.

In the first embodiment, C4 of special reproduction data is used.
The (20,15,6) Reed-Solomon code is adopted as the check code. Therefore, during special playback, the above C
Since error correction is performed using the 4-check code, the error detection probability at a symbol error rate of 0.01 is improved by about 10 10 times, which is a level at which there is no practical problem. As described in the conventional example, the symbol error rate is 0.
In many cases, the number becomes 01 or more, but as far as the calculation result regarding the error rate is seen, the above code configuration has a practically no problem level and a good special reproduction image can be obtained.

The details of the recording format of the first embodiment will be described above. In the bit stream of the input ATV signal, two transport packets are composed of five sync blocks as described above, and one sync block is used as a unit for the ATV data area on the recording track (see FIG. 5).
It is recorded in an area other than the special reproduction data recording area above.

On the other hand, the above 20 with the error correction code added
The special reproduction data for each speed of the sync block is shown in FIG.
It is recorded in the corresponding special reproduction data recording area shown in (a). The trick play data corresponding to each double speed number is repeatedly recorded a predetermined number of times as described above. Note that a
In the case of one area, the first 20 sync blocks compose one error correction block, and the latter 20 sync blocks compose another error correction block. That is, the first half error correction block and the second half error correction block have different contents. Further, in the case of 16-times speed reproduction data, FIG.
1 error correction block is divided into 10 sync blocks in the first half and 10 sync blocks in the latter half, and
After repeating 0 sync block data 8 times, the latter half 10 sync block data is repeatedly recorded 8 times. FIG. 12 shows the recording format on the magnetic tape of the first embodiment.

When the refresh time of the special reproduction data corresponding to each speed is set to 0.5 seconds as described above, the 4x speed is every 2 seconds, the 8x speed is every 4 seconds, and the 16x speed is The intra image is extracted from the input bit stream and the special reproduction image is updated every 8 seconds. The refresh time is not limited to this. Further, the refresh time may be set to a different time for each multiple speed.

The recording operation of the first embodiment will be described below with reference to FIGS. In the first embodiment,
The following description will be continued on the assumption that the video signal in the transport packet transmits data encoded in frame units. The bit stream input from the input terminal 1 includes a digital video signal, a digital audio signal,
Further, digital data regarding a video signal and an audio signal are included, and these are divided into transport packets shown in FIG. 7A and transmitted. The packet is composed of a 4-byte header part and a 184-byte data part. In the first embodiment, a bitstream is detected in transport packet units,
Fig. 7 (b) shows the detected two transport packets.
As shown in, the data is converted into a recording data block of 5 sync blocks and recorded. Therefore, first, the bit stream input via the input terminal 1 is the packet detection circuit 11
At, the transport packet is detected and input to the first memory 12 and the intra detection circuit 13.

In the SD standard, as described in the conventional example, FIG.
As shown in (or FIG. 34), 149 sync blocks are prepared as an area for recording video data per track. Of these, 3 blocks are provided as a VAUX data recording area, and 11 blocks are provided as a C2 check code area. Similarly to the conventional example, one sync block is composed of 90 bytes as shown in FIG. 35, of which the first 5 bytes are the sync pattern and the ID.
The signal is recorded, and the C1 detection code is recorded in the rear 8 bytes. Therefore, the data that can be stored in one sync block is 77 bytes as shown in the figure.

In the first memory 12, the bit stream data input in the transport packet unit is temporarily stored in the memory, and the data is read so as to have the structure of the recording data block shown in FIG. 7B. . Figure 7
(B) is such that, when the data length in one sync block is 77 bytes as described above, two transport packets are composed of five sync blocks. In the figure, H1 is the first header and H2 is the second header. Identification data indicating the number of sync of 5 sync blocks, a flag for identifying whether the data is special reproduction data or normal reproduction data, and the like are recorded in H1. Identification data such as video data or audio data is recorded in H2.

On the other hand, the bit stream output from the packet detection circuit 11 is input to the intra detection circuit 13. The operation of the intra detection circuit 13 will be described below with reference to FIGS. 2 and 3. In the first embodiment, as special reproduction data, 3 × 4 ×, 8 ×, and 16 × speeds are used.
Since the types of data are generated, the intra detection circuit 13 is configured by the three circuits shown in FIG. Also, the second
It is assumed that the memory 14 is also provided independently for each double speed number. Specifically, as the memory for quadruple speed, a memory having a capacity of 30 sync blocks is arranged because two error correction blocks are recorded on one track. With respect to, a memory having a capacity of 15 sync blocks is arranged.

The intra packet header detection circuit 42 separates the picture header from the bit stream input through the input terminal 40, and the coding mode of the image of each frame is detected. If the detection result indicates that the intra coding mode is set, the intra packet header detection circuit 42
A write address for writing the bit stream to the memory 43 and a write control signal are generated.
At that time, the intra packet header detection circuit 42 counts the code amount of one frame of the intra image, and outputs the count result to the code amount control circuit 44. The code amount control circuit 44 predicts the data transmission rate in advance based on the code amount count result. Specifically, in the first embodiment, the sequence of data in the DCT block to be transmitted is predicted based on the code amount count result. Then, the code amount of each transport packet is controlled by using this prediction result as an initial value. Details of the operation of the code amount control circuit 44 will be described later.

In the first embodiment, when the intra-frame data is written to the memory 43, the picture header of the next frame data is detected from the transport packet in which the picture header is detected in transport packet units. Up to transport packets shall be written. This is because the header portion added to the beginning of the transport packet is added with information regarding the transport packet, and this information is required when generating the special reproduction data. Further, the memory 43 is composed of two memory blocks capable of storing an intra image for one frame. When one memory block generates a trick play transport packet, the other data is stored in the intra frame. Shall be controlled to write the bit stream of.

On the other hand, when the format generation control signal is input from the input terminal 46, the intra detection circuit 13 outputs a predetermined number of special reproduction transport packets. For example, in the first embodiment, 6 trick play transport packets are generated for 16 × speed data. Therefore, in the memory 43, when the format generation control signal is input, the intra-frame transport packets stored in the memory 43 are sequentially read until the generation of the six trick play transport packets is completed. In the first embodiment, the data read control signal from the memory 43 is output from the code amount control circuit 44. The data output from the memory 43 is input to the variable length decoder 4 and the slice generation circuit 45. The variable length decoder 4 performs variable length decoding on the input bit stream and outputs the code length and the run length to the code amount control circuit 44. The code amount control circuit 44 controls the code amount based on the above prediction result.

The method of generating the transport packet for special reproduction will be described below. The data input via the input terminal 50 is input to the transport header adding circuit 53. In the transport header adding circuit 53,
A special reproduction transport header is generated based on the transport header added in advance to the bitstream. The generated transport header is added to the bit stream based on the control signal output from the slice generation control circuit 53. Note that the transport header in the bitstream (transmitted together with the bitstream) is the transport header adding circuit 5
Removed in 3.

The slice header adding circuit 54 adds a slice header to the bit stream to which the transport header has been added to reconstruct a slice. The slice reconstruction method will be described in detail later. The slice generation control circuit 55 detects the slice header from the bit stream and outputs a control signal for adding the slice header to the slice header adding circuit 54. In addition,
The slice header following the transport header is added to the bit stream based on the control signal output from the code amount control circuit 44. The transmitted slice header is removed by the slice header adding circuit 54.

The special reproduction data to which the slice header has been added by the slice header adding circuit 54 is input to the EOB adding circuit 7. The EOB adding circuit 7 detects the DCT block from the input bit stream and forcibly adds the EOB to each DCT block based on the control signal output from the code amount control circuit 44. Then, the high frequency data of the DCT block after the EOB that is forcibly added is removed. The data to which EOB is forcibly added is output to the second memory via the output terminal 52.

The operation of the code amount control circuit 44 will be briefly described below. First, when the special reproduction transport packet generation is started, the code amount control circuit 44
The slice generation control circuit 55 outputs a control signal for adding a transport header. At the same time, the initial value of the code amount counter arranged in the code amount control circuit 44 is set. When the transport header is added to the bitstream, a control signal for adding the slice header is output to the slice generation circuit 55, and the code amount count value is increased by the code length of the slice header. When the addition of the slice header is completed, the read address for reading the data in the memory 43,
And a read control signal is output.

The data read from the memory 43 is subjected to variable length decoding by the variable length decoder 4, and the code length and the run length data are input to the code amount control circuit 44. The code amount control circuit 44 determines how many sequences are currently transmitted by counting the run length data. Further, the code amount is calculated by counting the code length. The code amount is compared with the target value each time the transmission of one macroblock is completed. When the code amount is larger than the target value, the transmission sequence amount is reduced, and when it is smaller, the transmission sequence amount is increased. The initial value of the transmission sequence amount is the above prediction result.

The EOB insertion position of each DCT block is
The code amount control circuit 44 compares and detects the sequence position information and the transmission sequence amount. Specifically, a control signal is generated so that the variable length codeword whose sequence position information exceeds the transmission sequence amount is replaced with EOB. Regarding the data break, the code amount control circuit 44 outputs the data based on the variable length decoding result. When the transmission of the predetermined number of macroblocks is completed, dummy bits are added to the empty area to generate a 188-byte special reproduction transport packet. When the horizontal macroblock row on the screen changes in the special reproduction transport packet, the slice generation circuit 55 detects the slice header to detect the transition of the horizontal macroblock row and add a new slice header. A control signal for doing so is output to the slice header adding circuit 65. The detection of the transport header or the slice header is also performed by the variable length decoder 4, and is output to the code amount control circuit 44 for controlling the code amount.

The intra detection circuit 13 is provided with three circuits shown in FIGS. 2 and 3, and each circuit operates as described above.

The above operation is repeated a predetermined number of times to obtain a predetermined number of transport packets. Specifically, in the case of data for 16 × speed reproduction, 6 transport packets are generated and output each time the format generation control signal is input to the intra detection circuit 13 as described above. The trick play transport packet generated in the above manner is stored in the second memory 14. It should be noted that the removal of the data in the DCT block forcibly terminated is executed in the first embodiment by not writing the data to the second memory 14. Therefore, the EOB adding circuit 7 adds a flag indicating whether or not to write data and transmits the special reproduction transport packet.

When the format generation control signal is input, the data stored in the second memory 14 is read from the second memory by a predetermined number in units of one error correction block. At that time, the data is read so as to have the structure of the recording data block shown in FIG. That is, as described above, the data length in one sync block is 77 bytes, and two transport packets are composed of 5 sync blocks. In the figure, H1 and H2 are headers to which the above-mentioned signals are added.

15 trick play transport packets read from the second memory 14 in units of 5 sync blocks (the data length of one sync block is 77 bytes).
The sync blocks are collected and an error correction code is added by the first error correction encoder 15. The operation of the first error correction encoder 15 will be briefly described below with reference to FIG. FIG. 8 shows the code structure of the error correction code added to the special reproduction data. In the first embodiment, the same (85, 77, 9) Reed-Solomon code (C1 check code) as the error correction code added to the bit stream of the ATV signal in the recording direction is used as the error correction code of the special reproduction data. , (20, 15, 6) Reed-Solomon code (C4 check code) having the same minimum distance as the audio signal in the vertical direction is used.

The special reproduction data read from the second memory 14 in units of 5 sync blocks is collected by the first error correction encoder 15 into 15 sync blocks to form one error correction block. Then, the C4 check code is added in the vertical direction. The C1 check code is added together with the ATV signal output from the first memory 12 by a second error correction encoder 17 described later to form an error correction block in the product code format. Since the minimum distance of the C4 check code is the same as that of the C3 check code of the audio signal as described above, the coding circuit can be shared with that of the audio signal only by changing the code length.

The data output from the first memory 12 and the first error correction encoder 15 is input to the first data synthesis circuit 16. In the first data synthesis circuit 16,
The data output from the first memory 12 and the first error correction encoder 15 are combined to generate the track format shown in FIG. Hereinafter, the first data synthesis circuit 1
The format generation control signal output from No. 6 will be briefly described.

As the recording format generation signal, a control signal is output to the first memory 12 in units of one sync block in the area for recording the bit stream of the ATV signal shown in FIG. 10 (or FIG. 12). The data of the one sync block output from the first memory 12 is stored in a predetermined area in the memory for track format generation provided in the first data synthesis circuit 16.

On the other hand, regarding the special reproduction data, when the format generation control signal is output from the first data synthesizing circuit 16, the data corresponding to the double speed number is read from the second memory and the first error correction code is read. After the C4 code is added by the device 15, it is temporarily stored in the buffer memory for each double speed provided in the first data synthesizing circuit 16. (Note that the special reproduction data is stored in the buffer memory in units of one error correction block. For quadruple speed reproduction, a buffer memory for two error correction blocks is provided.) Then, at a predetermined timing, the double speed trick play data is read by a predetermined number of sync blocks and is combined in the track format generation memory. To update the data in the above buffer memory,
When the reading of each special reproduction data is completed, the number of times the special reproduction data is repeated is confirmed. Then, when the number of repetitions is a predetermined number of times, it is executed by outputting a format generation control signal corresponding to the special reproduction data.

The data generated by the first data synthesizing circuit 16 is first added with the vertical error correction code (C2 check code) by the second error correction encoder 17 and then added with the error correction code in the recording direction. (C1 check code) is added.
Therefore, the C1 check code is added to the special reproduction data shown in FIG. 7 at this timing. The recording data to which the error correction code is added is digitally modulated by the recording amplifier 18, amplified, and then recorded on the magnetic tape via the rotary heads 20a and 20b.

A method for generating the trick play transport packet, which is an embodiment of the present invention, will be described below. FIG. 17 shows the scanning loci of the rotary head 20 (a) in the cases of 2 ×, 4 ×, 8 ×, and 16 × speed reproduction. As shown in the figure, the rotary head 20
8A and 2B in one scan of FIG. 8A, one error correction block in one scan of the rotary head 20 (a) in the 8 × speed reproduction, and 16 × speed reproduction in the 8 × speed reproduction.
The error correction block is set to 1 by two scans of the rotary head 20 (a).
You can play blocks.

Therefore, in the first embodiment, the trick play transport packet is generated in consideration of the above. FIG. 13A shows the screen structure of one frame of the ATV signal. As shown in the figure, the screen is composed of 1080 lines × 1920 pixels. In the first embodiment, when the ATV signal is encoded, as shown in FIG.
It is assumed that line dummy data (for example, black level data) is inserted for encoding. Therefore, 1 in the horizontal direction
20 macroblocks are arranged, and 68 macroblock rows are arranged vertically.

In the first embodiment, when the special reproduction transport packet is generated, the slice is constructed as follows in consideration of the data control at the time of high speed reproduction. When transmitting slice data, the code amount control circuit 44 controls the code amount so that the data in the same slice does not straddle two consecutive transport packets. In addition, when generating a transport packet,
The code amount control circuit 4 so that the data of all macroblocks belonging to the same macroblock row can be configured in the scanning period.
4 controls the code amount. Since the 16 × speed reproduction data is configured as described above, the code amount is controlled so that the data of all macroblocks belonging to two identical macroblock rows can be reproduced in the two scanning periods of the rotary head. And

Hereinafter, a method for generating a trick play transport packet corresponding to each double speed will be described with reference to FIGS. 2 and 3, focusing on the code amount control and the packet configuration method. First, a method of generating quadruple speed data will be briefly described.

The bit stream data input through the input terminal 50 is added with the transport header by the transport header adding circuit 53 in the above-described manner. The transport header (transmitted together with the bitstream) in the bitstream is removed.

The slice header adding circuit 54 adds a slice header to the bit stream to which the transport header has been added to reconstruct a slice. Specifically, every time the transport header is added by the transport header adding circuit 53, a slice header is generated and added to the bit stream. The data for quadruple speed reproduction can reproduce the data of two error correction blocks in one scanning period of the rotary head. That is, all the macroblock data belonging to the same macroblock row are transmitted by 12 transport packets. Therefore, the slice start code in the slice header takes the same value during this period. Regarding the generation of the slice header, the slice generation control circuit 55 detects the slice header from the bitstream, and detects the macroblock row of the bitstream currently input from the slice start code added in the slice header. . Also,
The transmitted slice header is removed after detection of the macroblock row.

The special reproduction data to which the slice header is added detects a DCT block from the bit stream, and EOB is forcibly added to each DCT block based on the control signal output from the code amount control circuit 44. Then, the transmission of the high frequency sequence data is terminated. The code amount control is performed so that the data of all the macroblocks belonging to the same macroblock row is included in the 12 transport packet. Specifically, in the first embodiment, since the transport header (4 bytes) and the slice header (4 bytes only with the slice start code) are added to the beginning of each transport packet, the code amount is taken into consideration. Control is performed.

Similarly, for 8-times speed data, code amount control is performed so that data of all macroblocks belonging to the same macroblock row can be transmitted by 6 transport packets. For 16x speed data, code amount control is performed so that data of all macroblocks belonging to two identical macroblock rows can be transmitted by 6 transport packets. The 16 × speed data will be briefly described below.

The bit stream data input through the input terminal 50 is added with a transport header by the transport header adding circuit 53. A slice header is added to the bit stream to which the transport header is added by the slice header adding circuit 54 to reconstruct a slice. (The method of adding the slice header is as described above.) As for the 16 × speed reproduction data, one error correction block data can be reproduced in two scanning periods of the rotary head. That is, data of all macroblocks belonging to two identical macroblock rows are transmitted by 6 transport packets.

In the first embodiment, control is not performed so as to transmit data of all macroblocks belonging to the same macroblock row by 3 transport packets, but 6 transport packets belong to two same macroblock rows. Control is performed so that data of all macroblocks is transmitted. This is because during high speed reproduction, the reproduction data has the error correction block shown in FIG. 7 once constructed and subjected to error correction. Therefore, the signal processing on the reproduction system side at the time of 16 × speed reproduction is performed in units of two scanning periods of the rotary head 20 (a). Therefore, in the 16 × speed reproduction data, there is one packet in which a slice start code indicating a different slice row appears in the middle of the transport packet. Regarding the generation of the slice header, the slice generation control circuit 55 detects the slice header from the bitstream, and detects the macroblock row of the bitstream currently input from the slice start code added in the slice header. .

The special reproduction data added with the slice header detects a DCT block from the bit stream, and EOB is forcibly added to each DCT block based on the control signal output from the code amount control circuit 44. It The code amount control is performed so that the data of all the macroblocks belonging to two identical macroblock rows are contained in the six transport packets. Specifically, the first embodiment
In consideration of the transport header (4 bytes) at the beginning of each transport packet, the slice header (4 bytes for the slice start code only), and the slice header portion of the packet that adds a slice to the middle of the transport packet Quantity control is performed.

The trick play transport packet constructed as described above has the following features. First of all, it has a characteristic of being strong against error propagation. This is because the transport packet is configured as described above, so the slice header is always added to each transport packet, and even if an error is detected in the reproduced data, the error propagation is the same horizontal macro. When the error is only one transport packet, it can be inferred by the continuity of the transport packet, since it does not spread to other than the block row.
An incorrect macroblock position can be estimated from the remaining data. Specifically, according to the MPEG2 standard, an image that has been intra-coded cannot be subjected to the macroblock skipping. By detecting the number of macroblocks, the position of the macroblock in which the error is detected can be detected. Then, at the time of transport packet synthesis, a still image packet is generated by the still image packet generation circuit 30 for this part of the packet, and a good reproduced image can be obtained. (Details of the still image packet generation circuit 30 will be described later.)

The second major feature is that the circuit configuration of the reproduction system during special reproduction is very simple. This will be described in detail later in the operation of the reproduction system.

The operation of the reproducing system when normal reproduction is performed by the digital VTR having the above recording format will be described below with reference to FIG. The data reproduced from the magnetic tape via the rotary heads 20a and 20b is amplified by the head amplifier 21 and then the signal detection circuit 2
At 2, the signal is detected and converted into reproduced digital data. At that time, the sync signal added to the head of each sync block is detected. The reproduced digital data output from the signal detection circuit 22 is digitally demodulated by the digital demodulation circuit 23. The digitally demodulated data is input to the ID detection circuit 24 and the first error correction decoding circuit 25. The ID detection circuit 24 separates the ID signal added to the head portion of each sync block on the basis of the synchronization signal detected by the signal detection circuit 22, and uses the error detection code added to the ID signal. I
An error included in the D signal is detected. On the other hand, in the first error correction decoding circuit 25, C1 added in the recording direction is added.
Correction of errors that occurred in the reproduced signal using the check code,
And detection is performed. The error-corrected data is input to the second error correction decoder 26 and the third error correction decoder 28.

In the second error correction decoder 26, the above C1
Data that has not been error-corrected by the check code (data for which an error has been detected or data for which an error has been overlooked) is subjected to error correction or error detection using the C2 check code. (C
2 Decoded. ) The data subjected to C2 decoding is input to the third memory 27. The third memory 27 separates the bit stream of the ATV signal from the input data and stores only the bit stream in the memory.
(The trick play data is discarded at this stage as in the conventional example.)

On the other hand, regarding the data input to the third error correction decoder 28, first, the special reproduction data recorded in the special reproduction data recording area is separated from the reproduction data, as shown in FIG. An error correction block is constructed. The special reproduction data recording area is separated by detecting the position of the special reproduction data recording area on the track by the sync block number recorded in the ID signal in the sync block and detecting the header in the sync block. By doing so, the data is special reproduction data or a normal AT.
It is determined whether the bit stream is the V signal.

When the data of one error correction block is constructed, the third error correction decoder 28 uses the C4 check code to perform error correction or error detection on the data that has not been error corrected by the C1 check code. Give. The data subjected to the C4 decoding is input to the fourth memory 29.

In the first embodiment, the minimum distance of the C4 check code of the trick play data and the minimum distance of the C3 check code of the audio data are designed to be the same. This is AT
Since the audio signal of the V signal is transmitted together with the digital video data in the bit stream of the ATV signal as described in the conventional example, it is not recorded in the audio signal area but is recorded together with the video signal in the video signal area. It will be. Therefore, the digital VT in which the ATV signal is recorded
When reproducing R, the error correction decoding circuit for audio signals is not used. In the first embodiment,
As described above, by making the minimum distance of the C4 check code and the minimum distance of the C3 check code the same, the third error correction decoder 28 is used in common with the error correction decoder of the audio signal to reduce the circuit scale. Plan.

The fourth memory 29 stores the inputted error-corrected special reproduction data in the memory. At the time of normal reproduction, the switch 32 is configured to always select the output of the third memory 27, and the ATV bit stream restored to the 188-byte packet information in the third memory 27 is output from the output terminal 33. To be done.

Next, FIG. 14 shows the operation of the reproducing system during high speed reproduction.
~ It demonstrates using FIG. In addition, in the first embodiment, as illustrated in FIG.
The case of the configuration of the rotary head shown in (a) will be described. FIG. 17 shows scanning loci of the rotary head 20a in the case of performing 2 ×, 4 ×, 8 ×, and 16 × speed reproduction. The scanning locus of the rotary head 20a shown in FIG. 17 is shown in FIG.
The configuration of the rotary head shown in (b) has the same trajectory.
(However, the rotary head 20 (b) has a completely different trajectory due to the different head arrangement.) First, the tracking control method during high-speed reproduction in the first embodiment will be described with reference to FIG. The number of sync blocks that can be reproduced from the track at each reproduction speed is as shown in FIG.

Therefore, in order to effectively acquire the special reproduction data, the rotary head 20 (a) is set so that the reproduction output becomes maximum at the center of the area in which the special reproduction data is recorded at each speed. ) Tracking control can be performed. 18A to 18C show the tracking control points of the rotary head 20 (a) at each reproduction speed. In the recording format shown in the first embodiment, 90
In the 00 rpm system, the data of one error correction block shown in FIG. 8 can be formed without using the data reproduced from the rotary head 20 (b). Was omitted.

Next, the transmission method of the special reproduction transport packet at the time of high speed reproduction in the first embodiment will be described. Particularly, the case of high speed reproduction in the reverse direction, in which the effectiveness of the transmission method becomes remarkable, will be described. When high-speed reproduction in the reverse direction is performed by the digital VTR having the recording format shown in FIG. 12, the slices are reproduced in the order opposite to that at the time of recording.

The reproduction order of the special reproduction data packet at the time of reverse high speed reproduction will be described with reference to FIG. FIG. 19
One example of the structure of the slice block in one frame is shown in (a). FIG. 2B shows the scanning locus of the rotary head 20 (a) when the -2 speed reproduction is performed. The same figure (c)
The reproduction order of the special reproduction data output from the rotary head 20 (a) is shown in FIG. The rotary head 20 is shown in FIG.
It shows the output order of the special reproduction data recorded in the quadruple speed area reproduced from (a).
(Reproduction signal output reproduced from the rotary head 20 (a) (different from envelope output)) As shown in the figure, during high-speed reproduction, the slice data is reproduced in reverse as described above. It is necessary to rearrange the slice data in the memory 29.

This is defined by the MPEG2 standard. According to the MPEG2 standard, the macroblocks must be transmitted in the order of raster scan from the macroblock arranged at the upper left of the screen as described above. Therefore, when the intra-frame data is input, the ATV decoder starts decoding the image data from the first slice. At that time, if the transmission order of the slices in the input bit stream is different from the predetermined order, the ATV decoder cannot compose the reproduced image. this is,
When the order of the reproduced slices is different in the ATV decoder (MPEG2 standard) This occurs because the function of deshuffling the decoded slices at a predetermined position on the screen is not supported. In such a case, in order to realize reverse high-speed reproduction, it is necessary to prepare a memory capable of storing at least one frame of the special reproduction data in the reproduction system and rearrange the reproduced data. is there.

In the first embodiment, the special reproduction data is divided into a plurality of frames and transmitted in order to eliminate the need for a data rearrangement memory during high speed reproduction in the reverse direction. 20 and 22 show the data transmission method of the first embodiment. In the first embodiment, data is detected from transport packets for special reproduction that are intermittently reproduced during high-speed reproduction, and data of all macroblocks belonging to a plurality of identical macroblock rows is collected to form slice blocks. This slice block is combined with a still image packet (details will be described later) generated by the still image packet generation circuit 30 to generate a transport packet of one frame and output to the ATV decoder. (Hereinafter, referred to as a partial refresh method.) Specifically, the output mode of the transport packet (image data) is transmitted as an inter-frame mode (field-to-field or frame-to-frame prediction mode).

In this case, the special reproduction data in slice units, which are intermittently reproduced at the time of high-speed reproduction, have headers changed so as to be transmitted in a forced intra-frame mode. 20 and 22 show a case where one frame is divided into n slice blocks. (N is an integer of 2 or more) Since the data is recorded on the magnetic tape as described above in the first embodiment, the slice block is formed by using the data of the macro blocks belonging to the same macro block row as a unit. Generally, a plurality of macroblocks having continuous macroblock addresses are collected to form the slice block.

The above partial refresh method in the case of performing high-speed reproduction in the forward direction will be described below with reference to FIGS. 20 and 21. FIG. 20A shows special reproduction data reproduced by the rotary head 20 when high-speed reproduction in the forward direction is performed. FIG. 11B shows a reproduction transport packet output from the switch 32 during special reproduction. It should be noted that one frame described in the figure indicates a reproduction transport packet for one frame of the special reproduction. A switching signal of the switch 31 is shown in FIG. Also, FIG.
Reference numeral 1 indicates data of each interframe output from the digital VTR. In the figure, the shaded portion of the data represents special reproduction data transmitted in the forced intra mode, and the other portion represents the transmission portion of the still image packet output from the still image packet generation circuit 30. In the first embodiment, as shown in FIG. 20, one frame of special reproduction image is divided into n slice blocks and transmitted.

Similarly, the above partial refresh method in the case of performing high speed reproduction in the reverse direction will be described with reference to FIGS. 22 and 23. FIG. 20A shows special reproduction data reproduced by the rotary head 20 when high speed reproduction in the reverse direction is performed. FIG. 11B shows a reproduction transport packet output from the switch 32 during special reproduction. It should be noted that one frame described in the figure indicates a reproduction transport packet for one frame of the special reproduction. A switching signal of the switch 31 is shown in FIG. Also, FIG.
3 shows data of each interframe output from the digital VTR.

Based on the above, the operation of the reproducing system during high speed reproduction will be described with reference to FIGS. When the high speed reproduction mode signal is input, the switch 32 is switched to the switch 3
Select the output of 1. Rotating heads 20a and 20b
The reproduction data intermittently reproduced via the head amplifier 21 is amplified by the head amplifier 21 and then detected by the signal detection circuit 22 to be converted into reproduction digital data. At that time, the sync signal added to the head of each sync block is detected. The reproduced digital data output from the signal detection circuit 22 is digitally demodulated by the digital demodulation circuit 23. Data that has been digitally demodulated is an ID
It is input to the detection circuit 24 and the first error correction decoding circuit 25. The ID detection circuit 24 separates the ID signal added to the head portion of each sync block on the basis of the synchronization signal detected by the signal detection circuit 22, and uses the error detection code added in the ID signal. To detect an error included in the ID signal.

On the other hand, in the first error correction decoding circuit 25,
The C1 check code added in the recording direction is used to correct and detect an error generated in the reproduced signal.
The data subjected to the C1 decoding is input to the third error correction decoder 28. The output of the first error correction decoding circuit 25 is also input to the second error correction decoding circuit 26, but C2 decoding cannot be performed because the data is intermittently reproduced as described above, and the transport is performed. Since a packet cannot be generated, the C2 decoding operation is not performed during high speed reproduction in the first embodiment.

The data corrected by the third error correction decoding circuit 28 is stored in the fourth memory 29.

On the other hand, the still picture packet generation circuit 30 generates a still picture packet. When the ATV decoder detects the still image packet, it replaces the slice data portion transmitted in the still image packet with the decoded image data of the previous frame. An example of a specific method of constructing a still image packet is shown below. The still image packet is a transport packet in which data of all macroblocks in all slices to which the transport packet belongs is composed of data having a motion vector of 0 and a prediction error of 0. The still image packet will be described first with reference to FIGS. 15 and 24.

FIG. 24A shows a method of constructing slices in the still image packet. In the first embodiment, the still image slice data is configured as shown by using macroblock skip. Specifically, following the slice header (including the slice start code), the data in the macroblock is composed of two macroblocks having a motion vector of 0 and a prediction error of 0. Therefore, when the slice is generated, it can be generated by generating the slice address added to the slice start code in the slice header and the macroblock address of the second macroblock and rewriting only that portion. The skipped macroblock is MP
In EG2, it will be interpolated on the screen of the previous frame,
The result is the same as when data of a macroblock having a motion vector of 0 and a prediction error of 0 is transmitted. Macroblock skip can be performed only for interframe data. (Note that the interpolation of data in the data of the previous frame is defined in the P frame.)

Then, the still picture packet generation circuit 30 collects a plurality of the still picture slices and generates a transport packet as shown in FIG. 24 (b). Note that one still image slice may form a transport packet.

The method of generating a still image packet will be described below with reference to FIG. A data output request signal from the input terminals 60 and 61, and the head of the slice block,
And the address of the last macroblock is input from the fourth memory 29.

When the macroblock address of the trick play data is input, the packet generation control circuit 69 generates two still picture packets based on this information. Specifically, the first still picture packet up to the macroblock immediately before the input first macroblock and the second still picture packet up to the last macroblock of one frame from the macroblock next to the last macroblock. Generate a still image packet. If the start of the input macroblock address is the first macroblock on the screen, only the latter packet is generated, and the last address of the input macroblock address is the last macroblock address on the screen. If it is, only the former packet is generated. The determination is made by the packet generation control circuit 69.

The packet generation control circuit 69 calculates a slice address based on the macro block address and outputs the slice address to the slice header generation circuit 65. The slice header generation circuit 65 generates a slice header based on the slice address. It should be noted that when the head slice header of each frame is generated, a picture header is also generated. Further, the transport packet header is also generated by the slice header generation circuit 65. In addition,
Regarding the generation of the picture header and the transport header, it is assumed that a control signal is output from the packet generation control circuit 69 to the slice header generation circuit 65 and generated based on the control information.

The macroblock address generation circuit 66 generates a macroblock address based on the control signal output from the packet generation control circuit 69. At this time, header information regarding the motion vector (the motion vector is 0) is also added. As a macro block address,
The relative address 1 of the first macro block and the relative address when the second macro block is skipped are generated. The relative address when skipping is
It is calculated based on the macroblock address output from the packet generation control circuit 69. The generated macroblock address is added to the bitstream based on the timing pulse output from the packet generation control circuit 69. In the still image macroblock generation circuit 67, the data of the macroblock having a prediction error of 0 is added to the bitstream based on the control signal output from the packet generation control circuit 69 to form a still image slice.
(See FIG. 24 (a))

Then, still picture slices including data from the head macroblock of one frame to the macroblock immediately before the head macroblock output from the fourth memory 29 are collected, and the first still picture slice is collected. An image packet is generated. Similarly, a still picture slice including data up to the last macroblock of one frame from the macroblock next to the last macroblock output from the fourth memory 29 is collected to generate a second still picture packet.
The first and second still image packets may be composed of a plurality of transport packets. In the case of being configured by being divided into a plurality of transport packets, it is assumed that the slice header generation circuit 65 adds a transport header in advance.

The fourth memory 29, the still image packet generating circuit 30, the switch 3 will be described below with reference to FIGS.
1 and the operation of the header replacement circuit 34 will be described.
In the first embodiment, at the time of 4 × speed reproduction and 8 × speed reproduction, 1 frame of special reproduction data is divided into 12 frames and transmitted. As described above, one frame of special reproduction data can be configured by scanning the rotary head 20 (a) 68 times. (That is, in the first embodiment, the data of all macroblocks belonging to the same macroblock row can be reproduced by one scan of the rotary head 20 (a).
This is because the frame is composed of 68 macroblock rows. Therefore, in the first embodiment, the rotary head 20
It is assumed that the special reproduction image is configured by transmitting the slice block configured by 5 scans of (a) for 4 frames and then transmitting the slice block configured by 6 scans for 8 frames. Similarly, during 16x speed reproduction, one frame of special reproduction data is divided into 6 frames and transmitted.

In the fourth memory 29, slice blocks are generated from the data output from the third error correction decoding circuit 28 in the above-described manner. When the slice block generation is completed, the fourth memory 29 stores the still image packet generation circuit 30.
To the data output request signal and the addresses of the first and last macroblocks of the slice block. When the data output request signal is input, the timing control circuit 68 confirms the state of the transport packet currently being output. When a still image packet is generated, the output of the packet is in a standby state until the output of the packet for one frame is completed. When a no-data packet (details will be described later) is being generated, the output of the packet is in a standby state until the completion of outputting the currently generated one packet. As described above, when the still image packet generation circuit 30 is generating a still image packet, the output of the packet is in a standby state because the inter-frame data is interrupted by the ATV decoder in the middle, and the data of another frame is lost. If the beginning of is input, malfunction may occur. The timing control circuit 68 controls the generation of packets to avoid this.

In the timing control circuit 68, when the standby state is released, the packet generation control circuit 69 receives the first
To output the first still image packet generation start signal to generate the still image packet, and the control signal to the switch 71 to select the output of the still image macroblock generation circuit 67. The switch 31 also outputs a control signal so as to select the output of the still image packet generation circuit 30. When the first still image packet generation start signal is input from the timing control circuit 68, the packet generation control circuit 6
9 controls the slice header generation circuit 65, the macroblock address generation circuit 66, and the still image macroblock data generation circuit 67 to generate a first still image packet. When the packet generation control circuit 69 finishes the generation of the first still image packet, it outputs a first still image packet generation end signal to the timing control circuit 68. When the timing control circuit 68 confirms the end of the output of the first still image packet, it outputs a data read start signal to the fourth memory 29, and outputs the signal to the switch 31 to the fourth memory 29.
The control signal is output so as to select the output of.

Upon receipt of the above signal, the fourth memory 29 reads the slice block constructed above from the beginning. When the reading of the slice block is completed, a data reading end signal is output to the timing control circuit 68. Upon receiving the signal, the timing control circuit 68 outputs a second still image packet generation start signal to the packet generation control circuit 69 to generate the second still image packet. (Note that the switch 71 selects the output of the still image macroblock generation circuit 67 until the transmission of data for one frame is completed.) Also, the switch 3
1 also outputs a control signal to select the output of the still image packet generation circuit 30.

When the second still image packet generation start signal is input from the timing control circuit 68, the packet generation control circuit 69 causes the slice header generation circuit 65, macroblock address generation circuit 66, and still image macroblock data generation circuit 67. To generate a second still image packet. When the packet generation control circuit 69 finishes generating the second still image packet, it outputs a second still image packet generation end signal to the timing control circuit 68. When the timing control circuit 68 confirms the end of the output of the second still image packet, the switch 71 outputs a control signal to select the output of the no-data packet generation circuit 70.
Then, the output of the packet generation circuit 70 is selected as no data until the next slice macroblock data or still image data is formed.

In the ATV bit stream, no data packet can be defined in the transport header. If no data packet is detected in the bitstream, the ATV decoder discards the packet. The no-data packet generation circuit 70 generates and outputs the packet.

The transport packet constructed as described above is input to the header changing circuit 34 via the switch 31. In the first embodiment, as described above, the transport packet is in the interframe mode (between fields,
Alternatively, it is transmitted as an interframe prediction mode). The special reproduction data output from the fourth memory 29 is transmitted in the forced intra-frame mode.
Therefore, when the trick play data is output, the header changing circuit 34 detects the header portion indicating the decoding mode of each macroblock, and changes this header to the compulsory intra frame mode header. Also,
When the special reproduction data has a picture header, a header portion indicating the transmission mode of the image is detected from the picture header and replaced with a header indicating an interframe (or interfield).

The operation of the header replacement circuit 34 will be described below with reference to FIG. The picture header of the data input through the input terminal 75 is detected by the picture header generation circuit 77. When the picture header is detected, the flag indicating the image transmission mode in the header is replaced with the interframe mode flag. The picture header added to the first still image packet is transmitted in the interframe mode in advance. However, in the first embodiment, the header portion is replaced without distinction.

The data whose picture header contents have been changed in the above manner is input to the forced intra flag adding circuit 79 and the special reproduction slice detecting circuit 78. The special reproduction slice detection circuit 78 outputs the fourth data from the input data.
The macro block address in the special reproduction slice block output from the memory 29 is detected. Example 1
Then, the switching signal of the switch 31 is used for detecting the special reproduction slice block. The detection result is input to the forced intra flag adding circuit 79. The forced intra flag adding circuit 79 replaces the flag indicating the decoding mode of the macro block following the detected macro block address with a flag for forcibly performing intra decoding. The header replacement circuit 34 also replaces the transport header in the bitstream. (Specifically, the header part indicating the continuity of the transport packet is changed.)

The reproduction transport packet at the time of special reproduction in which the header is changed is supplied to the output terminal 33 via the switch 32. As a result, the reproduction transport packet at the time of special reproduction is transmitted as an interframe packet, and the data of each macroblock is decoded by the ATV decoder in the forced intraframe mode.

The still image packet generation circuit 30 switches the packet to be output according to the amount of data output to the ATV decoder up to the present. Specifically, the amount of data (number of frames) transmitted to the ATV decoder side is too large ATV
When the memory in the decoder is likely to overflow, a packet of no data is output to control the code amount.
On the other hand, when the number is too small (underflow), the still image packet generation circuit 30 generates and outputs a transport packet in which one frame is composed of all still image slices.

Also in the first embodiment, in order to match the number of reproduction frames, about 3 frames per second during special reproduction, the above 1
It is necessary to generate a transport packet in which all frames are composed of still image slices. Then, the code amount of the ATV bit stream is controlled by using this transport packet and the no-data transport packet (the number of output frames is set so that the memory in the ATV decoder does not overflow or underflow as described above). Control.)

The generation timing is controlled by the timing control circuit 68 based on the data transmission amount information of the reproduced transport packet transmitted during the special reproduction. Further, the count of the data transmission amount (the number of frames) is counted at the output stage of the switch 32 in the first embodiment,
It is assumed that the count result is input to the still image packet generation circuit 30. Further, the data transmission amount can be obtained by counting the number of frame data that have been transmitted and have not been decoded yet, and the code amount thereof. In addition,
For simplicity, the number of frame data that has not been decoded may be used.

FIG. 20 and FIG. 21 show the reproduction transport packet at the time of special reproduction when the high speed reproduction in the forward direction generated in the above manner is performed. As shown in the figure, one frame of special reproduction data is divided into n frames of the transport packet and transmitted. The reproduced image is refreshed only in the special reproduction slice portion transmitted in the forced intra mode. In FIG. 21, the position on the screen (the position of the reproduced special reproduction area) that is rewritten when the transport packet of each frame is transmitted is shown by hatching. As shown in the figure, by transmitting the reproduction transport packet at the time of special reproduction, the reproduced image can be refreshed at a cycle of n frames from the slice data on the upper side of the screen of one frame at the time of high speed reproduction in the forward direction.

Similarly, FIG. 22 and FIG. 23 show the reproduction transport packet at the time of special reproduction when the reverse high speed reproduction generated in the above manner is performed. As shown in the figure, one frame of special reproduction data is divided into n frames of the transport packet and transmitted. The reproduced image is refreshed only in the special reproduction slice portion transmitted in the forced intra mode. In FIG. 23, the position on the screen (the position of the reproduced special reproduction area) that is rewritten when the transport packet of each frame is transmitted is shown by hatching. As shown in the figure, during high-speed reproduction in the reverse direction, the reproduced image can be refreshed at a cycle of n frames from the lower slice data of the screen of one frame. The operation of the reproduction system at the time of high-speed reproduction is almost the same in the forward direction and the reverse direction, or only the refresh direction of the reproduced image is different. The only difference in control is the operation of rearranging the slice data that has been played back during high-speed playback in the reverse direction when forming slice blocks.

As described above, by controlling the fourth memory 29, the still image packet generation circuit 30, the switch 31, the header reassignment circuit 34, and the switch 32,
The ATV decoder can compose a reproduced image without paying attention to the high-speed reproduction mode, and can generate a good high-speed reproduction image. Further, by adopting a combination of the still image packet and the no-data packet, it is possible to prevent the overflow and underflow of the memory in the ATV decoder and form a good special reproduction image.

Further, since the special reproduction data is generated at the time of recording as described above, when the still image packet is generated, each still image slice generated in the still image packet generation circuit 30 belongs to the same macroblock row. Macroblocks can be composed of slices that are still images. Therefore, when a still picture slice is generated, the still picture slice can be configured by only changing the slice address in the slice start code, so that the circuit scale can be reduced. Also, when constructing a slice block, the special reproduction data reproduced from each track is very easy to separate the slice headers at the time of high-speed reproduction because the head slice of the special reproduction data is the leftmost macroblock on the screen. Therefore, the circuit scale can be reduced. (Note that
The 16 × speed reproduction data can be detected every two scans of the rotary head. )

Further, since the special reproduction data of all macroblocks belonging to the same macroblock row can be constructed by one scanning of the rotary head, when the slice block is constructed, the rotation of the drum 19 corresponds to one frame. Interframe data can be generated, and the circuit scale of the timing control circuit 68 can be considerably reduced. If the control as described above is not performed at the time of recording, the data amount of the slice reproduced at the input of the fourth memory 29 must be counted and the slice block must be configured by the data amount.

Further, the control of writing and reading data in the fourth memory 29 can be greatly simplified. If the control as described above is not performed at the time of recording, if a slice is extracted from the reproduced packet and a new transport packet is not generated at the input of the fourth memory 29, the part as described above is generated. Data transmission by refresh was not possible. This occurs because the slice (or slice block) break does not necessarily match the transport packet break.

As described above, at the time of high speed reproduction, in the first embodiment, the reproduction data is not stored in the memory for high speed reproduction in units of one frame, but is stored in the memory for high speed reproduction in units of one slice block. The capacity can be reduced. Also, during high speed playback in the reverse direction,
Since the slices are reproduced in the order opposite to that at the time of recording, in order to compose a reproduced image by the ATV decoder, a rearrangement memory capable of storing at least one frame of high-speed reproduction data is used as a reproduction system. It was necessary to rearrange the reproduced data, but as mentioned above, the mode is switched to the interframe mode during high-speed reproduction, and the special reproduction data reproduced in slice units is forced into intraframe mode. By generating the mode-switching transport packet, the rearrangement memory becomes unnecessary. Further, as in the case of high speed reproduction in the forward direction, since the reproduction data is stored in the memory for high speed reproduction in units of one slice, the memory capacity can be reduced.
For example, in the first embodiment, since one frame of data is divided into 12 slice blocks and transmitted, the memory capacity can be reduced to about 1/12.

Therefore, in the first embodiment, since the output transport packet is controlled as described above, the memory capacity of the fourth memory 29 can be greatly reduced as compared with the case of the first embodiment. Specifically, a memory capable of storing data for one slice (several slices depending on the slice configuration) may be arranged, and it is not necessary to arrange the memory for one frame on the reproduction system side as described above. In particular, a read-only machine does not need to have a memory for one frame, so the circuit scale can be reduced. In the first embodiment, specifically,
The fourth memory 29 may be constituted by a memory having a memory capacity of 6 slice blocks × 2 for the 4 × speed data, which has the largest data amount. The ATV decoder can decode the transport packet without paying attention to the special reproduction mode.

Example 2. In the second embodiment, a method of generating another trick play transport packet at the time of recording will be described. In the first embodiment, when the special reproduction transport packet is generated, the slice is configured as follows in consideration of the data control at the time of high speed reproduction. When transmitting slice data, data in the same slice does not span two consecutive transport packets. Further, when the transport packet is generated, the data of all macroblocks belonging to the same macroblock row can be constructed in one scanning period of the rotary head. 16
Since the double speed reproduction data is configured as described above, the code amount control is performed so that the data of all macroblocks belonging to two identical macroblock rows can be reproduced in the two scanning periods of the rotary head.

The method of constructing the trick play transport packet in the second embodiment will be described below. Example 1
As described above, the trick play transport packets generated by the intra detection circuit 13 are combined and converted into a record data block of 5 sync blocks in the second memory 14 and recorded. (See FIG. 7) In the first embodiment, when the transport packet is generated, the slice header is always arranged at the head of each transport packet, but in the second embodiment, a plurality of transport packets are collected. For example, when transmitting slice data in a digital VTR having a recording format for reconstructing a recording data block as shown in FIG. 7B and recording it on a recording medium, data in the same slice is recorded in the plurality of recording data blocks. The code amount control circuit 44 controls the code amount so that the numbers do not cross over. When the transport packet is generated, the code amount control is performed so that the data of one macroblock row can be constructed in one scanning period of the rotary head as in the first embodiment. Further, with respect to the 16 × speed reproduction data, code amount control is performed so that two macroblock rows can be reproduced in two scanning periods of the rotary head.

The digital VTR in the second embodiment
The recording system configuration, the intra detection circuit 13 configuration, and the slice generation circuit 45 configuration are shown in FIGS.
Shall be the same as the one shown in. The recording format on the magnetic tape and the macroblock structure on the screen are also the same as those in the first embodiment.

In the following, a method for generating a trick play transport packet corresponding to each double speed number in the second embodiment will be briefly explained with reference to FIGS. 2 and 3 for controlling a code amount and a method for constructing a packet. First, a method of generating quadruple speed data will be described.

The bit stream data input through the input terminal 50 is added with the transport header for special reproduction by the transport header adding circuit 53. The transport header (transmitted together with the bitstream) in the bitstream is removed.

The slice header adding circuit 54 adds a slice header to the bit stream to which the transport header has been added to reconstruct a slice. When reconstructing a slice, the transport packet at the head of the recording block is detected, and a slice header is generated following the transport header. The data for quadruple speed reproduction can reproduce the data of two error correction blocks in one scanning period of the rotary head. That is, 12 transport packets form data of all macroblocks belonging to the same macroblock row. During this period, the slice start code in the slice header has the same value. The generation of the slice header is the same as that in the first embodiment, and therefore its description is omitted. The transmitted slice header is removed after detection of the macroblock row.

In the special reproduction data to which the transport header and the slice header are added, the DCB block is detected from the bit stream by the EOB adding circuit 7. Then, EOB is forcibly added to each DCT block based on the control signal output from the code amount control circuit 44. The code amount control is performed so that the data of all the macroblocks belonging to the same macroblock row is included in the 12 transport packet. Specifically, in the second embodiment, a transport header (4 bytes) is added to the beginning of each transport packet, and a slice header (4 bytes with only a slice start code) is added to each recording block. The code amount control is performed in consideration.

Similarly, for 8-times speed data, code amount control is performed so that data of all macroblocks belonging to the same macroblock row can be transmitted by 6 transport packets. For 16x speed data, code amount control is performed so that data of all macroblocks belonging to two identical macroblock rows can be transmitted by 6 transport packets. The 16 × speed data will be briefly described below.

The bit stream data input through the input terminal 50 is added with a transport header by the transport header adding circuit 53. A slice header is added to the bit stream to which the transport header has been added by the slice header adding circuit 54 to reconstruct a slice. When reconstructing a slice, as in the case of quadruple speed data, a transport packet at the head of the recording block is detected, and control is performed so that a slice header is generated following the transport header. Further, as the data for 16 × speed reproduction, the data of one error correction block can be reproduced in two scanning periods of the rotary head. Therefore, as described above, data of all macroblocks belonging to two identical macroblock rows are constituted by 6 transport packets. The control of the code amount is 6
It is done in transport packets.

The special reproduction data to which the slice header has been added is converted from the bit stream to DC by the EOB adding circuit 7.
T blocks are detected. Then, the code amount control circuit 44
The EOB is forcibly added to each DCT block based on the control signal output from the DCT block. The code amount control is performed so that the data of all the macroblocks belonging to two identical macroblock rows are included in the six transport packets. Specifically, as in the first embodiment, a transport header (4 bytes) is placed at the beginning of each transport packet, and a slice header (4 bytes with only a slice start code) in each recording block, and a transport packet Code amount control is performed in consideration of a slice header portion of a packet to which a slice is added on the way.

The transport packet for special reproduction constructed as described above has the following features. First, since the slice header is added to each recording block, basically only the slice header added to the transport packet at the head of the recording block needs to be considered at the time of reproduction. That is, the slice block can be configured without detecting the slice header in the transport packet during special reproduction. Further, since the slice header is not added to each transport header, the data amount of the image data for special reproduction is slightly improved, and the reproduction image quality during special reproduction is slightly improved.

Next, there is a characteristic of being strong against error propagation. This is because the transport packet is configured as described above, so a slice header is always added to each recorded data block, and even if an error is detected in the reproduced data, the error propagation is the same macroblock. If the error is only one transport packet, the slice header can be inferred by the continuity of the recording data blocks, and
An incorrect macroblock position can be estimated from the remaining data. Specifically, according to the MPEG2 standard, an image that has been intra-coded cannot be subjected to the macroblock skipping. By detecting the number of macroblocks, the position of the macroblock in which the error is detected can be detected. Then, when the transport packet is combined, the packet of this portion is transferred to the still image packet generation circuit 30.
A good reproduced image can be obtained by substituting the still image packet generated in.

Further, since the special reproduction data is generated at the time of recording as described above, when generating a still image packet as in the first embodiment, each still image slice is processed by all macroblocks belonging to the same macroblock row. Since the configuration can be made only by generating slices that are still images, the circuit scale of the still image packet generation circuit 30 can be reduced. Also, when composing slice blocks, the head special playback data played from each track is the leftmost macroblock on the screen, so it is very easy to separate slice headers during high-speed playback. The circuit scale can be reduced. (Note that the 16 × speed reproduction data can be detected every two scans of the rotary head.)

Further, the special reproduction data of all the macro blocks belonging to the same macro block row is the rotary head 1.
Since it can be configured by scanning, when constructing the slice block, one frame of interframe data can be generated in accordance with the rotation of the drum 19. Therefore,
The circuit scale of the timing control circuit 68 can be considerably reduced. In addition, data writing and reading control in the fourth memory 29 can be greatly simplified.

Example 3. In the third embodiment, a method of generating another trick play transport packet at the time of recording will be described. A method of constructing a trick play transport packet in the third embodiment will be described. As described in the first embodiment, two special reproduction transport packets generated by the intra detection circuit 13 are combined,
In the second memory 14, it is converted into a recording data block of 5 sync blocks and recorded. (See FIG. 7) Also, as described above, during special reproduction, the rotary head 20 is reproduced across the track diagonally. Therefore, when error correction is performed using only the C1 check code, the error detection probability is as described above. It becomes very high and a good reproduced image cannot be synthesized.

Therefore, as shown in the first embodiment, an error correction code as shown in FIG. 8 may be added to special reproduction data and recorded at the time of recording. As shown in FIG. 8, one error correction block is formed by special reproduction data and a C4 check code is added. In some cases, the error that has not been corrected by the C1 check code is subjected to error correction by the C4 check code to suppress the error that occurs in the special reproduction data. A method of generating a transport packet of a digital VTR having a recording format in which the C4 check code is added to the special reproduction data and transmitted will be described below.

First, a method of constructing the one error correction block will be described. Similar to the first embodiment, a recording data block composed of the above-mentioned 5 sync blocks is generated from two special reproduction transport packets (see FIG. 7). Then, collect three of the above recording data blocks and
The information symbol portion of the error correction block is formed, and the C1 check code and the C4 check code are added.

Next, a method of generating a transport packet according to the third embodiment will be described below. In the third embodiment, the digital VT having the recording format as described above is used.
When transmitting slice data in R, the code amount control circuit 44 controls the code amount so that the data in the same slice does not span the plurality of error correction blocks. That is, the slice header is always added to the transport packet at the head of the one error correction block. In addition,
When the transport packet is generated, the code amount control is performed so that the data of all macroblocks belonging to the same macroblock row can be constructed in one scanning period of the rotary head 20 as in the first embodiment. With respect to the 16 × speed reproduction data, the code amount is controlled so that the data of all the macroblocks belonging to two identical macroblock rows can be reproduced in two scanning periods of the rotary head 20.

The digital VTR in the third embodiment
Since the configuration and operation of the recording system are the same as those of the first embodiment except for the slice header generation unit, detailed description thereof will be omitted. Less than,
The operation of the slice header generation portion will be briefly described with reference to FIG. The bit stream data input via the input terminal 50 is added with a transport header for special reproduction by the transport header adding circuit 53. A slice header is added to the bit stream to which the transport header is added by the slice header adding circuit 54 to reconstruct a slice. In slice reconstruction, the transport packet at the head of the one error correction block is detected, and a slice header is generated following the transport header.

In the special reproduction data to which the transport header and the slice header are added, the DCT block is detected from the bit stream by the EOB adding circuit 7. Then, EOB is forcibly added to each DCT block based on the control signal output from the code amount control circuit 44. The code amount control is performed as described in the first embodiment. The recording format on the magnetic tape and the macroblock structure on the screen are the same as those in the first embodiment.

The transport packet for special reproduction constructed as described above has the following features. First of all, it has a characteristic of being strong against error propagation. In this, data of all the macroblocks belonging to the same macroblock row is formed in one scanning period of the rotary head as described above. In addition, the slice header is always added to the transport packet at the head of one error correction block, and even if an error is detected in the reproduced data, the propagation of the error does not spread to other than the same macroblock row, Further, since the slice header can be inferred from the continuity of the recording data blocks, when the error is only one transport packet, the incorrect macroblock position can be estimated from the remaining data.

In the data processing at the time of special reproduction, since the error correction is performed by the C4 check code, the slice block is formed after the error correction block shown in FIG. 8 is formed, so that the signal processing can be performed without difficulty. The error correction block does not need to be configured by one scan of the rotary head, and may be, for example, two scan periods or more scan periods (such as 0.5 scan period, or one scan period) as in 16 × speed reproduction data. The recording format may be constituted by a non-integer period such as .3 scanning period).

Further, since the special reproduction data is generated at the time of recording as described above, when generating a still image packet as in the first embodiment, each still image slice is processed by all macro blocks belonging to the same macro block row. Since the configuration can be made only by generating slices that are still images, the circuit scale of the still image packet generation circuit 30 can be reduced. Also, when composing slice blocks, the head special playback data played from each track is the leftmost macroblock on the screen, which makes it very easy to separate slice headers during high-speed playback. The circuit scale can be reduced. (Note that the 16x speed playback data is recorded on the rotary head 2
It can be detected for each scan. )

Further, the special reproduction data of all the macro blocks belonging to the same macro block row is stored in the rotary head 20.
Since it can be configured by one scan of the above, when the slice block is configured, interframe data of one frame can be generated in accordance with the rotation of the drum 19, so that the circuit scale of the timing control circuit 68 can be considerably reduced. In addition, data writing and reading control in the fourth memory 29 can be greatly simplified. In addition, since the slice header is small, the reproduction image quality is improved as compared with the first and second embodiments.

Example 4. In the above description, all the macro blocks belonging to one macro block row are set to the rotary head 20.
However, the present invention is not limited to this, and in the first embodiment, it is at the beginning of each transport packet, in the second embodiment, at the beginning of the recording data block, and in the third embodiment, 1 If at least a slice header is added to the beginning of the error correction block, when a slice block is generated, the number of transport packets is reproduced in the first embodiment, the number of recording data blocks in the second embodiment, and the number of recorded data blocks in the second embodiment. The number of error corrections should be counted and configured when the number of error corrections reaches a predetermined number.
When a still image packet is generated with 0, since the start address of the slice block is assigned as described above, all processing can be performed in transport packet units for special reproduction. Further, the end of the slice address can be confirmed by the slice header added to the next transport packet.

Therefore, by generating the transport packet for special reproduction as described above, the slice header is detected from the reproduced bit stream during the construction of the slice block during the special reproduction, and the transport packet is reconstructed. Since the bit stream of the special reproduction data can be generated without doing so, the circuit scale on the reproduction system side can be greatly reduced.

Example 5. In the fifth embodiment, a method of generating another trick play transport packet at the time of recording will be described. A method of constructing a trick play transport packet in the fifth embodiment will be described. In the fifth embodiment, when the transport packets are generated, the code amount control is performed so that the data of the macroblock on the left side of the screen comes to the head of each transport packet.

In a digital storage medium (for example, a digital VTR, a digital disc player, etc.) for recording MPEG2 signals, it is expected that data will be recorded in the form of transport packets. At this time, it is expected that the data of the intra packet is extracted as described above in order to realize the special reproduction and the signal is recorded in a predetermined area on the recording medium. For example 4: 2:
When a component signal defined by 2 is converted to a 4: 2: 0 signal to form an MPEG2 bit stream, the data amount of all special reproduction data belonging to the same macroblock row is smaller than that of the ATV signal. Become.

Therefore, one or more slice data composed of all macroblocks belonging to the same macroblock row can be transmitted by one transport packet. At that time, if the transport packet for special reproduction is configured so that the data of the macroblock on the left side of the screen comes at the beginning of each transport packet,
Control in the playback system is greatly simplified, and the circuit scale can be greatly reduced. Especially, in a reproduction-only machine of a digital disc player, the circuit scale of the reproduction system can be greatly reduced, which is a very effective means.

Further, the transport packet for special reproduction constructed as described above has a characteristic of being strong against error propagation. This is because the switching of macroblock rows is synchronized with the beginning of the transport packet, so that error propagation stays only within the transport packet.

Further, since the special reproduction data is generated at the time of recording as described above, when generating a still image packet as in the first embodiment, each still image slice is processed by all macro blocks belonging to the same macro block row. Since the configuration can be made only by generating slices that are still images, the circuit scale of the still image packet generation circuit 30 can be reduced. Also, when constructing slice blocks, the data at the beginning of each transport packet is the leftmost macroblock on the screen, so slice headers can be separated very easily during high-speed playback, and the circuit scale can be reduced. Can be achieved.

Since the special reproduction data of all macroblocks belonging to the same macroblock row can be composed of one transport packet, the number of reproduced transport packets is counted when composing the slice block. Since the slice block can be constructed by the above, the circuit scale of the timing control circuit 68 can be considerably reduced. In addition, data writing and reading control in the fourth memory 29 can be greatly simplified.

Example 6. Although the slice header is added in the transport packet unit, the recording data block unit, or the one error correction block unit in the above embodiment, the slice header is provided in the one sync block unit in the digital VTR in the sixth embodiment. It is a thing. In a digital disc player or the like, a slice header is added to the beginning of special reproduction data following a sync signal added to the data. If the slice header is constructed as described above, the control in the reproducing system can be greatly simplified and the circuit scale can be greatly reduced, as in the above embodiment. Especially, in a reproduction-only machine of a digital disc player, the circuit scale of the reproduction system can be greatly reduced, which is a very effective means.

Example 7. Hereinafter, another operation of the reproduction system during special reproduction of the digital VTR will be described. The recording format is the same as that in the first embodiment. The block configuration of the reproduction system, the block configuration of the still image packet generation circuit 30, and the configuration of the header changing circuit 34 are also the first embodiment.
Is the same as. The operation of the reproducing system will be described with reference to FIGS. The seventh embodiment differs from the first embodiment in the timing generation method at the time of outputting a reproduction transport packet for one frame of special reproduction during special reproduction. In the first embodiment, the output timing of the reproduction transport packet at the time of special reproduction of one frame is generated by the number of times the magnetic tape of the rotary head 20 (a) is operated. This time, the timing information of the output transport packet is synchronized with the frame synchronization of the TV or the like.

Hereinafter, the operation during high-speed reproduction of the fourth memory 29 and thereafter, which is a characteristic part of the seventh embodiment, will be described with reference to FIGS.
This will be described using 6. The circuit operation before the fourth memory 29 is the same as that of the first embodiment.

The data subjected to error correction by the third error correction decoding circuit 28 is stored in the fourth memory 29. On the other hand, in the still image packet generation circuit 30, a still image packet,
And generating an output timing signal of the bit stream for special reproduction. Hereinafter, a method for generating the output timing signal will be described. As described above, in the seventh embodiment, when the reproduction transport packet at the time of special reproduction is output to the ATV decoder, the output timing of the special reproduction image to be generated is output in synchronization with the frame synchronization of the TV or the like.

When the high speed reproduction mode signal is input, the switch 32 selects the output of the header changing circuit 34 and detects the frame frequency of the bit stream from the picture header. In the seventh embodiment, the description will be continued assuming that the frame frequency is 30 Hz. The detection result of the frame frequency is input to the timing control circuit 68. The timing control circuit 68 sets the frequency division value in the counter provided inside. Then, based on the frequency division result, the output timing signal is output so as to output the reproduction transport packet for the special reproduction for 30 sheets per second. Note that the still image packet generation operation in the still image packet generation circuit 30 is the same as that in the first embodiment, so description thereof will be omitted.

The output timing signal is output to the fourth memory 29 via the output terminal 64. Fourth memory 2
In 9, the slice blocks are constructed using the transports synthesized up to now, and the head and end macroblock addresses of the slice blocks are output to the packet generation control circuit 69. When two frames of transport packets are present in the memory, the macro block address of the frame data to be transmitted first is transmitted. The remaining special reproduction data is output when the reproduction transport packet for the next special reproduction is transmitted.

In the packet generation control circuit 69, when the macroblock address of the trick play data is input, based on this information, just before the input top macroblock as in the first embodiment, A first still image packet up to the macroblock and a second still image packet from the macroblock next to the last macroblock to the last macroblock of one frame are generated. If the start of the input macroblock address is the first macroblock on the screen, only the latter packet is generated, and the last address of the input macroblock address is the last macroblock address on the screen. If it is, only the former packet is generated. The determination is made by the packet generation control circuit 69.

On the other hand, when the output timing signal is output to the fourth memory 29, the timing control circuit 68 confirms the state of the transport packet currently being output. Then, when the bit stream of the previous frame is generated, the output of the first still image packet is in a standby state until the output of the packet for one frame is completed. When a no data packet is generated, the output of the first still image packet is in a standby state until the output of the currently generated one packet is completed.

In the timing control circuit 68, when the standby state is released, the packet generation control circuit 69 receives the first
To output the first still image packet generation start signal to generate the still image packet, and the control signal to the switch 71 to select the output of the still image macroblock generation circuit 67. The switch 31 also outputs a control signal so as to select the output of the still image packet generation circuit 30. When the first still image packet generation start signal is input from the timing control circuit 68, the packet generation control circuit 6
9 controls the slice header generation circuit 65, the macroblock address generation circuit 66, and the still image macroblock data generation circuit 67 to generate a first still image packet. When the packet generation control circuit 69 finishes the generation of the first still image packet, it outputs a first still image packet generation end signal to the timing control circuit 68. When the timing control circuit 68 confirms the end of the output of the first still image packet, it outputs a data read start signal to the fourth memory 29, and outputs the signal to the switch 31 to the fourth memory 29.
The control signal is output so as to select the output of.

Upon receipt of the above signal, the fourth memory 29 reads the slice block constructed above from the beginning. When the reading of the slice block is completed, a data reading end signal is output to the timing control circuit 68. Upon receiving the signal, the timing control circuit 68 outputs a second still image packet generation start signal to the packet generation control circuit 69 to generate the second still image packet. The switch 71 selects the output of the still image macroblock generation circuit 67. The switch 31 also outputs a control signal so as to select the output of the still image packet generation circuit 30.

When the second still image packet generation start signal is input from the timing control circuit 68, the packet generation control circuit 69 causes the slice header generation circuit 65, macroblock address generation circuit 66, and still image macroblock data generation circuit 67. To generate a second still image packet. When the packet generation control circuit 69 finishes generating the second still image packet, it outputs a second still image packet generation end signal to the timing control circuit 68. When the timing control circuit 68 confirms the end of output of the second still image packet, it outputs a control signal so that the switch 71 selects the output of the no-data packet generation circuit 70 until the next output timing signal is input. .

The transport packet constructed as described above is input to the header changing circuit 34 via the switch 31. The operation of changing the header information is the same as that in the first embodiment, and will not be described. The special reproduction data packet with the changed header is supplied to the output terminal 33 via the switch 32. As a result, the reproduction transport packet at the time of special reproduction is transmitted as an interframe packet, and the data of each macroblock is decoded by the ATV decoder in the forced intraframe mode.

In the seventh embodiment, it is not necessary to send a dummy frame packet in which one frame is a still image packet as in the first embodiment. This is because one frame of data is generated according to the frame cycle of the ATV decoder. Therefore, in the digital VTR, the reproduction transport packet at the time of special reproduction can be generated without considering the control such as overflow or underflow of the data transmitted to the ATV decoder side, and the circuit scale can be reduced. Specifically, the timing control can be greatly simplified because it is not necessary to generate the still image packet of one frame. In particular, the rotational speed of the drum is slightly changed in order to match the relative speeds of the magnetic tape and the rotary head 20 during special reproduction, but in this case the timing control becomes much simpler than in the first embodiment. In addition, the data transmission is the size of the slice block,
And the number of frames of partially refreshed and transmitted data varies from frame to frame.

As described above, by controlling the fourth memory 29, the still image packet generating circuit 30, the switch 31, the header changing circuit 34, and the switch 32,
The ATV decoder can compose a reproduced image without paying attention to the high-speed reproduction mode, and can generate a good high-speed reproduction image. Further, on the side of the digital VTR, control can be performed without worrying about the overflow and underflow of the memory in the ATV decoder, and a good special reproduction image can be constructed.

Further, since the special reproduction data of all the macro blocks belonging to the same macro block row can be constituted by one scanning of the rotary head, the output timing signal and the rotation of the drum 19 are constituted when the slice blocks are constituted. It is generated by the phase. In this way, by generating the data output timing, each still picture slice can be configured only by generating slices in which all macroblocks belonging to the same macroblock row are still pictures when a still picture packet is generated. When a still image slice is generated, it can be generated only by changing the slice address in the slice start code in the slice header, so that the circuit scale can be reduced.

When constructing a slice block,
Since the special reproduction data reproduced from each track is the leftmost macroblock on the screen, the slice header can be separated very easily during high speed reproduction, and the circuit scale can be reduced. (Note that the 16 × speed reproduction data can be detected every two scans of the rotary head.) Although not specifically described in the seventh embodiment, if the slice block is configured with one error correction block as a unit, the circuit scale is further increased. Reduction can be achieved. The slice structure during recording is not limited to that shown in the first embodiment. Example 2
The same effect can be obtained with the slice configuration shown in the sixth embodiment.

When the control for slice configuration as described above is not performed at the time of recording, the data amount of the slice reproduced at the input of the fourth memory 29 is set as described in the first embodiment. It is necessary to count and configure a slice block by the amount of data. Therefore, the writing and reading control of data in the fourth memory 29 becomes complicated. Also, in the reproduced transport packet, a slice is extracted from the transport packet, and the transport packet corresponding to the slice break does not generate a new transport packet for each detected slice, Data transmission by such partial refresh could not be performed. this is,
This occurs because the slice (or slice block) break does not necessarily match the transport packet break.

As described above, at the time of high-speed reproduction, in the seventh embodiment, the reproduction data is not stored in the memory for high-speed reproduction in 1-frame units, but is stored in the memory for high-speed reproduction in 1-slice block units. The capacity can be reduced. In addition, the rearrangement memory, which was necessary for high-speed reproduction in the reverse direction, is unnecessary. Also,
Since the reproduction data is stored in the memory for high-speed reproduction in units of one slice as in the case of high-speed reproduction in the forward direction, the memory capacity can be reduced. In particular, since it is not necessary to have a memory for one frame in a reproduction-only machine or the like, the circuit scale can be reduced, and the ATV decoder can decode transport packets without being aware of the special reproduction mode.

Example 8. Further, in the above embodiment, a still image packet having a motion vector of 0 and a prediction error of 0 is transmitted. However, the present invention is not limited to this. For example, when data during special reproduction is not transmitted, the previous frame (or the previous frame) is transmitted. A similar effect can be obtained with a packet that is interpolated with a field image. In particular, if the special reproduction image of one frame is divided into a plurality of frames and transmitted as described in the first or seventh embodiment, the memory capacity in the reproduction system can be reduced and the circuit scale can be reduced. Needless to say.

For example, as another still picture packet generation method, a flag called DSM trick mode is defined in the system header portion of MPEG2. In the high-speed playback mode defined by this flag, a flag called intra slice refresh is defined, and if slice data has not been played back in the transport packet in which this flag is defined, it is interpolated by the data of the previous frame. Have meaning. However, the position of the macroblock in the slice data is defined only by the relative address, so for example, how to control the data of the first slice when the address in the row direction of the slice is skipped, or There is no description in the decoder that the head slice must always start from the data of the left macroblock.

Therefore, when transmitting the special reproduction data that has been reproduced by using the DSM trick play flag, when the slice addresses in the row direction are discontinuously output when the partial refresh is performed, , The data of the first macroblock of the first slice of the discontinuous portion is transmitted so as to be composed of the macroblock on the left side of the screen. As described above, if the slice is configured, the transport packet at the time of special reproduction by the partial refresh can be transmitted even if the decoder of MPEG2 uses the above DSM trick mode flag, and the circuit scale of the reproducing system can be reduced. You can do it. Needless to say, the circuit scale in the reproducing system can be further reduced by configuring the slices as shown in Examples 1 to 6 during recording.

Example 9. In the above embodiment, the still image packet is described to be generated in transport packet units, but the present invention is not limited to this, and it is reproduced (when slice blocks in special reproduction are configured in transport packet units). The same effect can be obtained by generating a transport packet by inserting a macroblock having a motion vector of 0 and a prediction error of 0 from the middle of the special reproduction transport packet. Further, the same effect can be obtained even if the special reproduction data (slice unit) reproduced after the macro block showing the still image is inserted to form the transport packet.

Example 10. In the above embodiment, the recording data block is composed of block data of 5 sync blocks by using two transport packets as shown in FIG. 8B, but the present invention is not limited to this. (In particular,
In a disc player for recording / reproducing or reproducing a digital signal which has not been standardized yet, it is expected that the structure of one sync block is different from that of the digital VTR. ) In addition, 1 constructed by using special playback data
The structure of the error correction block is not limited to that shown in FIG.

Example 11. Although the trick play data is handled as frame image data in this embodiment, the present invention is not limited to this, and if the transmitted transport packet is a field image, it is treated as a field image and similar processing is performed. For example, the same effect is obtained. It may also be a non-interlaced image. Further, in the above embodiment, the data recording format is shown in FIG.
However, the present invention is not limited to this, and a digital VTR for recording a digital signal that has been subjected to high efficiency coding by a high efficiency coding method using motion compensation prediction represented by MPEG2 is used. If the digital signal reproducing apparatus has a format in which the intra-coded data as the special reproduction data is separated from the signal, and the separated special reproduction data is recorded in a predetermined area on the recording medium. It goes without saying that the same effect can be obtained by the above control. In the above embodiment, the special reproduction data is recorded on one track on the operation track of the rotary head, but the special reproduction data area is recorded on a plurality of tracks on the operation track of the rotary head. Even in the case, the same effect can be obtained by configuring the trick play transport packet as described above. In the above embodiment, the digital VTR was described as one embodiment of the digital signal reproducing apparatus, but the present invention is not limited to this, and the slice structure at the time of recording such as a disc player for recording the above signal in the above-mentioned manner,
Also, the same effect can be obtained when used for controlling the reproduction system during special reproduction.

[0210]

Since the present invention is constructed as described above, it has the following effects.

According to a first aspect of the present invention, there is provided a digital signal reproducing apparatus and a recording / reproducing apparatus, which are digital coded in a frame or field, or in a frame or interfield coded in a transport packet state. In a digital signal recording / reproducing apparatus in which a video signal and a digital audio signal are transparently recorded, data separation for separating a frame or intra-field-encoded digital video signal from the transport packet, and the separated frame Alternatively, the intra-field-encoded digital video signal is reconstructed to generate a special reproduction transport packet, and a plurality of special reproduction transport packets thus generated are collected to form a special reproduction block. At this time, the special reproduction block is configured so that the slice data does not straddle the plurality of special reproduction blocks, and the data output from the special reproduction block configuring means is predetermined on the recording medium. Since it is recorded in a different area, transport packets for special reproduction that are extremely resistant to error propagation can be generated, and the control in the reproduction system is greatly simplified, resulting in a significant reduction in circuit scale.

According to the second aspect, when the special reproduction transport packet is generated, the special reproduction transport packet is prevented so that the data in the same slice does not straddle a plurality of the special reproduction transport packets. Since a port packet is generated, it is possible to generate a bitstream without performing the operation of extracting the slice header from the special reproduction transport header and generating a new special reproduction transport header during special reproduction. This has the effect of reducing the circuit scale of the system.

According to the third aspect, when the special reproduction transport packet is generated, the special reproduction packet is generated so that the slice data is composed of all macroblocks belonging to the same macroblock row. Therefore, since the timing of outputting a one-frame bit stream at the time of special reproduction can be controlled by the number of reproduction packets of the special reproduction transport packet, it is possible to generate the output timing of data very easily.
The amount of data for one frame is smaller than that of the ATV signal. For example, 4:
A digital storage medium that records / reproduces or reproduces data generated by taking over the MPEG2 standard after converting a 2: 2 component signal into a 4: 2: 0 color-difference line-sequential signal is very effective in a circuit scale of a reproducing system. There is an effect that can be reduced.

According to the fourth aspect, when the special reproduction block is constructed, the special reproduction block is constructed so that the data in the special reproduction block is composed of all macroblocks belonging to the same macroblock row. Since it is possible to control the timing of outputting a one-frame playback transport packet during special playback by the number of playback blocks of the special playback block, it is possible to generate data output timing very easily. One transport packet has an effect that the circuit scale of the reproducing system can be very effectively achieved with an ATV signal having a relatively large amount of data in which it is difficult to transmit all macroblocks belonging to the same macroblock row. In addition, the reproduced image quality is improved as compared with the other embodiments, which have fewer slice headers.

According to the present invention, the special reproduction block is formed on the recording medium so that the special reproduction block can be constructed in one scanning period of the rotary head when the special reproduction is performed at a predetermined speed. Since the playback system can generate the timing for outputting the bit stream data of one frame at the time of special playback, the playback system can use the number of operations of the rotary head of the drum to further reduce the circuit scale in the playback system. There is an effect that can be.

According to the sixth aspect, since the special reproduction block configuring means is controlled so that the special reproduction block is composed of the two special reproduction transport packets, it is defined by the SD standard. Digital VT
There is an effect that the transport packet for special reproduction can be effectively packed in R.

According to claim 7, a plurality of the special reproduction transport packets are collected, and the special reproduction block is the data of one error correction block to which an error correction code in a direction different from the recording direction is added. Since the trick play block forming means is controlled so as to configure the above, it is possible to generate the timing of outputting the bit stream data of one frame at the time of the trick play by using the completion timing of the error correction decoding, and to increase the circuit scale in the playback system. There is an effect that can be further reduced.

According to the eighth aspect, the special reproduction transport packet is generated such that the data of the head macroblock of the special reproduction transport packet is composed of the macroblock on the left side of the screen. ,
When recording data, which is transmitted at a relatively low rate as compared with the ATV signal, on the digital storage medium, the special reproduction packet can be efficiently constructed and the circuit scale of the reproduction system can be effectively reduced.

According to the ninth aspect, a digital video signal, which is input in the form of a transport packet and is encoded in a frame or field or between frames or fields, and a digital audio signal are transparently recorded. At the same time, the special reproduction data used for special reproduction is generated from the digital video signal encoded in the frame or field by the transport, and the generated special reproduction data is recorded at a predetermined position. In a digital signal reproducing apparatus for reproducing a recording medium, a data separation means for separating the special reproduction data from the reproduction signal at the time of special reproduction, a data storage means for storing the separated special reproduction data, and a digital signal Data output from the playback device When decoding and restoring the reproduced image data, a specific area fixed packet generating means for generating a transport packet for stopping the signal of the specific area on the screen and a special reproduction transport packet data for one frame are output. The data output control means for generating the output timing control signal is provided, and when the reproduced image is constructed by using the data reproduced intermittently, the data output control means outputs the output timing signal at a predetermined timing. . When the output timing signal is output, the data storage means detects the position of the special reproduction data stored on the screen, and outputs the detected position information to the specific area fixed packet generation means. The specific area fixed packet generation means outputs a transport packet for stopping the image data portion of one frame which is not yet constructed in the data storage means.
Since these signals are combined and output, the memory capacity of the memory for storing the special reproduction data can be significantly reduced in the reproduction system, and the reproduction system can be controlled very much. There is an effect that can be simplified.

According to the tenth aspect of the invention, the output timing signal output from the data output control means is generated at a predetermined timing by counting the number of times of scanning of the rotary drum head. Even if the number of rotations of the drum is changed for matching, the signal can be generated according to the number of rotations of the drum, so that there is an effect that the timing can be generated very easily.

According to the eleventh aspect, the output timing signal output from the data output control means is generated in synchronism with the frame frequency of the externally connected display device separated from the reproduced data. Since it is configured as described above, it is not necessary to change the control for generating the special reproduction data depending on the type of external display device.
There is an effect that the timing can be generated very easily and the connection with the device having different frame frequency can be performed very easily.

According to the twelfth aspect of the invention, the data of all macroblocks in the transport packet by the specific area fixed packet generating means constitutes data in which the motion vector is 0 and the prediction error is 0. When transmitting data, the picture header is generated and changed so that the transmission mode of all image data becomes the interframe mode, and only the special playback data is decoded as the forced intra mode in the interframe image. As described above, since the header information is changed and transmitted, the circuit scale of the reproduction system on the digital storage medium side can be reduced, and the ATV decoder side does not recognize the reproduction state of the digital storage medium and directly The effect of being able to decode the input bitstream There is.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a recording system of a digital VTR which is an embodiment of the present invention.

FIG. 2 is a block configuration diagram of an intra detection circuit that is an embodiment of the present invention.

FIG. 3 is a block configuration diagram of a slice generation circuit according to an embodiment of the present invention.

FIG. 4 is a configuration diagram of a DCT block and a macro block in an ATV signal.

FIG. 5 is one embodiment of the present invention based on the SD standard 1
It is a figure which shows the data arrangement in a track.

FIG. 6 is a layout diagram of rotary heads 20 (a) and 20 (b) on a typical rotary drum 19 used in the SD mode.

FIG. 7 is a transport packet diagram of an input bitstream that is an embodiment of the present invention and a record data packet diagram to be recorded on a magnetic tape.

FIG. 8 is a code configuration diagram of an error correction code added to special reproduction data of a digital VTR according to an embodiment of the present invention.

FIG. 9 is a diagram showing the number of sync blocks capable of collecting data during high-speed reproduction.

FIG. 10 is a digital VTR which is an embodiment of the present invention.
The layout of the data recording area for special playback in the track
FIG. 3 is a diagram showing an arrangement of data to be recorded in a special reproduction data recording area.

FIG. 11 is a digital VTR which is an embodiment of the present invention.
FIG. 6 is a diagram showing a method of dividing one error correction block of 16 × speed data (−14 × speed).

FIG. 12 is a digital VTR which is an embodiment of the present invention.
It is a figure which shows the track format of.

FIG. 13 is a diagram showing a configuration on a screen of a macro block of an ATV signal which is an embodiment of the present invention.

FIG. 14 is a digital VTR which is an embodiment of the present invention.
3 is a block configuration diagram of a reproduction system of FIG.

FIG. 15 is a block configuration diagram of a still image packet generation circuit that is an embodiment of the present invention.

FIG. 16 is a block configuration diagram of a header replacement circuit according to an embodiment of the present invention.

FIG. 17 is a digital VTR which is an embodiment of the present invention.
FIG. 7 is a head scanning locus diagram of the rotary head 20 (a) when high-speed reproduction of 2 times, 4 times, 8 times, and 16 times is performed.

FIG. 18 is a digital VTR which is an embodiment of the present invention.
FIG. 8 is an operation explanatory view for explaining the tracking control operation of FIG.

FIG. 19 is a digital VTR which is an embodiment of the present invention.
FIG. 8 is an explanatory diagram of an operation during special reproduction in the reverse direction of FIG.

FIG. 20 is a digital VTR which is an embodiment of the present invention.
FIG. 7 is a diagram for explaining the state of a reproduction transport packet at the time of special reproduction in the forward direction.

FIG. 21 is a digital VTR which is an embodiment of the present invention.
FIG. 7 is a diagram showing partial refresh on the screen during special playback in the forward direction of FIG.

FIG. 22 is a digital VTR which is an embodiment of the present invention.
FIG. 6 is a diagram for explaining a state of a reproduction transport packet at the time of special reproduction in the reverse direction of FIG.

FIG. 23 is a digital VTR which is an embodiment of the present invention.
FIG. 6 is a diagram showing partial refresh on the screen during special playback in the reverse direction of FIG.

[Fig. 24] Fig. 24 is a configuration diagram of a still image slice according to an embodiment of the present invention and a configuration of a transport packet including the still image slice.

FIG. 25 is a track pattern diagram of a general home digital VTR.

FIG. 26 is a diagram showing a head scanning locus during normal reproduction and high-speed reproduction of a conventional digital VTR.

[Fig. 27] Fig. 27 is a block configuration diagram of a conventional bitstream recording device capable of high-speed reproduction.

FIG. 28 is a diagram showing an outline of a conventional digital VTR during normal reproduction and high-speed reproduction.

FIG. 29 is a head scanning locus diagram during general high-speed reproduction.

[Fig. 30] Fig. 30 is a diagram for explaining an overlapping area at a plurality of conventional high-speed reproduction speeds.

FIG. 31 is a head scanning locus diagram at 5 × speed and 9 × speed in a conventional digital VTR.

FIG. 32 is a locus diagram of two head scans during 5 × speed reproduction in a conventional digital VTR.

FIG. 33 is a track layout diagram of a conventional digital VTR.

FIG. 34 is a data format diagram of a video signal recording area in one track of a video signal according to the SD standard.

FIG. 35 is a diagram showing the structure of one sync block in the SD standard.

[Explanation of symbols]

4 variable length decoder, 7 EOB addition circuit, 11 packet detection circuit, 12 first memory, 13 intra detection circuit, 14 second memory, 15 first error correction encoder, 16 first data combination circuit, 29 fourth memory, 30 still image packet generation circuit, 31, 32, 71
Switch, 34 header changing circuit, 42 intra packet header detection circuit, 43 memory, 44 code amount control circuit, 45 slice generation circuit, 53 transport header addition circuit, 54 slice header addition circuit, 55 slice generation control circuit, 65 slice Header generation circuit, 66 macroblock address generation circuit,
67 still picture macroblock data generation circuit, 68 timing control circuit, 69 packet generation control circuit, 70
No data packet generation circuit, 77 picture header generation circuit, 78 special reproduction slice detection circuit, 79 forced intra flag addition circuit.

Claims (12)

[Claims] 1. A digital signal recording / reproducing apparatus for transparently recording a digital audio signal and a digital video signal input in the form of a transport packet and encoded in a frame or field or between frames or fields. ,
Data separation means for separating the frame or field encoded digital video signal from the transport packet and the frame or field encoded digital video signal separated by the data separation means are reproduced. Special reproduction packet generating means for forming special reproduction transport packets, and special reproduction forming a special reproduction block by collecting a plurality of special reproduction transport packets output from the special reproduction packet generating means. A special reproduction block, and when the special reproduction block is generated, the special reproduction block is configured so that the data of the same slice does not straddle a plurality of special reproduction blocks. Data output from the block forming means is predetermined on the recording medium. Digital signal recording and reproducing apparatus characterized by comprising a recording data control means for controlling the recording data to record in the area. 2. When the special reproduction transport packet is generated, the special reproduction packet generating means is controlled so that the data in the same slice does not straddle a plurality of the special reproduction transport packets. The digital signal recording / reproducing apparatus according to claim 1, which is characterized in that. 3. The special reproduction packet generating means is controlled so that when the special reproduction transport packet is generated, the slice data is composed of all macroblocks belonging to the same macroblock row. The digital signal recording / reproducing apparatus according to claim 2. 4. When configuring the special reproduction block,
2. The digital signal recording / reproducing apparatus according to claim 1, wherein the special reproduction block forming means is controlled so that the data in the special reproduction block is composed of all macroblocks belonging to the same macroblock row. 5. The special reproduction block is arranged on a recording medium so that at least one special reproduction block can be formed in one scanning period of the rotary head when special reproduction is performed at a predetermined speed. Claim 1 characterized by the above.
Digital signal recording / reproducing apparatus described 6. The digital signal recording / reproducing apparatus according to claim 4, wherein the special reproduction block is composed of two special reproduction transport packets. 7. The digital signal recording / reproducing apparatus according to claim 1, wherein the special reproduction block is composed of one error correction block to which an error correction code in a direction different from the recording direction is added. 8. The digital signal recording / reproducing apparatus according to claim 2, wherein the data of the head macroblock of the trick play transport packet is composed of a macroblock on the left side of the screen. 9. A digital video signal, which is input in the form of a transport packet and is encoded in a frame or field, or between frames or fields, and a digital audio signal are transparently recorded, and the transport packet is also provided. The special reproduction data used for special reproduction is generated from the digital video signal encoded in the frame or field, and the recording medium in which the generated special reproduction data is recorded at a predetermined position is reproduced. In the digital signal reproducing device, data separating means for separating the special reproducing data from the reproduced signal during special reproduction, data storing means for storing the separated special reproducing data, and the digital signal reproducing device Decode and play data A specific area fixed packet generating means for generating a transport packet for stopping a signal in a specific area on the screen when restoring the image data,
Data output control means for generating an output timing control signal when outputting one-frame special reproduction transport packet data is provided, and when the reproduced image is constructed using the data reproduced intermittently, the above data output is carried out. When the output timing signal is output from the control means at a predetermined timing, the special reproduction of one frame is performed by using the output of the specific area fixed packet generation means and the special reproduction data stored in the data storage means. A digital signal reproducing device characterized by controlling so as to generate and transmit data for use. 10. A digital signal reproducing apparatus according to claim 9, wherein the output timing signal output from said data output control means is generated in synchronization with the number of scanning times of the rotary drum head. 11. The output timing signal output from the data output control means is synchronized with the frame frequency of a display device connected to the outside.
The digital signal reproducing device described. 12. The transport packet output from the specific area fixed packet generating means is configured such that data of all macroblocks in the packet is data having a motion vector of 0 and a prediction error of 0, and is special. 10. The digital signal reproducing apparatus according to claim 9, wherein the transmission mode of all the image data during reproduction is an interframe mode, and only the special reproduction data is transmitted as a forced intra mode in the interframe image.