[go: up one dir, main page]

JPH09508496A - Semiconductor memory device having a plurality of memory chips in a common package - Google Patents

Semiconductor memory device having a plurality of memory chips in a common package

Info

Publication number
JPH09508496A
JPH09508496A JP7520319A JP52031995A JPH09508496A JP H09508496 A JPH09508496 A JP H09508496A JP 7520319 A JP7520319 A JP 7520319A JP 52031995 A JP52031995 A JP 52031995A JP H09508496 A JPH09508496 A JP H09508496A
Authority
JP
Japan
Prior art keywords
substrate
memory device
semiconductor memory
board
outer lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7520319A
Other languages
Japanese (ja)
Inventor
ミヒアエル、エワルト
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of JPH09508496A publication Critical patent/JPH09508496A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

(57)【要約】 半導体メモリ素子は、共通の基板（Ｔ）に固定されかつその外側リード端子（Ａ）と接続されている同一或いは異種のメモリ種類（ＤＲＡＭ、ＳＲＡＭ、Ｅ（Ｅ）ＰＲＯＭ等）の複数個のメモリチップ（Ｃ）を備え、各メモリチップ（Ｃ）の各接続点（Ｋ）に正確に基板（Ｔ）の外側リード端子（Ａ）が付属している。第一の実施例においては複数個のメモリチップ（Ｃ）を備えた基板（Ｔ）がその外側リード端子（Ａ）を除いて封止するパッケージ（Ｕ）を備え、選択的にモジュール板（Ｍ）に固定される。第二の実施例においては複数個のメモリチップ（Ｃ）を備えた基板（Ｔ）がモールド型（Ｆ）或いはモールド樹脂（Ｈ）で、基板（Ｔ）のモジュール板（Ｍ）の反対側を、基板（Ｔ）の下にあるモジュール板（Ｍ）部分及びモールド型（Ｆ）或いはモールド樹脂（Ｈ）からなるパッケージ（Ｕ）が基板（Ｔ）の外側リード端子（Ａ）をも含むように覆われる。 (57) [Summary] A semiconductor memory device is the same or different type of memory (DRAM, SRAM, E (E) PROM, etc.) fixed to a common substrate (T) and connected to its outer lead terminal (A). ), A plurality of memory chips (C) are provided, and the outer lead terminals (A) of the substrate (T) are accurately attached to each connection point (K) of each memory chip (C). In the first embodiment, a substrate (T) having a plurality of memory chips (C) is provided with a package (U) which is sealed except for its outer lead terminals (A), and a module plate (M) is selectively provided. ) Fixed. In the second embodiment, the substrate (T) provided with a plurality of memory chips (C) is a mold (F) or a mold resin (H), and the opposite side of the module plate (M) of the substrate (T) is used. , The package (U) consisting of the module plate (M) under the substrate (T) and the mold (F) or the mold resin (H) also includes the outer lead terminals (A) of the substrate (T). To be covered.

Description

【発明の詳細な説明】 共通のパッケージに複数個のメモリチップを備えた半導体メモリ素子 この発明は、請求項１及び２の上位概念による半導体メモリ素子及び請求項１ ４及び１５の上位概念による半導体メモリ素子の製造方法に関する。 コンピュータシステムにおいてはメモリ需要の増大によりかなり以前から例え ばＤＲＡＭ、ＳＲＡＭ、、Ｅ（Ｅ）ＰＲＯＭ等の特定のメモリ種類のメモリチッ プをコンピュータに装着する個別モジュールは殆ど使用されていない。寧ろ標準 的には、ＳＩＭＭ（シングル・イン・ライン・メモリモジュール）と呼ばれる、 例えば同一メモリ種類の９個のメモリ素子を１つのモジュール板に差し込み或い はろう付け接続（例えば表面実装）で固定されるメモリモジュールが採用される 。メモリ素子を装着したメモリモジュールは一体としてコンピュータに組み込ま れ（ろう付け或いは差し込みにより）、また必要な場合全体として交換もしくは 他のものにより補完される。 図１はモジュール板Ｍ、９個のメモリ素子Ｓ（ＤＲＡＭの代わりにＳＲＡＭ、 Ｅ（Ｅ）ＰＲＯＭ等も可）及びモジュール端子１乃至３０を備えた標準メモリモ ジュール（例えば４Ｍ×９ＤＲＡＭ）を示す。モジュール端子１乃至３０は図示 されていない電気導体を介して、差し込み接続或いは表面接続（例えばろう付け ）でメモリ素子Ｓの外側のリード端子Ａが固定されている接続点に接続されてい る。メモリ素子Ｓはこの場合素子４個の列と５個の列との２列に配置されている が、他の構成も可能である。 図２は代表的なメモリ素子を示す。メモリチップＣは基板Ｔ1（金属スパイダ 、フィルム等）に糊付け、合金接続等によって取り付けられている。メモリチッ プＣの接続点Ｋと基板Ｔ1の外側リード端子Ａとの間に電気接続線Ｂ（例えば金 線）が取り付けられている。その他メモリチップＣ及び基板Ｔ1は、主としてプ ラスチックからなり（代わりにセラミックも使用される）予め製作されている（ プレモールド）か、直接基板Ｔ1とチップＣにモールドされている（ポストモー ルド）パッケージＵを備えている。基板Ｔ1とパッケージＵとは電気接続線Ｂを 含めて メモリチップＣのケーシングを構成する。 図３ａ乃至３ｃは、図２において示されたメモリ素子（図３では平面で示され る）の製造工程を示す。図３ａは、その形からスパイダとも言われる基板Ｔ1を 示す。基板Ｔ1の中央にメモリチップＣが固定されている。Ａは基板Ｔ1の外側リ ード端子である。メモリチップＣは図示されてない電気接続線により外部接続点 Ｋと接続されている。 図３ｂは、パッケージＵ（ここでは輪郭だけ示されている）を備えたメモリ素 子の構造を示す。例えばプラスチックからなるこのパッケージは例えばメモリチ ップＣを備え基板Ｔ1の周囲にモールドされるが、基板Ｔ1の外側リード端子Ａは モールドされずに残されている。 図３ｃは、外側リード端子Ａが例えばモジュール板に固定されて接続されるた めに下に折り曲げられている素子を示す。 このようにして作られたメモリ素子はさらに機能試験を受けるが、その際複数 のメモリ素子を並列的に試験することのできる自動試験装置（例えばアトバンテ スト社の１６個用のＴ５３６３）が使用される。続いてメモリ素子はモジュール 板に固定される。 このようなモジュールの製造方法は多数のプロセス工程を必要とする。その中 の幾つかの工程は全て（例えば９個）のメモリ素子に対して同一である。従って もしこのようなプロセス工程が複数個のメモリ素子に対して同時に行われるなら ば有利である。また技術の進歩により市場価格が低下し、それと共にメモリチッ プのパッケージ及び機能試験に対する製造コストの重要性が上がってる。標準モ ジュールにおける将来の使用に向けられているメモリ素子の別の製造方法により プロセス工程を省略しコストを引き下げることが望ましい。 メモリ密度を高めるために、２つ以上のメモリチップを１つのケーシングにパ ッケージする試みが行われてきた。国際特許出願公開ＷＯ−Ａ−８１／０２３６ ７号明細書はこのような構成を示している。ここでは４個の同一のメモリチップ が１つの共通のケーシング内に納められ、そのうち２個は導体を備えた積層基板 の上面に、２個がその下面に設けられるメモリ素子が開示されている。メモリ素 子をコンパクトに保持するために、４個のメモリチップは基板の多数の外側リー ド端子、例えばアドレスピンを共有している。このようなメモリ素子は、メモリ 素子の標準仕様に合致せず、素子内のメモリチップを積層基板に取り付けるのが 複雑で製造コストが高いので、大量生産市場には採用されていない。この素子は メモリモジュールでの使用に対して進歩がない。 日本国特許出願公開特開昭６０−２０８８５１号明細書はまた別の半導体メモ リ素子を開示している。メモリチップは直接メモリ基板の上に取り付けられ、電 気接続線を備え、共通のキャップで覆われている。この構成もまた製造方法が不 利なことにより普及していない。メモリチップをメモリ基板に直接固定すること により特別な基板が使用されなければならず、メモリチップの試験（チップを基 板に電気的に接続した後初めて行われる）が困難になり、欠陥と認められたメモ リチップは、（基板にろう付け固着されているので）機能的に欠陥のないチップ と交換するのが困難であり、チップと基板との間の電気的接続も面倒でコスト高 となる。 日本国特許公開特開昭６４−１２７０号明細書も同様にこのような半導体メモ リ素子を示している。勿論その場合個々のメモリチップの動作中同一のデータ信 号もしくは電位を導く接続点はそれぞれ唯一の外部端子に接続されている。しか しながらこのことは、配置上の視点から考察すると、ほぼ同一数の接続点の場合 標準的に唯一個のメモリチップに使用されるパッケージよりも大きくなる特別な パッケージが必要であり、その結果接続点がその配置的関係から及びその数から （種々のメモリチップのためもしくはそのデータ入力及び／又はデータ出力信号 がそれぞれ１つの接続点に共通に付属され得ない）、例えば標準化された基板が ＳＩＭＭモジュールに対して接続点の数及び配置に関して持つ要件に一致しない ことになる。 この発明の課題は、モジュール板と共に使用する際にできるだけ簡単でかつコ スト的に有利に取扱い可能であり、またその製造に際して大幅に標準化された部 品を使用できるメモリ素子を提供することにある。 この課題は、請求項１及び２に記載された特徴事項を備えた半導体メモリ素子 により、並びに請求項１４及び１５に特徴付けられた方法により解決される。 この発明を以下に図により詳細に説明する。 図１乃至３は従来技術によるメモリモジュール及びメモリ素子を、 図４乃至９はこの発明の第一の実施例をその有利な構成及び適用並びに製造方 法の工程と共に、 図１０乃至１４はこの発明の第二の実施例をその有利な構成と共に示す。 図４ａ及び４ｂはこの発明の第一の有利な実施例を示す。この図において半導 体メモリ素子はＦで示され、共通の基板Ｔに固定されている同一の種類の５個の メモリチップＣ（ＤＲＡＭ、ＳＲＡＭ、Ｅ（Ｅ）ＰＲＯＭ等）を有する。同一の 種類のメモリチップＣの代わりに、この発明によれば、異なるメモリ種類（例え ばＤＲＡＭ、ＳＲＡＭ及び／又はＥＥＰＲＯＭを混ぜて）のメモリチップを共通 の基板に固定することもできる。メモリチップＣは（図４ａには図解されていな いが図２のものと同様）、電気接続線Ｂを介して基板Ｔの外側リード端子Ａと接 続されている接触点Ｋを備える。基板Ｔは、図２及び３ａ乃至３ｂにおいて図解 されたタイプの互いに接続された５個の基板Ｔ1にその形において対応する。そ れ故基板Ｔは、従来の基板Ｔ1の５倍の数の外側リード端子Ａを備える。従来の 基板構造の中央部に対応する基板Ｔの部分に固定された５個のメモリチップＣは 、図２に示された方式で、基板Ｔの外側リード端子Ａに接続されている。各メモ リチップＣの各接触点Ｋにはそれ故、正確に基板Ｔの外側リード端子が対応して いる。メモリチップＣの接続点Ｋの総数は基板Ｔの外側リード端子Ａの数と等し い。図４ｂは（この図では見えない）メモリチップＣとそれらに共通な基板Ｔの 外側リード端子Ａを露出させるパッケージＵとを備えている基板Ｔを示す。 この発明はしかしながら、少なくともメモリチップＣの動作中にデータ信号（ アドレス信号、制御信号、データ入力及び出力信号）を通す接続点Ｋがそれぞれ 外側リード端子Ａの１つに付属しており（線接続、ボンディング）、一方動作中 に供給電位（代表的にはＶＤＤ及びＶＳＳ）を通す接続点Ｋが必ずしもそれぞれ １つの外側リード端子Ａに接続されずに、それぞれの供給電位の方式に従って分 離されて、１：１の関係に相当するものより少数の外側リード端子Ａと接続され るようにも実現可能である。この場合それぞれの方式の供給電位の接続点Ｋは他 で（例えばパッケージＵの内部のボンディングワイヤにより或いはパッケージＵ の外部の短絡ブリッジにより）電気的に互いに接続されなければならない。 この発明によるメモリ素子Ｆはその構造及び機能において図２に図解されたメ モリ素子の５個に対応する。しかしながら、その製造において及びモジュール板 を備えた使用においてコスト的に有利である。従来の素子の製造の際に使用され た基板Ｔ1は一般に、列に配置され互いに接続される多数の同一の基板構造Ｔ1の 帯の形に加工される。この発明によるメモリ素子Ｆにおいては基板Ｔを製造する ために同一の帯板の基板構造が使用され、この帯板はメモリチップＣを装着して その電気的接続線Ｂを取り付けた後個々の基板Ｔ1に切断されるかもしくは５個 の基板構造を持つ部片に切断される。それ故標準化された基板構造を使用するこ とにより追加的なコストは発生しない。 共通のパッケージＵの形成、それに続く素子Ｆのテスト（例えば自動試験装置 への装着）、素子Ｆのモジュール板への固定など、要するにケーシングの製造か らメモリモジュールの製造の際のそれに続く使用までのいわゆるメモリ素子の「 ハンドリング」は、部品点数、プロセス工程、従ってコストの減少をもたらす。 同一の或いは異種のメモリ種類の多数のメモリチップＣを唯一個のメモリ素子 Ｆに使用することによってプロセス工程はそれ故簡単化され、低廉化される。 図５はこの発明の第一の有利な適用例を示す。モジュール板Ｍには図１のよう な９個の個別素子の代わりに、これより大きい２つのこの発明によるメモリ素子 Ｖ及びＦが固定され、一方の素子Ｖは４個の従来のメモリ素子の機能を、他方の 素子Ｆは５個の従来のメモリ素子の機能を満たしている。素子Ｖ及びＦの外側リ ード端子Ａの数並びにそれらの間の間隔は従来の列に配置された個別素子のそれ に正確に対応する。それ故図１に示されるような標準モジュール板Ｍを使用する ことができる。 メモリ素子Ｖ及びＦの製造の際に使用される帯状の基板構造はその場合隣接の 個別構造の間に、列に配置された２つの個別素子の間の間隙に相当する間隔をも たなければならない。 図６はこの発明による素子に対する共通のパッケージＵの製造方法を概略的に 示し、その外側リード端子Ａは、素子が列にそして互いに間隔をもって配置され るとき、相互の間隔において従来のメモリ素子のそれに相当する。メモリチップ Ｃを備えた帯状の基板構造ＴＢは、注入口を備えたモールド型ＳＦによって囲ま れ、この注入口Ｅを通してプラスチック材が注入される。各々２つの従来の個別 素子に相当するモールド型の間に間隔ｄが置かれ、この間隔は従来の方法で標準 モジュール板Ｍに固定された個別素子の間の間隔に等しい。他のパッケージ材料 を使用或いは他の製造方法を適用する場合には（例えば予め製造されたモールド 型でプレモールドされる）製法工程はそれに応じて適当に適合される。 図７は第一の実施例の第一の変形例とその適用を示す。図５に示されたこの発 明の第一の有利な適用例と同様にモジュール板Ｍにはこの発明による２つのメモ リ素子Ｖ及びＦが装着され、そのうち１つの素子Ｖは４個の従来のメモリ素子の 機能を、他の素子Ｆは５個の従来の素子の機能を満たしている。メモリ素子Ｖ及 びＦの外側リード端子Ａの間隔は、２つの列にそれぞれ４個もしくは５個の素子 が配置されている９個の従来のメモリ素子の間隔に相当するが、相互間の間隔は 保持されていない。 この発明によるメモリ素子Ｖ及びＦの外側リード端子Ａのこのような構成は、 従来の個別素子の基板Ｔ1に対応する個別構造を相互に直接接触して、相互の間 隔なく備えた帯板の基板構造ＴＢの使用に相当する。 共通のパッケージＵの製造は、図８に示されるように、同様に適合されたモー ルド型ＳＦで行われる。この変形例の利点はモジュール板Ｍの寸法を小さくする ことができることにある。 図９は第一の実施例の第二の変形例及びその適用を示す。図５及び７と同様に モジュール板Ｍが示されている。この上に９個の従来のメモリ素子の機能を果た すこの発明によるメモリ素子Ｎが固定されている。外側リード端子Ａの配置は２ 列に配置された９個の従来のメモリ素子のそれに対応する。素子Ｎは、共通の基 板Ｔの上に固定され、共通のパッケージＵで封止された９個のメモリチップＣを 備えている。 メモリ素子Ｎを製造するために例えば図７の素子Ｖ及びＦに使用されたものに 相当する２つの基板が互いに１つの基板Ｔに結合され、基板Ｔはその後９個のメ モリチップＣが装着され共通のパッケージＵが設けられる。 特にメモリチップＣの数及びその結果生ずるメモリ素子の形状の他の変形例は 当業者にとってこの開示から容易に推定することができるので、ここではこれ以 上は言及しない。 なお言及すべき点は、この発明による素子の機能試験において素子の個々のメ モリチップＣにおける欠陥が確認される場合には、素子の簡単なモジュール構造 によりこの欠陥品は問題なく個々のチップ間の範囲で分離できることである。 図４ｂに示された素子Ｆにおいては素子の長手軸に対して直角方向に図におい て線分ＳＳ’で示された４つの位置において分離工程が可能である。この分離線 ＳＳ’は、それに沿って基板Ｔが個別素子の基板Ｔ1に相当する構造に分解され る線に相当する。このようにして１回或いは複数回の切断により素子Ｆの一部が 切り取られると、この切り取られた部分はサイズ及び機能において１個或いは複 数個の従来の個別素子に相当する。それ故この切り取られた部分は従来の個別素 子で補完される。 比較的大きい寸法の素子（例えば３６個のメモリチップＣを備えた）を製作し 、試験し、機能試験の結果に従って特に各４個或いは５個のメモリチップＣの素 子に分割することも考えられる。素子がどのようなサイズであるかに応じてモジ ュール板Ｍは２個或いはそれ以上の数の素子が装着される。 図１０はこの発明の第二の有利な実施例を示す。モジュール板Ｍには２つの基 板ＴＶ及びＴＦが固定され、これは図７の素子Ｖ及びＦの製造の際に使用される 基板Ｔに相当する。基板ＴＶ及びＴＦはそれぞれ４個もしくは５個の互いに接し て固定された個別素子の基板Ｔ1に対応する構造からなり、それ故それぞれ個別 素子の４倍もしくは５倍の数の外側リード端子Ａを備えている。従来の基板Ｔ1 に対応する各構造の中央にメモリチップＣが固定され、各メモリチップの各接続 点Ｋに正確に基板ＴＶ或いはＴＦの外側リード端子Ａが付属するように電気的に 接続されている。その上にメモリチップＣを備えた基板ＴＶ或いはＴＦは、それ 故共通のパッケージＵのない図７の素子Ｖ及びＦに相当する。 その上にメモリチップＣを備えた基板ＴＶ及びＴＦは両基板ＴＶ及びＴＦ並び にその外側リード端子Ａを被覆する１個のパッケージＵにより包囲されている。 基板ＴＶ及びＴＦは、図７の素子Ｖ及びＦのそれと異なり、外側リード端子Ａを 露出させるパッケージを備えてモジュール板Ｍに取り付けられているのではなく 、寧ろモジュール板Ｍに取り付けられて外側リード端子Ａをも被覆するパッケー ジ Ｕを備えているので、モジュール板ＭはパッケージＵの一部をなす。 共通のパッケージＵは２つの部分、即ちそれぞれモジュール板Ｍに固定された 両基板ＴＶ及びＴＦの１つをその外側リード端子Ａと共に被覆する２つの部分か らなることもできる。 図１１乃至１４は第二の実施例の種々の変形例を示す。簡単化するために、そ の上に固定されたメモリチップＣと、電気接続線Ｂ及び外側リード端子Ａとを備 えた、それぞれ１つの基板Ｔが示されている。この基板ＴはメモリチップＣに共 通なパッケージＵにより囲まれ、このパッケージは外側リード端子Ａをも一緒に 封止している。図１０と同様に２つ或いはそれ以上の基板を１つのパッケージＵ で被覆することもできる。図１１乃至１４はこの発明による素子を基板Ｔの長手 軸に対して直角の断面で示す。 図１１は、メモリチップＣを備えた基板Ｔと、外側リード端子Ａとを被覆する パッケージＵを示し、このパッケージは基板Ｔの下にあるモジュール板Ｍの部分 と、モジュール板Ｍと反対側の基板Ｔ側を覆うモールド型Ｆとから構成されてい る。モールド型Ｆは例えばプラスチック（プレモールド）からなる。この発明の 第二の実施例による素子の製造方法は第一の実施例の製造方法と、パッケージが 予めでなく、基板Ｔをモジュール板Ｍに取り付ける際に初めて作られるという点 で異なることは明らかである。 さらに強調したいことは、この発明による素子は特開昭６０−２０８８５１号 明細書において開示された従来の技術とも明らかに異なるということである。即 ちメモリチップＣはモジュール板Ｍに直接固定されるのではなく、基板Ｔに固定 されるので、この発明による素子の製造の際に特開昭６０−２０８８５１号明細 書に関連して既に挙げた欠点が発生することはない。 図１２は、メモリチップＣを備えた基板Ｔと、外側リード端子Ａとを被覆する パッケージＵを示し、このパッケージは基板Ｔの下にあるモジュール板Ｍの部分 と、モジュール板Ｍと反対側の基板Ｔ側を被覆するモールド樹脂Ｈとから構成さ れている。モールド樹脂Ｈは例えばプラスチック（ポストモールド）からなる。 モールド樹脂封止Ｈの製造には例えば図６及び８に示されたモールド型ＳＦと類 似のモールド型が使用され、その際モールド型はそれに応じて選ばれた形状を持 つ。選択されたモールド型の形に応じてモールド樹脂Ｈは、図１３に示されるよ うに、モジュール板Ｍの裏側にまでも広がる。これによりこの発明による素子の 機械的強度がより大きくなる。 図１４は、両側に基板Ｔ1及びＴ2を装着しているモジュール板Ｍを示す。基板 Ｔ1及びＴ2はこの発明による素子の第一の実施例の基板Ｔに相当し、多数のメモ リチップＣ1及びＣ2並びにその電気接続線Ｂを備える。メモリチップを備えた基 板Ｔ1及びＴ2はモジュール板Ｍの一部と、その外側リード端子Ａと共にモールド 樹脂Ｈで被覆されているので、基板Ｔ1及びＴ2はモジュール板Ｍの一部及びモー ルド樹脂Ｈによりパッケージとして被覆されている。図１４に示されたこの発明 による素子は従来の素子に対してコストが低くかつ製造が簡単化される。複数個 のメモリチップＣに共通な基板Ｔと、全てのメモリチップＣ並びに基板Ｔに共通 なパッケージを使用することにより両面にメモリ素子を装着したモジュール板Ｍ の製造に必要なプロセス工程が減少されるからである。 さらに言及したいことは、この発明の第二の実施例において使用される基板Ｔ は標準化された要素（帯板基板構造）で製造され、モジュール板Ｍでの接続及び 固定に関して、選択的に差し込み接続或いは表面接続、即ちろう付けを採用でき ることである。 この発明による半導体メモリ素子において使用されるメモリチップＣの数は、 半導体メモリ素子のデータの入力及び出力端子に対してｎ×４或いは（ｎ×４） ＋１（但しｎ＞０）の数となるように選ばれると有利である。後者の場合は半導 体メモリ素子においていわゆるパリティビットの使用を可能にする。Detailed Description of the Invention      Semiconductor memory device having a plurality of memory chips in a common package   The present invention provides a semiconductor memory device according to the broader concept of claims 1 and 2 and claim 1. The present invention relates to a method for manufacturing a semiconductor memory device according to the concepts of 4 and 15.   In computer systems, due to the increasing memory demand, Memory chips of a specific memory type, such as DRAM, SRAM, E (E) PROM, etc. The individual modules that attach the plug to the computer are rarely used. Rather standard Is called SIMM (single in line memory module), For example, insert 9 memory devices of the same memory type into one module board or A memory module that is fixed by brazing (for example, surface mounting) is used. . The memory module equipped with the memory device is integrated into the computer Replacement (by brazing or plugging), and if necessary replace or Complemented by others.   FIG. 1 shows a module board M, nine memory devices S (SRAM instead of DRAM, E (E) PROM etc.) and standard memory module with module terminals 1 to 30 Joule (for example, 4M × 9 DRAM) is shown. Module terminals 1 to 30 are shown Plug-in or surface connection (eg brazing) via unconducted electrical conductors ) Is connected to the fixed connection point of the lead terminal A outside the memory element S. You. The memory elements S are in this case arranged in two rows of four and five elements. However, other configurations are possible.   FIG. 2 shows a typical memory device. Memory chip C is substrate T1(Metal Spider , Film, etc.) by glueing, alloy connection, etc. Memory chip Connection point K and substrate T1An electrical connection line B (for example, gold Line) is attached. Other memory chips C and substrate T1Is mainly Made of plastic (ceramic is used instead) Pre-molded) or direct substrate T1And the chip C is molded (post-mode It has a package U. Board T1And package U with electrical connection line B Including It constitutes a casing of the memory chip C.   3a to 3c show the memory device shown in FIG. 2 (shown in plan view in FIG. 3). The manufacturing process of FIG. 3a shows a substrate T also called a spider due to its shape.1To Show. Board T1A memory chip C is fixed at the center of the. A is the substrate T1Outside of It is a terminal. The memory chip C is connected to an external connection point by an electric connection line not shown. It is connected to K.   FIG. 3b shows a memory element with a package U (only the contour is shown here). Shows the structure of the child. This package, made of plastic for example, Substrate T with C1Is molded around the substrate T1The outer lead terminal A of It is left unmolded.   FIG. 3c shows that the outer lead terminals A are fixedly connected to, for example, a module board. The element is shown folded down for this purpose.   The memory device made in this way undergoes further functional tests, in which case Automatic test equipment that can test memory devices in parallel Strike's 16-piece T5363) is used. Then the memory element is a module Fixed to the board.   The manufacturing method of such a module requires a large number of process steps. In it Some steps of are the same for all (eg, 9) memory devices. Therefore If such process steps are performed on multiple memory devices simultaneously, Is advantageous. Also, due to technological advances, market prices have fallen, which has accompanied memory chips. Manufacturing costs are becoming more important for package and functional testing of packages. Standard model By another method of manufacturing memory devices intended for future use in modules It is desirable to reduce process costs by omitting process steps.   To increase memory density, pack two or more memory chips in one casing. Attempts have been made to package it. International Patent Application Publication WO-A-81 / 236 No. 7 specification shows such a structure. Here four identical memory chips Are housed in one common casing, two of which are conductors On the upper surface of the memory element, two memory elements are provided on the lower surface thereof. Memory element In order to keep the child compact, four memory chips are used in multiple outer leads of the substrate. Common terminals, for example, address pins. Such a memory device is a memory It is not possible to attach the memory chip in the device to the laminated substrate because it does not meet the standard specifications of the device. Due to its complexity and high manufacturing cost, it has not been adopted in the mass production market. This element No progress for use in memory modules.   Japanese patent application publication JP-A-60-208851 describes another semiconductor memory. Re-elements are disclosed. The memory chips are mounted directly on the memory board and It has an air connection line and is covered by a common cap. This structure also has an inconvenient manufacturing method. It is not popular because of its advantage. To fix the memory chip directly to the memory board Due to the special substrate must be used for testing memory chips (chip based Note that it is difficult to do it after it is electrically connected to the board) and it is recognized as a defect. Rechip is a chip that is functionally free (because it is brazed to the substrate) Is difficult to replace, and the electrical connection between the chip and substrate is cumbersome and costly Becomes   Japanese Patent Laid-Open Publication No. 64-1270 also discloses such a semiconductor memory. 2 shows a re-element. Of course, in that case, the same data signal is sent during the operation of each memory chip. Signal or a connection point for conducting a potential is connected to only one external terminal. Only However, from the viewpoint of placement, this is the case when the number of connection points is almost the same. A special package that is typically larger than the package used for a single memory chip. A package is needed, so that the connection points are (For various memory chips or their data input and / or data output signals Cannot be commonly attached to each single connection point), eg a standardized board Does not meet requirements for SIMM module regarding number and placement of connection points Will be.   The object of this invention is to be as simple and co-operative as possible when used with a module board. Parts that can be handled in an advantageous manner and that have a significantly standardized An object of the present invention is to provide a memory device that can be used as a product.   This problem is a semiconductor memory device having the features described in claims 1 and 2. And by the method characterized in claims 14 and 15.   The present invention will be described in detail below with reference to the drawings.   1 to 3 show a conventional memory module and memory device,   4 to 9 show the first preferred embodiment of the present invention, its advantageous construction, application and manufacturing method. With the process of the law,   10 to 14 show a second embodiment of the invention with its advantageous construction.   4a and 4b show a first advantageous embodiment of the invention. In this figure The body memory element is designated by F and comprises five of the same type fixed on a common substrate T. It has a memory chip C (DRAM, SRAM, E (E) PROM, etc.). Same Instead of different types of memory chips C, according to the invention, different memory types (eg Common memory chips (eg mix DRAM, SRAM and / or EEPROM) It can also be fixed to the substrate. The memory chip C (not shown in FIG. 4a 2), but is connected to the outer lead terminal A of the substrate T via the electrical connection line B. With the contact points K being continued. The substrate T is illustrated in FIGS. 2 and 3a-3b. Five substrates T of different types connected to each other1Corresponds in that form. So Therefore, the substrate T is the conventional substrate T15 times the number of outer lead terminals A. Traditional The five memory chips C fixed to the portion of the substrate T corresponding to the central portion of the substrate structure are , Is connected to the outer lead terminals A of the substrate T in the manner shown in FIG. Each note Therefore, the contact points K of the re-chip C are accurately corresponded to by the outer lead terminals of the substrate T. I have. The total number of connection points K of the memory chip C is equal to the number of outer lead terminals A of the substrate T. Yes. FIG. 4b shows a memory chip C (not visible in this view) and a substrate T common to them. 1 shows a substrate T having a package U exposing the outer lead terminals A.   However, the present invention, at least during operation of the memory chip C Address points, control signals, data input and output signals) Attached to one of the outer lead terminals A (wire connection, bonding), while one is operating The connection points K through which the supply potentials (typically VDD and VSS) pass through are not always Instead of being connected to one outer lead terminal A, it is divided according to the method of each supply potential. Separated and connected to a smaller number of outer lead terminals A than corresponding to a 1: 1 relationship It is also feasible. In this case, the connection point K of the supply potential of each method is (For example, by bonding wires inside the package U or the package U Must be electrically connected to each other (by means of a short-circuit bridge outside).   The memory device F according to the present invention has the structure and function illustrated in FIG. Corresponds to 5 memory elements. However, in its manufacture and module board Is advantageous in terms of cost in use. Used in conventional device manufacturing Board T1Is generally a number of identical substrate structures T arranged in rows and connected to each other.1of It is processed into a band shape. In the memory device F according to the present invention, the substrate T is manufactured. For this purpose, the same strip board structure is used. After mounting the electrical connection line B, the individual substrate T1Or cut into 5 pieces It is cut into pieces with the substrate structure. Therefore it is possible to use standardized substrate structures. Does not incur additional costs.   Formation of common package U, followed by testing of device F (eg automatic test equipment Mounting), fixing the element F to the module plate, etc. From the so-called memory device to subsequent use in the manufacture of memory modules "Handling" results in a reduction in the number of parts, process steps and thus costs.   A large number of memory chips C of the same or different types of memory as a single memory device By using F, the process steps are therefore simplified and cheaper.   FIG. 5 shows a first advantageous application of the invention. The module board M is as shown in Fig. 1. 2 larger memory elements according to the invention instead of 9 individual elements V and F are fixed, one element V functions as four conventional memory elements and the other element V Element F fulfills the functions of five conventional memory elements. Outside of elements V and F The number of the terminal terminals A and the distance between them are the same as those of the individual elements arranged in the conventional row. Correspond exactly to. Therefore use a standard module board M as shown in FIG. be able to.   The strip-shaped substrate structure used in the manufacture of the memory devices V and F is then Between the individual structures there is also a spacing corresponding to the gap between two individual elements arranged in a row. I have to hit.   FIG. 6 schematically shows a method of manufacturing a common package U for a device according to the present invention. The outer lead terminals A of which the elements are arranged in rows and spaced from one another In comparison with each other, it corresponds to that of a conventional memory device. Memory chip A strip-shaped substrate structure TB provided with C is surrounded by a mold SF having an injection port. Then, the plastic material is injected through the injection port E. 2 conventional individual each A space d is placed between the molds corresponding to the elements, and this space is standard by the conventional method. Equal to the spacing between the individual elements fixed to the module board M. Other packaging materials When using or applying other manufacturing methods (for example, prefabricated mold The process steps (pre-molded in the mold) are adapted accordingly.   FIG. 7 shows a first modification of the first embodiment and its application. This departure shown in Figure 5 As in the first advantageous application of the invention, the module board M has two notes according to the invention. Re-elements V and F are mounted, one of which is one of four conventional memory elements. Other elements F fulfill the functions of the five conventional elements. Memory element V and And the outer lead terminals A of F are separated from each other by four or five elements in each of the two rows. Corresponds to the spacing of the nine conventional memory elements in which are arranged, but the spacing between them is Not held.   Such a configuration of the outer lead terminals A of the memory devices V and F according to the present invention is Conventional individual element substrate T1Directly contact the individual structures corresponding to This corresponds to the use of the substrate structure TB of strips provided without a gap.   The manufacture of the common package U is done in a similarly adapted mode, as shown in FIG. It is performed in the field type SF. The advantage of this modification is to reduce the dimensions of the module board M. Is to be able to do it.   FIG. 9 shows a second modification of the first embodiment and its application. Similar to Figures 5 and 7 A module board M is shown. On top of this, the functions of nine conventional memory devices were performed. The memory element N according to the invention is fixed. The layout of the outer lead terminals A is 2 It corresponds to that of nine conventional memory elements arranged in columns. Element N is a common substrate The nine memory chips C fixed on the plate T and sealed with the common package U Have.   In order to manufacture the memory device N, for example those used in devices V and F of FIG. Corresponding two substrates are bonded to each other on one substrate T, which is then connected to the nine substrates. The memory chip C is mounted and a common package U is provided.   In particular, other variations of the number of memory chips C and the resulting shape of the memory elements are Those skilled in the art can easily extrapolate from this disclosure, so that Don't mention above.   It should be noted that in the functional test of the device according to the present invention, the individual memory of the device is tested. If a defect in the molybdenum chip C is confirmed, a simple module structure of the element Therefore, this defective product can be separated within a range between individual chips without any problem.   In the element F shown in FIG. 4b, the element F is shown perpendicular to the longitudinal axis of the element. The separation step is possible at the four positions indicated by the line segment SS '. This separation line SS 'is a substrate T along which the substrate T is an individual device.1Is decomposed into a structure equivalent to Equivalent to a line. In this way, a part of the element F is cut by cutting once or plural times. When cut out, this cut-out section can be single or multiple in size and function. It corresponds to several conventional discrete elements. Therefore, this cut-out part is Complemented by the child.   Fabricate relatively large size device (eg with 36 memory chips C) , And each of the four or five memory chips C is tested according to the result of the function test. It is also possible to divide into children. Depending on what size the element is, Two or more elements are mounted on the tool board M.   FIG. 10 shows a second advantageous embodiment of the invention. The module board M has two bases The plates TV and TF are fixed, which are used in the manufacture of the elements V and F of FIG. It corresponds to the substrate T. Substrate TV and TF contact each other 4 or 5 Substrate T of individual element fixed by1Corresponding structure, and therefore each individual It has four or five times as many outer lead terminals A as there are elements. Conventional board T1 The memory chip C is fixed at the center of each structure corresponding to Correctly electrically connect the outer lead terminal A of the substrate TV or TF to the point K. It is connected. Substrate TV or TF with memory chip C on it Therefore, it corresponds to the devices V and F of FIG. 7 without the common package U.   Substrate TV and TF with memory chip C on it are both substrate TV and TF side by side. It is surrounded by a single package U which covers the outer lead terminals A. The substrates TV and TF differ from those of the elements V and F in FIG. 7 in that the outer lead terminals A are Rather than being attached to the module board M with exposed packages , A package that is attached to the module plate M and covers the outer lead terminals A as well. The Since it has U, the module board M is a part of the package U.   The common package U is fixed to two parts, namely the module board M, respectively. Two parts that cover one of both substrates TV and TF with its outer lead terminals A? Can also consist of   11 to 14 show various modifications of the second embodiment. For simplicity, A memory chip C fixed on the upper side, an electric connection line B and an outer lead terminal A. Each one substrate T is shown. This substrate T is used together with the memory chip C. Surrounded by a common package U, this package also includes the outer lead terminals A It is sealed. As in FIG. 10, two or more substrates are packaged in one package U. Can also be coated with. 11 to 14 show the device according to the invention in the longitudinal direction of the substrate T. It is shown in a cross section perpendicular to the axis.   In FIG. 11, the substrate T having the memory chip C and the outer lead terminal A are covered. Shows package U, which is the part of module board M under substrate T And a mold F that covers the side of the substrate T opposite to the module plate M. You. The mold die F is made of, for example, plastic (premold). Of this invention The device manufacturing method according to the second embodiment is different from the manufacturing method of the first embodiment in that the package is The point that it is not made in advance but only when the board T is attached to the module board M. It is clear that   It is further emphasized that the device according to the present invention is disclosed in JP-A-60-208851. It is clearly different from the prior art disclosed in the specification. Immediately The memory chip C is not fixed directly to the module board M, but is fixed to the substrate T. Therefore, in manufacturing the element according to the present invention, the specification of JP-A-60-208851 The disadvantages already mentioned in connection with the book do not occur.   In FIG. 12, a substrate T having a memory chip C and an outer lead terminal A are covered. Shows package U, which is the part of module board M under substrate T And a molding resin H that covers the side of the substrate T opposite to the module plate M. Have been. The mold resin H is made of, for example, plastic (post mold). For example, the mold resin SF shown in FIGS. A similar mold is used, with the mold having a shape selected accordingly. One. Depending on the shape of the selected mold, the mold resin H is shown in FIG. Like, spreads to the back side of the module board M. This allows the device according to the invention to The mechanical strength becomes larger.   FIG. 14 shows the substrate T on both sides.1And T22 shows a module board M on which is mounted. substrate T1And T2Corresponds to the substrate T of the first embodiment of the device according to the invention, and contains a large number of memos. Re-chip C1And C2And its electrical connection line B. Base with memory chip Board T1And T2Is molded with a part of the module board M and its outer lead terminals A Since it is covered with resin H, the substrate T1And T2Is a part of the module board M and It is covered with a resin H as a package. The invention shown in FIG. The device according to claim 1 is lower in cost and simpler to manufacture than conventional devices. Multiple Substrate T common to all memory chips C and all memory chips C and substrate T Module board M with memory devices mounted on both sides by using various packages This is because the number of process steps required for manufacturing is reduced.   It should be further noted that the substrate T used in the second embodiment of the present invention Is manufactured with standardized elements (band plate substrate structure), connection with module board M and For fixing, you can choose to use plug-in connection or surface connection, that is, brazing Is Rukoto.   The number of memory chips C used in the semiconductor memory device according to the present invention is N × 4 or (n × 4) for the data input and output terminals of the semiconductor memory device Advantageously, it is chosen to be a number of +1 (where n> 0). In the latter case, it is semi-conducting It enables the use of so-called parity bits in body memory devices.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ Ｈ０１Ｌ 25/07 25/18 【要約の続き】 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 6 Identification code Internal reference number FI H01L 25/07 25/18 [Continued summary]

Claims (1)

【特許請求の範囲】 １．共通のパッケージ（Ｕ）の中に複数個のメモリチップ（Ｃ）を備え、メモリ チップ（Ｃ）が電気接続線（Ｂ）を介して基板（Ｔ）の外側リード端子（Ａ）に 接続されている接続点（Ｋ）を備える半導体メモリ素子において、メモリチップ （Ｃ）が全て共通に基板（Ｔ）に取り付けられ、各メモリチップ（Ｃ）の各接続 点（Ｋ）に正確に基板（Ｔ）の外側リード端子（Ａ）が付属し、その結果メモリ チップ（Ｃ）の接続点（Ｋ）の総数が基板（Ｔ）の外側リード端子（Ａ）の数と 等しいことを特徴とする半導体メモリ素子。 ２．共通のパッケージ（Ｕ）の中に複数個のメモリチップ（Ｃ）を備え、メモリ チップ（Ｃ）が電気接続線（Ｂ）を介して基板（Ｔ）の外側リード端子（Ａ）に 接続されている接続点（Ｋ）を備え、メモリチップ（Ｃ）の動作中接続点（Ｋ） 及び外側リード端子（Ａ）のそれぞれ数個がデータ信号を導く半導体メモリ素子 において、メモリチップ（Ｃ）が全て共通に基板（Ｔ）に取り付けられ、各メモ リチップ（Ｃ）の各接続点（Ｋ）に正確に基板（Ｔ）の外側リード端子（Ａ）が 付属し、その結果データ信号を導くメモリチップ（Ｃ）の接続点（Ｋ）の総数が データ信号を導く基板（Ｔ）の外側リード端子（Ａ）の数と等しいことを特徴と する半導体メモリ素子。 ３．基板（Ｔ）がモジュール板（Ｍ）に取り付けられ、この上にその外側リード 端子（Ａ）を介して電気的に接続され、メモリチップ（Ｃ）に共通のパッケージ （Ｕ）が基板（Ｔ）の外側リード端子（Ａ）をも封止していることを特徴とする 請求項１又は２記載の半導体メモリ素子。 ４．基板（Ｔ）がモジュール板（Ｍ）に取り付けられ、このモジュール板上にそ の外側リード端子（Ａ）を介して電気的に接続され、メモリチップ（Ｃ）に共通 のパッケージ（Ｕ）が基板（Ｔ）の外側リード端子（Ａ）を露出していることを 特徴とする請求項１又は２記載の半導体メモリ素子。 ５．複数個の基板（Ｔ）がモジュール板（Ｍ）に取り付けられることを特徴とす る請求項３又は４記載の半導体メモリ素子。 ６．基板（Ｔ）がモジュール板（Ｍ）の両面に取り付けられることを特徴とする 請求項５記載の半導体メモリ素子。 ７．単数或いは複数個の基板（Ｔ）によりモジュール板（Ｍ）に取り付けられこ れに電気的に接続されるメモリチップ（Ｃ）の総数が、半導体メモリ素子のデー タ入力／出力端子に対してｎ×４（但しｎ＞０）の数が生ずるように選ばれてい ることを特徴とする請求項１乃至６の１つに記載の半導体メモリ素子。 ８．単数或いは複数個の基板（Ｔ）によりモジュール板（Ｍ）に取り付けられこ れに電気的に接続されるメモリチップ（Ｃ）の総数が、半導体メモリ素子のデー タ入力／出力端子に対して（ｎ×４）＋１（但しｎ＞０）の数が生ずるように選 ばれていることを特徴とする請求項１乃至６の１つに記載の半導体メモリ素子。 ９．パッケージ（Ｕ）がプラスチック材からなることを特徴とする請求項１乃至 ８の１つに記載の半導体メモリ素子。 １０．共通のパッケージ（Ｕ）がメモリチップ（Ｃ）及びその電気接続線（Ｂ） と直接接触して配置されていることを特徴とする請求項１乃至９の１つに記載の 半導体メモリ素子。 １１．共通のパッケージ（Ｕ）がメモリチップ（Ｃ）及びその電気接続線（Ｂ） に関して接触することなく配置されていることを特徴とする請求項１乃至９の１ つに記載の半導体メモリ素子。 １２．メモリチップ（Ｃ）が同一のメモリ種類であることを特徴とする請求項１ 乃至１１の１つに記載の半導体メモリ素子。 １３．メモリチップ（Ｃ）が異なるメモリ種類であることを特徴とする請求項１ 乃至１１の１つに記載の半導体メモリ素子。 １４．メモリチップ（Ｃ）が共通の基板（Ｔ）に取り付けられ、それに電気接続 線（Ｂ）が設けられ、各メモリチップ（Ｃ）の各接続点（Ｋ）に正確に基板（Ｔ ）の外側リード端子（Ａ）が付属され、その結果メモリチップ（Ｃ）の接続点（ Ｋ）の総数が基板（Ｔ）の外側リード端子（Ａ）の数と等しくかつ基板（Ｔ）が その上に設けられるメモリチップ（Ｃ）と共に共通のパッケージ（Ｕ）が備えら れることを特徴とする、共通のパッケージ（Ｕ）に封止される複数個のメモリチ ップ（Ｃ）を備えた半導体メモリ素子の製造方法。 １５．メモリチップ（Ｃ）が共通の基板（Ｔ）に取り付けられ、それに電気接続 線（Ｂ）が設けられ、メモリチップ（Ｃ）の動作中データ信号を導く各メモリチ ップ（Ｃ）の接続点（Ｋ）に正確に基板（Ｔ）の外側リード端子（Ａ）が付属さ れ、その結果データ信号を導くメモリチッブ（Ｃ）の接続点（Ｋ）の総数がこれ に属する基板（Ｔ）の外側リード端子（Ａ）の数と等しくかつ基板（Ｔ）がその 上に設けられるメモリチップ（Ｃ）と共に共通のパッケージ（Ｕ）が備えられる ことを特徴とする、共通のパッケージ（Ｕ）に封止される複数個のメモリチップ （Ｃ）を備えた半導体メモリ素子の製造方法。 １６．その上にメモリチップ（Ｃ）を備えた基板（Ｔ）が共通のパッケージ（Ｕ ）を取り付ける際にモジュール板（Ｍ）に固定され、これとその外側リード端子 （Ａ）を介して電気的に接続され、次いで基板（Ｔ）に基板（Ｔ）のモジュール 板（Ｍ）の反対側を覆うモールド型（Ｆ）が設けられ、その結果共通のパッケー ジ（Ｕ）がこのモールド型（Ｆ）及び基板（Ｔ）の下側にあるモジュール板（Ｍ ）部分を被覆していることを特徴とする請求項１４又は１５記載の半導体メモリ 素子の製造方法。 １７．その上にメモリチップ（Ｃ）を備えた基板（Ｔ）が共通のパッケージ（Ｕ ）を取り付ける際にモジュール板（Ｍ）に固定され、これとその外側リード端子 （Ａ）を介して電気的に接続され、次いで基板（Ｔ）に基板（Ｔ）のモジュール 板（Ｍ）の反対側を被覆するモールド樹脂（Ｈ）が設けられ、その結果共通のパ ッケージ（Ｕ）がこのモールド樹脂（Ｈ）及び基板（Ｔ）の下側にあるモジュー ル板（Ｍ）部分を被覆していることを特徴とする請求項１４又は１５記載の半導 体メモリ素子の製造方法。 １８．その上にメモリチップ（Ｃ）を備えた基板（Ｔ）が共通のパッケージ（Ｕ ）を取り付けた後にモジュール板（Ｍ）に固定され、これとその外側リード端子 （Ａ）を介して電気的に接続されることを特徴とする請求項１４又は１５記載の 半導体メモリ素子の製造方法。 １９．基板（Ｔ）がモジュール板（Ｍ）と差し込み接続により電気的に接続され ることを特徴とする請求項１５乃至１８の１つに記載の半導体メモリ素子の製造 方法。 ２０．基板（Ｔ）がモジュール板（Ｍ）と表面接続（表面実装）により電気的に 接続されることを特徴とする請求項１５乃至１８の１つに記載の半導体メモリ素 子の製造方法。 ２１．基板（Ｔ）がモジュール板（Ｍ）とろう接合により電気的に接続されるこ とを特徴とする請求項１５乃至１８の１つに記載の半導体メモリ素子の製造方法 。 ２２．共通のパッケージ（Ｕ）が射出成形（ポストモールド）により形成される ことを特徴とする請求項１８記載の半導体メモリ素子の製造方法。 ２３．共通のパッケージ（Ｕ）が予め製作された部品（プレモールド）から形成 されることを特徴とする請求項１８記載の半導体メモリ素子の製造方法。[Claims] 1. A plurality of memory chips (C) in a common package (U) The chip (C) is connected to the outer lead terminal (A) of the substrate (T) via the electrical connection line (B). In a semiconductor memory device having connected connection points (K), a memory chip (C) are all commonly attached to the substrate (T), and each connection of each memory chip (C) Accurately attach the outer lead terminal (A) of the substrate (T) to the point (K), resulting in memory The total number of connection points (K) of the chip (C) is equal to the number of outer lead terminals (A) of the substrate (T). A semiconductor memory device characterized by being equal. 2. A plurality of memory chips (C) in a common package (U) The chip (C) is connected to the outer lead terminal (A) of the substrate (T) via the electrical connection line (B). The connected connection point (K) is provided, and the connection point (K) during operation of the memory chip (C) And a semiconductor memory device in which a plurality of outer lead terminals (A) each lead a data signal In memory, all the memory chips (C) are commonly attached to the substrate (T). The outer lead terminal (A) of the substrate (T) is accurately attached to each connection point (K) of the rechip (C). The total number of connection points (K) of the memory chips (C) that are attached and that lead data signals as a result It is characterized in that it is equal to the number of outer lead terminals (A) of the board (T) for guiding data signals. Semiconductor memory device. 3. The substrate (T) is attached to the module plate (M), on which the outer leads A package that is electrically connected through the terminal (A) and is common to the memory chip (C) (U) also seals the outer lead terminals (A) of the substrate (T). The semiconductor memory device according to claim 1 or 2. 4. The substrate (T) is attached to the module board (M) and is mounted on the module board. Is electrically connected via the outer lead terminal (A) of the memory and is common to the memory chip (C) Package (U) exposes the outer lead terminals (A) of the substrate (T). The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device. 5. A plurality of substrates (T) are attached to the module board (M). The semiconductor memory device according to claim 3 or 4, wherein. 6. Boards (T) are attached to both sides of the module board (M) The semiconductor memory device according to claim 5. 7. It can be attached to the module board (M) by one or more boards (T). The total number of memory chips (C) electrically connected to this is the data of the semiconductor memory device. Selected so that a number of n × 4 (where n> 0) occurs for each input / output terminal. 7. The semiconductor memory device according to claim 1, wherein the device is a semiconductor memory device. 8. It can be attached to the module board (M) by one or more boards (T). The total number of memory chips (C) electrically connected to this is the data of the semiconductor memory device. Input / output terminals so that a number of (n × 4) +1 (where n> 0) occurs. 7. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is exposed. 9. The package (U) is made of a plastic material. 8. The semiconductor memory device as described in 1 above. 10. The common package (U) is the memory chip (C) and its electrical connection line (B). 10. It is arranged in direct contact with and is arranged according to one of claims 1 to 9. Semiconductor memory device. 11. The common package (U) is the memory chip (C) and its electrical connection line (B). 1 to 9 are arranged without contacting each other. A semiconductor memory device according to claim 1. 12. The memory chips (C) are of the same memory type. 11. The semiconductor memory device according to any one of 1 to 11. 13. The memory chip (C) is of a different memory type. 11. The semiconductor memory device according to any one of 1 to 11. 14． Memory chip (C) is mounted on a common substrate (T) and electrically connected to it A line (B) is provided so that the substrate (T) can be accurately connected to each connection point (K) of each memory chip (C). ) Outer lead terminal (A) is attached, and as a result, the connection point of the memory chip (C) ( K) is equal to the number of outer lead terminals (A) of the board (T) and the board (T) is A common package (U) is provided together with the memory chip (C) provided thereon. A plurality of memory chips sealed in a common package (U) A method of manufacturing a semiconductor memory device having a chip (C). 15. Memory chip (C) is mounted on a common substrate (T) and electrically connected to it A line (B) is provided for each memory chip to guide the operating data signal of the memory chip (C). The outer lead terminal (A) of the board (T) is accurately attached to the connection point (K) of the top (C). As a result, the total number of connection points (K) of the memory chip (C) that leads the data signal is Is equal to the number of outer lead terminals (A) of the substrate (T) belonging to A common package (U) is provided together with the memory chip (C) provided above. A plurality of memory chips sealed in a common package (U) A method for manufacturing a semiconductor memory device including (C). 16. A package (U) having a common substrate (T) having a memory chip (C) thereon ) Is fixed to the module board (M) when it is attached, and this and its outer lead terminals Module of board (T) electrically connected through (A) and then to board (T) A mold (F) covering the opposite side of the plate (M) is provided so that a common package The module plate (M) below the mold (F) and the substrate (T). 16. The semiconductor memory according to claim 14 or 15, characterized in that it covers the portion. Device manufacturing method. 17． A package (U) having a common substrate (T) having a memory chip (C) thereon ) Is fixed to the module board (M) when it is attached, and this and its outer lead terminals Module of board (T) electrically connected through (A) and then to board (T) A mold resin (H) covering the opposite side of the plate (M) is provided, and as a result, a common resin is provided. The package (U) is a module under the mold resin (H) and the substrate (T). 16. The semiconductor device according to claim 14 or 15, characterized in that it covers the ruled plate (M) portion. Method of manufacturing body memory device. 18. A package (U) having a common substrate (T) having a memory chip (C) thereon ) Is fixed to the module board (M) after mounting the 16. It is electrically connected via (A), The claim 14 or 15 characterized by the above-mentioned. Method of manufacturing semiconductor memory device. 19. The board (T) is electrically connected to the module board (M) by a plug connection. Manufacturing of a semiconductor memory device according to one of claims 15 to 18, characterized in that Method. 20. The board (T) is electrically connected to the module board (M) by surface connection (surface mounting) 19. A semiconductor memory device according to claim 15, wherein the semiconductor memory device is connected. Child manufacturing method. 21. The board (T) is electrically connected to the module board (M) by brazing. 19. The method of manufacturing a semiconductor memory device according to claim 15, further comprising: . 22. A common package (U) is formed by injection molding (post molding) 19. The method of manufacturing a semiconductor memory device according to claim 18, wherein 23. Common package (U) is formed from prefabricated parts (premold) 19. The method for manufacturing a semiconductor memory device according to claim 18, wherein the method is performed.
JP7520319A 1994-02-07 1995-02-06 Semiconductor memory device having a plurality of memory chips in a common package Pending JPH09508496A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4403733 1994-02-07
DE4403733.3 1994-02-07
PCT/DE1995/000155 WO1995021459A1 (en) 1994-02-07 1995-02-06 Semiconductor storage component with a plurality of storage chips in a shared casing

Publications (1)

Publication Number Publication Date
JPH09508496A true JPH09508496A (en) 1997-08-26

Family

ID=6509654

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7520319A Pending JPH09508496A (en) 1994-02-07 1995-02-06 Semiconductor memory device having a plurality of memory chips in a common package

Country Status (5)

Country Link
EP (1) EP0744084A1 (en)
JP (1) JPH09508496A (en)
KR (1) KR970700940A (en)
TW (1) TW354859B (en)
WO (1) WO1995021459A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001065605A1 (en) * 2000-03-03 2001-09-07 Hitachi, Ltd. Semiconductor device
JP2005150670A (en) * 2003-03-12 2005-06-09 Samsung Electronics Co Ltd Manufacturing method of semiconductor module and printed circuit board used therefor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3341649A (en) * 1964-01-17 1967-09-12 Signetics Corp Modular package for semiconductor devices
US4642419A (en) * 1981-04-06 1987-02-10 International Rectifier Corporation Four-leaded dual in-line package module for semiconductor devices
JP3125891B2 (en) * 1991-08-20 2001-01-22 日立電線株式会社 Semiconductor device
US5280193A (en) * 1992-05-04 1994-01-18 Lin Paul T Repairable semiconductor multi-package module having individualized package bodies on a PC board substrate
US5337216A (en) * 1992-05-18 1994-08-09 Square D Company Multichip semiconductor small outline integrated circuit package structure

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001065605A1 (en) * 2000-03-03 2001-09-07 Hitachi, Ltd. Semiconductor device
US6492727B2 (en) 2000-03-03 2002-12-10 Hitachi, Ltd. Semiconductor device
US6501173B2 (en) 2000-03-03 2002-12-31 Hitachi, Ltd. Semiconductor device
US6531773B2 (en) 2000-03-03 2003-03-11 Hitachi, Ltd. Semiconductor device
KR100828855B1 (en) * 2000-03-03 2008-05-09 가부시키가이샤 히타치세이사쿠쇼 Semiconductor device
KR100842140B1 (en) * 2000-03-03 2008-06-27 가부시키가이샤 히타치세이사쿠쇼 Semiconductor devices
JP2005150670A (en) * 2003-03-12 2005-06-09 Samsung Electronics Co Ltd Manufacturing method of semiconductor module and printed circuit board used therefor

Also Published As

Publication number Publication date
KR970700940A (en) 1997-02-12
WO1995021459A1 (en) 1995-08-10
EP0744084A1 (en) 1996-11-27
TW354859B (en) 1999-03-21

Similar Documents

Publication Publication Date Title
US5313096A (en) IC chip package having chip attached to and wire bonded within an overlying substrate
JP2516319B2 (en) Semiconductor package equipment
US6975039B2 (en) Method of forming a ball grid array package
US20020192862A1 (en) BGA package and method of fabrication
US6861764B2 (en) Wiring substrate having position information
KR970006529B1 (en) Semiconductor device
KR20000071326A (en) Semiconductor device and method of production of the semiconductor device
JPH041503B2 (en)
JPH02502323A (en) Support assembly for integrated circuits
JPH07307405A (en) Semiconductor package using solder ball and its preparation
JPH09508496A (en) Semiconductor memory device having a plurality of memory chips in a common package
JPH088385A (en) Resin sealed semiconductor device
JPH0367345B2 (en)
JPH04320365A (en) Resin-encapsulated semiconductor devices and memory cards
JPH0517709B2 (en)
JPS6130067A (en) Hybrid IC
JPH1079466A (en) Semiconductor device
JP3665609B2 (en) Semiconductor device and semiconductor device unit having a plurality of semiconductor devices mounted thereon
JPH07122701A (en) Semiconductor device, manufacturing method thereof, and lead frame for PGA
JP4412437B2 (en) Semiconductor device identification method
JPS59175753A (en) Semiconductor device and lead frame
JPH077816B2 (en) Semiconductor sealed container
JPH0750388A (en) Resin-sealed semiconductor device and manufacturing method
KR100357209B1 (en) method for testing semiconductor packages in strip unit
JPS60206144A (en) Semiconductor device and manufacture thereof