JPH0965215A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device in which the range of a reference voltage received externally is set widely with respect to a low power supply voltage. SOLUTION: Anodes of photo diodes 101 are connected to ground in common and a 1st amplifier 102 is connected to each cathode of the photo diodes 101. Outputs of the 1st amplifiers are sequentially selected by a shift register 106 by each selector switch 103 and each selected signal is given to a common signal line 107, which is connected to an output terminal 108 via a 2nd amplifier 105. A reference voltage Vref applied to an input terminal 109 to decide a reference level of an output signal is applied to an internal reference voltage generating circuit 104, in which the reference voltage Vref is converted into an internal reference voltage VRR, which is impressed to the 1st amplifier 102. The 1st amplifier 102 outputs a voltage equivalent to a photo charge generated in each photo diode 101 as a change from the reference voltage VRR.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device having peripheral circuits mounted on the same chip, and more particularly to a solid-state image pickup device capable of obtaining a large output signal with a small circuit scale even at a low power supply voltage. .

[0002]

2. Description of the Related Art A CCD is generally known as a solid-state image pickup device, but since the CCD has a high power supply voltage of 12 V, it is not suitable for applications requiring a low power supply voltage. Therefore, a MOS type solid-state image sensor that can operate at a power supply voltage of 5V is used in part, but this is a CCD in terms of S / N.
Inferior to On the other hand, in order to improve the S / N of the MOS type solid-state imaging device, the one-dimensional line sensor has an amplification element for each pixel, and the two-dimensional area sensor has an amplification element for each pixel or each vertical signal line. A type of solid-state imaging device has been proposed.

In the solid-state image pickup device having these amplifying elements, random noise becomes small, but fixed pattern noise (Fixed Pattern Noise,
Hereinafter, it will be abbreviated as FPN). So this F
Although various techniques for suppressing PN have been proposed, Japanese Patent Laid-Open No. 5-207220 discloses an FP having a configuration as shown in FIG.
A solid-state image sensor including a circuit for suppressing N is disclosed. In FIG. 6, S is a source-grounded amplification type pixel,
It is composed of a photodiode 1, a source-grounded amplification nMOS transistor 2, an active load pMOS transistor 5, a reset nMOS transistor 3, and a feedback capacitance element 6. In the source-grounded pixel S, photoelectric charges are accumulated in the feedback capacitance element 6 and the accumulated light amount is detected as a change in the drain voltage of the nMOS transistor 2.

The output node 28 of the source-grounded pixel S
Are affected by the threshold voltage (V _Th ) of the nMOS transistor 2, therefore, when the potential V _P of the output node 28 is directly output to the signal line 23, the threshold voltage V _Th of the nMOS transistor 2 between the pixels is _reduced . Due to variations, FPN occurs. Therefore, the threshold voltage V of the nMOS transistor 2 is connected between the node 28 and the selection switch 21 connected to the signal line 23.
_An FPN suppressing circuit including an amplifier circuit that provides a constant output even if _Th varies is provided.

That is, in FIG. 6, reference numeral 10 is a source grounded pMOS transistor 16 and n operating as a load.
It is an inverting amplifier composed of MOS transistors 17, and its output is connected to a source follower circuit composed of nMOS transistors 25 and 26. A switching pMOS transistor 14 is provided between the input and output of this two-stage amplifier.
The capacitance C ₂ is provided via the capacitance C ₂ , and the input end thereof is connected to the output node 28 of the source-grounded amplification type pixel S via the capacitance C ₁ . Further, in FIG. 6, 13, 15
Is a reset pMOS transistor for applying an initial potential to the capacitors C ₁ and C ₂ , and 20 is a reference voltage (V _ref ) source connected to one end of the reset pMOS transistor 15. Then, these capacitances C ₁ , C ₂
And the pMOS transistor for switching 14
The staged amplifier operates as an inverting amplifier with a gain of C ₁ / C ₂ .

Next, the operation of the solid-state image pickup device shown in FIG. 6 will be described based on the timing chart shown in FIG. First, in the period T ₁ , the pixel S and the suppression circuit are reset. After that, the reset nMOS transistor 3 is turned off, and the integration operation in the pixel is performed from the period T ₂ . After the start of this integration, after the potential V _{P of the} node 28 has settled down, the pMOS transistors 13 and 15 are turned off,
The pMOS transistor 14 is turned on to connect the capacitive element 12 in the suppression circuit and the feedback system of the switching pMOS transistor 14. In the period T ₃ , the integration operation of the pixel S is continued and the node caused by the integration operation is continued.
The rise in potential V _P at 28 appears at node 29 as an inverted output V _OUT . After the elapse of a certain integration time, the nMOS transistor 21 is turned on by the pulse from the shift register, and the inverted output V _OUT is transmitted to the signal output line 23.

In this operation, the reference voltage is set to the period T ₂
It is the potential of the pixel output (V _P ) at the time of switching from T ₃ to T ₃ , and this reference need not be immediately after reset. It is also possible to carry out after integration for a certain period of time, and a reset pulse ψ for driving the reset nMOS transistor 3
The fall of _R and the rise of ψ _RC for driving the pMOS transistor 13 may be the same time, and the period of T ₂ may be zero. The potential of V _P at the time of moving from the period T ₂ to T ₃ as a reference, the signal component V _PS by light integration was then increased, as the decrease in the reference voltage V _ref, (V _ref
-C ₁ / C ₂ · V _PS ) V of node 29 as the voltage value
_It is transmitted to _OUT . The potential is transmitted to the signal output line 23 by scanning the shift register and read.

Further, in the solid-state image pickup device having the structure shown in FIG. 6, a switching MOS transistor and a sample hold capacitor are added between the output of the inverting amplifier 10 and the gate of the nMOS transistor 26 forming the source follower circuit. It is possible to configure a sample and hold circuit.

Next, the range of the reference voltage V _ref allowed in this FPN suppressing circuit will be described. Node 29
Must be set so that the source-drain voltage V _DS of the pMOS transistor 16 and the source-gate voltage V _{GS of the} nMOS transistor 26 become operable voltages. Regarding V _DS, about 0.2 V is sufficient, but
Since V _GS has a substrate effect, a value represented by V _GS = V _TH + kV _BS is required. Here, V _TH is the threshold voltage of the nMOS transistor 26, and V _BS is the substrate (p well).
-Source-to-source voltage, k is a coefficient representing the influence of the substrate effect. Due to this substrate effect, in a normal CMOS process, when V _DD = 5 V, V _ref is 3 V or less, V _DD = 3 V
In this case, V _ref must be set to 1.5 V or less. When the power supply voltage becomes low in this way, the reference voltage V
_{Since ref} must be set low, the output range must be small.

Therefore, in order to increase the output amplitude,
It is necessary to amplify the signal output from the common signal line.
An amplifier circuit normally used in an image sensor is disclosed in, for example, Japanese Patent Laid-Open No. 63-288581 or Japanese Patent Laid-Open No. 59-59581.
As disclosed in Japanese Laid-Open Patent Publication No. 154880, a method is generally used in which a light-shielding pixel is provided, a level of the light-shielding pixel is sampled and held, and the level is set to a reference voltage level. is there.

FIG. 8 is a diagram showing the configuration of the differential amplifier shown in each of the above-mentioned publications. The light-shielded pixel output V _DOS is input to the input terminal DOS, and the effective pixel output V is input to the input terminal OS.
_{The OS} is input, and the output V _OUT represented by the following equation is output to the output terminal OUT. V _OUT = V _ref −R ₂ / R ₁ (V _OS −V _DOS ) Here, by increasing R ₂ / R ₁ , the output amplitude can be increased.

[0012]

When the differential amplifier circuit shown in FIG. 8 is considered to be applied to the solid-state image pickup device having the FPN suppressing circuit shown in FIG. 6, the following problems occur. I found out that When the reference voltage _Vref applied from the outside is commonly used for the FPN suppressing circuit of the solid-state image sensor shown in FIG. 6 and the differential amplifier circuit shown in FIG. 8, the reference voltage is applied only within the operable range of the FPN suppressing circuit. Because I can't decide the value of V _ref ,
The degree of freedom of the reference voltage that can be set for the power supply voltage is low. The light-shielded pixel output V is applied to the input terminal DOS of the differential amplifier circuit.
_A sample and hold circuit is required to keep _{applying DOS,} and a valid pixel output V _OS input to the input terminal _OS also drives the resistors R ₁ and R ₂ , so a buffer is required.
Therefore, the circuit scale becomes large. In the normal MOS process, since there is no diffusion layer having a large sheet resistance, the layout area of the resistors R ₁ and R ₂ becomes large. Therefore, in order to reduce the values of the resistors R ₁ and R ₂ , the capacity of the buffer connected to the input terminals OS and DOS must be increased, which increases power consumption. The light-shielded pixel output V is applied to the input terminal DOS of the differential amplifier circuit.
_{Although DOS} must be applied, it is difficult to make the dark current characteristics of the effective pixels and the dark current characteristics of the light-shielded pixels the same, and depending on the pixel structure, there is a problem such as blooming, so that complete light-shielded pixels can be obtained. Is difficult.

The present invention has been made in order to solve the above problems in a solid-state image pickup device having a conventional FPN suppressing circuit, and has the following objects. (1) An object of the present invention is to provide a solid-state imaging device capable of setting a wide range of a reference voltage applied from the outside with respect to a low power supply voltage.
This is an object corresponding to the invention described in item 5. (2) An object of the present invention is to provide a solid-state image pickup device having a peripheral circuit which has a small circuit size, a small layout area, and a small current consumption.
This is an object corresponding to the described invention. (3) An object of the present invention is to provide a solid-state imaging device capable of obtaining a signal output corresponding to a reference voltage applied from the outside without providing pixels other than effective pixels for forming a reference level, such as light-shielded pixels. , This is claim 1, 3, 4, 5
This is an object corresponding to the described invention. (4) Provided is a solid-state imaging device in which an output signal falls within the reference voltage range even if the internal reference voltage generating circuit or the second amplifying circuit according to the first or second aspect of the invention varies in offset voltage and the like. This is the purpose corresponding to the invention of claim 4. (5) An object is to provide a solid-state imaging device capable of reducing the number of external input terminals, which is an object corresponding to the invention of claim 5.

[0014]

In order to solve the above problems, the invention according to claim 1 has a plurality of pixels formed of photoelectric conversion elements arranged one-dimensionally or two-dimensionally and a peripheral circuit in the same chip. In the solid-state imaging device configured as above and having a reference voltage application terminal applied from the outside of the chip for setting the reference level of the output signal on the same chip, the reference voltage applied from the outside to the inside of the device An internal reference voltage generating circuit for generating an internal reference voltage of 1 pixel, and an output according to the signal amount of the pixel provided for each pixel in the one-dimensional sensor and for each vertical signal line in the two-dimensional sensor from the internal reference voltage. A plurality of first amplifier circuits for outputting as the amount of change, and a plurality of selection switching elements provided between the output terminals of the plurality of first amplifier circuits and the common signal line,
A second amplifier circuit provided between the common signal line and the output terminal is provided.

By providing the internal reference voltage generating circuit as described above, the range of the externally applied reference voltage can be freely set even when the power supply voltage is low, and the internal reference voltage at which the first amplifier circuit operates can be set. Can be set, and the signal output can be increased by the second amplifier circuit, and a large amplitude signal output can be obtained even with a low power supply voltage. Further, by providing the first amplifier circuit, the output for the reference voltage can be obtained without providing the light-shielding pixel,
Since the light-shielded pixel is unnecessary, it is possible to eliminate the influence of variations in the light-shielded pixel output.

According to a second aspect of the present invention, the second amplifying circuit in the solid-state image pickup device according to the first aspect is configured by an amplifying circuit having a high input impedance. This eliminates the need for extra buffers, sample and hold circuits, etc., and makes it possible to reduce the circuit scale and current consumption. Further, even if the resistance that determines the voltage amplification factor is reduced, only the driving capability of the output stage of the second amplifier circuit needs to be increased, so even when the resistance value needs to be reduced in the layout, the minimum power consumption is required. It will be possible to increase it by.

According to a third aspect of the present invention, in the solid-state image pickup device according to the first or second aspect, the internal reference voltage generating circuit applies a reference voltage applied from the outside to 1 / k (a real number larger than k: 1). In addition to including the voltage dividing circuit, the voltage amplification factor of the second amplifier circuit is set to approximately k. With this configuration, the reference level (black level) at which the sensor signal is zero can be completely matched with the reference voltage applied from the outside.

According to a fourth aspect of the present invention, in the first or second aspect of the invention, the internal reference voltage generating circuit sets the reference voltage applied from the outside to 1 / k (a real number larger than k: 1). A voltage divider circuit is included and the voltage amplification factor of the second amplifier circuit is set to k to 0.7 k. With this configuration, even if the offset voltage of the internal reference voltage generation circuit or the second amplifier circuit varies, and the external input reference voltage is small and the offset voltage is large, the output signal is within the reference voltage range. Can be entered. That is, the reference level (black level) is slightly deviated from the external reference voltage, but the signal is output within the reference voltage range even if the offset voltage varies.

According to a fifth aspect of the present invention, in the solid-state image pickup device according to any one of the first to fourth aspects, a reference voltage applied from the outside is also used as a power supply voltage inside the device. This makes it possible to reduce the number of external input terminals.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Next, examples will be described. FIG. 1 is a block configuration diagram showing a first embodiment of a solid-state imaging device according to the present invention. In this embodiment, the present invention is applied to a line sensor in which photodiodes are arranged one-dimensionally. In FIG. 1, reference numeral 101 denotes a photodiode which constitutes a pixel, and an anode is commonly connected to each pixel and grounded, and a cathode is connected to an input of a first amplifier 102 provided for each photodiode. . The output of the first amplifier 102 is the shift register 10
The common signal line 107 is connected via a selection switch 103 which is sequentially selected by 6, and the common signal line 107 is connected to an output terminal 108 via a second amplifier 105.

On the other hand, the reference voltage V _ref applied to the input terminal 109 for determining the reference level of the output signal is input to the internal reference voltage generation circuit 104 and converted into the internal reference voltage V _RR for the inside of the chip. . This internal reference voltage V _RR is applied to the first amplifier 102 provided for each pixel, and the first amplifier 102 changes the photocharge generated in the photodiode 101 by the change amount from the internal reference voltage V _RR. Is output as.

In the solid-state image pickup device configured as described above, the internal reference voltage V _RR that enables the first amplifier 102 to operate is referred to the power supply voltage and the external input reference voltage V _ref as an internal reference voltage generation circuit. By being generated by 104, it is possible to cope with a wide range of external input reference voltage V _ref even if the power supply voltage is low. The second amplifier 105 is connected to the external input reference voltage V _ref and the internal reference voltage V _ref.
By setting the amplification factor according to the relationship of _RR , an output based on the external input reference voltage V _ref can be obtained and the output amplitude can be increased.

Next, the first amplifier 102 and the second amplifier 10
5 and the internal configuration of the internal reference voltage generation circuit 104, and the detailed operation indicating the signal level will be described. First, the configuration of the first amplifier 102 uses the common source type amplifier included in the FPN suppressing circuit of the conventional solid-state image pickup device shown in FIG. 6, instead of the reference voltage V _ref in FIG. The internal reference voltage V _RR generated in the internal reference voltage generation circuit 104 may be applied. As a result, each output of the first amplifier 102 has an internal reference voltage V
_The voltage change corresponding to the photocharge is output based on _RR .

Next, the internal reference voltage generating circuit 104 and the second
The specific configuration of the amplifier 105 of FIG. 2 will be described with reference to FIGS. FIG. 2 is a diagram showing a configuration example of the internal reference voltage generating circuit 104, in which the external input reference voltage V _{ref is set} to the resistors R ₁ and R _2.
The voltage is divided by and the internal reference voltage V _RR is output via the buffer (op amp) 111. In the internal reference voltage generating circuit 104 thus configured, the external input reference voltage V _ref and the internal reference voltage V _RR are
It has the relationship shown in the following expression (1). V _RR = {R ₁ / (R ₁ + R ₂ )} × V _ref (1)

FIG. 3 is a view showing a specific configuration of the second amplifier 105 is configured by a forward amplifier using an operational amplifier 112, the relationship between the input voltage V _in and the output voltage V _OUT,
It is as shown in the following equation (2). V _OUT = {(R ₃ + R ₄ ) / R ₃ } × V _in (2)

The output V _sig of each pixel signal appearing on the common signal line 107 is expressed by the following equation (3) by the first amplifier 102.
It is represented by V _sig = V _RR −Δv (3) Here, Δv is a voltage output corresponding to the incident light amount of each pixel.

The following equation (4) is derived from the above equations (1) to (3). V _OUT = k ₂ / k ₁ × V _ref −k ₂ × Δv (4) Note that k ₁ = (R ₁ + R ₂ ) / R ₁ , k ₂ = (R ₃ + R
₄ ) / R ₃ . Here, if k ₁ = k ₂ , then V
_OUT = V _ref −k ₂ × Δv, and the external input reference voltage V
A signal output based on _ref is obtained.

The signal output V _sig on the common signal line 107 and the signal output V _OUT at the output terminal 108 expressed by these equations are
A waveform as a function of time is shown in FIG. In FIG.
Both V _sig and V _OUT represent the signal output for four pixels in time series. As can be seen from FIG. 4, the signal output V _sig on the common signal line 107 outputs a signal based on the internal reference voltage V _RR , but the signal output V _sig from the output terminal 108
_OUT is output with reference to the external input reference voltage V _ref .

As described above, according to this embodiment, by providing the internal reference voltage generating circuit 104 and the second amplifier 105, even if the external input reference voltage V _ref is close to the power supply voltage, it is provided in each pixel. The internal reference voltage V _{RR that} enables the first amplifier 102 to operate enables the operation of the first amplifier for each pixel and the output terminal 108.
Can obtain an output V _OUT with the external input reference voltage V _ref as a reference level. This is effective for obtaining a large signal output even when the power supply voltage becomes low.

Further, in this embodiment, the second amplifier
Unlike the differential amplifier circuit shown in FIG. 8, a non-inverting amplifier 112 with high input impedance as shown in FIG. 3 can be used as 105, so that the output V _sig of the common signal line 107 can be directly output to the second Can be input to the amplifier 105. This is effective for reducing the circuit scale and power consumption. Further, in the present embodiment, since the reference level can be determined without providing the light-shielding pixel, the influence of the nonuniformity of the light-shielding pixel when the light-shielding pixel is provided is not affected.

Next, the influence of the offset voltage of the operational amplifiers forming the internal reference voltage generating circuit 104 and the second amplifier 105 shown in FIGS. 2 and 3 will be described. _Assuming that the operational amplifiers constituting the internal reference voltage generating circuit and the second amplifier shown in FIGS. 2 and 3 have offset voltages V _OF1 and V _OF2 , respectively, the above equation (1) is given by the following equation (5) ) Is represented. V _RR = {R ₁ / (R ₁ + R ₂ )} × V _ref + V _OF1 (5) The above equation (2) is expressed as the following equation (6). V _OUT = {(R ₃ + R ₄ ) / R ₃ } × (V _in + V _OF2 ) ... (6) Therefore, the equation (4) is expressed by the following equation (7). V _OUT = (k ₂ / k ₁ ) × V _ref −k ₂ × Δv + k ₂ × (V _OF1 + V _OF2 ) ... (7) In the above formula (7), k _{When 1} / k ₂ = 1 is set, if there are offset voltages V _OF1 and V _OF2 , the reference of V _OUT is deviated. This means that the output V _OUT is GND to V
_When connected to an A / D or the like having an input voltage range of _ref , the offset voltages V _OF1 and V _OF2 may deviate from the input range of A / D.

In order to prevent this, k ₂ / k ₁ <1 may be set. When k ₂ / k ₁ <1, the equation (7) is given by the following equation (8).
It is represented as V _OUT = V _ref −k ₂ × Δv + {k ₂ × (V _OF1 + V _OF2 ) − (1-k ₂ / k ₁ ) × V _ref } (8) This (8 ), The third term {k ₂ × (V _OF1 + V
_{OF2) - (1-k 2} / k 1) × V ref} is such that a negative relative variation of the offset voltage V _OF1, V _OF2, may be set to k ₂ / k _1. However, k ₂ / k ₁
If 1 is set to be much smaller than 1, the output range of V _OUT is narrowed. Therefore, it is normally set to 0.9 <k ₂ / k ₁ <1. However, when V _ref is small and V _OF1 and V _OF2 are large, it may be necessary to set k ₂ / k ₁ <0.9, but due to the effective range of A / D, k ₂ / k ₁
It is desirable to set it to> 0.7.

In the first embodiment, the description has been given assuming that the power supply voltage and the external input reference voltage V _ref are input separately, but in the case where the power supply voltage is 3.3 V or less. When a large signal output is required, the power supply voltage and the external input reference voltage may be common. Thus, by using the power supply voltage as the external input reference voltage, the number of terminals can be reduced. In this case, the second amplifier 10
Since the input voltage range of 5 becomes smaller, the output voltage amplitude must be increased. However, increasing the output voltage amplitude of the second amplifier is easier than increasing the input voltage range and can be expanded to the power supply voltage range by improving only the output stage. It is possible to realize a solid-state imaging device that can output a swing.

Next, a second embodiment will be described with reference to FIG. In this embodiment, the present invention is applied to an area sensor in which photodiodes are arranged in a two-dimensional manner. Vertical selection switches 121 selected by the photodiodes 101 and vertical shift registers 123 are arranged in a matrix and vertical One end of the selection switch 121 is commonly connected to the vertical signal line 122 for each column, and is input to the first amplifier 102 provided for each column. The other configuration is shown in FIG. The same as in the first embodiment.

Next, the operation of the second embodiment having such a configuration will be described. First, after resetting the first amplifier 102, by selecting one row by the vertical shift register 123, the output of each first amplifier 102 has an internal voltage Δv corresponding to the photocharge accumulated in the selected pixel. It appears in the form of a value (V _RR −Δv) changed from the reference voltage V _RR . The output of each first amplifier 102 is supplied to the horizontal shift register 10
By sequentially reading by 6, the output V _OUT amplified by the second amplifier 105 is obtained from the output terminal 108.

Also in this embodiment, the first shown in FIG.
Similar to the embodiment, the reference level of the signal output on the common signal line 107 is the internal reference voltage V _RR , and the external input reference voltage V _ref is the reference level at the signal output V _OUT at the output terminal 108. Also in this second embodiment, all the features of the first embodiment shown in FIG. 1 can be obtained in the same manner.

[0037]

As described above on the basis of the embodiments,
According to the first aspect of the present invention, the range of the reference voltage applied from the outside can be freely set even when the power supply voltage is low, and the output range can be widened even with the low power supply voltage. Further, since the output for the reference voltage can be obtained without providing the light-shielding pixel, the influence of the variation of the light-shielding pixel is eliminated. According to the second aspect of the present invention, an extra buffer, a sample hold circuit, etc. are not required, so that the circuit scale can be reduced and the current consumption can be reduced. According to the third aspect of the invention, the reference level (black level) at which the sensor signal is zero can be completely matched with the reference voltage applied from the outside. According to the invention described in claim 4, even when the offset voltage or the like of the internal reference voltage generating circuit or the second amplifier circuit is varied, and the external input reference voltage is small and the offset voltage is large, it is within the reference voltage range. The output signal can be input to. According to the invention of claim 5, it is possible to reduce the number of terminals for input from the outside.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a diagram showing a specific configuration example of an internal reference voltage generation circuit of the first embodiment shown in FIG.

FIG. 3 is a diagram showing a specific configuration example of a second amplifier of the first embodiment shown in FIG.

FIG. 4 is a diagram showing a waveform example of a signal output of the first embodiment shown in FIG.

FIG. 5 is a circuit configuration diagram showing a second embodiment of the present invention.

FIG. 6 is a circuit configuration diagram showing a solid-state image sensor including a conventional FPN suppressing circuit.

7 is a signal waveform diagram for explaining the operation of the conventional example shown in FIG.

FIG. 8 is a diagram showing a differential amplifier circuit used in a conventional image sensor.

[Explanation of symbols]

 101 photodiode 102 first amplifier 103 selection switch 104 internal reference voltage generation circuit 105 second amplifier 106 shift register 107 common signal line 108 output terminal 109 input terminal 111 buffer 112 operational amplifier 121 vertical selection switch 122 vertical signal line 123 vertical shift register

Claims (5)

[Claims] 1. A plurality of pixels composed of photoelectric conversion elements arranged one-dimensionally or two-dimensionally and a peripheral circuit are formed on the same chip, and a reference level of an output signal applied from the outside of the chip is set. In a solid-state image pickup device having a reference voltage application terminal on the same chip for controlling the internal reference voltage generation circuit for generating an internal reference voltage for the inside of the device from a reference voltage applied from the outside, each one-dimensional sensor A plurality of first amplifier circuits, which are provided for each pixel in each vertical signal line in the two-dimensional sensor, and which output an output according to the signal amount of the pixel as an amount of change from the internal reference voltage; and the plurality of first amplifier circuits. A plurality of switching elements for selection provided between the output end of the amplifier circuit and the common signal line, and a second amplifier circuit provided between the common signal line and the output terminal. Tosu Solid-state imaging device. 2. The solid-state imaging device according to claim 1, wherein the second amplifier circuit is composed of a non-inverted amplifier circuit having a high input impedance. 3. The internal reference voltage generation circuit uses a reference voltage applied from the outside as 1 / k (k: a real number greater than 1).
3. The solid-state imaging device according to claim 1, wherein the solid-state imaging device includes a voltage dividing circuit according to claim 2, and a voltage amplification factor of the second amplifier circuit is set to approximately k. 4. The internal reference voltage generating circuit uses a reference voltage applied from the outside as 1 / k (k: a real number larger than 1).
3. The solid-state imaging device according to claim 1, wherein the solid-state imaging device includes a voltage dividing circuit according to claim 2, and a voltage amplification factor of the second amplifier circuit is set to k to 0.7 k. 5. The solid-state imaging device according to claim 1, wherein a reference voltage applied from the outside is also used as a power supply voltage inside the device.