JPH11103028A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) Abstract: Provided is a technique capable of improving the manufacturing yield of a DRAM having a memory cell having a COB structure. SOLUTION: Two dummy bit lines D are provided in one dummy area between a main body memory cell area and a direct peripheral circuit area.
BL and two columns of dummy memory cells DMC are arranged, and in the other dummy region, three columns of dummy bit lines DBL and two columns of dummy memory cells DMC are arranged. That is,
A dummy bit line DBL is always arranged at the outermost part of the dummy region, and the dummy memory cell DMC is directly sandwiched between the bit line BL and the dummy bit line DBL or between the dummy bit line DBL and the dummy bit line DBL. The inclination to the peripheral circuit area side is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device and, more particularly, to a DRAM (Dynamic Random Access Memory).
mory) and SRAM (Static Random Access Memory)
), Which are effective technologies.

[0002]

2. Description of the Related Art In one of semiconductor integrated circuit devices, a memory cell is a memory cell selecting MISFET (Metal Insulator).
There is a DRAM composed of a field effect transistor (Semicoductor) and an information storage capacitor. But D
With the increase in the capacity of the RAM, the miniaturization of the memory cell progresses, and the amount of charge stored in the information storage capacitor element decreases, which causes a problem that the information holding characteristic deteriorates. Therefore, in recent large-capacity DRAMs, a memory cell having a stack structure in which an information storage capacitor element is arranged above a MISFET for selecting a memory cell and the surface area of a storage electrode is increased to increase the amount of stored charge is adopted. Have been.

[0003] Among the memory cells having the stack structure, a capacitor over bit line in which an information storage capacitor is arranged above a bit line used for input / output of information stored in the memory cell.
ne; COB) memory cell of 16 Mbit or more D
Used for RAM. By employing the memory cell having the COB structure, the structure of the information storage capacitor can be made three-dimensional, for example, a fin structure or a crown structure, so that the surface area of the storage electrode can be increased.

However, in the memory cell having the COB structure, it is difficult to accurately process all the memory cells due to its complicated structure. The shape defect is likely to occur. Therefore, usually, a dummy bit line and a dummy memory cell are arranged at the end of the memory cell array in parallel with the bit line to prevent a shape defect occurring in the main body memory cell.

FIG. 9 shows a dummy bit line DBL and a dummy memory cell DM in a conventional memory cell array MA.
An example of the arrangement of C is shown. Two columns of dummy bit lines DBL and two columns of dummy memory cells DMC are arranged at both ends of the main body memory cell region in parallel with the bit lines BL.

A DRAM in which dummy patterns are arranged in a memory cell array is described in, for example, "Super LSI Memory" published by Baifukan on November 5, 1994, written by Kiyo Ito, pp. 227-P231.

[0007]

However, the present inventor has found that the memory cell array having the dummy region has the following problems.

That is, the dummy area shown in FIG.
Since the dummy memory cell is constituted by the dummy bit lines in the column and the dummy memory cells in the two columns, in either one of the dummy regions provided at both ends of the memory cell array, the dummy memory cell is always directly adjacent to the peripheral circuit region. . Dummy memory cells are similar to memory cells in the main body memory cell area.
Because of the OB structure, the height (elevation) from the surface of the semiconductor substrate is high, and the altitude difference between adjacent direct peripheral circuit regions is large. For this reason, the information storage capacitance element of the dummy memory cell is directly inclined to the peripheral circuit region side, resulting in a defective shape and lowering the manufacturing yield.

An object of the present invention is to provide a technique capable of improving the production yield of a DRAM having a memory cell having a COB structure.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor integrated circuit device of the present invention, n rows of word lines to which m memory cells are connected
Dummy regions formed by dummy bit lines and dummy memory cells are provided on both sides in the column direction of a main body memory cell region having m × n memory cells formed of m columns of bit pairs connected to the memory cells. A memory cell array provided respectively, a dummy bit line is arranged at the outermost part of the dummy region, and the dummy memory cell is sandwiched between the bit line and the dummy bit line or between the dummy bit line and the dummy bit line. .

According to the above-mentioned means, the dummy bit line is arranged at the outermost part of the dummy area of the memory cell array directly adjacent to the peripheral circuit area, and the dummy memory cell is replaced with the bit line and the dummy bit line or the dummy bit line and the dummy bit line. By sandwiching the dummy memory cell with the line, it is possible to prevent the dummy memory cell from directly adjoining the peripheral circuit region and not directly tilting toward the peripheral circuit region.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

A dummy region of a memory cell array of a DRAM according to an embodiment of the present invention will be described with reference to FIGS. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is a plan view of a semiconductor chip constituting a DRAM for explaining an embodiment of the present invention.

The DRAM of the present embodiment is, for example, 64M
It is a bit DRAM. The semiconductor chip is made of, for example, a small piece of silicon single crystal formed in a rectangular shape, and has a size of, for example, about 10 mm × 20 mm.

On the main surface of the semiconductor chip, an indirect peripheral circuit area and eight memory mats M are arranged. In the indirect peripheral circuit area, peripheral circuits (not shown) such as an input circuit, an output circuit, a control circuit, and a power supply circuit are formed. Also, one memory mat M
Is divided into 128 sub-memory mats SM each including a memory cell array MA and a direct peripheral circuit region arranged adjacent to the memory cell array MA.

The memory cell array MA has word lines WL
And the bit lines BL are arranged so as to be orthogonal to each other, and the memory cells MC are regularly arranged near the intersection of the word lines WL and the bit lines BL.

The word line WL is connected to a direct peripheral circuit including a row decoder and a row driver, and the bit line BL is connected to a direct peripheral circuit including a sense amplifier, a column decoder and a column driver.

Next, FIG. 2 shows an arrangement of the dummy bit lines DBL and the dummy memory cells DMC in the memory cell array MA of the present embodiment.

Two dummy bit lines DBL and two columns of dummy memory cells DMC are arranged in parallel with the bit lines BL in one dummy area disposed between the main memory cell area and the direct peripheral circuit area. In the other dummy region, three columns of dummy bit lines DBL and two columns of dummy memory cells DMC are arranged in parallel with the bit lines BL.

That is, a dummy bit line DBL is always arranged at the end of the memory cell array MA, and the dummy memory cell DMC is connected to the bit line BL and the dummy bit line DBL or the dummy bit line DBL and the dummy bit line DBL.
BL, the dummy memory cell DM
C is prevented from directly tilting toward the peripheral circuit area.

Next, FIG. 3 is a cross-sectional view of a main part of a semiconductor substrate showing a dummy bit line DBL and a dummy memory cell DMC arranged in the memory cell array MA of the present embodiment, and a direct peripheral circuit. The dummy memory cell DMC is a MISFET for selecting a memory cell constituting the memory cell MC.
And a memory cell selecting MISFET and an information storage capacitor having substantially the same shape and dimensions as the information storage capacitor. In the direct peripheral circuit, only the n-channel MISFET Qs is shown.

As shown in FIG. 3, a main surface of a semiconductor substrate (semiconductor chip) 1 made of p ^- type silicon single crystal is
A mold well 2 is formed, and a field insulating film 3 for element isolation made of a silicon oxide film is formed on a main surface of the non-active region of the p-type well 2. Dummy memory cell D
The memory cell selecting MISFET constituting part of the MC and the n-channel MISFET Qs of the direct peripheral circuit are:
The p-type well 2 is formed on the main surface of the active region surrounded by the field insulating film 3.

The gate electrode 5 of the memory cell selecting MISFET is formed integrally with the word line WL. The gate electrode 5 is made of, for example, a polycrystalline silicon film into which an n-type impurity (for example, phosphorus (P)) is introduced. In addition,
The gate electrode 5 may be composed of a polycide film in which a high-melting metal silicide film is laminated.

An insulating film 7 is formed on the gate electrode 5 and on the side wall in the gate length direction. This insulating film 7 is made of, for example, a silicon nitride film.

On top of the insulating film 7, a silicon oxide film 8,
BPSG (Boron-doped Phospho Silicate Glass) film 9
A dummy bit line DBL is formed via an insulating film made of a silicon oxide film 13. Although not shown in the figure, the dummy bit line DBL is
It is connected to one of the n-type semiconductor regions of the memory cell selecting MISFET through a second contact hole formed in the same insulating film as the PSG film 9, the silicon oxide film 8, and the gate insulating film 4. This dummy bit line DB
L denotes a polycrystalline silicon film 15 into which, for example, an n-type impurity (for example, P) is introduced and tungsten silicide (WSi).
_X ) It is composed of a laminated film of the film 16.

A silicon oxide film 18 and a silicon nitride film 19 are formed above the dummy bit line DBL.

On the upper layer of the silicon nitride film 19, a storage electrode of an information storage capacitor constituting another part of the dummy memory cell DMC is formed. This storage electrode
It is composed of polycrystalline silicon films 22, 23, 25, and 27 into which n-type impurities (for example, P) are introduced.

The storage electrode is provided on the other n-type semiconductor region 10 of the memory cell selection MISFET through a third contact hole 24 formed in the silicon nitride film 19, the silicon oxide film 18, and the silicon oxide film 13. Connected to a plug electrode made of the polycrystalline silicon film 12 into which the n-type impurity (for example, P) is introduced.

A plate electrode of the information storage capacitor is formed above the storage electrode of the information storage capacitor via a capacitor insulating film. This capacitance insulating film is formed of, for example, a laminated film of a silicon nitride film and a silicon oxide film. The plate electrode is made of, for example, a titanium nitride film 28.

On the upper layer of the dummy memory cell DMC composed of the memory cell selecting MISFET and the information storage capacitance element, a first layer metal wiring is formed via an interlayer insulating film composed of a silicon oxide film 29 and a BPSG film 30. Have been. The first layer metal wiring is, for example, a titanium film 3
2, a three-layer film in which a tungsten film 33 and a titanium nitride film 34 are sequentially laminated.

The first-layer metal wiring is a BPSG film 30.
And a fourth contact hole 31a opened in the silicon oxide film 29, and connected to the plate electrode.
It is connected to a bit line through a fourth contact hole 31b opened in the SG film 30, the silicon oxide film 29, and the silicon oxide film 18. Further, the BPSG film 30, the silicon oxide film 29, the silicon oxide film 18, and the silicon oxide film 13, is connected to the n-type semiconductor region 6 through a fourth contact hole 31c formed in the same insulating film as the BPSG film 9, the silicon oxide film 8 and the gate insulating film 4.

On the upper layer of the first-layer metal wiring, a second-layer metal wiring is formed via an interlayer insulating film 35. The second layer metal wiring is, for example, a tungsten film 3
7, a three-layer film in which an aluminum film 38 and a titanium nitride film 39 are sequentially laminated. The second-layer metal wiring is a through-hole 36 a formed in the interlayer insulating film 35.
To 36c are connected to the first-level metal wiring.

Next, the dummy bit line DBL and the dummy memory cell DMC, which are arranged in the memory cell array MA,
A method of manufacturing the n-channel MISFET Qs of the direct peripheral circuit will be described with reference to FIGS. The dummy bit line DBL and the dummy memory cell DMC shown in FIGS. 2 and 3 are formed in the same manufacturing process as the bit line BL and the memory cell MC in the main body memory cell region.

First, as shown in FIG. 4, p ^- type silicon single crystal is formed on a main surface of a semiconductor substrate 1 by a known method.
Mold well 2, field insulating film 3, and gate insulating film 4
Are sequentially formed.

Next, although not shown, the polycrystalline silicon film P is introduced on the semiconductor substrate 1, WSi _X film, sequentially depositing a silicon oxide film and a silicon nitride film. Thereafter, the silicon nitride film using the photoresist as a mask, the silicon oxide film, by sequentially etching the laminated film made WSi _X film and polycrystalline silicon film, W
A gate electrode 5 of a MISFET for selecting a memory cell of a dummy memory cell DMC composed of a Si _x film and a polycrystalline silicon film and an n-channel MISFET Q of a direct peripheral circuit
s gate electrode 5 is formed.

[0039] Although using the WSi _X film to the metal silicide film constituting the gate electrode 5, other metal silicide films such as molybdenum silicide (MoSi
_X ) film, a titanium silicide (TiSi _x ) film, a tantalum silicide (TaSi _x ) film, or the like may be used.

Next, by performing thermal oxidation treatment on the semiconductor substrate 1 to form a thin silicon oxide film on the side wall of the WSi _X film and polycrystalline silicon film constituting the gate electrode 5 (not shown).

Next, the photoresist and the silicon nitride film, a silicon oxide film, WSi _X film and polycrystalline silicon film comprising a laminated film as a mask, n-type impurities into the p-type well 2 of the direct peripheral circuit region, e.g. P ions are implanted to form an n-type semiconductor region (source region, drain region) 6 of the n-channel type MISFET Qs in a self-aligned manner with respect to the gate electrode 5.

Thereafter, the silicon nitride film deposited on the semiconductor substrate 1 is processed by anisotropic etching such as RIE (Reactive Ion Etching) to form a sidewall spacer on the side wall of the gate electrode 5 and to form a gate spacer. 5 is covered with an insulating film 7 made of a silicon nitride film.

After the formation of the sidewall spacers, the high-concentration n is directly added to the p-type well 2 in the peripheral circuit region.
By implanting a type impurity, for example, arsenic (As), the source region and the drain region of the n-channel MISFET Qs may have an LDD (Lightly Doped Drain) structure.

Next, a silicon oxide film 8 is formed on the semiconductor substrate 1.
And a BPSG film 9 are sequentially deposited by a CVD method.
The surface of the G film 9 is flattened.

Thereafter, using the photoresist as a mask, B
By sequentially etching the insulating film of the same layer as the PSG film 9, the silicon oxide film 8, and the gate insulating film 4, a first contact hole is formed on the n-type semiconductor region 10 formed after one of the memory cell selecting MISFETs. 11 is formed.

Next, the first contact hole 11
A plug electrode made of a polycrystalline silicon film 12 into which P is introduced is formed. Note that the diffusion of P introduced into the polycrystalline silicon film 12 causes the memory cell selecting MISF
One n-type semiconductor region 10 of ET is formed.

Next, the silicon oxide film 1 is formed on the semiconductor substrate 1.
3 is deposited by a CVD method. Next, although not shown, the silicon oxide film 1 is formed using a photoresist as a mask.
3, by sequentially etching the same insulating film as the BPSG film 9, the silicon oxide film 8 and the gate insulating film 4, the second contact is formed on the n-type semiconductor region formed after the other of the memory cell selecting MISFET. Form a hole. At this time, a second contact hole 14 for extending a bit line BL to be formed later directly to the peripheral circuit region and directly connecting to the semiconductor substrate 1 in the peripheral circuit region may be formed.

Next, a P-doped polycrystalline silicon film 15 and a WSi _x film 16 are sequentially deposited on the semiconductor substrate 1 by a CVD method, and then the WSi _x film 16 and the polycrystalline silicon film 15 are Are sequentially etched. Accordingly, the dummy bit line DBL consisting WSi _X film 16 and the polycrystalline silicon film 15.

The other n-type semiconductor region of the memory cell selecting MISFET is formed by the diffusion of P introduced into the polycrystalline silicon film 15, and the dummy bit line DBL is passed through the second contact hole to form the memory cell selecting MISFET. MISFET is connected to the other n-type semiconductor region.
At this time, the n-type semiconductor region 17 is also formed directly in the p-type well 2 in the peripheral circuit region by the diffusion of P introduced into the polycrystalline silicon film 15, and the second contact hole 1 is formed.
Through 4, the extension of the bit line BL is connected to the n-type semiconductor region 17.

Next, as shown in FIG. 5, a silicon oxide film 18, a silicon nitride film 19 and a BP
After the SG film 20 is sequentially deposited by the CVD method, 900
The surface of the BPSG film 20 is flattened by a reflow process at ９950 ° C., and then a silicon oxide film 21 is deposited on the semiconductor substrate 1.

Next, after the P-doped polycrystalline silicon film 22 is deposited on the semiconductor substrate 1 by the CVD method, the polycrystalline silicon film 22 is etched using a photoresist as a mask. Next, the P-introduced polycrystalline silicon film 23 deposited on the semiconductor substrate 1 by the CVD method is processed by anisotropic etching such as RIE, and the polycrystalline silicon film 23 is formed on the side wall of the polycrystalline silicon film 22. Is formed.

Then, using the photoresist as a mask, the silicon oxide film 21, the BPSG film 20, the silicon nitride film 1
9, a third contact hole 24 is formed on the plug electrode provided in the first contact hole 11 by sequentially etching the silicon oxide film 18 and the silicon oxide film 13, and thereafter, on the semiconductor substrate 1. The P-doped polycrystalline silicon film 25 and BPSG film 26 are
The layers are sequentially deposited by the VD method.

Next, using the photoresist as a mask, the BP
After sequentially etching the SG film 26 and the polycrystalline silicon films 25 and 22, a polycrystalline silicon film 27 in which P is introduced is deposited on the semiconductor substrate 1 by a CVD method. Then, the polycrystalline silicon film 27 is processed by anisotropic etching such as RIE, and the polycrystalline silicon film 27 is formed on the side walls of the BPSG film 26 and the polycrystalline silicon films 25 and 22.
Leave.

Next, as shown in FIG. 6, the BPSG film 26, the silicon oxide film 21 and the BPSG film 20 are removed by, for example, wet etching using a hydrofluoric acid solution, and the polycrystalline silicon films 22, 23, and 25 are removed. , 27 are formed.

Next, a silicon nitride film (not shown) having a thickness of about 2 nm is deposited on the semiconductor substrate 1 by a CVD method.
Subsequently, an amorphous tantalum oxide (Ta) having a thickness of about 30 nm is used.
After depositing a ₂ O ₅ ) film (not shown) by a CVD method, the Ta ₂ O ₅ film is crystallized by subjecting the semiconductor substrate 1 to a thermal oxidation treatment. Thereafter, a titanium nitride film 28 is deposited on the semiconductor substrate 1 by a CVD method, and then the titanium nitride film 2 is deposited using a photoresist as a mask.
By etching 8, a plate electrode made of a titanium nitride film 28 is formed. Through the above manufacturing steps, the information storage capacitor of the dummy memory cell DMC is completed.

Although the Ta ₂ O ₅ film was used as the capacitor insulating film, other metal oxide films (for example, (Ba, Sr) T
An iO film or a Pb (Zr, Ti) O ₃ film) may be used, and a titanium nitride film is used as a film constituting the plate electrode. However, other metal nitride films (for example, a tungsten nitride film) ) Or metal film (for example,
For example, a tungsten film) may be used.

Next, as shown in FIG. 7, after a silicon oxide film 29 and a BPSG film 30 are sequentially deposited on the semiconductor substrate 1 by the CVD method, the surface of the BPSG film 30 is reflowed at 900 to 950 ° C. Flatten. The surface of the BPSG film 30 is planarized by CMP (Chem).
ical Mechanical Polishing).

Next, using the photoresist as a mask, B
By sequentially etching the PSG film 30 and the silicon oxide film 29, a fourth contact hole 31a is formed on the plate electrode made of the titanium nitride film 28.

Simultaneously, the BPSG film 30, the silicon oxide film 29, and the silicon oxide film 18 are sequentially etched to form the WSi _x film 16 and the polycrystalline silicon film 15.
A fourth contact hole 31b is formed on the extending portion of the bit line BL made of.

At the same time, the BPSG film 30, the silicon oxide film 29, the silicon oxide film 18, the silicon oxide film 1
3, the insulating film of the same layer as the BPSG film 9, the silicon oxide film 8, and the gate insulating film 4 is sequentially etched to form the n-type semiconductor region 6 of the n-channel MISFET Qs.
A fourth contact hole 31c is formed thereon.

Next, for example, a titanium film 32, a tungsten film 33 and a titanium nitride film 34 are sequentially deposited on the semiconductor substrate 1 to form a metal film having a laminated structure, and this metal film is formed using a photoresist as a mask. By etching, a first layer metal wiring connected to the plate electrode, the extending portion of the bit line BL or the n-type semiconductor region 6 of the n-channel MISFET Qs is formed.

Next, as shown in FIG. 8, TEOS (Tetra Ethyl Ortho Silicate; Si (OC)
_A silicon oxide film is deposited by a plasma CVD method using ₂ H ₅ ) ₄ ) as a source.
An OG (Spin On Glass) film is applied. Then, this S
The OG film is etched back by the RIE method to perform a flattening process, and then a silicon oxide film is deposited again by the plasma CVD method using TEOS as a source to provide an interlayer insulating film 35 having a three-layer structure.

Thereafter, the interlayer insulating film 35 is etched using a photoresist as a mask, so that the first-layer metal wiring connected to the bit line BL is formed on the first-layer metal wiring connected to the plate electrode. Through holes 36a to 36c are formed on the wiring and on the first layer wiring connected to the n-type semiconductor region 6 of the n-channel MISFET Qs.

Next, for example, a tungsten film 37, an aluminum film 38 and a titanium nitride film 39 are sequentially deposited on the semiconductor substrate 1 to form a metal film having a laminated structure, and this metal film is formed using a photoresist as a mask. To form a second-layer metal wiring.

Finally, by covering the surface of the semiconductor substrate 1 with the passivation film 40, the dummy bit line DBL and the dummy memory cell DMC arranged in the memory cell array MA of this embodiment shown in FIG. The peripheral circuit is completed.

As described above, according to the present embodiment, the dummy bit line DBL is arranged at the outermost part of the dummy area of the memory cell array MA directly adjacent to the peripheral circuit area, and the dummy memory cell DMC is connected to the bit line BL and the dummy line. Bit line DB
L or dummy bit line DBL and dummy bit line DBL
The dummy memory cell DMC can be prevented from directly adjoining the peripheral circuit region and leaning directly to the peripheral circuit region side.

In the present embodiment, the dummy region located at one end of the memory cell array MA is constituted by two columns of dummy bit lines DBL and two columns of dummy memory cells DMC, and is provided at the other end. Dummy regions located are three columns of dummy bit lines DBL and two columns of dummy memory cells DM.
C, the number of columns of the dummy bit lines DBL and the number of columns of the dummy memory cells DMC need to be changed if the dummy bit line DBL is arranged at the outermost part of the dummy region directly adjacent to the peripheral circuit region. Is possible.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, the case where the present invention is applied to a DRAM has been described. However, the present invention can also be applied to an SRAM.

[0070]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, it is possible to prevent the dummy memory cell arranged at the end of the memory cell array from tilting to the adjacent direct peripheral circuit region side.
Can improve the production yield.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a DRA for explaining an embodiment of the present invention;
FIG. 3 is a plan view of a semiconductor chip constituting M.

FIG. 2 is a plan view showing a layout of dummy bit lines and dummy memory cells in a memory cell array according to an embodiment of the present invention.

FIG. 3 is a sectional view of a main part of a semiconductor substrate showing a DRAM according to an embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 9 is a diagram showing a layout of dummy bit lines and dummy memory cells in a conventional memory cell array.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 p-type well 3 field insulating film 4 gate insulating film 5 gate electrode 6 n-type semiconductor region (source region, drain region) 7 insulating film 8 silicon oxide film 9 BPSG film 10 n-type semiconductor region 11 first contact Hole 12 polycrystalline silicon film 13 silicon oxide film 14 second contact hole 15 polycrystalline silicon film 16 tungsten silicide film 17 n-type semiconductor region 18 silicon oxide film 19 silicon nitride film 20 BPSG film 21 silicon oxide film 22 polycrystalline silicon film 23 Polycrystalline silicon film 24 Third contact hole 25 Polycrystalline silicon film 26 BPSG film 27 Polycrystalline silicon film 28 Titanium nitride film 29 Silicon oxide film 30 BPSG film 31a Fourth contact hole 31b Fourth contact hole 31c Contact hole 32 titanium film 33 tungsten film 34 titanium nitride film 35 interlayer insulating film 36a through hole 36b through hole 36c through hole 37 tungsten film 38 aluminum film 39 titanium nitride film 40 passivation film M memory mat SM sub memory mat MA memory cell array CA Cross region WL Word line BL Bit line DBL Dummy bit line MC Memory cell DMC Dummy memory cell Qs N-channel MISFET

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 27/11 (72) Inventor Tsutomu Takahashi 2326 Imai, Ome-shi, Tokyo Inside Device Development Center, Hitachi, Ltd. (72) Inventor Tanaka Atsushiya 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd.Device Development Center (72) Inventor Yasushi Takahashi Shunichi 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Prefecture (72) Inside of Texas Instruments Instruments Co., Ltd. 2350 Kihara, Miura-mura, Inashiki-gun, Japan Texas Instruments Co., Ltd.

Claims (8)

[Claims] 1. An m.times.n comprising n (n is a natural number) row word lines to which m (m is a natural number) memory cells are connected and m column bit pair lines to which n memory cells are connected. A semiconductor integrated circuit device having a memory cell array in which dummy bit lines and dummy regions each including a dummy memory cell are provided on both sides in a column direction of a main body memory cell region having memory cells. Wherein a dummy bit line is arranged at the outermost part of the semiconductor integrated circuit device. 2. A main body memory cell region having m × n memory cells including n rows of word lines to which m memory cells are connected and bit pairs of m columns to which n memory cells are connected. A semiconductor integrated circuit device having a memory cell array in which a dummy region formed by a dummy bit line and a dummy memory cell is provided on both sides in the column direction, wherein the dummy memory cell formed in the dummy region is A semiconductor integrated circuit device sandwiched between a dummy bit line and a dummy bit line or between a dummy bit line and a dummy bit line. 3. A main body memory cell region having m × n memory cells including n rows of word lines to which m memory cells are connected and bit pairs of m columns to which n memory cells are connected. A semiconductor integrated circuit device having a memory cell array provided on both sides in a column direction with dummy bit lines and dummy regions formed by dummy memory cells, wherein the dummy located at one end of the memory cell array is provided. 2. The semiconductor integrated circuit device according to claim 1, wherein the dummy bit lines formed in the region are even columns, and the dummy bit lines formed in the dummy region located at the other end of the memory cell array are odd columns. 4. A main body memory cell region having m × n memory cells consisting of n rows of word lines to which m memory cells are connected and bit pairs of m columns to which n memory cells are connected. A semiconductor integrated circuit device having a memory cell array provided on both sides in a column direction with dummy bit lines and dummy regions formed by dummy memory cells, wherein the dummy located at one end of the memory cell array is provided. A semiconductor integrated circuit device, wherein the number of columns of dummy bit lines formed in a region is different from the number of columns of dummy bit lines formed in the dummy region located at the other end of the memory cell array. 5. A main body memory cell region having m × n memory cells including n rows of word lines to which m memory cells are connected and bit pairs of m columns to which n memory cells are connected. A semiconductor integrated circuit device having a memory cell array provided on both sides in a column direction with dummy bit lines and dummy regions formed by dummy memory cells, wherein the dummy located at one end of the memory cell array is provided. Two columns of dummy bit lines and two columns of dummy memory cells are formed in the region, and three columns of dummy bit lines and two columns of dummy memory cells are formed in the dummy region located at the other end of the memory cell array. And a semiconductor integrated circuit device. 6. The semiconductor integrated circuit device according to claim 1, wherein a dummy bit line in said dummy region has substantially the same shape as a bit line in said main body memory cell region. Semiconductor integrated circuit device. 7. The semiconductor integrated circuit device according to claim 1, wherein the dummy memory cells in the dummy area have substantially the same shape as the memory cells in the main body memory cell area. Semiconductor integrated circuit device. 8. The semiconductor integrated circuit device according to claim 1, wherein said memory cells are one stacked information storage capacitor and one memory cell selecting M.
A semiconductor integrated circuit device comprising: a DRAM cell composed of an ISFET; or an SRAM cell composed of one flip-flop circuit and a pair of transfer MISFETs.