JPH11103028A5 - - Google Patents

Claims (11)

A semiconductor integrated circuit device having a memory cell array in which dummy areas formed by dummy bit lines and dummy memory cells are provided on both sides in the column direction of a main memory cell area having m×n memory cells each consisting of n (n is a natural number) word lines in rows to which m (m is a natural number) memory cells are connected and m (m is a natural number) bit pair lines in columns to which n memory cells are connected, and the semiconductor integrated circuit device is characterized in that dummy bit lines are arranged at the outermost edges of the dummy areas. A semiconductor integrated circuit device having a memory cell array in which dummy regions formed by dummy bit lines and dummy memory cells are provided on both sides in the column direction of a main memory cell region having m×n memory cells each consisting of n rows of word lines to which m memory cells are connected and m columns of bit pair lines to which n memory cells are connected, wherein the dummy memory cells formed in the dummy regions are sandwiched between the bit lines and the dummy bit lines or between the dummy bit lines and the dummy bit lines. A semiconductor integrated circuit device having a memory cell array in which dummy areas formed by dummy bit lines and dummy memory cells are provided on both sides in the column direction of a main memory cell area having m×n memory cells each consisting of n rows of word lines to which m memory cells are connected and m columns of bit pair lines to which n memory cells are connected, wherein the dummy bit lines formed in the dummy area located at one end of the memory cell array are for even columns, and the dummy bit lines formed in the dummy area located at the other end of the memory cell array are for odd columns. A semiconductor integrated circuit device having a memory cell array in which dummy areas formed by dummy bit lines and dummy memory cells are provided on both sides in the column direction of a main memory cell area having m×n memory cells each consisting of n rows of word lines to which m memory cells are connected and m columns of bit pair lines to which n memory cells are connected, wherein the number of columns of dummy bit lines formed in the dummy area located at one end of the memory cell array is different from the number of columns of dummy bit lines formed in the dummy area located at the other end of the memory cell array. A semiconductor integrated circuit device having a memory cell array in which dummy areas formed by dummy bit lines and dummy memory cells are provided on both sides in the column direction of a main memory cell area having m×n memory cells each consisting of n rows of word lines to which m memory cells are connected and m columns of bit pair lines to which n memory cells are connected, wherein two columns of dummy bit lines and two columns of dummy memory cells are formed in the dummy area located at one end of the memory cell array, and three columns of dummy bit lines and two columns of dummy memory cells are formed in the dummy area located at the other end of the memory cell array. 6. The semiconductor integrated circuit device according to claim 1, wherein the dummy bit lines in the dummy region are configured to have substantially the same shape as the bit lines in the main memory cell region. 6. The semiconductor integrated circuit device according to claim 1, wherein the dummy memory cells in the dummy region are configured to have substantially the same shape as the memory cells in the main memory cell region. 8. The semiconductor integrated circuit device according to claim 1, wherein the memory cell is a DRAM cell composed of one stacked type information storage capacitance element and one memory cell selection MISFET, or wherein the memory cell is an SRAM cell composed of one flip-flop circuit and a pair of transfer MISFETs. a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines; a plurality of first dummy memory cells arranged at intersections of a first dummy bit line and the plurality of word lines; and a plurality of second dummy memory cells arranged at intersections of a second dummy bit line and the plurality of word lines. a second dummy memory cell, wherein the plurality of bit lines, the plurality of memory cells, and the plurality of first and second dummy memory cells are arranged between the first dummy bit line and the second dummy bit line. A semiconductor integrated circuit device having a region including a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines, a plurality of first dummy memory cells arranged at intersections of a first dummy bit line and the plurality of word lines, a plurality of second dummy memory cells arranged at intersections of a second dummy bit line and the plurality of word lines, and a plurality of word drivers for driving the plurality of word lines, wherein the first dummy bit line and the second dummy bit line are closer to the region than the plurality of first and second dummy memory cells. 11. The semiconductor integrated circuit device according to claim 9, wherein the memory cell includes a capacitance element, and the plurality of bit lines are arranged at a position closer to the semiconductor substrate than the capacitance element.