JPH11232891A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a capacitive load of a bit line by increasing capacity of a non-volatile semiconductor memory, and to increase operation speed by setting voltage satisfying each condition of erasing a memory cell, programming, and reading out. SOLUTION: A memory cell array is divided into plural blocks 13, 14, and bit lines specified by the same column address of each block are constituted with divided bit lines BLa, BLb. The bit lines BLa, BLb of each block are selectively connected to a main bit line BL connected to a column address decoder by selection transistors 15, 17, further, connected selectively to a potential line ARGND by selection transistors MOS 16, 18. Thereby, a capacitive load of a bit line is reduced, also, a bit line being not selected is connected to the potential line ARGND and made to a discharge state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory using a memory transistor having a floating gate and a control gate.

[0002]

2. Description of the Related Art An electrically erasable programmable ROM (EEPROM: E) in which a memory cell comprises a single transistor.
lectricaly Erasable Programmable ROM)
2 with floating gate and control gate
Each memory cell is constituted by a transistor having a heavy gate structure. In the case of such a double-gate transistor, information is written by accelerating hot electrons generated on the drain side of the floating gate to the source side and injecting the electrons through the gate insulating film into the floating gate. Then, information is read by detecting a difference in operation characteristics of the memory cell transistor depending on whether or not charge is injected into the floating gate.

There are roughly two types of such memory cell structures, one is called a stack gate type and the other is called a split gate type. In particular, as shown in FIG.
A floating gate 4 is partially formed on the channel formed between the source region 2 and the source region 2 via an insulating film 3, and a control gate 5 is partially formed on the channel between the source region 2 and the insulating film 6. Are formed so as to overlap with the floating gate 4.

FIG. 3 shows a schematic configuration of a nonvolatile semiconductor memory using such a split gate type memory cell. In a memory cell array 8 in which a plurality of memory cells 7 are arranged in n × m rows and columns, each memory cell 7 has n word lines WL (0 to n−1) and m bit lines. The control gate (5 in FIG. 2) of the memory cell 7 is connected to the word line WL, and the drain (1 in FIG. 2) is connected to the bit line BL. The source (2 in FIG. 2) of the memory cell 7 in each row connected to the adjacent word line WL is connected to the common source line SL.
(0 to n / 2-1). For example, the word line WL
0 and WL1 are connected to a common source line SL
Connected to 0. The row address decoder 9 selects one of the word lines WL based on the applied row address data RAD, and selects based on signals ES, PG, and RE indicating an erase mode, a program mode, and a read mode, respectively. A voltage according to each mode is supplied to the selected word line WL. Further, the row address decoder 9
A voltage according to each mode is supplied to the common source line SL related to the selected word line WL. The column address decoder 10 selects one of the bit lines BL based on the applied column address data CAD, and writes and reads data to the selected bit line BL in accordance with the program mode signal PG and the read mode signal RE. Apply a controlled voltage.

On the other hand, each bit line BL and potential line ARGND
In order to prevent bit line discharge in the erase mode and read mode and erroneous write in the program mode, control is performed by inverted signals * Y0 to * Ym-1 of the decode output of the column address decoder 10. MOS transistors 12 are provided. For example,
In the read mode and the program mode, as a result of decoding the column address data CAD, the bit line B
When L0 is selected, its decoded output * Y0 is "L"
Level, and other decoded outputs * Y1 to * Ym-1
Becomes the “H” level. Therefore, the selected bit line B
The bit lines BL1 to BLm-1 other than L0 are connected to the potential line AGND via the turned-on MOS transistor 12.

Next, the erase mode, program mode, and read mode of the nonvolatile semiconductor memory will be described with reference to FIGS. (1) Erase Mode When the erase mode signal ES becomes active, the row address decoder 9 applies an erase voltage Ve (eg, 14.5 V) to the word line WL (eg, WL0) selected by the row address data RAD. The other unselected word lines WL1 to WLn-1 are connected to the ground voltage (0
V). Further, the row address decoder 9 applies a ground potential to all the common source lines SL0 to SLn / 2-1.

On the other hand, in the column address decoder 10, all the MOS transistors 12 are turned on and all the bit lines BL are set to the potential lines in order to set all the decoded inverted outputs * Y0 to * Ym-1 to the "H" level. Connected to AGND. At this time, since the potential line ARGND is at the ground potential, all the bit lines BL are in a state where the ground potential is applied. Therefore, the erase voltage 14.5 is applied to the control gates 5 of all the memory cells 7 connected to the word line WL0, and 0 V is applied to the drain 1 and the source 2. In the memory cell 7, since the capacitive coupling between the source 2 and the floating gate 4 is much larger than the capacitive coupling between the control gate 5 and the floating gate 4, the potential of the floating gate 4 at this time is The same as source 2 due to capacitive coupling
V, the potential difference between the control gate 5 and the floating gate 4 becomes 14.5 V, and an FN tunnel current (Fowler-Nordheim Tunnel Current) flows through the tunnel oxide film 6. That is, the floating gate 4
Are extracted from the protrusion of the floating gate 4 to the control gate 5. Thus, the memory cells 7 connected to one word line WL
Are collectively erased. (2) Program Mode (Write Mode) When the program mode signal PG becomes active, the row address decoder 9 selects the word line WL (for example, WL) selected based on the applied row address data RAD.
0), a selection voltage Vgp (for example, 2.0 V) is applied, and other unselected word lines WL1 to WLn−1
Is applied with a ground line pressure of 0V. Further, the row address decoder 9 applies the program voltage Vp (eg, 12.2 V) to the common source line SL0 related to the selected word line WL0.
Supply. On the other hand, the column address decoder 10 connects the bit line BL (for example, BL0) selected based on the column address data CAD to the write / read circuit 11. Therefore, a voltage based on the write data applied to the input / output terminal I / O is applied to the selected bit line BL0. For example, "0" for input / output I / O
Is applied to the bit line BL0, a writable source voltage Vse (0.9 V) is applied to the bit line BL0, and when "1" is applied to the input / output I / O, the bit line BL0 is applied to the bit line BL0. Is the write inhibit source voltage Vsd (4.0 V)
Is applied. Further, the other unselected bit lines BL1
To BLm-1 from the potential line A set to the write inhibit voltage Vsd (4.0 V) by the MOS transistor 12.
Connected to RGND.

Therefore, in the memory cell 7 designated by the word line WL0 and the bit line BL0, when the input / output I / O is "0", 12.2 V is applied to the source 2 and 0.9 V is applied to the drain 1.
V, 2.0 V is applied to the control gate 5. As a result, carriers flow from the drain 1 toward the source 2, but the voltage of the floating gate 4 becomes substantially the same as the potential of the source 2 because of the capacitive coupling between the floating gate 3 and the source 2. Therefore, carriers are injected into the floating gate 4 via the insulating film 3 as hot electrons. On the other hand, in the unselected memory cell 7, since the voltages of the drain 1, the source 2, and the control gate 5 do not satisfy the program condition, no injection into the floating gate 4 is performed. (3) Read Mode When the read mode signal RE becomes active, the row address decoder 9 applies a selection voltage Vgr (4.0 V) to a word line WL (for example, WL0) selected based on the row address data RAD. At the same time, a ground voltage (0 V) is applied to all the common source lines SL. on the other hand,
The column address decoder 10 selects a bit line BL (for example, BL0) selected based on the column address data CAD.
Is connected to the write / read circuit 11. This allows
The data held in the memory cell 7 selected by the word line WL0 and the bit line BL0 is read. On the other hand, the unselected bit lines BL1 to BLm-1 are connected via the MOS transistor 12 to the potential line AGND held at the ground voltage (0 V). Thereby, when the column address changes, the initial state of reading of the other bit lines BL is biased from 0 V by the writing / reading circuit 11, thereby preventing a reading malfunction.

As described above, in each mode, by selectively applying a predetermined voltage to the word line WL, the bit line BL, and the common source line SL, the erase condition, the program condition, and the read condition of the memory cell 7 are satisfied. it can.
In a standby mode other than the above-mentioned modes, MOS
All the transistors 12 are turned on, connected to the potential line AGND set to the ground voltage 0V, and all the bit lines BL are discharged to 0V.

[0010]

In the nonvolatile semiconductor memory shown in FIG. 3, miniaturization has progressed more and more due to advances in semiconductor manufacturing technology, and when the storage capacity has increased to 16 Mbits, 32 Mbits, and even 64 Mbits, the bit line The parasitic capacitance of BL dramatically increases. That is, since the junction capacitance of the drain 1 is connected in parallel to one bit line BL, if the number of connected memory cells 7 is doubled or quadrupled, the parasitic capacitance is also doubled or quadrupled. It is. As a result, the load on the write call circuit 11 increases, and the write time and the read time increase. In addition, bit line B
L is set to the potential line AGND by the MOS transistor 12.
, And the time required for discharging (or precharging) to a predetermined voltage becomes longer. As a result, the operation speed of the non-volatile semiconductor memory is reduced, and the characteristics are deteriorated.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and firstly, a memory in which a plurality of nonvolatile memory cells are arranged on a plurality of word lines and bit lines. In a nonvolatile semiconductor memory including a cell array, a row decoder that selects the word line based on row address data, and a column decoder that selects the bit line based on column address data, the memory cell array includes a plurality of blocks. And a selection switch for selectively connecting any of the bit lines of each block to the column address decoder and a selection switch for connecting to a predetermined potential line, whereby the divided bit lines are selected. Since it is connected to the column address decoder, the capacitive load of the write / read circuit is reduced.

Second, a memory cell array in which a plurality of nonvolatile memory cells are arranged on a plurality of word lines and bit lines, a row decoder for selecting the word line based on row address data, and a column decoder based on column address data A non-volatile semiconductor memory including a column decoder for selecting the bit line, wherein at least a first and a second memory cell array block divided with respect to the row address, and a plurality of memory cells provided in the first memory cell array block. A first bit line, and a plurality of second bit lines provided in the second memory cell array block,
A plurality of main bit lines connected to the column address decoder; the main bit lines, the first bit lines and the second bit lines;
A first selection switch provided between bit lines, and a first and second discharge switch provided between the first and second bit lines and a predetermined potential. is there.

Third, in the second configuration, the first selection switch and the second discharge switch are
The first memory cell array block and the second memory cell array are controlled by the same first control signal, and the second selection switch and the first discharge switch are controlled by the same second control signal. When one of the blocks is connected to the main bit line, the bit line of the other block is connected to the potential line by the same control signal, so that when one block is selected, all the bit lines of the other block are , The discharge state is set, and the next block can be started up immediately when the other block is selected.

[0014]

FIG. 1 shows an embodiment in which a memory cell array is divided into two. In FIG. 1, a row address decoder 9, a column address decoder 10 and a write / read circuit 11 are the same as those in FIG. Since they are almost the same, the description is omitted. The memory cell array includes a first cell array block 13 and a second cell array block 14.
Each of the cell array blocks 13 and 14 has a configuration in which the memory cells 7 are arranged in rows and columns of k × m. In the first cell array block 13, word lines are WL0 to WLk-1, and common source lines are SL0 to SLk / 2-1. In addition, m bit lines BLa0 to BLam-1 are provided, and the main bit lines BL0 to BLm-1 derived from the bit lines BLa0 to BLam-1 and the column address decoder 10 are provided.
Between them, a selection switch controlled by a control signal DCBLa, that is, a MOS transistor 15 is provided. Further, each bit line BLa0 to BLam-1 and a potential line ARG
A selection switch controlled by a control signal DCBLb, that is, a MOS transistor 16 is provided between ND.

On the other hand, in the second cell array block 14, word lines are WLk to WLk-1, and common source lines are SL.
k / 2 to SLn / 2-1. The bit lines are BLb0 to BLb
a selection switch controlled by a control signal DCBLb between m bit lines BLb0 to BLbm-1 and main bit lines BL0 to BLm-1 derived from the column address decoder 10; That is, the MOS transistor 1
7 are provided. Further, a selection switch controlled by a control signal DCBLa, that is, a MOS transistor 18 is provided between each of the bit lines BLb0 to BLbm-1 and the potential line ARGND.

The control signals DCBLa and DCBLb are output from a row address data detection circuit (not shown) according to the contents of the row address data RAD. That is, the control signal DCBLa corresponds to the row address data RAD.
Is a signal that goes to the “H” level when the first cell array block 13 is selected, ie, when the first cell array block 13 is selected.
Lb is a signal that goes to “H” level when the row address data RAD has contents that generate word lines WLk to WLn−1, that is, when the second cell array block 14 is selected. Therefore, the control signal DCBLa becomes “H”.
, The MOS transistors 15 and 18 are turned on, the bit line BLa of the first cell array block 13 is connected to the main bit line BL, and the bit line BLb of the second cell array block 14 is connected to the potential line AGND. . When the control signal DCBLb goes to “H” level, the operation is reversed.

Next, each mode of the embodiment of FIG. 1 will be described. (1) Erasing Mode When the erasing mode signal ES becomes active and the row address data RAD is for selecting the first cell array block 13, the word line WL (for example, WL0) is set to an erasing voltage Ve (for example, WL0). , 14.5V)
The other unselected word lines WL1 to WLn-1 have the ground voltage (0 V), and all the common source lines SL have the ground potential. Further, the column address decoder 10 sets all the decoded inverted outputs * Y0 to * Ym-1 to the "H" level, so that all the MOS transistors 12 are turned on,
All main bit lines BL are connected to potential line AGND. At this time, the potential line AGND is connected to the ground voltage (0 V).
, All the bit lines BL are in a state where 0V is applied.

On the other hand, since the control signal DCBLa is at "H" level and DCBLb is at "0" level, the MOS transistor 15 is turned on, and all the bit lines BLa are
It is connected to the main bit line BL and the potential line AGND is
0 V is applied via the S transistor 12. MOS
Since the transistor 18 is turned on, the bit line BLb of the second cell array block 14 is connected to the potential line AGND and becomes 0V.

Therefore, all the memory cells 7 connected to the word line WL0 are collectively erased. (2) Program Mode (Write Mode) When the program mode signal PG becomes active, the row address decoder 9 selects the word line WL (for example, WL) selected based on the applied row address data RAD.
0), and a ground line pressure of 0 V is applied to other unselected word lines WL1 to WLn-1. Further, the row address decoder 9 supplies the program voltage Vp (eg, 12.2 V) to the common source line SL0 related to the selected word line WL0. On the other hand, the column address decoder 10 writes the bit line BL (for example, BL0) selected based on the column address data CAD to the write / read circuit 1
Connect to 1. Therefore, a voltage based on the write data applied to the input / output terminal I / O is applied to the selected bit line BL0. For example, "0" for input / output I / O
Is applied to the bit line BL0, a writable source voltage Vse (0.9 V) is applied to the bit line BL0, and when "1" is applied to the input / output I / O, the bit line BL0 is applied to the bit line BL0. Is the write inhibit source voltage Vsd (4.0 V)
Is applied. Further, the other unselected bit lines BL1
To BLm-1 from the potential line A set to the write inhibit voltage Vsd (4.0 V) by the MOS transistor 12.
Connected to RGND. At this time, the control signal DCBLa
Is at "H" level and DCBLb is at "L" level, so that the MOS transistors 15 and 18 are turned on, and
The S transistors 16 and 17 are turned off. Therefore, the bit line BLa of the first cell array block 13 is connected to the main bit line BL, and the bit line BLb of the second cell array block 14 is connected to the potential line AGND. Therefore, the bit line BLa0 is connected to the write / read circuit 11 via the main bit line BL0, and the other bit lines BLa1 to BLam-1 are applied with the write inhibit voltage of 4.0 V from the potential line AGND. Further, a write inhibit voltage of 4.0 V is applied to all the bit lines BLb from the potential line AGND via the MOS transistor 18. As a result, writing is performed only on the memory cell 7 selected by the word line WL0 and the bit line BLa0. (3) Read Mode When the read mode signal RE becomes active, the row address decoder 9 applies a selection voltage Vgr (4.0 V) to a word line WL (for example, WL0) selected based on the row address data RAD. At the same time, a ground voltage (0 V) is applied to all the common source lines SL. on the other hand,
The column address decoder 10 selects a bit line BL (for example, BL0) selected based on the column address data CAD.
Is connected to the write / read circuit 11. On the other hand, the unselected bit lines BL1 to BLm-1 are connected to the potential line ARGND held at the ground voltage (0 V) by the MOS transistor 12
Connected via At this time, since the control signal DCBLa is at “H” level and DCBLb is at “L” level,
As in the program mode, the bit line BLa is
Connected to the main bit line BL via the transistor 15;
The bit line BLb is connected to the potential line AGND via the MOS transistor 18 and 0 V is applied. Therefore, the data held in the memory cell 7 selected by the bit line BLa0 and the word line WL0 is read, and the other bit lines BLa1 to BLam-1 are discharged to 0V. In addition, since all the bit lines BLb of the unselected second cell array block 14 are also discharged to 0 V, when the column address changes or the row address changes, the initial state of reading is It is biased from 0 V by the write / read circuit 11 and a read malfunction can be prevented. (4) Standby Mode In the above three modes, the control signals DCBLa and DCBLb are inverted signals, that is, complementary signals. However, in the standby mode, in order to prevent malfunction and quickly rise to the next mode,
It is necessary to discharge all the bit lines of the memory cell array to the ground voltage. Therefore, the control signal DCBLa
, And DCBLb are both at the “H” level, and all the outputs * Y of the column address decoder 10 are also at the “H” level. Thereby, the MOS transistors 12, 1
5, 16, 17, and 18 are all turned on, and the bit line BL
a, BLb, and BL are potential lines ARG set to the ground voltage.
Connected to ND and discharged. In the embodiment shown in FIG. 1, the memory cell array is divided into the first cell array block and the second cell array block. However, the memory cell array is divided into four blocks or six blocks. You may. For example, in the case of dividing into four blocks, third and fourth cell array blocks having the same configuration as the first and second cell array blocks in FIG.
The connection is made via a transistor. In this case, the control signals corresponding to the control signals DCBLa and DCBLb are, for example, DCBLc and DCBLd, which are complementary to each other. Is selected, the control signals DCBLc and DCBLd
Sets the bit line of the third or fourth cell array block to an "L" level in a floating state so as not to be connected to the main bit line. Conversely, the third or fourth
Are selected, control signals DCBLa and DCBLb attain an "L" level.

[0020]

As described above, the bit lines of the divided cell array blocks 13 and 14 are set to the column address decoder 1 only when that block is selected.
Since it is connected to the 0 main bit line, the capacitive load of the write / read circuit 11 is reduced. In addition, since the bit lines of the cell array blocks that are not selected are connected to the potential line AGND by the MOS transistors for discharging, the initial value when the block is selected becomes constant, and malfunction can be prevented. In addition, since the applied voltage condition in each mode can be achieved with a low capacitive load, high-speed operation of the nonvolatile semiconductor memory can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a cell structure of a nonvolatile semiconductor memory.

FIG. 3 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 7 memory cell 8 memory cell array 9 row address decoder 10 column address decoder 11 write / read circuit 12 MOS transistor 13 first cell array block 14 second cell array block 15, 16, 17, 18 MOS transistor

Claims (4)

[Claims] A memory cell array in which a plurality of nonvolatile memory cells are arranged on a plurality of word lines and bit lines; a row decoder for selecting the word line based on row address data; In a nonvolatile semiconductor memory provided with a column decoder for selecting a bit line, the memory cell array is divided into a plurality of blocks, and a selection switch for selectively connecting any one of the bit lines of each block to a column address decoder is provided. A nonvolatile semiconductor memory including a selection switch connected to a potential line. A memory cell array in which a plurality of nonvolatile memory cells are arranged on a plurality of word lines and bit lines; a row decoder for selecting the word line based on row address data; In a nonvolatile semiconductor memory including a column decoder for selecting a bit line, at least a first memory cell array block divided with respect to the row address and a plurality of first memory cell arrays provided in the first memory cell array block. One bit line, a plurality of second bit lines provided in the second memory cell array block, a plurality of main bit lines connected to the column address decoder, the main bit line and the first bit line And first and second selection switches respectively provided between the first and second bit lines, and the first and second selection switches. A non-volatile semiconductor memory comprising first and second discharge switches provided between a bit line and a predetermined potential. 3. The first selection switch and the second discharge switch are controlled by the same first control signal, and the second selection switch and the first discharge switch are controlled by the same second control. 3. The nonvolatile semiconductor memory according to claim 2, wherein the nonvolatile semiconductor memory is controlled by a signal. 4. The nonvolatile semiconductor memory according to claim 3, wherein said first control signal and said second control signal are complementary signals to each other.