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JPH1174307A - Electrode of semiconductor element and method of forming the same - Google Patents

Electrode of semiconductor element and method of forming the same

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Publication number
JPH1174307A
JPH1174307A JP23312797A JP23312797A JPH1174307A JP H1174307 A JPH1174307 A JP H1174307A JP 23312797 A JP23312797 A JP 23312797A JP 23312797 A JP23312797 A JP 23312797A JP H1174307 A JPH1174307 A JP H1174307A
Authority
JP
Japan
Prior art keywords
layer
pure
electrode
film
sputtering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP23312797A
Other languages
Japanese (ja)
Inventor
Seiji Nishimura
誠司 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
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Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP23312797A priority Critical patent/JPH1174307A/en
Publication of JPH1174307A publication Critical patent/JPH1174307A/en
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0103Zinc [Zn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10329Gallium arsenide [GaAs]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【課題】 高いパターン認識性と強固なボンダビリティ
の両立を実現する半導体素子における電極及びその形成
方法を提供する。 【解決手段】 半導体素子の電極を、N2が混入された
Al膜からなるパターン認識補助層4の上に純Al又は
純Alに近い材料からなる第2のAl層5を形成した多
層ボンディングパッド層を有する構成とする。この電極
は、Arガスに対してN2ガスを混入させたスパッタリ
ングガスを用いて、第1のAl膜をスパッタリングする
工程と、Arガスのみからなるスパッタリングガスを用
いて、この第1のAl膜の上に純Al又は純Alに近い
材料からなる第2のAl膜をスパッタリングする工程と
を経て、作製することが可能となる。
(57) [Problem] To provide an electrode in a semiconductor device and a method for forming the same, which realize both high pattern recognition and strong bondability. SOLUTION: A multi-layer bonding pad in which a second Al layer 5 made of pure Al or a material close to pure Al is formed on a pattern recognition auxiliary layer 4 made of an Al film mixed with N 2 is formed as an electrode of a semiconductor element. It has a structure having a layer. This electrode is formed by a step of sputtering a first Al film using a sputtering gas in which an N 2 gas is mixed with an Ar gas, and a step of sputtering the first Al film using a sputtering gas consisting only of an Ar gas. And a step of sputtering a second Al film made of pure Al or a material close to pure Al thereon.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子におけ
る電極構造に関し、より詳しくは半導体レーザ、発光ダ
イオード等の化合物半導体発光素子の電極及びその形成
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode structure in a semiconductor device, and more particularly to an electrode of a compound semiconductor light emitting device such as a semiconductor laser and a light emitting diode and a method of forming the same.

【0002】[0002]

【従来の技術】図3は、一般的な化合物半導体における
ワイヤーボンディング側電極の基本構造を示す。この電
極は、ウェハ6上に結晶と電極間の抵抗を下げるオーミ
ック層1、ボンディングパッド層ヘのGa、Zn等の拡
散を抑止するバリア層2及びワイヤーボンディング時に
ワイヤーをチップ上に融着するボンディングパッド層3
が順に積層された構造からなる。
2. Description of the Related Art FIG. 3 shows a basic structure of a wire bonding side electrode in a general compound semiconductor. This electrode includes an ohmic layer 1 for lowering the resistance between the crystal and the electrode on the wafer 6, a barrier layer 2 for suppressing the diffusion of Ga, Zn, etc. to the bonding pad layer, and a bonding for fusing wires onto the chip during wire bonding. Pad layer 3
Are sequentially laminated.

【0003】図4は、ワイヤーボンディング時のチップ
のパターン認識方法の一例を示しており、チップのパタ
ーン認識は、光投射器7によりチップ8の斜め上方から
光L1を投射し、その際に電極パターンによって反射さ
れる反射光L2を受光素子9で受光することによって行
われる。ボンディングパッドのパターン認識性を向上さ
せるには、鏡面である結晶表面に対して、投射光を乱反
射させるために電極表面を微細な粗面状態とするのが望
ましい。
FIG. 4 shows an example of a method of recognizing a chip pattern during wire bonding. In recognizing a chip pattern, light L1 is projected from obliquely above a chip 8 by a light projector 7, and an electrode is used at that time. This is performed by receiving the reflected light L2 reflected by the pattern by the light receiving element 9. In order to improve the pattern recognizability of the bonding pad, it is desirable that the electrode surface be in a fine rough state in order to irregularly reflect the projection light on the crystal surface which is a mirror surface.

【0004】粗面化処理は、スパッタリング装置にて成
膜したAl面を希フッ酸で表面エッチングして行う。エ
ッチングはAl粒界面に沿って進み、デンドライト状に
粗面化されたAl表面が現れる。このように、ボンディ
ングパッドのパターン認識性を向上させるために、Al
表面を薬液にてエッチングして粗面化し、ワイヤーボン
ディング時にチップに光を投射した際の電極からの乱反
射を大きくし、結晶表面との二値化を容易にする方法を
とっている。
The surface roughening treatment is performed by etching the Al surface formed by a sputtering apparatus with dilute hydrofluoric acid. The etching proceeds along the Al grain interface, and the Al surface roughened like a dendrite appears. Thus, in order to improve the pattern recognition of the bonding pad,
The surface is etched with a chemical solution to roughen the surface, irregular reflection from the electrode when light is projected onto the chip during wire bonding is increased, and binarization with the crystal surface is facilitated.

【0005】Al膜はスパッタリング条件によってAl
膜の結晶粒界の大きさに変化を与えることができる。一
般にボンディングパッドとしてAlスパッタリングを行
う場合は、スパッタリング室を一旦高真空状態(1×1
-7torr)にし、続いてArガス(1×10-3torr)を
封入する。ArガスはAlターゲットに印加した負電圧
によってAr+イオンになりAlターゲットヘ加速衝突
する。衝突したAr+イオンによってAlターゲットか
ら非弾性衝突によりAlを基板に形成する。Al膜の結
晶粒界の大きさに変化を与える最も有効的な手段とし
て、Arガスに対してN2ガスを3%〜4%以上混入す
ることがあげられ、これにより粗面化処理後、デンドラ
イト状に見られるAl結晶粒界が約10μm程度から1
μm〜2μmまで小さくなる。
[0005] The Al film is made of Al depending on sputtering conditions.
The size of the grain boundary of the film can be varied. Generally, when Al sputtering is performed as a bonding pad, the sputtering chamber is once in a high vacuum state (1 × 1).
0 -7 torr), and then Ar gas (1 × 10 -3 torr) is sealed. The Ar gas is converted into Ar + ions by a negative voltage applied to the Al target and accelerates and collides with the Al target. Al is formed on the substrate by inelastic collision from the Al target by the colliding Ar + ions. The most effective means for changing the size of the crystal grain boundary of the Al film is to mix N 2 gas at 3% to 4% or more with Ar gas. The dendrite-like Al grain boundary is about 10 μm to 1
It becomes smaller from μm to 2 μm.

【0006】図5にボンディングパッド層の粒界サイズ
の変化の様子をモデルで示しており、(a)にオーミッ
ク層1、バリア層2及び純Alによるボンディングパッ
ド層3が順に積層された場合を、(b)にオーミック層
1、バリア層2及びN2混入Alによるボンディングパ
ッド層3’が順に積層された場合をそれぞれ示す。図5
に示すように、粒界面に沿ってエッチングが進む粗面化
処理において、ボンディングパッド層がN2混入Alに
よる場合には、純Alによる場合と比較して表面状態が
より微細なデンドライト形状をもつAl表面を実現で
き、パターン認識性が向上する。
FIG. 5 shows a model of a change in the grain boundary size of the bonding pad layer. FIG. 5A shows a case where an ohmic layer 1, a barrier layer 2 and a bonding pad layer 3 made of pure Al are sequentially stacked. (B) shows a case where an ohmic layer 1, a barrier layer 2 and a bonding pad layer 3 'made of Al mixed with N 2 are sequentially stacked. FIG.
As shown, in the roughening process proceeds etching along the grain boundary, if the bonding pad layer due to N 2 mixed Al, the surface state as compared with the case of pure Al has a finer dendrite shape The Al surface can be realized, and the pattern recognizability is improved.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、上記の
ようにボンディングパッド層をN2混入Alにより形成
する場合には、純Alにより形成する場合に比較して、
その硬度が増しAuワイヤーが融着せずボンダビリティ
を著しく損なってしまう。
However, when the bonding pad layer is formed of Al mixed with N 2 as described above, as compared with the case where the bonding pad layer is formed of pure Al.
The hardness is increased, and the Au wire does not fuse and the bondability is significantly impaired.

【0008】図6にArガスに対するN2混入比を変化
させた場合のボンディングパッド層のデンドライト形状
の粒界サイズの変化の様子を組織写真で示しており、
(a)はN2混入比0%の場合を、(b)はN2混入比
1.3%の場合を、(c)はN2混入比3.3%の場合
をそれぞれ示す。
FIG. 6 is a structural photograph showing how the dendrite-shaped grain boundary size of the bonding pad layer changes when the N 2 mixing ratio with respect to the Ar gas is changed.
(A) shows the case where the N 2 mixing ratio is 0%, (b) shows the case where the N 2 mixing ratio is 1.3%, and (c) shows the case where the N 2 mixing ratio is 3.3%.

【0009】図7に、N2混入比とワイヤーボンディン
グでボンディングが可能であったチップ数との関係を示
す。ここで、Al表面形状に大きく変化が現れるのは図
6(c)のN2混入比を3.3%以上とした場合である
が、ボンダビリティ及びボール押し強度は図7に示した
ようにN2混入比1.3%からすでにかなりの低下が認
められる。
FIG. 7 shows the relationship between the N 2 mixing ratio and the number of chips that could be bonded by wire bonding. Here, a large change in the Al surface shape appears when the N 2 mixing ratio in FIG. 6C is set to 3.3% or more, but the bondability and the ball pressing strength are as shown in FIG. Already a considerable decrease is observed from the N 2 mixing ratio of 1.3%.

【0010】上記のように、Al粒界をより小さくする
パラメーターとしてスパッタリングガスヘのN2混入が
あげられが、ボンディングパッド層をN2混入Alによ
り形成する場合には、パターン認識性とボンダビリティ
は相反する関係となる。即ち、ボンディングパッド層の
2混入比を上げればAl粒界は小さくなり、パターン
認識に優れた膜になるが、ボンダビリティが低下してし
まう。逆に純度の高いAl膜のボンディングパッド層と
した場合には、ボンディングは強固となるが、パターン
認識に適さない膜となる。
[0010] As described above, the parameter for making the Al grain boundary smaller is N 2 mixed into the sputtering gas. However, when the bonding pad layer is formed of Al mixed with N 2 , the pattern recognizability and bondability can be improved. Is a conflicting relationship. That is, if the N 2 mixing ratio of the bonding pad layer is increased, the Al grain boundaries become smaller, and the film becomes excellent in pattern recognition, but the bondability is reduced. Conversely, when the bonding pad layer is made of a high-purity Al film, the bonding becomes strong, but the film is not suitable for pattern recognition.

【0011】本発明は、こうした従来技術の課題を解決
するものであり、高いパターン認識性と強固なボンダビ
リティの両立を実現できる半導体素子における電極及び
その形成方法を提供することを目的とする。
An object of the present invention is to solve such problems of the prior art, and an object of the present invention is to provide an electrode in a semiconductor device capable of realizing both high pattern recognizability and strong bondability, and a method of forming the same.

【0012】[0012]

【課題を解決するための手段】本発明の半導体素子の電
極は、N2が混入されたAl膜からなるパターン認識補
助層の上に、純Al又は純Alに近い材料からなる第2
のAl層を形成した多層ボンディングパッド層を有して
なり、そのことにより上記目的が達成される。
An electrode of a semiconductor device according to the present invention comprises a second layer made of pure Al or a material close to pure Al on a pattern recognition auxiliary layer made of an Al film mixed with N 2.
And a multi-layer bonding pad layer having an Al layer formed thereon, thereby achieving the above object.

【0013】好ましくは、前記パターン認識補助層の膜
厚を900nmとし、前記第2のAl層の膜厚を300
nmとする。
Preferably, the thickness of the pattern recognition auxiliary layer is 900 nm, and the thickness of the second Al layer is 300 nm.
nm.

【0014】本発明の半導体素子の電極の形成方法は、
Arガスに対してN2ガスを混入させたスパッタリング
ガスを用いて、第1のAl膜をスパッタリングする工程
と、Arガスのみからなるスパッタリングガスを用い
て、該第1のAl膜の上に純Al又は純Alに近い材料
からなる第2のAl膜をスパッタリングする工程とを包
含してなり、そのことにより上記目的が達成される。
The method for forming an electrode of a semiconductor device according to the present invention comprises:
A step of sputtering the first Al film using a sputtering gas in which an N 2 gas is mixed with an Ar gas, and a step of purely forming a pure gas on the first Al film using a sputtering gas consisting of only an Ar gas. And a step of sputtering a second Al film made of a material close to Al or pure Al, whereby the object is achieved.

【0015】以下に、本発明の作用について説明する。The operation of the present invention will be described below.

【0016】上記のように、本発明は、半導体素子の電
極を構成する多層ボンディングパッド層を、N2が混入
されたAl膜からなるパターン認識補助層の上に純Al
又は純Alに近い材料からなる第2のAl層を形成する
構成をとる。このため、パターン認識補助層はN2混入
Al膜からなるので粒界サイズは縮小され、その上に形
成される第2のAl層はパターン認識補助層で縮小され
た粒界サイズを引き継ぎながら堆積される。その結果、
この第2のAl層は純Al又は純Alに近い材料であり
ながら、粗面化処理後、微細なデンドライト形状をもつ
表面状態となり、パターン認識性が向上する。しかも、
この第2のAl層は純Al又は純Alに近い材料からな
るので、Auワイヤーが融着し易くボンダビリティが向
上する。
As described above, according to the present invention, a multi-layer bonding pad layer constituting an electrode of a semiconductor element is formed by depositing pure Al on a pattern recognition auxiliary layer comprising an Al film mixed with N 2.
Alternatively, a configuration is employed in which a second Al layer made of a material close to pure Al is formed. For this reason, since the pattern recognition auxiliary layer is made of the N 2 mixed Al film, the grain boundary size is reduced, and the second Al layer formed thereon is deposited while inheriting the grain boundary size reduced by the pattern recognition auxiliary layer. Is done. as a result,
Although the second Al layer is made of pure Al or a material close to pure Al, it has a surface state having a fine dendrite shape after the surface roughening treatment, and the pattern recognizability is improved. Moreover,
Since the second Al layer is made of pure Al or a material close to pure Al, the Au wire is easily fused and the bondability is improved.

【0017】特に、上記パターン認識補助層の膜厚を9
00nmとし、上記第2のAl層の膜厚を300nmと
した場合には、ボンダビリティ及びパターン認識性に優
れた電極となる。
In particular, the thickness of the pattern recognition auxiliary layer is set to 9
When the thickness is set to 00 nm and the thickness of the second Al layer is set to 300 nm, the electrode is excellent in bondability and pattern recognition.

【0018】また、上記の半導体素子の電極の形成方法
によれば、上記利点を有する電極を確実に作製すること
が可能となる。
Further, according to the above-described method for forming an electrode of a semiconductor element, it is possible to reliably manufacture an electrode having the above advantages.

【0019】[0019]

【発明の実施の形態】以下に、本発明の実施の形態を図
面に基づき具体的に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the drawings.

【0020】図1に本発明の半導体素子の電極構造を示
す。
FIG. 1 shows an electrode structure of a semiconductor device according to the present invention.

【0021】この電極は、ウェハ6上に結晶と電極間の
抵抗を下げるオーミック層1、ボンディングパッド層ヘ
のGa、Zn等の拡散を抑止するバリア層2、N2が混
入されたAl膜からなるパターン認識補助層4及び純A
l又は純Alに近い材料からなるボンディングパッド層
5をこの順に積層した多層構造からなる。
The electrodes are formed on the wafer 6 from an ohmic layer 1 for lowering the resistance between the crystal and the electrode, a barrier layer 2 for suppressing the diffusion of Ga, Zn and the like to the bonding pad layer, and an Al film mixed with N 2. Pattern recognition auxiliary layer 4 and pure A
1 or a multilayer structure in which bonding pad layers 5 made of a material close to pure Al are stacked in this order.

【0022】次に、上記多層構造からなる電極の形成方
法を説明する。
Next, a method for forming an electrode having the above-mentioned multilayer structure will be described.

【0023】マルチチャンバー型スパッタリング装置の
成膜室に、オーミック層1としてAgZn蒸着が施され
たGaAsウェハ6を導入して、Ti/Alスパッタリ
ングを行う。Tiスパッタリング工程で、ウェハ6のオ
ーミック層1上にバリア層2を形成する。
A GaAs wafer 6 on which AgZn is deposited is introduced as an ohmic layer 1 into a film forming chamber of a multi-chamber type sputtering apparatus, and Ti / Al sputtering is performed. The barrier layer 2 is formed on the ohmic layer 1 of the wafer 6 by a Ti sputtering process.

【0024】続くAlスパッタリング工程では、Arガ
スに対してN2ガスを5%混入させたスパッタリングガ
スを用いて、バリア層2の上に、N2が混入されたAl
膜からなるパターン認識補助層4を形成する。次に、A
rガスのみからなるスパッタリングガスを用いて、この
パターン認識補助層4の上に純Alからなるボンディン
グパッド層5を形成する。
In the subsequent Al sputtering process, a sputtering gas in which N 2 gas is mixed at 5% with respect to Ar gas is used to deposit N 2 mixed Al on the barrier layer 2.
A pattern recognition auxiliary layer 4 made of a film is formed. Next, A
A bonding pad layer 5 made of pure Al is formed on the pattern recognition auxiliary layer 4 using a sputtering gas consisting of only r gas.

【0025】下記の表1に上記のAlスパッタリングの
条件を示す。
Table 1 below shows the conditions of the above Al sputtering.

【0026】[0026]

【表1】 [Table 1]

【0027】以上の工程を経て、本発明の半導体素子の
電極が作製される。
Through the above steps, the electrode of the semiconductor device of the present invention is manufactured.

【0028】次に、Arガスに対するN2混入比を5%
としたスパッタリングガスを用いてスパッタリングを行
い、パターン認識補助層であるN2混入Al層の膜厚を
600nm〜1350nmまで変化させた場合のボンデ
ィングパッド層である純Al層の表面の観察結果につい
て説明する。図2はそのときの純Al層の粒界サイズの
変化の様子を組織写真で示すものであり、(a)はN2
混入Al層の膜厚600nm、純Al層の膜厚300n
mの場合を、(b)はN2混入Al層の膜厚900n
m、純Al層の膜厚300nmの場合を、(c)はN2
混入Al層の膜厚1200nm、純Al層の膜厚を30
0nmの場合を、(d)はN2混入Al層の膜厚135
0nm、純Al層の膜厚300nmの場合をそれぞれ示
す。
Next, the N 2 mixing ratio with respect to the Ar gas is set to 5%.
Of the surface of the pure Al layer as the bonding pad layer when the film thickness of the N 2 mixed Al layer as the pattern recognition auxiliary layer was changed from 600 nm to 1350 nm by performing sputtering using the sputtering gas set as above. I do. Figure 2 shows the manner of change of the grain boundary size of the pure Al layer when the organization photograph, (a) represents N 2
600 nm thickness of mixed Al layer, 300 n thickness of pure Al layer
(b) is a film thickness of 900 n of the Al layer mixed with N 2.
m, in the case of thickness 300nm of pure Al layer, (c) is N 2
The thickness of the mixed Al layer is 1200 nm and the thickness of the pure Al layer is 30
In the case of 0 nm, (d) shows the thickness 135 of the N 2 mixed Al layer.
0 nm and a case where the thickness of the pure Al layer is 300 nm are shown.

【0029】その結果、図2に示すように、粗面化処理
後に見られるAl表面のデンドライト形状が、N2混入
Al層の膜厚が厚くなるに従い、小さくなっていくのが
わかる。これは、図1にモデルで示しているように、N
2混入Al膜の上に純Al層を形成すると、純Al層は
純AlでありながらN2混入Al層の縮小された粒界サ
イズが引き継がれて堆積されるためである。従って、純
Al層は粗面化処理後、微細なデンドライト形状をもつ
表面状態となり、パターン認識性が向上する。しかも、
純AlからなるのでAuワイヤーが融着し易くボンダビ
リティも向上する。
As a result, as shown in FIG. 2, it can be seen that the dendrite shape on the Al surface observed after the surface roughening treatment becomes smaller as the film thickness of the N 2 -containing Al layer increases. This is, as shown by the model in FIG.
When forming a pure Al layer on the 2 mixed Al film, a pure Al layer is for reduced intergranular size of N 2 mixed Al layer yet pure Al is deposited taken over. Therefore, the pure Al layer becomes a surface state having a fine dendrite shape after the surface roughening treatment, and the pattern recognizability is improved. Moreover,
Since it is made of pure Al, the Au wire is easily fused and the bondability is improved.

【0030】特に、図2(b)のN2混入Al層の膜厚
を900nm、純Al層の膜厚を300nmとした場合
に、パターン認識性及びボンダビリティに優れたボンデ
ィングパッド層が実現できた。尚、ボンダビリテイは純
Al層の膜厚を300nm以上とすれば確保されること
が実験で確認されている。
In particular, when the thickness of the N 2 -containing Al layer is 900 nm and the thickness of the pure Al layer is 300 nm in FIG. 2B, a bonding pad layer excellent in pattern recognition and bondability can be realized. Was. It has been confirmed by experiments that bondability is ensured when the thickness of the pure Al layer is 300 nm or more.

【0031】上記の実施例ではスパッタリング装置をマ
ルチチャンバー型を用いたが、コンパクトチャンバー型
としても良い。
In the above embodiment, a multi-chamber type sputtering apparatus is used, but a compact chamber type sputtering apparatus may be used.

【0032】[0032]

【発明の効果】上記本発明によれば、多層ボンディング
パッド層を、N2が混入されたAl膜からなるパターン
認識補助層の上に純Al又は純Alに近い材料からなる
第2のAl層を形成する構成をとるので、この第2のA
l層はパターン認識補助層で縮小された粒界サイズを引
き継ぎながら堆積される。その結果、この第2のAl層
は純Al又は純Alに近い材料でありながら、粗面化処
理後、微細なデンドライト形状をもつ表面状態となるの
で、パターン認識性を向上することができる。しかも、
第2のAl層は純Al又は純Alに近い材料からなるの
で、ボンダビリティも向上することができる。
According to the present invention, the multi-layer bonding pad layer is formed by forming the second Al layer made of pure Al or a material close to pure Al on the pattern recognition auxiliary layer made of the Al film mixed with N 2. , The second A
The l layer is deposited while inheriting the grain boundary size reduced by the pattern recognition auxiliary layer. As a result, although the second Al layer is made of pure Al or a material close to pure Al, the second Al layer has a surface state having a fine dendrite shape after the surface roughening treatment, so that the pattern recognizability can be improved. Moreover,
Since the second Al layer is made of pure Al or a material close to pure Al, bondability can be improved.

【0033】また、特に、請求項2記載の半導体素子の
電極によれば、パターン認識補助層の膜厚を900nm
とし、第2のAl層の膜厚を300nmとしているの
で、ボンダビリティ及びパターン認識性に優れた電極と
することができる。
According to the second aspect of the present invention, the pattern recognition auxiliary layer has a thickness of 900 nm.
Since the thickness of the second Al layer is 300 nm, an electrode having excellent bondability and pattern recognizability can be obtained.

【0034】また、請求項3記載の半導体素子の電極の
形成方法によれば、上記利点を有する電極を確実に作製
することができる。
Further, according to the method for forming an electrode of a semiconductor device according to the third aspect, an electrode having the above advantages can be reliably manufactured.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体素子の電極構造を示す図であ
る。
FIG. 1 is a diagram showing an electrode structure of a semiconductor device of the present invention.

【図2】本発明の多層ボンディングパッド層におけるN
2混入Al層の膜厚を変化させた場合の純Al層の粒界
サイズの変化の様子を示す組織写真であり、(a)はN
2混入Al層の膜厚600nm、純Al層の膜厚300
nmの場合を、(b)はN2混入Al層の膜厚900n
m、純Al層の膜厚300nmの場合を、(c)はN2
混入Al層の膜厚1200nm、純Al層の膜厚300
nmの場合を、(d)はN2混入Al層の膜厚1350
nm、純Al層の膜厚300nmの場合をそれぞれ示
す。
FIG. 2 shows N in a multilayer bonding pad layer of the present invention.
2 is a structural photograph showing a change in the grain boundary size of the pure Al layer when the thickness of the mixed Al layer is changed, and FIG.
(2) 600 nm thickness of mixed Al layer, 300 thickness of pure Al layer
(b) is a 900 nm film thickness of the N 2 mixed Al layer.
m, in the case of thickness 300nm of pure Al layer, (c) is N 2
The thickness of the mixed Al layer is 1200 nm, and the thickness of the pure Al layer is 300
(d) is a film thickness of 1350 of the N 2 mixed Al layer.
nm, and a case where the thickness of the pure Al layer is 300 nm.

【図3】一般的な化合物半導体におけるワイヤーボンデ
ィング側の電極構造を示す図である。
FIG. 3 is a diagram showing an electrode structure on a wire bonding side in a general compound semiconductor.

【図4】ワイヤーボンディング時のチップのパターン認
識方法の一例を示す図である。
FIG. 4 is a diagram illustrating an example of a chip pattern recognition method during wire bonding.

【図5】従来のボンディングパッド層における純Al層
とN2混入Al層の粒界サイズの変化の様子を示すモデ
ルである。
FIG. 5 is a model showing how a grain boundary size of a pure Al layer and an N 2 mixed Al layer in a conventional bonding pad layer changes.

【図6】従来のボンディングパッド層におけるN2混入
比を変化させた場合のデンドライト形状の粒界サイズの
変化の様子を示す組織写真であり、(a)はN2混入比
0%の場合を、(b)はN2混入比1.3%の場合を、
(c)はN2混入比3.3%の場合をそれぞれ示す。
FIG. 6 is a structural photograph showing a state of a change in the grain boundary size of the dendrite shape when the N 2 mixing ratio in the conventional bonding pad layer is changed, and (a) shows a case where the N 2 mixing ratio is 0%. , (B) shows the case where the N 2 mixing ratio is 1.3%,
(C) shows the case where the N 2 mixing ratio is 3.3%.

【図7】N2混入比とボンディング可能なチップ数との
関係を示す図である。
FIG. 7 is a diagram showing the relationship between the N 2 mixing ratio and the number of chips that can be bonded;

【符号の説明】[Explanation of symbols]

1 オーミック層 2 バリア層 3、3’、5 ボンディングパッド層 4 パターン認識補助層 6 ウェハ DESCRIPTION OF SYMBOLS 1 Ohmic layer 2 Barrier layer 3, 3 ', 5 Bonding pad layer 4 Pattern recognition auxiliary layer 6 Wafer

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 N2が混入されたAl膜からなるパター
ン認識補助層の上に純Al又は純Alに近い材料からな
る第2のAl層を形成した多層ボンディングパッド層を
有する半導体素子の電極。
1. An electrode of a semiconductor element having a multilayer bonding pad layer in which a second Al layer made of pure Al or a material close to pure Al is formed on a pattern recognition auxiliary layer made of an Al film mixed with N 2. .
【請求項2】 前記パターン認識補助層の膜厚が900
nmであり、 前記第2のAl層の膜厚が300nmである請求項1記
載の半導体素子の電極。
2. The method according to claim 1, wherein the thickness of the pattern recognition auxiliary layer is 900.
2. The electrode according to claim 1, wherein the thickness of the second Al layer is 300 nm. 3.
【請求項3】 Arガスに対してN2ガスを混入させた
スパッタリングガスを用いて、第1のAl膜をスパッタ
リングする工程と、 Arガスのみからなるスパッタリングガスを用いて、該
第1のAl膜の上に純Al又は純Alに近い材料からな
る第2のAl膜をスパッタリングする工程とを包含する
半導体素子の電極の形成方法。
3. A step of sputtering a first Al film using a sputtering gas in which an N 2 gas is mixed with an Ar gas, and a step of sputtering the first Al film using a sputtering gas comprising only an Ar gas. Sputtering a second Al film made of pure Al or a material close to pure Al on the film.
JP23312797A 1997-08-28 1997-08-28 Electrode of semiconductor element and method of forming the same Withdrawn JPH1174307A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23312797A JPH1174307A (en) 1997-08-28 1997-08-28 Electrode of semiconductor element and method of forming the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23312797A JPH1174307A (en) 1997-08-28 1997-08-28 Electrode of semiconductor element and method of forming the same

Publications (1)

Publication Number Publication Date
JPH1174307A true JPH1174307A (en) 1999-03-16

Family

ID=16950178

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23312797A Withdrawn JPH1174307A (en) 1997-08-28 1997-08-28 Electrode of semiconductor element and method of forming the same

Country Status (1)

Country Link
JP (1) JPH1174307A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9861035B2 (en) 2015-05-01 2018-01-09 Deere & Company Height of cut control system
JP2018197631A (en) * 2017-05-24 2018-12-13 大日本印刷株式会社 Vapor chamber, metal sheet for vapor chamber, and vapor chamber manufacturing method
JP2023172020A (en) * 2022-05-23 2023-12-06 ルネサスエレクトロニクス株式会社 Semiconductor device and semiconductor device manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9861035B2 (en) 2015-05-01 2018-01-09 Deere & Company Height of cut control system
JP2018197631A (en) * 2017-05-24 2018-12-13 大日本印刷株式会社 Vapor chamber, metal sheet for vapor chamber, and vapor chamber manufacturing method
JP2023172020A (en) * 2022-05-23 2023-12-06 ルネサスエレクトロニクス株式会社 Semiconductor device and semiconductor device manufacturing method

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