JPS5858757A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5858757A JPS5858757A JP56158395A JP15839581A JPS5858757A JP S5858757 A JPS5858757 A JP S5858757A JP 56158395 A JP56158395 A JP 56158395A JP 15839581 A JP15839581 A JP 15839581A JP S5858757 A JPS5858757 A JP S5858757A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- platinum
- impurity
- internal wiring
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05669—Platinum [Pt] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置に関し、特にショットキー接合を有
する半導体装置の耐湿性を同上する構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a structure that improves the moisture resistance of a semiconductor device having a Schottky junction.
一般に、半導体装置は水分等の影響を受は故障しやすい
ため半導体素子表向に絶縁保賎膜が形成されている。ま
た、半導体装置では半導体素子と外部端子とをワイヤ等
の内部リードで電気的に接続しており、そのため半導体
素子表向に電極を設ける必要がある。In general, since semiconductor devices are susceptible to failure due to the influence of moisture, etc., an insulating protective film is formed on the surface of the semiconductor element. Further, in a semiconductor device, a semiconductor element and an external terminal are electrically connected by an internal lead such as a wire, and therefore it is necessary to provide an electrode on the surface of the semiconductor element.
従米の半導体装置では、上記電極はアルミニウムで形成
されている例が多く、外部から侵入した水分等によりア
ルミニウム電極及び該電極に接続するアルミニウム配線
が腐賞されるという欠点がおる。In conventional semiconductor devices, the electrodes are often made of aluminum, which has the disadvantage that the aluminum electrodes and the aluminum wiring connected to the electrodes are corroded by moisture entering from the outside.
第１図は従来の半導体装置の一例の断（３）図である。FIG. 1 is a cross-sectional view (3) of an example of a conventional semiconductor device.
半導体基板１０に杷縁腺１１を設けて開口し。A loquat gland 11 is provided on a semiconductor substrate 10 and opened.
拡散／１１２を形成する。この拡散層１２の所望部分に
白金珪化物層１４を形成し、ショット接合又はオーミッ
ク接合を得る。しかる後、スパッタ法るるいは蒸着法等
により全表面をアルミニウムで槍い、Ｐ）ｒ望部分を残
す選択エツチングを行って所望のアルミニウム配線１５
及び電極１６を得る。Diffusion/112 is formed. A platinum silicide layer 14 is formed on a desired portion of this diffusion layer 12 to obtain a shot bond or an ohmic bond. After that, the entire surface is coated with aluminum by sputtering, vapor deposition, etc., and selective etching is performed to leave the desired portions to form the desired aluminum wiring 15.
and electrode 16 is obtained.
爽に全表面を絶縁＠１７で機い、１４Ｌ極１６の所のみ
を選択エツチングして電極１６を蕗出させ内部リード１
ｇを取付ける。Insulate the entire surface with insulation@17, selectively etch only the 14L pole 16, expose the electrode 16, and install the internal lead 1.
Install g.
上記のように、半導体装置の電悦１６はアルミニウムで
形成されているため水分尋により腐食されやすい。ま九
、電極１６に接続するアルミニウム配−１５は電極１６
上の絶縁膜１７の段差部の界面から侵入した水分等によ
り容易に腐食されるという欠点がある。As mentioned above, since the electric conductor 16 of the semiconductor device is made of aluminum, it is easily corroded by moisture. Nine, the aluminum wiring 15 connected to the electrode 16
There is a drawback that it is easily corroded by moisture or the like that enters from the interface of the stepped portion of the upper insulating film 17.
このような腐食はアルミニウムだけでなく、多結晶シリ
コンやモリブデンを用いた場合も起る。Such corrosion occurs not only with aluminum but also with polycrystalline silicon and molybdenum.
また、腐食さｎる場所も電極だけに限らず内部配線にも
起る。これらの腐食が進行すると、内部配線の断−を引
起し、動作不能となるので、内部配線の腐食は信頼性を
低下させるという欠点がありた。Furthermore, corrosion occurs not only in electrodes but also in internal wiring. When this corrosion progresses, the internal wiring becomes disconnected and becomes inoperable, so the corrosion of the internal wiring has the disadvantage of lowering reliability.
本％明は上記欠点を除き、内部配−及び電極が腐食され
にくい構造を有し、信頼性を向上させたを
半導体装置る提供するものでろる。The present invention provides a semiconductor device which eliminates the above-mentioned drawbacks, has a structure in which internal wiring and electrodes are not easily corroded, and has improved reliability.
本兄明の手４体装ぼけ、半導体基板に設けられた素子領
域の不純物尋人層と、前ｉピ不純物導入層と間隔をおい
て設けられた接続用不純物導入層と。The present inventor's four-body arrangement includes an impurity layer in an element region provided on a semiconductor substrate, and a connecting impurity doped layer provided at a distance from the previous i-pi impurity doped layer.
一端が前記素子領域の不純物導入Ｉ−に接続し他端が前
記接続用不純物導入層の一部に接続する内部ｂｃ巌と、
前記接続用不純物導入層の前記内部配線接秋部？ｆ−除
く六面の一部に設けられた白金族元素の珪化物Ｊ−と、
前記内部配線を芋面的に覆いかつ前ｍｌ珪化物ノー以外
の接続用不純物導入層表面を少くとも積う絶縁保護腺と
を含んで１肇成される。an internal bc cave whose one end is connected to the impurity doped I- of the element region and whose other end is connected to a part of the connection impurity doped layer;
The internal wiring connection part of the connection impurity introduction layer? silicide J- of a platinum group element provided on a part of the six faces excluding f-;
It is made up of one piece, including an insulating protection layer that covers the internal wiring and deposits at least the surface of a connecting impurity layer other than silicide.
本９６明の実施例について図面を用いて説明する。An embodiment of the present invention will be described with reference to the drawings.
第２図を工杢兄明の一釆施９＋１の断四図である。Figure 2 is a four-section diagram of one pottery 9 + 1 by Ken Moku.
半導体基板２０に絶縁膜２１を設けて開口し。An insulating film 21 is provided on a semiconductor substrate 20 and an opening is formed.
系子埃域の不純ｖＩ尋人１−２２と接続用不純物導入増
２３とを形成する。口金族元累のうちの一つ。The impurity vI human being 1-22 in the system dust area and the connection impurity introduction increase 23 are formed. One of the original clan members.
例えば１蛍を蒸盾し、選択エツチングして接続用不＋ｆ
ｔＢ物導入１１２の所墓饋城に白金層１ｈ−ｒ、 もし
系子穎域にショットキ接合累子全含むならはその穎填に
も白金を沃す。以下の説明は素子領域にショットキ接合
素子を含むものとし、そ九が不純物導入層２２に形成さ
れるものとして説明する。白金層を形成した後、熱処理
して白金珪化物層２４Ｍ＋２４ｂ＊２４ｃｔ−形成する
。ここで白金珪化物ノー２４８と２４ｂとは間隔をおい
ておくことが必要である。For example, evaporate one firefly, selectively etch it, and use +f for connection.
A platinum layer 1 hour is added to the tomb of tB material introduction 112, and if the glume region of the system contains all the Schottky junctions, the glume is also impregnated with platinum. The following description will be made on the assumption that the element region includes a Schottky junction element, and that the Schottky junction element is formed in the impurity-introduced layer 22. After forming the platinum layer, heat treatment is performed to form a platinum silicide layer 24M+24b*24ct-. Here, it is necessary to leave a space between the platinum silicide layers 248 and 24b.
次に、アルミニロム等で内部ｇｋＭ２５ｅ形成し。Next, form the internal gkM25e with aluminum ROM etc.
白金珪化物層２４ｂと２４Ｃとを接続する。次に。Connect platinum silicide layers 24b and 24C. next.
全表面を絶縁保賎膜２７で覆い５口金珪化物１−２４ａ
の部分を開口し、内部リード２８を取付ける。The entire surface is covered with an insulating film 27 and the 5-cap silicide 1-24a
Open the part and attach the internal lead 28.
絶縁保腫膜２７は内部配線２５を全開的に覆い。The insulating cell membrane 27 completely covers the internal wiring 25.
かつ白金珪化物層２４ａを除く接続用不純物導入層２３
を覆うことが必要である。この絶縁保鎖腺２７の形成に
より内部配線２５は半導体基板２００表面において白金
珪化物層２４ａと分離され、内部配Ｍ２５は完全に杷縁
保咳膜２７で憶われ、突気や水分と接触しない。内部配
線２５と内部リード２８とは接続用不純物導入７１２３
．白金珪化物ｊ１７ｉ ２４ ｍを介して電気的に接続
する。and the connection impurity introduced layer 23 excluding the platinum silicide layer 24a
It is necessary to cover the Due to the formation of this insulating chain gland 27, the internal wiring 25 is separated from the platinum silicide layer 24a on the surface of the semiconductor substrate 200, and the internal wiring M25 is completely covered by the lozenge-edge cough-retaining film 27, so that it does not come into contact with sudden air or moisture. . The internal wiring 25 and internal leads 28 are doped with connection impurities 7123
．． Electrical connection is made via platinum silicide j17i 24 m.
このようにすれは、蕗出するのは白金珪化物ノ胃２４１
のみでるり、白金珪化物は水分による腐食は起らないか
ら、断線がなく１６籾性の高い半導体装置が侍ら扛る。In this way, it is the stomach of platinum silicide that is exposed.
Since platinum silicide is not corroded by moisture, semiconductor devices with high resistance to wire breakage are popular.
上記笑施しリにおいて内部配線にモリブデンや多結晶シ
リコン等を使用することができ、珪化物はパラジウム等
の他の白金族元ｘ’ｉ使用することもでさる。In the above embodiment, molybdenum, polycrystalline silicon, etc. can be used for the internal wiring, and other platinum group elements x'i such as palladium can also be used as the silicide.
以上硅ｍｌに説明したように、本祐明によれば。As explained above, according to Yumei Moto.
腐食されヤすい材料で作られた内部配線は絶縁保蹟膜で
完全に横われ、線用部分ｅよ耐食性の高い白金族元累の
珪化物でおり、裏山している珪化物ノーと内部配線とは
千４体基板に設けた接続用不純物導入ノーで接続さする
ので、水分時による腐食を防ざｈ （ｓ幀法の筒い半導
体装置が侍られるという効米が得られる。The internal wiring, which is made of corrosion-resistant materials, is completely covered with an insulating and protective film, and the wiring part (e) is made of platinum group element silicide, which has high corrosion resistance, and the silicide layer in the back and the internal wiring are Since the connection is made with a connection impurity introduction hole provided on the substrate, corrosion due to moisture is prevented, and a cylindrical semiconductor device using the s-thickness method can be used.
紀１図は便米の半導体装置の一例の断面図、第２図は不
晃明の一実施例の断面図である。
１０・・・・・・半２４体基板、１１・・・・・・絶縁
膜、１２・°。
ｈ＠
・・・拡散層、１４・・・・・・白金珪化、１５・・・
・・・アルミニウム配置癲、１６・・・・・・電極、１
７・・・・・・絶緘膜、１８・・・・・・内部リード、
２０・・・・・・半導体基板、２１・・・・・・絶縁膜
、２２・・・・・・素子領域の不純物導入層、２３・・
・・・・接続用不純物導入層、２４ ａ ＋ ２４ ｂ
＋ ２４ｃ・・・・・・白金珪化物層、２５・・・・
・・内部配線、２７°・・・・・絶縁保護膜、２８・・
・・・・内部リード。
第１図
８
第２図1 is a sectional view of an example of a standard semiconductor device, and FIG. 2 is a sectional view of an example of a standard semiconductor device. 10...Semi-24 body substrate, 11...Insulating film, 12°. h@...Diffusion layer, 14...Platinum silicide, 15...
... Aluminum arrangement, 16 ... Electrode, 1
7... Instal membrane, 18... Internal lead,
20... Semiconductor substrate, 21... Insulating film, 22... Impurity introduced layer in element region, 23...
.... Impurity introduction layer for connection, 24 a + 24 b
+ 24c...Platinum silicide layer, 25...
・・Internal wiring, 27°・・Insulating protective film, 28・・
...Internal lead. Figure 1 8 Figure 2
Claims (1)
記不純物導入層と間隔をおいで設けられた接続用不純物
導入層と、一端が前記累＋領域の不純物導入層に接続し
他端が前記接杭用小純物導入ノーの一部に接続する内部
配線と、前記接α用不純物導入層の前記内部配ｌｉｔ！
接続部を除く表向の一部に設けられた白金族元累の珪化
物層と、前記内部配１１１１ｔ″全面的に嶺いかつ前記
珪化物ｌ−以外の接続用不純物導入層表面を少くとも穏
う絶縁保護膜とを含むことを特徴とする半２４停鉄置。An impurity-introduced layer in the confectionery region provided on a semiconductor substrate, a connecting impurity-introduced layer provided at a distance from the impurity-introduced layer, one end connected to the impurity-introduced layer in the cumulative region, and the other end connected to the contacting impurity-introduced layer. The internal wiring connected to a part of the impurity introduction layer for the pile and the internal wiring of the impurity introduction layer for the contact α!
At least the surface of the platinum group element silicide layer provided on a part of the surface excluding the connection portion, and the surface of the connection impurity introduction layer other than the silicide 1- that extends over the entire surface of the internal wiring 1111t'' is softened. A semi-24-stop train station characterized by comprising an insulating protective film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56158395A JPS5858757A (en) | 1981-10-05 | 1981-10-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56158395A JPS5858757A (en) | 1981-10-05 | 1981-10-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5858757A true JPS5858757A (en) | 1983-04-07 |
Family
ID=15670794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56158395A Pending JPS5858757A (en) | 1981-10-05 | 1981-10-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5858757A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004064088A (en) * | 2002-07-30 | 2004-02-26 | Agilent Technol Inc | Thin film resonator protected from electrostatic discharge |
-
1981
- 1981-10-05 JP JP56158395A patent/JPS5858757A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004064088A (en) * | 2002-07-30 | 2004-02-26 | Agilent Technol Inc | Thin film resonator protected from electrostatic discharge |
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