JPS62236052A - Microprocessor - Google Patents

Abstract

PURPOSE:To avoid deterioration of the cache hit factor and also to improve both operability and availability of a system, by invalidating a cache part on the corresponding side in case a cache part has a high error frequency and utilizing the other cache part for both instructions and data. CONSTITUTION:The parity error detecting circuits 114 and 153 detect a errors respectively. In other words, a counter 154 counts those detected errors when signal lines 175 and 177 are set at logical '1'. Then the count value of the counter 154 is added with 1 for each detection of an error. The initial value of the counter 154 is equal to '0'. A comparator 156 checks whether the value of the counter 154 is coincident with the contents of a register 155 set previously. If the coincidence is secured through the comparator 156, an interruption signal line 182 is equal to logical '1' and an interruption is given to a microprocessor 1. That is, a data cache part 5 can be used for both instructions and data by setting both an instruction access mode F/F and a data access mode F/F to the part 5.

Description

Detailed Description of the Invention "Field of Industrial Application" The present invention relates to a microprocessor processing device having a microprocessor, a main memory section, an instruction cache section and a data cache section interposed therebetween. .

"Conventional technology" Improving the processing speed of microprocessors (accompanied by:

In order to improve the performance of the f2 system, a cache (memory) is provided between the microprocessor and the main memory. His size has also grown and his catch rate has increased.

Normally, the cache is divided into a directory part and a data part.The contents of the directory part and the main memory part are compared with the address to be accessed, and if they match, the contents of the data part are transferred to the processor instead of the main memory part. (: Send. If the comparison results of the addresses do not match (cache miss), information is read from the main memory.

A parity pit is added to the directory section and data section of the cache, and when the directory section or data section is successively read out (if there is a parity error, the cache hit is also treated as a miss and the main storage section is accessed).

In addition, some devices consider a parity error in the directory section to be a serious failure and perform a system check.

``Problems to be Solved by the Invention'' In the above-described conventional microprocessor processing device having a cache, if a cache parity/f error occurs during a cache hit, the main memory is accessed as a miss. Therefore, when a cache memory failure or a failure of the cache parity error detection circuit occurs, the cache hit rate decreases and the performance of the system decreases. Furthermore, if a parity error in the cache directory section is used as a system check (system failure), there are drawbacks such as a decrease in system availability.

"Means for Solving the Problems" A microprocessor processing device of the present invention comprises a microprocessor, a main memory, an instruction cache and a data cache interposed between the microprocessor and the main memory. has.

The instruction cache section and data cache section are
When a cache parity error occurs, a cache miss is detected in the main memory (-), and the parity error count is greater than or equal to a predetermined IL!! (2). Then, the microprocessor stops using the instruction cache section or the data cache section, and replaces the instruction cache section as an instruction and data cache section, or replaces the data cache section as a data and instruction cache section. (Secondly, this prevents a decrease in cash hit rate and system availability.)

"Example" Next (2) This invention (2) will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the invention. The microprocessor 1 and the main memory section 2 are connected to a bus 3 (-), and an instruction cache section 4 and a data cache section 5 are interposed between the microprocessor 1 and the main memory section 2 via the bus 3. Furthermore, there is an address line 6 and an information line 7 between these two lines.
is connected.

The instruction cache unit 4 and the data cache unit 5 have the same configuration, and are distinguished only by the settings of flip-flops 116 and 117, which will be described later. Therefore, the instruction cache unit 4 is shown in FIG. In FIG. 2, the cache directory section 11 stores the upper part of the access address to the main storage section 2.

The directory section 11f2 has a parity section 112.

Cache data section (data in this case means instruction code) 15 (Secondly, a parity section 152 is provided. Cash hit. Cache miss is determined by cash hit judgment circuit 113. Parity check of directory section 11 is performed in circuit 114.

The access mode (instruction or data) of the microprocessor 1 is decoded by the decode circuit 115. The logical product of each output of the instruction access mode F/F (flip flop) 116 and the data access mode F/Fl 17 and each output of the decoding circuit 115 is calculated by the AND circuits 191a and 19.
It is taken in 1b. When writing an upper address to the directory section 11 (in the event of a miss), the parity generation circuit 118 writes a parity pit to the parity section 112 (2). When the data section 15 is read, the parity pit is checked by the data parity check circuit 153. The number of parity errors in the directory section 11 or the data section 15 is counted by a counter 154, and an arbitrary constant preset by the microprocessor l (2) is held in a register 155. 155 is detected by the comparison circuit 156.

As an initial setting, the microprocessor l sets the instruction access mode F/F 116 and resets the data access mode F/F 117 in the instruction cache unit 4.
16 and set F/F117. Furthermore, a predetermined arbitrary value (binary number) is set in the register 155 (2).The instruction cache section 4 will be described below.

After the initial setting of the microprocessor 1, when a read access of an instruction is issued, the access address lower part 1
The directory section 11 and the data section 15 are accessed from 71+2. A determination circuit 113 determines whether there is a hit or a miss. That is, the address upper part 17
2 and the content 173 read from the directory section 11 match, and the instruction access mode signal line 180 is logic +1111, and the parity error detection circuit 114 of the directory section 11 does not detect a parity error (signal 5).
9 line 174 is the logic P1"), the parity r of the data section 15
When the error detection circuit 153 does not detect a parity error (the signal line 176 is at logic "1"), a cache hit occurs, a hit signal 178 is output, and the contents of the data section 15 are sent to the microprocessor 1. The above conditions/
If 1 is not confirmed, a cache miss signal 179 is output, and the main storage section 2 is accessed.

The error is detected by the harrity error detection circuit 114 or 153. That is, the signal line 175 or 177 is connected to logic 11"l"
! -, this is counted by the counter 154, and is counted by 1 for each error detected. Counter 15
The initial value of 4 is "O'-t".

A comparison circuit 156 compares whether the value of the counter 154 matches the preset contents of the register 155. If they match, the interrupt signal line 182 becomes logic "L" and the microprocessor Add 1 to 1. The microprocessor 1 sets the instruction access mode F/ to prohibit the use of the instruction cache section 4 during its interrupt processing.
The F L 16 is reset, and the cash hit determination circuit 113 is therefore disabled. Furthermore, the instruction access mode F/F of the data cache section 5 (not shown since it has the same configuration as the instruction cache section 1) is set. That is, since both the instruction access mode F/F and the data access mode F/F are set in the data cache section 5, the data cache section 5 can serve as both an instruction cache and a data cache. The instruction cache unit 4 prohibits the use of the data cache unit 5 (
From the second.

It is easy to understand from the above explanation that it can also serve as a data cache (I will omit it because it is obvious).

``Effects of the Invention'' As explained above, the present invention is a microprocessor processing device having an instruction cache and a data cache, and when the frequency of errors in the cache section is low, the main memory section is accessed as a cache miss. , if the error frequency is high, disable the cache section on the corresponding −r side ≦
Second, the other cache section i can be used both for instructions and data (secondly, this has the effect of preventing a decrease in the cache hit rate and increasing the usability and availability of the system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing a specific example of the instruction cache unit 4, which is the essential part of the present invention. 1 is a microprocessor, 2 is a memory section, 4 is an instruction cache section, and 11 is a directory section. 15: data section, 113: cache hit determination circuit,
114, 153: Parity error detection circuit, 115: Decoding circuit, 116, 117: Flip-flop for access mode, 118: Parity generation circuit, 154: Counter for number of error occurrences, 155: Register, 156 two-number structure Circuit, 190: OR circuit, 191: AND circuit. Patent applicant: Japanese-style company representative Takusai Kusano 1 Kuchika 2 Figure 1 Micro professional solicitor

Claims (1)

[Claims] (1) A microprocessor processing device comprising a microprocessor, a main memory, and an instruction cache and a data cache interposed between the microprocessor and the main memory, the instruction cache and the data cache being interposed between the microprocessor and the main memory. The cache section for
When a cache parity error occurs, it has means for accessing the main storage section as a cache miss, and means for counting the number of occurrences of the parity error, and when the number of occurrences of the parity error exceeds a predetermined value. The microprocessor discontinues use of the instruction cache section or the data cache section, and replaces the data cache section with an instruction and data cache section, or replaces the instruction cache section with a data and instruction cache section. A microprocessor processing device comprising: means.