KR0177400B1 - Redundancy word line checking circuit - Google Patents

Abstract

The present invention relates to a redundancy word line check circuit for checking a failure of a normal cell array of a memory device and a failure of a redundant cell array to replace a failed normal cell array. External control logic means for selectively ANDing the / CAS signal and the / WE signal to output the first and second word line driving signals, and receiving the first word line driving signal and outputting the word line driving means as normal words. Normal word line selecting means for checking whether or not the normal cell array is broken by transmitting a line, and receiving the first and second word line driving signals, and outputting the word line driving means when the normal cell array fails. Redundancy word line selection means for transmitting to the line and checking for a failure of the redundant cell array. Therefore, by checking the failure state of the normal memory cell arrays of the device in the wafer state and checking the failure of the redundant cell array replacing and replacing the failed normal memory cell arrays, the device is repaired by replacing it with a redundant cell array that has not failed. Can improve the production yield.

Description

Redundancy Wordline Check Circuit

1 is a word line check circuit diagram in accordance with the present invention.

2 is an operational waveform diagram of FIG.

* Explanation of symbols for main parts of the drawings

10: external control logic means 20: normal word line selection means

30: redundancy word line selection means 40: word line check circuit

I1 to I9: First to ninth inverters N1 to N3: First to third NAND gates

T1, T2: first and second transmission gates

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a wordline check circuit for checking the failure of a memory device. In particular, the present invention relates to a repair of a normal wordline as well as a failed normal wordline. The present invention relates to a redundancy word line check circuit capable of checking whether or not a redundancy word line fails.

When manufacturing a semiconductor device, in particular, a memory device such as DRAM, it is very difficult to perform a perfect process, and there is a problem that normal cells, which are unit memory elements, fail and fail to use the memory device.

In order to solve these problems, an adequate number of redundant cell arrays, that is, redundant cell arrays having the same size and structure as those of normal cell arrays in a manufacturing process, are made to test the failure of the normal cell array in a wafer state. Therefore, the failed cell array among the normal cell arrays is replaced with a redundant cell array to be repaired. As described above, when a repaired memory device receives an address for accessing a failed normal cell array, a redundant circuit operates to access the replaced redundancy cell array, thereby allowing the memory device to operate normally.

However, redundancy cell arrays that replace failed normal memory cell arrays can also fail. In this case, the memory device is maintained in a fault state by the failed redundancy cell array and cannot operate normally. The memory device cannot be repaired by replacing the failed redundancy cell array with another normal redundancy cell array. Therefore, when repairing a failed normal memory cell array, it should be replaced with a normal redundancy cell array in which a failure has not occurred.

However, conventionally, before repairing a failed normal memory cell array, it is not known whether a redundancy cell array is broken and there is a problem in that a production yield is lowered.

Accordingly, an object of the present invention is to provide a redundancy word line check circuit capable of checking the failure of a redundant cell array before repairing a failed normal memory cell array, thereby increasing the production yield of the device.

To achieve the above object, a redundancy word line check circuit for checking a failure of a normal cell array of a memory device according to the present invention and a failure of a redundant cell array for replacing a failed normal cell array is input from an external circuit. An external control logic unit for selectively outputting the / RAS signal, the / CAS signal, and the / WE signal to output first and second word line driving signals, and receiving the first word line driving signal, Normal word line selection means for transmitting an output to a normal word line to check whether the normal cell array has failed, and receiving the first and second word line driving signals to receive a word line driving means in case of failure of the normal cell array. Redundancy word line selection means for sending an output to the redundancy word line to check for any failure of the redundancy cell array. Include.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a redundancy word line check circuit diagram in accordance with the present invention.

The redundancy word line check circuit 40 according to the present invention is composed of an external control logic means 10, a normal word line selection means 20 and a redundancy word line selection means 30.

The external control logic means 10 is an inverter (I1) (I2) for selectively inverting the / RAS (Row Address Strobe) signal, / CAS (Column Address Strobe) signal and / WE (Write Enable) signal input from the outside (I3) (I4), the first NAND gate (N1) and the first NAND gate which inverts and inputs the / RAS signal and the / CAS and / WE signals by being inverted by the inverters I1 and I2. Inverter I5 connected to the output terminal of N1 and outputting a first word line driving signal, and the / CAS signal, / RAS, and / WE signal are inverted and negatively multiplied by inverters I3 and I4. The second NAND gate N2 outputs a two word line driving signal.

The normal word line selecting means 20 comprises inverters I6 and I7 which latch to maintain a current state until the state of the first word line driving signal is changed, and the inverter I6 ( An output terminal of I7) is connected to each gate and includes a first transfer gate T1 formed of N and P morph transistors having a source and a drain connected in common. The drain and the source which are commonly connected to the first transfer gate T1 are connected to the word line driving means W / D and the normal word line NW / L, respectively, and applied to the gates of the N and P morph transistors, respectively. The output signal of the word line driving means W / D connected to the drain is transmitted or interrupted to the source in accordance with the output of the inverters I6 and I7. That is, when the first word line driving signal output from the inverter I5 is in a 'low' state, the outputs of the inverters I6 and I7 are respectively 'high' and 'low' states. Therefore, the first transfer gate T1 is 'on' to transmit the output signal of the word line driver W / D to the source to drive the normal word line NW / L. On the contrary, when the first word line driving signal is 'high', the first transfer gate T1 is 'off' so that the output signal of the word line driving means W / D is not transmitted to the source. The word line NW / L is not driven.

The redundancy word line selecting means 30 is a third NAND gate N3 that negatively crosses the first word line driving signal output from the inverter I5 and the second word line driving signal output from the second NAND gate N2. ), The inverter I8 for inverting the second word line driving signal, the outputs of the third NAND gate N3 and the inverter I8 are connected to the gates, respectively, and the sources are connected to the power supply terminal V _DD and the ground. Inverters I9 and I10 connected to the terminal V _SS and forming a latch connected to the P MOS transistor N and the N MOS transistor NM, which drains are commonly connected to output a signal, and the common drain. ) And a second transfer gate T2 formed of P and N MOS transistors having output terminals of the inverters I9 and I10 connected to respective gates, and having a source and a drain connected in common. The drain and the source which are commonly connected to the second transfer gate T2 are connected to the word line driving means W / D and the redundancy word line RW / L, respectively, and applied to the gates of the P and N MOS transistors, respectively. The output signal of the word line driving means W / D connected to the drain is transmitted or interrupted to the source in accordance with the output of the inverters I9 and I10. That is, when the outputs of the inverters I9 and I10 are 'low' and 'high', respectively, the second transfer gate T2 is 'on' to source the output signal of the word line driving means W / D. The redundancy word line (RW / L) is driven by transmitting to the. On the contrary, when the outputs of the inverters I9 and I10 are 'high' and 'low', the second transfer gate T2 is 'off' so that the output signal of the word line driving means W / D is sourced. The redundancy word line (RW / L) is not driven because it is not transmitted to.

2 is an operational waveform diagram of the redundancy word line check circuit 40 according to the present invention shown in FIG.

The operation of the redundancy word line check circuit 40 according to the present invention will be described with reference to the operation waveform diagram shown in FIG.

The / RAS signal, the / CAS signal and the / WE signal are inputted to the external control logic means 10 of the redundancy word line check circuit 40 from the outside of the memory device. The input / RAS signal, the / CAS signal and the / WE signal are selectively inverted to the first NAND gate N1 through the inverter I1 and I2, and the second gate through the inverter I3 and I4. N2). That is, the / CAS signal and the / WE signal are inputted inverted by the inverter I1 (I2) and the / RAS signal is directly input to the first NAND gate N1, and the / RAS signal is input to the second NAND gate N2. And the / CAS signal is input inverted by the inverters I3 and I4 and the / WE signal is directly input.

The / RAS signal, the / CAS signal, and the / WE signal are input to the 'low', 'high' and 'low' states at time t1, respectively. The signals cause the first word line driving signal having a 'low' state to be outputted to the node 12 through the inverters I1, I2, the first NAND gate N1, and the inverter I5. Therefore, the first transfer gate T1 is 'on' to transmit the output signal of the word line driving means (W / D) to the normal word line (NW / L), thereby causing the failure of the normal word line (NW / L). Check for presence. In this case, when the normal word line NW / L is broken, a fuse (not shown) connected to a corresponding address line is cut by a laser to prevent operation.

The inverters I6 and I7 maintain the node 12 in a 'low' state. At this time, the third NAND gate N3 of the redundancy word line driving means 30 outputs a 'high' signal by the node 12 in the 'low' state to 'off' the P MOS transistor PM. Let (16) be 'low'. Therefore, the second transfer gate T2 is 'off' so that the output of the word line driving means W / D is not transmitted to the redundancy word line RW / L.

The / RAS signal, the / CAS signal, and the / WE signal are input to the 'high', 'high' and 'high' states at time t2, respectively. Therefore, the node 12 maintains the state T1 by keeping the state 'low' to turn on the first transmission gate T1 and 'off' the second transmission gate T2.

The / RAS signal, the / CAS signal, and the / WE signal are input to the 'high', 'low' and 'low' states at time t3, respectively. The signals cause the first word line driving signal of the 'high' state to be outputted to the node 12 through the inverters I1, I2, the first NAND gate N1, and the inverter I5, and the inverter I3. Through the I4 and the second NAND gate N2, the second word line driving signal having a 'high' state is output to the node 14. Therefore, the third NAND gate N3 and the inverter K8 output a 'low' signal to 'turn on' the P MOS transistor PM and 'off' the N MOS transistor NM to turn off the node 16. Make it 'high'. The 'high' state of the node 16 is inverted and applied to the gate of the P MOS transistor constituting the second transfer gate T2 through the inverter I9, and directly applied to the gate of the N MOS transistor so that the second transfer gate ( T2) is turned on to transmit the output of the word line driving means W / D to the redundancy word line RW / W.

The / RAS signal, the / CAS signal, and the / WE signal are input in the states 'low', 'low' and 'low' at the time t4, respectively. The signals cause the first word line driving signal having a 'low' state to be output to the node I2 through the inverter I1, I2, the first NAND gate N1, and the inverter I5, and the inverter I3. The second word line driving signal having a 'high' state is output to the node I4 through the I4 and the second NAND gate N2. A low state of the node I4 turns on the first transfer gate T1, but a fuse (not shown) connected to a corresponding address line is lasered due to a failure of the normal word line NW / L. Since it is cut by, the output of the word line driving means W / D is not transmitted to the normal word line NW / L. At this time, the 'low' state of the node I2 and the 'high' state of the node I4 set the outputs of the third NAND gate N3 and the inverter I8 to be 'high' and 'low', respectively. The transistor PM and the N MOS transistor NM are both 'off'. However, the node I6 drives the word line by turning on the second transfer gate T2 by bringing the latches of the inverters I9 and I10 into the state of the time T3, that is, the 'high' state. The output of the means W / D is transferred to the redundancy word line RW / L.

Thereafter, when the / RAS signal, the / CAS signal, and the / WE signal are input as 'high', 'high' and 'high' states at time t5, respectively, the node 12 and the node 14 are 'low', respectively. And 'high' state. Therefore, as at time T4, the output of the word line driving means W / D is transmitted to the redundancy word line RW / L through the second transfer gate T2. At this time, if the address assigned in the initial design is applied as many as the number of redundancy word lines RW / L, the redundancy word lines RW / L are driven to check whether there is a failure.

When the / RAS signal, the / CAS signal, and the / WE signal are input in the states 'high', 'high', and 'high' at the time t6, respectively, the N MOS transistors of the redundancy word line selecting means 40 NM) is 'on' causing node 16 to be 'low'. Accordingly, the second transfer gate T2 is 'off' so that the output of the word line driving means W / D is blocked from being transmitted to the redundancy word line RW / L and is switched to the initial state.

Therefore, the present invention can check the failure of the redundancy cell array that repairs by replacing the defective normal memory cell arrays by testing the failure of the normal memory cell arrays of the device in the wafer state, and thus the redundancy cells having no failure. Replacing with arrays has the advantage of improving production yield.

Claims (4)

In the redundancy word line check circuit that checks the failure of the normal cell array of the memory device and the failure of the redundant cell array to replace the defective normal cell array, a / RAS (Row Address Strobe) signal is input from an external circuit. And external control logic means for outputting first and second word line driving signals by selectively ANDing a / CAS (Column Address Strobe) signal and a / WE (Write Enable) signal, and the first word line driving signal. A normal word line selection means for receiving an output of a word line driving means to a normal word line and checking whether the normal cell array has failed, and receiving the first and second word line driving signals and a failure of the normal cell array. Redundancy word line selection to check the redundancy cell array for failure by transmitting the output of the redundancy word line driving means to the redundancy word line A redundancy word line check circuit comprising means. 2. The apparatus of claim 1, wherein the external control logic means is configured to invert the output of the first NAND gate and the first NAND gate to be negatively multiplied by inputting the / CAS and / WE signals inverted from the / RAS signal. A word line check circuit comprising an inverter for outputting a single word line driving signal and a second NAND gate for inputting the / CAS signal and the inverted / RAS and / WE signals to be negatively multiplied to output a second word line driving signal. The method of claim 1, wherein the normal word line selecting means comprises: an inverter for inverting the first word line driving signal, an output of the inverter and the first word line driving signal connected to respective gates, and a drain and a source 1. A word line check circuit comprising a first transfer gate formed of N and P morph transistors connected to a word line driving means and a normal word line, respectively, and an inverter inverting the output of the inverter to maintain an input state of the inverter. The redundancy word line selecting means according to claim 1, wherein the redundancy word line selecting means comprises: a third NAND gate that negatively multiplies the first and second word line driving signals, an inverter for inverting the second word line driving signal, and the third The outputs of the NAND gate and the inverter are connected to the gates, the power terminals and the ground terminals of the sources, and the drains are connected in common, and the common drains of the P and N MOS transistors are connected to output the outputs. An inverting inverter and a P and N MOS transistor having respective gates connected to an output terminal of the inverter and a common drain of the P and N MOS transistors, and each drain and source connected to word line driving means and redundancy word lines in common. An output of the inverter connected to the formed second transfer gate and the common drain of the P and N MOS transistors to invert the output; Word line check circuit consisting of an inverter for inverting the input to maintain the state of the inverter.