KR100238669B1 - Adaptive digital filter - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

It relates to an adaptive digital filter.

I. The technical problem to be solved by the invention

Since the loop does not reflect this when loading coefficients in an adaptive digital filter, the problem of restarting from the beginning when the coefficients need to be changed during operation is solved.

All. Summary of Solution of the Invention

An adaptive digital filteret coefficient update loop is operated in conjunction with external coefficient loading, and has a function of center tap setting and coefficient divergence prevention.

la. Important uses of the invention

Applies to digital filters.

Description

Adaptive Digital Filter {ADAPTIVE DIGITAL FILTER}

The present invention relates to an adaptive digital filter, and more particularly, to an adaptive digital filter that operates in conjunction with an external coefficient loading and prevents center tap setting and coefficient divergence.

Today, due to the development of digital technology, many analog filter applications are rapidly replaced by digital filters, and these digital filters are applied as adaptive filters to remove adaptive control or multipath by adaptive algorithms. . However, in most applications of the adaptive digital filter, it is true that the pure filter part and the adaptive coefficient updater are performed separately. In other words, as can be seen in ghost eliminators, most practical applications are to load coefficients obtained by using a digital signal processor (DSP) in a general-purpose digital filter. In this configuration, since only one coefficient is loaded in one clock, a large amount of time must be devoted to loading the coefficient, thereby degrading the overall operation performance such as fast response characteristics.

Therefore, there have been many studies on the implementation of the adaptive digital filter including the coefficient updater, one of which is the configuration of the adaptive equalizer of the quadrature amplitude modulation (QAM) method proposed in US Patent 5,243,624. This allows one to load coefficients for existing general-purpose digital filters, but to increase the equalization speed by updating the coefficients of each filter tap every symbol clock.

The application of the adaptive filter can use a variety of algorithms, but here, the implementation of the present invention will be described using the LMS algorithm which is most commonly used for ease of explanation. For similar algorithms, the same can be applied to the contents of the present invention with a slight change.

When the input of the adaptive filter is x (n), the output is z (n), and the coefficient of the adaptive filter is w _i , the LMS algorithm is shown in Equation 1 below.

,

가 된다.here

,

Becomes

The LMS algorithm operates to minimize E [e ² (n)].

In the actual configuration, Equation 1 is changed to Equation 2 by the delay occurring in each operation.

Its characteristics and convergence are almost the same as those with no delay if the state of the input signal does not change drastically. In September 1993, G.LONG, F.LING, and JGProakis, "The LMS algorithm with delayed coefficient adaptation , "IEEE Trans. on Acoustics, Speech, and Signal Processing, VOL.37, NO.9, pp.1397-1405, sep 1989.

1 is a block diagram of a conventional adaptive filter.

The construction of the adaptive filter was published in 1994 by N.R. Shanbhag and K.K.Parhi, Pipelined Adaptive Digital Filters, and Kluwer Academic Publishers. Here we take a pipelined approach, and on page 42 we show the structure of a standard LMS for a direct filter structure. When this is converted into a transpose form, it is as shown in FIG. 1. As can be seen in FIG. 1, since the coefficient of the coefficient update unit is directly input to the multiplier of the filter unit, no initial value other than the initial value of the register in the loop can be provided. In a conventional adaptive filter application using a general-purpose digital filter, only a filter part exists in FIG. 1 and the coefficient update is dedicated to a DSP or the like. In this case, coefficient loading to each multiplier is done by parallel buses for the sake of simplicity. The multiplier f1 multiplies the delayed output data (udo) with the step size and the detected error signal (u-err) and outputs the multiplier. The adder e1 adds the output signal of the multiplier f1 and the signal delayed by a predetermined clock from the delay d1 and outputs the delayed signal to the delay d1. The delay unit d1 delays the signal output from the adder e1 by a predetermined clock and outputs a coefficient update value. In addition, the delayed output data is output by delaying predetermined clocks through the delays g1 -gn. The delayed output data (udo) is applied to a multiplier f2-fn, an adder e2-en, and a delay d2-dn, respectively, and outputs a coefficient update value by the multiplier f2-fn, the adder e2-en, and the delay d2-dn. do. The coefficient update values thus output are respectively applied to multipliers a1-an and multiplied by the input signal di to be output. In this case, the adder b1 adds the signal multiplied by the multiplier a1 and cascade input data (casecade data cdi), and outputs the delayed signal C1 through the delayers c1-cn.

In addition, the aforementioned US Patent 5,243, 624 is shown in Figure 2 to effectively use the conventional universal filter. The coefficient updating unit consists of a multiplier f1, an adder e1, and a delay unit d1. The coefficient updating unit of the next stage continuously performs coefficient updating in such a manner that the delay unit g1 is further added, and the coefficient loading is performed by intermediate N-to-1 MUX. One symbol per symbol is transmitted. It is a structure that can use the existing filter effectively and the coefficient update at almost the same speed as the adaptive algorithm by the coefficient update by the pseudo adaptive algorithm. However, even in this case, it is impossible to load new coefficients except by setting the initial coefficients of the register.

However, such a configuration is an effective application method of the conventional general-purpose filter, it is impossible to say that the configuration of the adaptive filter for the one chip. In addition, since the update and loading of coefficients of the digital filter are not directly related, the initial value of the coefficient update loop for coefficient update is limited. That is, the accumulator in the loop is always started only at a predetermined value in the initial state, and does not properly reflect when it is necessary to start at an arbitrary value. That is, even if an arbitrary coefficient is loaded in the filter unit, the coefficient update loop cannot directly affect the coefficient update loop. Therefore, coefficient loading and coefficient update cannot be linked. This is because the loop does not reflect the existing structure when loading the coefficients, so if the coefficients need to be changed during operation, the operation must be started again from the beginning.

Accordingly, an object of the present invention is to provide an adaptive digital filter capable of initializing a loop by an arbitrary value through linkage of coefficient loading and coefficient update.

Another object of the present invention is to provide an adaptive digital filter capable of setting a filter coefficient of a center tap in digital processing.

It is another object of the present invention to provide an adaptive digital filter which prevents the divergence of filter tap coefficients to prevent an abnormal increase in loop output.

1 is a block diagram of a conventional adaptive digital filter

2 is a block diagram of a conventional adaptive digital filter

3 is a block diagram of an adaptive digital filter in accordance with an embodiment of the present invention.

4 is a block diagram of an adaptive digital filter according to another embodiment of the present invention.

5 is a block diagram of an adaptive digital filter according to another embodiment of the present invention.

6 illustrates an ASIC of an adaptive digital filter according to an embodiment of the present invention.

7 is an exemplary view of configuring an equalizer using the adaptive digital filter of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the preferred embodiment of the present invention.

In the present invention, it is possible to operate only by external coefficient loading like the operation of a general-purpose digital filter. And as shown in the implementation of the ghost eliminator can be used in the case of obtaining a separate coefficient in the DSP, and loading to prevent divergence, etc. by comparison with the result updated by the coefficient updater.

In addition, in the VSB method recently determined by the US HDTV transmission standard, the reference signal sequence present in the field sync (initial state or on-demand) is required as announced in the Grand Alliance HDTV System Specifition, Submitted to the ACATS Technical Subgroup in February 1994. It is necessary to drive the loop by using the DSP to stably obtain the coefficients of the initial state or the necessary state. In such a case, it is impossible to drive the loop by calculating the coefficient of the initial state or the necessary state stably with the existing structure. In addition, a notch filter is applied to the channel equalizer for the application of a notch filter, which is a method of applying the NTSC Rejection Filter (NRF) used to remove co-channel interference caused by NTSC simultaneous broadcasting. It can also be used for application. It can also be used when a matched filter is implemented in an equalizer.

In the present invention, the value of the center tap can be set to 1 during signal processing. That is, since the filter coefficient of the center tap should be 1 for the post-stage processing on the signal path, a function for this is added.

An example of how to use a large number of latches to speed up the operation of the adaptive filter in most cases is described in November 1993 by MD Meyer Agrawal, "A High sampling rate delayed LMS filters architecture," IEEE. Trans. On Cicuits & Sytems, Vol. 40, NO, 11, pp. 727-729. However, such a configuration causes excessive hardware increase and is not always desirable in consideration of the speed of an adder or the like even in actual implementation. In the present invention, in consideration of the speed of each device in the actual implementation it can be implemented with a minimum of hardware.

3 is a block diagram of an adaptive digital filter according to an embodiment of the present invention.

With a plurality of MUX M1-Mn in the loop for coefficient update of the adaptive filter, the inputs of the plurality of MUX M1-Mn are the coefficients by the adaptive update by the loop and the external input, and the coefficient selection mode (cmode) By controlling, the loading of coefficients and the updating of coefficients are linked. That is, since the coefficient input from the outside in the coefficient selection mode (cmode) becomes the initial value of the loop, the adaptive coefficient can be initialized to a value necessary at a time required by the user. This enables various applications as described above.

The delay g1 outputs the delayed input signal udi by a predetermined clock delay. The multiplier f1 multiplies the output data delayed by the predetermined clock delay, the step size and the calculated error signal u-err from the delay g1, and outputs the multiplier. The adder e1 adds an output signal of the multiplier f1 and a signal delayed by a predetermined clock from the delay d1 and outputs the result to the MUX M1. The MUX M1 selects one of the set coefficient value ecoef1 and the signal output from the adder e1 by the coefficient selection mode cmode and outputs it to the retarder d1. The delay unit d1 delays a signal output from the MUX M1 by a predetermined clock and outputs a coefficient update value to the multiplier an.

Data delayed by a predetermined clock through the delay g1 is delayed and output by a predetermined clock through the delay g2-gn. Data delayed by a predetermined clock through the delay g2-gn is applied to the multiplier f2-fn, respectively, and in the multiplier f2-fn, the delayed output data, the step size and the detected error signal u are respectively delayed from the delay g1-gn. multiply each by -err) and output to MUX M2-Mn. In MUX M2-Mn, one of the set coefficient values ecoef2-ecoefn and the signal output from the adder e2-en is selected by the coefficient selection mode cmode and output to the delay unit d2-dn. The retarders d2-dn respectively delay the signals outputted from the MUX M2-Mn by predetermined clocks, and output the coefficient update values to the multipliers a2-an, respectively. The coefficient update values output for each filter tap are respectively applied to multipliers a1-an and multiplied by the input signal di to be output. In this case, the adders b1-bn add and output a signal multiplied by the multiplier a1-an and cascade input data (cdi), respectively. The signals output from the adder b1 are respectively clocked through the delayers c1-cn. Delayed each time to output a digital filtered signal (do). The delayed input signal udi is a signal in which the input signal di is delayed by a predetermined clock, and the delayed output signal udo is a signal in which the delayed input signal udi is finally delayed by a clock of a predetermined number of filter taps.

4 is a block diagram of an adaptive digital filter according to another embodiment of the present invention.

The adaptive digital filter of FIG. 4 is the same as that of FIG. 3, but is adapted by connecting a rounder r1-rn and a plurality of MUX N1-Nn to each filter tap between a plurality of delay units d1-dn and a plurality of multipliers a1-an. It has a structure in which divergence is prevented by adding a rounding function of coefficients that are updated and output as a result. In this case, the rounding limits the size of the adaptive coefficient to a predetermined value or less. In general, the rounding prevents the coefficient from exceeding 0.5.

5 is a block diagram of an adaptive digital filter according to another embodiment of the present invention.

MUX 40 allows you to set the center tap's coefficient to 1 or 0 for post-processing on signal processing. Latches 51 and 52 help solve the real hardware implementation delays on the signal path. The first and second filter units 10 and 20 include the adaptive digital filter of the present invention of FIG. 3 or FIG. 4. In this case, the latch unit 50 is composed of two latches 51 and 52, and may be omitted if there is a margin in clock timing, and when added, it acts as a delay of one clock on the output side as a whole. These multiple latches assist in the timing of the input signal di in a transpose type filter structure.

6 is an exemplary diagram of ASIC of an adaptive digital filter according to an embodiment of the present invention.

The microprocessor 100 provides a coefficient selection mode (cmode) or a set coefficient (ecoef) and step size. The step size error calculator 102 multiplies the error signal by the step size output from the microprocessor 100 and outputs the multiplied step size. The adaptive digital filter 108 adaptively digitally filters the input signal. The latches 104, 106, 110, and 112 are used to adjust the timing by connecting to the input / output side of the adaptive digital filter 108. Here, the interface unit for external coefficient input is provided. These interfaces can be implemented in parallel or serial processing, and are commonly used, so descriptions are omitted here. (References are detailed in the ZR33072 72-TAP Video-Rate Digital Filter, ZORAN Data Book. Multiplication of error input and step_size is generally performed using a shift circuit. This can be simplified: assign step_siz as the shift amount and replace multiplication with a variable shift.

The chip implementation can be simplified by omitting the microprocessor interface in FIG. 6, which is a useful structure when a simplified chip implementation is needed because the micro interface part occupies a lot of hardware, and has the same result as using an internal coefficient. (Cmode = 1).

Such adaptive filters are used in fields in which adaptive algorithms such as adaptive controllers or equalizers are used. Here, an example of the equalizer will be described. For ease of explanation, only the implementation of the equalizer by connecting a plurality of Fig. 6 will be described. Basically, all of the structures of FIGS. 3 to 7 can implement the equalizer using a single or multiple. An example of the equalizer configured in this way is shown in FIG. 7. Equalizers with feedback can also be implemented in the same way.

The timing (timing matching) is 3 ^* Because of the delay of (2 If possible, include a latch associated with the center tap) 3 tabs each chip block by aligning the formula (1) or the timing of the x and e Equation (2) It should be input to N delayed input signals (udi). To simplify this, you can connect the cdo output of #N to the delayed input signal (udi) of #N. The example of FIG. 7 is an N tap equalizer that sets the center tap to the second chip block and rounds the remaining coefficients. These values can be changed as needed. If there is a reference signal, an error detector detects an error by using a difference between the reference signal and the output. In digital communication, an error in determining an input signal may be used. Decision feedback equalizers, which are commonly used, can be implemented in the same manner.

As described above, the present invention operates the coefficient update loop in conjunction with external coefficient loading in the adaptive digital filter, prevents the center tap setting and the divergence of coefficients, and uses the reference signal sequence existing in the field synchronization to stably initialize the present invention. The loop can be driven by obtaining the coefficient of the state or the required state, and there is also the advantage of preventing divergence in order to prevent the non-ideal increase of the loop output in the adaptive digital filter.

Claims (4)

In the adaptive digital filter, A multiplier for multiplying a predetermined clock delayed output data (udo), a step size and a calculated error signal (u-err), an adder for adding and outputting the output signal of the multiplier and the predetermined clock delayed signal, and a set coefficient A mux for selecting and outputting one of the values ecoef and the signal output from the adder by a coefficient selection mode cmode, and a delayer for outputting a coefficient update value by delaying a signal output from the MUX by a predetermined clock; Adaptive digital filter characterized by generating a filter tap coefficient. In the adaptive digital filter, A first delayer for delaying and outputting the delayed input signal udi by a predetermined clock; And a first adder for adding and outputting an output signal of the first multiplier and a signal delayed by a predetermined clock from the first delayer, and a predetermined coefficient value ecoef and a signal output from the first adder. and a second delay unit for outputting a coefficient update value by delaying a signal output from the MUX by a predetermined clock, and a coefficient update value and an input signal (output from the second delay unit). a second multiplier that multiplies di), a second adder that adds and outputs a signal multiplied by the second multiplier and a cascade input data cdi, and a signal output from the second adder Delay to the adaptive digital filter, it characterized in that the connection of a plurality of filter tap consisting of a third delay for outputting a digital filtered signal (do) in series. In the adaptive digital filter, A first delayer for delaying and outputting the delayed input signal udi by a predetermined clock, and a first multiplier for multiplying the output data delayed by a predetermined clock, the step size, and the calculated error signal u-err from the first delayer And a first adder for adding and outputting an output signal of the first multiplier and a signal delayed by a predetermined clock from the first delayer, and a predetermined coefficient value ecoef and a signal output from the first adder. cmode), a first MUX which selects and outputs one, a second delayer which outputs a coefficient update value by delaying a signal output from the first MUX by a predetermined clock, and a coefficient update value output from the second delayer. A second limiter which selects one by a divcon and outputs a coefficient update value limited from the rounder and a coefficient update value output from the second delay unit; A second multiplier that multiplies the coefficient update value selected from the second MUX by an input signal di, a second adder that adds and outputs the multiplied signal and the cascade data cdi by the second multiplier, and the second multiplier; And a plurality of filter taps comprising a third delayer for outputting a digitally filtered signal do by delaying a signal output from the adder by a predetermined clock, in series. In the adaptive digital filter, The first filter unit having N filter taps, the second filter unit having M filter taps, and the delayed input data (udi) of the first filter unit are input as delayed output data (udo) of the second filter unit. A dopant tap control signal by inputting an adder for adding the data filtered from the first filter unit and the cascade output data cdo, and the data added from the adder and the filtered data do from the first filter unit; A MUX for selecting and outputting one by a first signal; a first delayer for delaying a cascade output data cdo output from the first filter part by a predetermined clock and applying it to the input signal di of the second filter part; And a second delayer for delaying the selected output data by a predetermined clock and applying it to the cascade input data cdi of the second filter unit.

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