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KR100247643B1 - A reaction chamber for forming metal layer and method for forming metal layer in semiconductor device using the same - Google Patents

A reaction chamber for forming metal layer and method for forming metal layer in semiconductor device using the same Download PDF

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KR100247643B1
KR100247643B1 KR1019970030370A KR19970030370A KR100247643B1 KR 100247643 B1 KR100247643 B1 KR 100247643B1 KR 1019970030370 A KR1019970030370 A KR 1019970030370A KR 19970030370 A KR19970030370 A KR 19970030370A KR 100247643 B1 KR100247643 B1 KR 100247643B1
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film
forming
titanium nitride
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nitride film
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KR19990006148A (en
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조경수
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김영환
현대전자산업주식회사
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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Abstract

본 발명은 금속 배선 형성용 반응 챔버 및 이를 이용한 반도체 소자의 금속 배선 형성방법에 관한 것으로, 보다 구체적으로는, 금속 배선간의 스트레스 및 전자들의 이동을 방지하는 베리어 금속막의 형성방법 및 베리어 금속막 형성용 반응 챔버에 관한 것이다.The present invention relates to a reaction chamber for forming a metal wiring and a method for forming a metal wiring of a semiconductor device using the same, and more particularly, to a method for forming a barrier metal film and a barrier metal film for preventing stress and movement of electrons between metal wires. It relates to a reaction chamber.

본 발명은, 전도층의 소정 부분을 노출시키는 콘택홀이 구비된 반도체 기판을 제공하는 단계; 상기 콘택홀 내부 및 반도체 기판 상부에 베리어 금속막을 형성하는 단계; 상기 콘택홀 저부의 베리어 금속막과 콘택되도록 금속 배선을 형성하는 단계를 포함하며, 상기 베리어 금속막은, 스퍼터링 방식에 의하여 제 1 티타늄 질화막을 형성하는 단계; 상기 제 1 티타늄 질화막 상부에 화학 기상 증착 방식에 의하여 제 2 티타늄 질화막을 형성하는 단계; 상기 제 2 티타늄 질화막 상부에 스퍼터링 방식에 의하여 제 3 티타늄 질화막을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention provides a semiconductor substrate having a contact hole for exposing a portion of a conductive layer; Forming a barrier metal layer in the contact hole and on the semiconductor substrate; Forming a metal wire to contact the barrier metal film at the bottom of the contact hole, wherein the barrier metal film comprises: forming a first titanium nitride film by a sputtering method; Forming a second titanium nitride film on the first titanium nitride film by chemical vapor deposition; And forming a third titanium nitride film on the second titanium nitride film by sputtering.

Description

금속 배선 형성용 반응 챔버 및 이를 이용한 반도체 소자의 금속 배선 형성방법Reaction chamber for metal wiring formation and metal wiring formation method of semiconductor device using same

본 발명은 금속 배선 형성용 반응 챔버 및 이를 이용한 반도체 소자의 금속 배선 형성방법에 관한 것으로, 보다 구체적으로는, 금속 배선간의 스트레스 및 전자들의 이동을 방지하는 베리어 금속막의 형성방법 및 이를 형성하기 위한 금속 배선 형성용 반응 챔버에 관한 것이다.The present invention relates to a reaction chamber for forming a metal wiring and a method for forming a metal wiring of a semiconductor device using the same. More specifically, a method for forming a barrier metal film for preventing stress and movement of electrons between metal wirings and a metal for forming the same The reaction chamber for wiring formation is related.

반도체 기술의 진보와 더불어 더 나아가서는 반도체 소자의 고속화, 고집적화가 진행되고 있고, 이에 수반해서 패턴에 대한 미세화의 필요성이 점점 높아지고 있으며, 또한 패턴의 칫수도 고정밀화가 요구되고 있다.In addition to the advances in semiconductor technology, the speed and integration of semiconductor devices are increasing, and the necessity of miniaturization of patterns is increasing, and the size of patterns is also required to be highly accurate.

여기서, 종래의 상층 배선과 하층 배선을 연결하기 위한 콘택 방법은, 하층 배선이 형성된 기판상에 절연막을 증착하고, 하층 배선의 소정 부분이 노출되도록 절연막을 식각하여, 콘택홀을 형성한다. 이때, 콘택홀의 사이즈는 고집적화된 반도체 소자에 적용하도록 현재의 노광 장비로 형성할 수 있는 최소 크기로 형성함이 바람직하다. 이어 콘택홀 내벽면에는 접촉 및 베리어 금속막으로 티타늄막과, 티타늄 질화막이 순차적으로 형성되고, 이 콘택홀내에 금속 배선막이 형성된다. 여기서, 베리어 금속막인 티타늄 질화막은 일반적으로 화학 기상 증착 방식 또는 스퍼터링 방식으로 형성된다.Here, in the conventional contact method for connecting the upper layer wiring and the lower layer wiring, an insulating film is deposited on the substrate on which the lower layer wiring is formed, and the insulating film is etched to expose a predetermined portion of the lower layer wiring, thereby forming a contact hole. In this case, the size of the contact hole is preferably formed to the minimum size that can be formed by the current exposure equipment to be applied to the highly integrated semiconductor device. Subsequently, a titanium film and a titanium nitride film are sequentially formed on the inner wall surface of the contact hole as a contact and barrier metal film, and a metal wiring film is formed in the contact hole. Here, the titanium nitride film, which is a barrier metal film, is generally formed by chemical vapor deposition or sputtering.

그러나, 상술한 바와 같이 티타늄 질화막을 형성하게 되면, 다음과 같은 문제점이 발생된다.However, when the titanium nitride film is formed as described above, the following problems occur.

먼저, 금속 배선간의 스트레스 및 전자 이동을 방지하기 위한 티타늄 질화막을 화학 기상 증착 방식에 의하여 형성하면, 콘택홀내의 피복 특성은 우수하나, 스퍼터링 방식에 의하여 형성된 티타늄 질화막 보다 저항이 크다. 또한, 이 화학 기상증착 공정시, 산소 원자 또는 탄소 원자가 막내에 함유하게 되어, 막질을 불안정하게 되는 문제점이 발생된다.First, when a titanium nitride film is formed by chemical vapor deposition to prevent stress and electron transfer between metal wires, the coating property in the contact hole is excellent, but the resistance is higher than that of the titanium nitride film formed by the sputtering method. In addition, in this chemical vapor deposition process, oxygen atoms or carbon atoms are contained in the film, resulting in unstable film quality.

또한, 이러한 문제점을 해결하고자, 스퍼터링 방식에 의하여 티타늄 질화막을 형성하게 되면, 미세한 사이즈를 갖는 콘택홀내에 제대로 피복이 이루어지지 않는 문제점이 발생된다.In addition, to solve this problem, when the titanium nitride film is formed by the sputtering method, there is a problem that the coating is not properly made in the contact hole having a fine size.

따라서, 본 발명은 저항이 낮으며, 피복 특성이 우수한 베리어 금속막을 형성하여 금속 배선 신뢰성을 향상할 수 있는 반도체 소자의 금속 배선 형성방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device which can improve barrier metal wiring reliability by forming a barrier metal film having low resistance and excellent coating characteristics.

또한, 본 발명은 상기한 금속 배선이 형성될 수 있는 반응 챔버를 제공하는 것을 목적으로 한다.It is also an object of the present invention to provide a reaction chamber in which the metal wiring described above can be formed.

제1a도 내지 제1c도는 본 발명에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위한 각 공정별 단면도.1A to 1C are cross-sectional views of respective processes for explaining a method for forming metal wirings of a semiconductor device according to the present invention.

제2도는 상기의 금속 배선이 이루어지는 반응 챔버를 개략적으로 나타낸 도면.2 is a view schematically showing a reaction chamber in which the metal wiring is formed.

〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

1 : 반도체 기판 2 : 제 1 전도층1 semiconductor substrate 2 first conductive layer

3 : 층간 절연막 4, 9 : 접촉 금속막3: interlayer insulating film 4, 9: contact metal film

5 : 제 1 티타늄 질화막 6 : 제 2 티타늄 질화막5: first titanium nitride film 6: second titanium nitride film

7 : 제 3 티타늄 질화막 8 : 텅스텐막7: third titanium nitride film 8: tungsten film

10 : 알루미늄 합금막 11 : 난반사 방지막10 aluminum alloy film 11 antireflection film

상기한 본 발명의 목적을 달성하기 위하여, 본 발명은, 전도층의 소정 부분을 노출시키는 콘택홀이 구비된 반도체 기판을 제공하는 단계; 상기 콘택홀 내부 및 반도체 기판 상부에 베리어 금속막을 형성하는 단계; 상기 콘택홀 저부의 베리어 금속막과 콘택되도록 금속 배선을 형성하는 단계를 포함하며, 상기 베리어 금속막은, 스퍼터링 방식에 의하여 제 1 티타늄 질화막을 형성하는 단계; 상기 제 1 티타늄 질화막 상부에 화학 기상 증착 방식에 의하여 제 2 티타늄 질화막을 형성하는 단계; 상기 제 2 티타늄 질화막 상부에 스퍼터링 방식에 의하여 제 3 티타늄 질화막을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object of the present invention, the present invention provides a semiconductor substrate having a contact hole for exposing a predetermined portion of the conductive layer; Forming a barrier metal layer in the contact hole and on the semiconductor substrate; Forming a metal wire to contact the barrier metal film at the bottom of the contact hole, wherein the barrier metal film comprises: forming a first titanium nitride film by a sputtering method; Forming a second titanium nitride film on the first titanium nitride film by chemical vapor deposition; And forming a third titanium nitride film on the second titanium nitride film by sputtering.

또한, 상기한 금속 배선을 형성하기 위한 반응 챔버는, 상기 제 1, 제 2, 제 3 티타늄 질화막을 증착하기 위한 증착 챔버들이 일정 간격을 가지며 순차적으로 위치되고, 상기 제 2 티타늄 질화막을 증착하기 위한 반응 챔버에 인접하여 배기용 펌프가 설치된다.In addition, the reaction chamber for forming the metal wiring, the deposition chambers for depositing the first, second, third titanium nitride film are sequentially positioned at a predetermined interval, and for depositing the second titanium nitride film Adjacent to the reaction chamber is an exhaust pump.

본 발명에 의하면, 베리어 금속막인 티타늄 질화막을 3층으로 구성하되, 1층과 3층은 스퍼터링 방식으로 형성하고, 2층은 화학 기상 증착 방식으로 형성하여, 베리어 금속막의 피복 특성 및 저항 특성을 개선하게 된다.According to the present invention, a titanium nitride film, which is a barrier metal film, is composed of three layers, one layer and three layers are formed by sputtering, and two layers are formed by chemical vapor deposition, thereby forming the coating and resistance characteristics of the barrier metal film. Will improve.

더불어, 상기 화학 기상 증착 방식에 티타늄 질화막의 형성시, 이 화학 기상 증착 챔버에 인접하여 반응하고 남은 가스를 신속히 배출하기 위한 펌프가 설치되어, 화학 기상 증착 방식에 의한 티타늄 질화막의 저항을 보다 낮출 수 있다.In addition, when the titanium nitride film is formed in the chemical vapor deposition method, a pump for rapidly discharging the gas remaining after reacting adjacent to the chemical vapor deposition chamber is installed to lower the resistance of the titanium nitride film by the chemical vapor deposition method. have.

[실시예]EXAMPLE

이하 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도면 도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위한 각 공정별 단면도이고, 도 2는 상기의 금속 배선이 이루어지는 반응 챔버를 개략적으로 나타낸 도면이다.1A to 1C are cross-sectional views for each process for explaining a method for forming metal wirings of a semiconductor device according to the present invention, and FIG. 2 is a view schematically illustrating a reaction chamber in which the metal wirings are formed.

먼저, 도 1a를 참조하여, 반도체 기판(1) 상에 제 1 도전층(2)이 소정 두께로 형성된다. 여기서, 반도체 기판(1)은 예를들어, 트랜지스터등의 소자 및 이를 절연시키기 위한 절연막이 구비된 실리콘 기판일 수 있다. 이어, 제 1 도전층(2) 상부에 이후에 형성된 도전층과 절연시키기 위한, 층간 절연막(3)이 형성된다. 그후, 제 1 도전층(2)의 소정 부분이 노출되도록 층간 절연막(3)이 식각되어, 콘택홀이 형성된다.First, referring to FIG. 1A, a first conductive layer 2 is formed on a semiconductor substrate 1 to a predetermined thickness. Here, the semiconductor substrate 1 may be, for example, a silicon substrate provided with a device such as a transistor and an insulating film for insulating the same. Subsequently, an interlayer insulating film 3 is formed on the first conductive layer 2 to insulate it from the conductive layer formed thereafter. Thereafter, the interlayer insulating film 3 is etched so that a predetermined portion of the first conductive layer 2 is exposed to form a contact hole.

그후, 콘택홀 내부 및 층간 절연막(3) 상부에 접촉 금속막으로 티타늄 금속막(4)과, 제 1, 제 2, 제 3 티타늄 질화막(5,6,7)이 순차적으로 증착된다. 이때, 제 1 및 제 3 티타늄 질화막(5,7)은 스퍼터링 방식에 의하여 형성되고, 제 2 티타늄 질화막(6)은 화학 기상 증착 방식에 의하여 약 600Å이하로 형성된다. 이와같이 형성하는 것은, 화학 기상 증착 방식에 의하여 형성된 티타늄 질화막(6)은 피복 특성은 우수하나 저항이 스퍼터링 방식으로 형성된 것 보다 약간 크므로, 스퍼터링 방식으로 형성된 티타늄 질화막(5,7) 사이에 개재하도록 한다. 따라서, 전도층(2)과 직접 접촉될 부분에는 스퍼터링 방식에 의하여 티타늄 질화막(5,7)이 형성되고, 그 사이에는 피복 특성을 완하시키기 위하여 화학 기상 증착 방식에 의하여 티타늄 질화막(6)이 형성되어, 피복 특성 및 전도 특성이 동시에 개선된다.Thereafter, the titanium metal film 4 and the first, second and third titanium nitride films 5, 6, and 7 are sequentially deposited as contact metal films in the contact holes and on the interlayer insulating film 3. In this case, the first and third titanium nitride films 5 and 7 are formed by the sputtering method, and the second titanium nitride film 6 is formed to about 600 kPa or less by the chemical vapor deposition method. Forming in this way, the titanium nitride film 6 formed by the chemical vapor deposition method is excellent in coating properties, but the resistance is slightly larger than that formed by the sputtering method, so as to interpose between the titanium nitride films (5, 7) formed by the sputtering method do. Therefore, the titanium nitride films 5 and 7 are formed in the portion to be in direct contact with the conductive layer 2 by the sputtering method, and the titanium nitride film 6 is formed by the chemical vapor deposition method therebetween to reduce the coating property. Thus, the coating properties and the conductive properties are improved at the same time.

그런다음, 경우에 따라, 막질의 특성을 개선하기 위하여 약 350℃이상의 온도에 열처리를 진행할 수 있다.Then, in some cases, heat treatment may be performed at a temperature of about 350 ° C. or more to improve the quality of the film.

그후, 반도체 기판(1) 상부에는 결과물이 충분히 매립되도록 텅스텐막(8)이 증착된다. 이때, 텅스텐막(8) 대신 다른 금속막 예를들어, 구리막, 알루미늄막등이 이용될 수 있다.Thereafter, a tungsten film 8 is deposited on the semiconductor substrate 1 so that the resultant material is sufficiently embedded. In this case, instead of the tungsten film 8, another metal film, for example, a copper film or an aluminum film, may be used.

그리고나서, 도 1b에 도시된 바와 같이, 텅스텐막(8)은 층간 절연막(3) 상의 제 2 티타늄 질화막(6) 표면이 노출되도록 화학적 기계적 연마하여 텅스텐 플러그를 형성한다. 이때, 제 2 티타늄 질화막(6)을 연마 저지점으로 하는 것은, 화학 기상 증착 방식에 의하여 형성된 막이 비교적 막질이 단단하기 때문이다.Then, as shown in FIG. 1B, the tungsten film 8 is chemically mechanically polished to expose the surface of the second titanium nitride film 6 on the interlayer insulating film 3 to form a tungsten plug. At this time, the second titanium nitride film 6 is the polishing stop point because the film formed by the chemical vapor deposition method is relatively hard in film quality.

이어서, 도 1c에 도시된 바와 같이, 플러그(8) 및 층간 절연막(2) 상부에 접촉 금속막으로 티타늄막(9)과 배선용 알루미늄 합금막(10) 및 난반사 방지막(11)을 순차적으로 형성한 후, 소정 부분 패터닝하여, 제 2 전도 배선을 형성한다. 여기서, 티타늄막(9) 대신 비저항이 약 60μΩ-㎝ 정도를 전이 금속막 예를들어, 탄탈륨막, 코발트막, 팔라티늄막등이 이용될 수 있다.Subsequently, as shown in FIG. 1C, a titanium film 9, an aluminum alloy film 10 for wiring, and an antireflection film 11 are sequentially formed of a contact metal film on the plug 8 and the interlayer insulating film 2. Subsequently, predetermined partial patterning is performed to form second conductive wiring. Here, instead of the titanium film 9, a transition metal film having a specific resistance of about 60 μΩ-cm, for example, a tantalum film, a cobalt film, a palladium film, or the like may be used.

도 2는 상기와 같은 전도 배선이 형성되는 반응 챔버로서, 도면 부호 21과 22는 입,출력 로드락 챔버이고, 여기서, 입출력 로드락 챔버(21,22)의 양측에는 다수개의 반응 챔버(23,24,25,26,27)들이 소정 간격을 두고 연달아 배치되어 있다. 즉, 이들 반응 챔버(23,24,25,26,27)들을 거치어, 상기한 금속 배선막, 층간 절연막, 티타늄막, 티타늄 질화막, 금속 배선막등이 증착되어 진다. 이 반응 챔버(23,24,25,26,27)각각에는 증착시 가스 유량을 조절하기 위한 밸브(20)가 설치되어 있다.2 is a reaction chamber in which the conductive wiring as described above is formed, and reference numerals 21 and 22 denote input and output load lock chambers, and the reaction chambers 23 and 22 are provided on both sides of the input / output load lock chambers 21 and 22. 24, 25, 26, 27 are arranged in succession at predetermined intervals. That is, the metal wiring film, the interlayer insulating film, the titanium film, the titanium nitride film, the metal wiring film and the like are deposited through these reaction chambers 23, 24, 25, 26 and 27. Each of the reaction chambers 23, 24, 25, 26, and 27 is provided with a valve 20 for adjusting the gas flow rate during deposition.

또한, 본 발명에서는 제 2 티타늄 질화막(6)이 형성되는 챔버(26) 즉, 화학 기상 증착 챔버의 밸브 앞측에 펌프(29)를 설치하여, 미반응된 개스를 용이하게 제거하도록 한다. 이는 제 2 티타늄 질화막(6)의 형성시 발생되는 산소 및 탄소 원자를 용이하게 제거하여, 막 저항을 낮추기 위함이다.In addition, in the present invention, a pump 29 is installed in the chamber 26 in which the second titanium nitride film 6 is formed, that is, in front of the valve of the chemical vapor deposition chamber, to easily remove unreacted gas. This is to easily remove oxygen and carbon atoms generated when the second titanium nitride film 6 is formed, thereby lowering the film resistance.

이상에서 자세히 설명된 바와 같이, 본 발명에 의하면 베리어 금속막인 티타늄 질화막을 3층으로 구성하되, 1층과 3층은 저항이 낮은 스퍼터링 방식으로 형성하고, 2층은 피복 특성이 우수한 화학 기상 증착 방식으로 형성하여, 베리어 금속막의 피복 특성 및 저항 특성을 동시에 개선하게 된다.As described in detail above, according to the present invention, the titanium nitride film, which is a barrier metal film, is composed of three layers, one layer and three layers are formed by a low resistance sputtering method, and the two layers are chemical vapor deposition with excellent coating properties. By forming in such a manner, the coating property and the resistance property of the barrier metal film can be improved simultaneously.

더불어, 상기 화학 기상 증착 방식에 의한 티타늄 질화막의 형성시, 이 화학 기상 증착 챔버에 인접하여 반응하고 남은 가스를 신속히 배출하기 위한 펌프가 설치되어, 화학 기상 증착 방식에 의한 티타늄 질화막의 저항을 보다 낮출 수 있다.In addition, when the titanium nitride film is formed by the chemical vapor deposition method, a pump for quickly discharging the gas remaining after reacting adjacent to the chemical vapor deposition chamber is installed to lower the resistance of the titanium nitride film by the chemical vapor deposition method. Can be.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (8)

전도층의 소정 부분을 노출시키는 콘택홀이 구비된 반도체 기판을 제공하는 단계; 상기 콘택홀 내부 및 반도체 기판 상부에 베리어 금속막을 형성하는 단계; 상기 콘택홀 저부의 베리어 금속막과 콘택되도록 금속 배선을 형성하는 단계를 포함하며, 상기 베리어 금속막은, 스퍼터링 방식에 의하여 제 1 티타늄 질화막을 형성하는 단계; 상기 제 1 티타늄 질화막 상부에 화학 기상 증착 방식에 의하여 제 2 티타늄 질화막을 형성하는 단계; 상기 제 2 티타늄 질화막 상부에 스퍼터링 방식에 의하여 제 3 티타늄 질화막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.Providing a semiconductor substrate having a contact hole exposing a predetermined portion of the conductive layer; Forming a barrier metal layer in the contact hole and on the semiconductor substrate; Forming a metal wire to contact the barrier metal film at the bottom of the contact hole, wherein the barrier metal film comprises: forming a first titanium nitride film by a sputtering method; Forming a second titanium nitride film on the first titanium nitride film by chemical vapor deposition; Forming a third titanium nitride film on the second titanium nitride film by a sputtering method. 제1항에 있어서, 상기 베리어 금속막을 형성하는 단계 이전에, 상기 콘택홀 내부 및 반도체 기판 상부에 접촉 금속막을 형성하는 단계를 부가적으로 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The method of claim 1, further comprising forming a contact metal film in the contact hole and on the semiconductor substrate before the forming of the barrier metal film. 제1항에 있어서, 상기 금속 배선을 형성하는 단계는, 상기 콘택홀내에만 플러그 금속막을 형성하는 단계; 상기 플러그 금속막과 콘택되도록 알루미늄 합금막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The method of claim 1, wherein the forming of the metal line comprises: forming a plug metal layer only in the contact hole; Forming an aluminum alloy film to be in contact with the plug metal film. 제3항에 있어서, 상기 플러그 금속막을 형성하는 단계와, 알루미늄 합금막을 형성하는 단계 사이에 접촉 금속막을 형성하는 단계를 부가적으로 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.4. The method of claim 3, further comprising forming a contact metal film between forming the plug metal film and forming the aluminum alloy film. 제2항 또는 제4항에 있어서, 상기 접촉 금속막은 티타늄막, 탄탈륨막, 코발트막, 팔라티늄막과 같은 전이 금속막 중 선택되는 하나의 막으로 형성되는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The metal wire formation of the semiconductor device according to claim 2 or 4, wherein the contact metal film is formed of one film selected from transition metal films such as titanium film, tantalum film, cobalt film, and palladium film. Way. 제1항 또는 제4항에 있어서, 상기 플러그 금속막을 형성하는 단계는, 상기 반도체 기판 구조물이 충분히 매립되도록 금속막을 증착하는 단계; 상기 금속막을 상기 제 2 티타늄 질화막 표면이 노출되도록 화학적 기계적 연마하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The method of claim 1, wherein the forming of the plug metal film comprises: depositing a metal film to sufficiently fill the semiconductor substrate structure; Chemical mechanical polishing the metal film to expose the surface of the second titanium nitride film. 제1항 기재의 반도체 소자의 금속 배선을 형성하는 반응 챔버로서, 상기 제 1, 제 2, 제 3 티타늄 질화막을 증착하기 위한 증착 챔버들이 일정간격을 가지며 순차적으로 위치되고, 상기 제 2 티타늄 질화막을 증착하기 위한 반응 챔버에 인접하여 배기용 펌프가 설치된 것을 특징으로 하는 금속 배선용 반응 챔버.A reaction chamber for forming a metal wiring of the semiconductor device according to claim 1, wherein deposition chambers for depositing the first, second, and third titanium nitride films are sequentially positioned at a predetermined interval, and the second titanium nitride film is formed. A reaction chamber for metal wiring, wherein an exhaust pump is provided adjacent to the reaction chamber for depositing. 제7항에 있어서, 상기 제 2 티타늄 질화막을 증착하기 위한 챔버는 화학 기상 증착 챔버인 것을 특징으로 하는 금속 배선용 반응 챔버.8. The reaction chamber of claim 7, wherein the chamber for depositing the second titanium nitride film is a chemical vapor deposition chamber.
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