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KR100265832B1 - A method for forming self aligned contact hole in semiconductor device - Google Patents

A method for forming self aligned contact hole in semiconductor device Download PDF

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KR100265832B1
KR100265832B1 KR1019970027877A KR19970027877A KR100265832B1 KR 100265832 B1 KR100265832 B1 KR 100265832B1 KR 1019970027877 A KR1019970027877 A KR 1019970027877A KR 19970027877 A KR19970027877 A KR 19970027877A KR 100265832 B1 KR100265832 B1 KR 100265832B1
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forming
contact hole
film
semiconductor device
gate
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KR19990003914A (en
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김도우
장경식
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

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  • Computer Hardware Design (AREA)
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Abstract

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 장치의 소오스/드레인 콘택홀을 자기정렬 방식으로 형성하는 방법에 관한 것이며, 게이트 전극과 소오스/드레인 콘택의 단락을 방지하면서 콘택홀 식각시의 공정 마진을 확보할 수 있는 자기정렬 콘택홀을 형성하는 반도체 장치 제조방법을 제공하는데 그 목적이 있다. 본 발명의 특징적인 반도체 장치 제조방법은, 반도체 기판 상에 차례로 적층된 게이트 절연막, 게이트 전극 및 마스크 절연막과, 게이트 측벽 스페이서를 포함하는 게이트 구조를 형성하는 제1 단계; 상기 제1 단계를 마친 전체 구조 표면을 따라 베리어 질화막을 증착하되, 상기 베리어 질화막 내부에 적어도 한 층의 폴리실리콘 박막이 포함되도록 하는 제2 단계; 상기 제2 단계를 마친 전체 구조 상부에 층간절연 산화막을 형성하는 제3 단계; 및 콘택홀 형성을 위한 마스크를 사용하여 상기 층간절연 산화막, 상기 베리어 질화막을 선택 식각하여 자기정렬 콘택홀을 형성하는 제4 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technology, and more particularly, to a method of forming a source / drain contact hole of a semiconductor device in a self-aligned manner, and to a process margin during contact hole etching while preventing a short between a gate electrode and a source / drain contact. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device for forming a self-aligned contact hole capable of securing a gap. A characteristic semiconductor device manufacturing method of the present invention includes a first step of forming a gate structure including a gate insulating film, a gate electrode and a mask insulating film sequentially stacked on a semiconductor substrate, and a gate sidewall spacer; Depositing a barrier nitride film along the entire structure surface after the first step, wherein at least one layer of polysilicon thin film is included in the barrier nitride film; A third step of forming an interlayer insulating oxide film on the entire structure after the second step; And forming a self-aligning contact hole by selectively etching the interlayer insulating oxide layer and the barrier nitride layer using a mask for forming a contact hole.

Description

반도체 장치의 자기정렬 콘택홀 형성방법{A method for forming self aligned contact hole in semiconductor device}A method for forming self aligned contact hole in semiconductor device

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 장치의 소오스/드레인 콘택홀을 자기정렬 방식으로 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a method of forming a source / drain contact hole of a semiconductor device in a self-aligning manner.

일반적으로, 반도체 장치의 고집적화에 따라 패턴의 선폭 및 패턴간의 거리가 좁아지고 있어 콘택홀 형성시 공정 마진이 줄어들고 있다.In general, as the integration of semiconductor devices increases, the line width of the pattern and the distance between the patterns are narrowed, thereby reducing the process margin when forming the contact hole.

이하, 첨부된 도면 도 1을 참조하여 종래기술 및 그 문제점을 살펴본다.Hereinafter, with reference to the accompanying drawings Figure 1 looks at the prior art and its problems.

종래의 자기정렬 콘택홀 형성 공정은, 우선 실리콘 기판(10) 상에 게이트 산화막(11), 게이트 전극(12) 및 마스크 산화막(13)이 적층된 게이트 구조를 형성하고, 저농도 도핑 드레인(lightly doped drain) 형성을 위한 저농도 불순물 이온주입을 실시한다. 계속하여, 전체구조 상부에 스페이서 형성을 위한 산화막을 화학기상증착 방식을 사용하여 증착하고 이를 전면성 건식 식각하여 게이트 측벽 부위에 스페이서 산화막(14)을 형성한 다음, 소오스/드레인 형성을 위한 고농도 불순물 이온주입을 실시한다.The conventional self-aligned contact hole forming process first forms a gate structure in which the gate oxide film 11, the gate electrode 12, and the mask oxide film 13 are stacked on the silicon substrate 10, and is lightly doped. Low concentration impurity ion implantation is performed to form drain. Subsequently, an oxide film for forming a spacer is formed on the entire structure by chemical vapor deposition, and the entire surface is dry etched to form a spacer oxide film 14 on the gate sidewall, and then a high concentration impurity for source / drain formation is formed. Ion implantation is performed.

계속하여, 전체구조 상부에 질화막(Si3N4)(15)을 증착하고, 그 상부에 평탄화된 층간절연 산화막(16)을 형성한 다음, 콘택홀 형성을 위한 마스크(도시되지 않음)를 사용하되, 층간절연 산화막(16) 및 질화막(15)의 식각 선택비를 이용하여 식각을 수행함으로써 자기정렬 콘택홀을 형성한다.Subsequently, a nitride film (Si 3 N 4 ) 15 is deposited on the entire structure, and a planarized interlayer insulating oxide film 16 is formed thereon, and then a mask (not shown) for forming a contact hole is used. However, the self-aligned contact hole is formed by performing etching using the etching selectivity of the interlayer insulating oxide layer 16 and the nitride layer 15.

상기와 같은 종래의 자기정렬 콘택홀 형성 공정을 통상 질화막 베리어 SAC 공정이라 명하고 있다. 질화막 베리어 SAC 공정은 질화막과 산화막의 식각 선택비를 이용하여 SAC 공정이 기본적으로 가지는 오버랩 마진의 확보와 더불어 실리콘 기판(10)의 식각 손상을 완화시키고 전체적인 공정 마진을 개선하고자 하는 것이다.The conventional self-aligned contact hole forming process as described above is generally referred to as a nitride film barrier SAC process. The nitride barrier SAC process is to reduce the etching damage of the silicon substrate 10 and improve the overall process margin by securing the overlap margin of the SAC process by using the etching selectivity of the nitride film and the oxide film.

그러나, 상기와 같은 종래의 질화막 베리어 SAC 공정은 오정렬 발생이나 의도에 의해 콘택홀이 게이트 구조 상부에 오버랩 되는 경우, 게이트 구조에 의한 단차 때문에 콘택홀 형성을 위한 층간절연 산화막(16) 식각시 게이트 전극(12) 상부의 질화막(15)이 식각되고, 이후 실리콘 기판(10)이 노출되어 콘택홀 식각 공정이 완료된 시점에서는 게이트 전극(12)의 일부가 노출되어 콘택과의 단락이 일어나는 문제점이 있었다.However, in the conventional nitride film barrier SAC process as described above, when the contact hole overlaps the upper portion of the gate structure due to misalignment or intention, the gate electrode is etched when the interlayer dielectric oxide film 16 is formed to form the contact hole due to the step difference caused by the gate structure. (12) When the upper nitride film 15 is etched, and then the silicon substrate 10 is exposed and the contact hole etching process is completed, a part of the gate electrode 12 is exposed to cause a short circuit with the contact.

이는 층간절연 산화막(16)을 구성하는 산화막과 질화막(15)의 식각 선택비가 통상 10 : 1 정도로 낮은 것에 기인한 것이다. 즉, 콘택홀 영역의 층간절연 산화막(16)의 식각이 진행되는 도중 게이트 구조 상부의 질화막(15)이 노출되면 나머지 영역의 층간절연 산화막(16)이 식각되는 동안 게이트 구조 상부의 질화막(15)의 큰 손실이 유발되는데 따른 것이다.This is because the etching selectivity of the oxide film and the nitride film 15 constituting the interlayer insulating oxide film 16 is usually as low as 10: 1. That is, if the nitride film 15 in the upper portion of the gate structure is exposed while the interlayer insulating oxide layer 16 in the contact hole region is etched, the nitride layer 15 in the upper gate structure is etched while the interlayer insulating oxide layer 16 in the remaining region is etched. This is caused by a large loss of.

본 발명은 게이트 전극과 소오스/드레인 콘택의 단락을 방지하면서 콘택홀 식각시의 공정 마진을 확보할 수 있는 자기정렬 콘택홀을 형성하는 반도체 장치 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device for forming a self-aligned contact hole capable of securing a process margin during contact hole etching while preventing a short between a gate electrode and a source / drain contact.

도 1a 내지 도 1c는 종래기술에 따른 자기정렬 콘택홀 형성 공정도.1A to 1C illustrate a process for forming a self-aligned contact hole according to the prior art.

도 2a 내지 도 2e는 본 발명의 일 실시예에 따른 자기정렬 콘택홀 형성 공정도.2A to 2E are diagrams illustrating a process of forming a self-aligned contact hole according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

20 : 실리콘 기판 21 : 게이트 산화막20 silicon substrate 21 gate oxide film

22 : 게이트 전극 23 : 마스크 산화막22 gate electrode 23 mask oxide film

24 : 스페이서 산화막 25, 27, 29 : 질화막24: spacer oxide film 25, 27, 29: nitride film

26, 28 : 폴리실리콘막26, 28: polysilicon film

상기의 기술적 과제를 달성하기 위한 본 발명의 특징적인 반도체 장치 제조방법은, 반도체 기판 상에 차례로 적층된 게이트 절연막, 게이트 전극 및 마스크 절연막과, 게이트 측벽 스페이서를 포함하는 게이트 구조를 형성하는 제1 단계; 상기 제1 단계를 마친 전체 구조 표면을 따라 베리어 질화막을 증착하되, 상기 베리어 질화막 내부에 적어도 한 층의 폴리실리콘 박막이 포함되도록 하는 제2 단계; 상기 제2 단계를 마친 전체 구조 상부에 층간절연 산화막을 형성하는 제3 단계; 및 콘택홀 형성을 위한 마스크를 사용하여 상기 층간절연 산화막, 상기 베리어 질화막을 선택 식각하여 자기정렬 콘택홀을 형성하는 제4 단계를 포함하여 이루어진다.A technical semiconductor device manufacturing method of the present invention for achieving the above technical problem is a first step of forming a gate structure comprising a gate insulating film, a gate electrode and a mask insulating film, and gate sidewall spacers sequentially stacked on a semiconductor substrate ; Depositing a barrier nitride film along the entire structure surface after the first step, wherein at least one layer of polysilicon thin film is included in the barrier nitride film; A third step of forming an interlayer insulating oxide film on the entire structure after the second step; And forming a self-aligning contact hole by selectively etching the interlayer insulating oxide layer and the barrier nitride layer using a mask for forming a contact hole.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

첨부된 도면 도 2a 내지 도 2e는 본 발명의 일 실시예에 따른 질화막 베리어 SAC 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.2A to 2E illustrate a nitride film barrier SAC process according to an embodiment of the present invention, which will be described with reference to the following.

본 실시예에 따른 자기정렬 콘택홀 형성 공정은, 우선 도 2a에 도시된 바와 같이 실리콘 기판(20) 상에 게이트 산화막(21), 게이트 전극(22) 및 마스크 산화막(23)이 차례로 적층된 게이트 구조를 형성한다. 계속하여, 전체구조 상부에 스페이서 형성을 위한 산화막을 증착하고, 이를 전면성 건식 식각하여 게이트 측벽 부위에 스페이서 산화막(24)을 형성한다. 여기서, LDD 구조 형성을 위한 저농도 불순물 이온주입 및 후속 고농도 불순물 이온주입 공정은 종래기술과 다르지 않기 때문에 따로 설명하지는 않기로 한다.In the self-aligned contact hole forming process according to the present embodiment, first, as shown in FIG. 2A, a gate in which a gate oxide film 21, a gate electrode 22, and a mask oxide film 23 are sequentially stacked on a silicon substrate 20. To form a structure. Subsequently, an oxide film for forming a spacer is deposited on the entire structure, and the entire surface is dry-etched to form a spacer oxide film 24 on the gate sidewall portion. Here, the low concentration impurity ion implantation and subsequent high concentration impurity ion implantation processes for forming the LDD structure will not be described separately because they are not different from the prior art.

다음으로, 도 2b에 도시된 바와 같이 전체구조 상부에 질화막(Si3N4)(25)을 100∼300Å 두께로 증착하고, 그 상부에 20∼30Å 두께의 폴리실리콘막(26)을 증착한다. 일반적으로, 질화막은 SiH4가스와 NH3가스를 주 반응 가스로 하여 증착하게 되는데 질화막(25) 증착을 소정 두께만큼 진행하다가 인-시츄(in-situ)로 NH3가스의 공급을 중단하거나 공급을 감소시켜 증착을 진행함으로써 질화막(25) 상부에 원하는 두께의 폴리실리콘막(26)이 증착되도록 할 수 있다.Next, as illustrated in FIG. 2B, a nitride film (Si 3 N 4 ) 25 is deposited to have a thickness of 100 to 300 mW on the entire structure, and a polysilicon film 26 having a thickness of 20 to 30 mW is deposited thereon. . In general, the nitride film is deposited using SiH 4 gas and NH 3 gas as the main reaction gas. The deposition of the nitride film 25 is performed by a predetermined thickness, and the supply of NH 3 gas is stopped or supplied in-situ. By reducing the deposition process, the polysilicon film 26 having a desired thickness may be deposited on the nitride film 25.

이어서, 도 2c에 도시된 바와 같이 NH4가스의 공급을 조절하여 폴리실리콘막(26) 상부에 질화막(27), 폴리실리콘막(28), 질화막(29)이 차례로 증착되도록 한다. 이때, 적층되는 질화막 및 폴리실리콘막의 수와 두께는 필요에 따라 결정한다.Subsequently, as shown in FIG. 2C, the supply of NH 4 gas is controlled so that the nitride film 27, the polysilicon film 28, and the nitride film 29 are sequentially deposited on the polysilicon film 26. At this time, the number and thickness of the nitride film and polysilicon film laminated | stacked are determined as needed.

다음으로, 도 2d에 도시된 바와 같이 전체구조 상부에 평탄화된 층간절연 산화막(30)을 증착한다. 여기서, 층간절연 산화막(30)은 평탄화를 고려하여 단층 또는 다층으로 형성할 수 있다. 계속하여, 콘택홀 형성을 위한 마스크를 사용하여 콘택홀 식각을 수행한다. 이때, 층간절연 산화막(30)의 식각이 진행되면서 종래와 같이 게이트 구조 상부에 오버랩 된 질화막(29)의 손실이 일어나 폴리실리콘막(28)이 노출되는데, 폴리실리콘막(28)은 질화막(29)에 비해 층간절연 산화막(30)과의 식각 선택비가 매우 크기 때문에 베리어로서의 역할을 충분히 수행할 수 있다.Next, as shown in FIG. 2D, a planarized interlayer insulating oxide film 30 is deposited on the entire structure. Here, the interlayer insulating oxide film 30 may be formed in a single layer or multiple layers in consideration of planarization. Subsequently, contact hole etching is performed using a mask for forming contact holes. At this time, as the interlayer insulating oxide film 30 is etched, loss of the nitride film 29 overlapping the gate structure occurs as in the prior art, and thus the polysilicon film 28 is exposed, and the polysilicon film 28 is formed of the nitride film 29. Compared with), the etching selectivity with the interlayer insulating oxide film 30 is very large, and thus it can fully function as a barrier.

이와 같은 원리로 최하단의 폴리실리콘막(26) 및 질화막(25)이 잔류할 때까지 식각을 수행하게 되면, 마스크 산화막(23) 상부의 질화막(25)이 손실될 염려가 없으므로, 도 2e에 도시된 바와 같이 게이트 전극(22)과 후속 공정에 의해 형성되는 콘택과 단락의 우려가 없는 자기정렬 콘택을 형성할 수 있게 된다.If etching is performed until the lowest polysilicon film 26 and nitride film 25 remain on the same principle, there is no fear that the nitride film 25 on the mask oxide film 23 will be lost. As described above, the contacts formed by the gate electrode 22 and subsequent processes and self-aligned contacts without fear of a short circuit can be formed.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

예컨대, 전술한 실시예에서는 질화막과 폴리실리콘막을 인-시츄(in-situ) 방식을 통해 증착하는 경우를 일례로 들어 설명하였으나, 상황에 따라서 별도의 챔버에서 증착을 수행할 수도 있다.For example, in the above-described embodiment, a case where the nitride film and the polysilicon film are deposited by an in-situ method has been described as an example. However, depending on the situation, the deposition may be performed in a separate chamber.

전술한 본 발명은 게이트 전극과 콘택의 단락을 방지할 수 있는 자기정렬 방식으로 소오스/드레인 콘택홀을 형성함으로써 공정 마진을 확보하고, 이로 인하여 고집적 반도체 장치의 제조에 적용될 수 있다.The present invention described above can secure a process margin by forming a source / drain contact hole in a self-aligned manner that can prevent a short circuit between the gate electrode and the contact, and thus can be applied to the manufacture of a highly integrated semiconductor device.

Claims (6)

반도체 기판 상에 차례로 적층된 게이트 절연막, 게이트 전극 및 마스크 절연막과, 게이트 측벽 스페이서를 포함하는 게이트 구조를 형성하는 제1 단계;A first step of forming a gate structure including a gate insulating film, a gate electrode and a mask insulating film sequentially stacked on a semiconductor substrate, and a gate sidewall spacer; 상기 제1 단계를 마친 전체 구조 표면을 따라 베리어 질화막을 증착하되, 상기 베리어 질화막 내부에 적어도 한 층의 폴리실리콘 박막이 포함되도록 하는 제2 단계;Depositing a barrier nitride film along the entire structure surface after the first step, wherein at least one layer of polysilicon thin film is included in the barrier nitride film; 상기 제2 단계를 마친 전체 구조 상부에 층간절연 산화막을 형성하는 제3 단계; 및A third step of forming an interlayer insulating oxide film on the entire structure after the second step; And 콘택홀 형성을 위한 마스크를 사용하여 상기 층간절연 산화막, 상기 베리어 질화막을 선택 식각하여 자기정렬 콘택홀을 형성하는 제4 단계A fourth step of forming a self-aligned contact hole by selectively etching the interlayer insulating oxide film and the barrier nitride film using a mask for forming a contact hole 를 포함하여 이루어진 반도체 장치 제조방법.A semiconductor device manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 자기정렬 콘택홀은,The self-aligned contact hole, 그 일부가 상기 게이트 구조와 오버랩 되도록 형성하는 것을 특징으로 하는 반도체 장치 제조방법.And a part thereof overlapping with the gate structure. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 제2 단계는,The second step, SiH4가스와 NH3가스를 주 반응 가스로 하여 질화막을 증착하는 제5 단계와,A fifth step of depositing a nitride film using SiH 4 gas and NH 3 gas as main reaction gases; 상기 NH3가스의 공급을 중단하거나 감소시켜 상기 질화막 상부에 폴리실리콘막이 증착되도록 하는 제6 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 장치 제조방법.And a sixth step of stopping or reducing supply of the NH 3 gas to deposit a polysilicon film on the nitride film. 제3항에 있어서,The method of claim 3, 상기 질화막은,The nitride film, 100∼300Å 두께인 것을 특징으로 하는 반도체 장치 제조방법.It is 100-300 micrometers thick, The semiconductor device manufacturing method characterized by the above-mentioned. 제3항에 있어서,The method of claim 3, 상기 폴리실리콘 박막은,The polysilicon thin film, 20∼30Å 두께인 것을 특징으로 하는 반도체 장치 제조방법.It is 20-30 micrometers thick, The semiconductor device manufacturing method characterized by the above-mentioned. 제3항에 있어서,The method of claim 3, 상기 마스크 절연막 및 상기 게이트 측벽 스페이서는,The mask insulating film and the gate sidewall spacer, 산화막인 것을 특징으로 하는 반도체 장치 제조방법.It is an oxide film, The semiconductor device manufacturing method characterized by the above-mentioned.
KR1019970027877A 1997-06-26 1997-06-26 A method for forming self aligned contact hole in semiconductor device Expired - Fee Related KR100265832B1 (en)

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