KR100359773B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention provides a method for manufacturing a semiconductor device suitable for inducing an electric field reduction at the edge of the active region so that no current flows in the off state. And a field region, patterning a gate material layer on a predetermined portion of the active region, forming a mask having an open region where the active region is exposed, and exposing the exposed gate material layer and active layer. And a step of forming a gate electrode, a source, and a drain region by doping a region having an opposite conductivity type with that of the semiconductor substrate.

Description

Semiconductor device manufacturing method {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a method for manufacturing a highly integrated semiconductor device.

In general, as the integration of semiconductor devices proceeds, design rules decrease, and cell sizes such as gate electrodes and channel lengths are decreasing.

However, there is a limitation in reducing the cell size for high integration, and there should be no problem in the operation and reliability of the device even if the cell size is reduced.

In particular, since the width of the gate electrode is very narrow in the case of the ultra-small semiconductor device, there are problems caused by it.

One problem is the Gate Induced Drain Leakage (GIDL).

This occurs in a narrow trench isolation structure, which occurs in a three-dimensional region between the edge of the trench and the gate and drain.

In general, an electric field is generated at an overlap portion between the gate and the drain. As a trench isolation structure is employed, the edge portion of the trench is formed by the GIDL at the edge portion of the trench, rather than the electric field in the two-dimensional region between the gate and the drain. The electric field in the three-dimensional region between the gate and the drain appears much higher.

Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

First, the prior art is a method of doping a poly gate when forming a MOS (MOS) device, such as NMOS, PMOS or CMOS, of which poly gate doping method according to the CMOS device is shown in Figs.

As shown in FIG. 1A, a region A in which a PMOS device is to be formed and a region B in which an NMOS device is to be formed are defined.

The first active region 11 and the second active region 11a which are isolated from each other by the device isolation region formed by the trench isolation process are defined.

Here, the first active region 11 is an active region of the PMOS element, and the second active region 11a is an active region of the NMOS element.

Subsequently, after forming a polysilicon layer not doped with impurities on the entire surface, the poly gate 12 is formed in a direction crossing the first and second active regions 11 and 11a.

Thereafter, a process of doping an impurity into the poly gate 12 is performed. The impurity doping may be performed by separately doping the poly gate 12 only and at the time of source / drain impurity ion implantation.

Typically, the concentration of impurities doped in the poly gate is higher than the concentration of the impurities for the source / drain. Therefore, when the poly gate and the source / drain are doped in separate processes, the concentration of the source / drain impurity is lower than that of the poly gate.

However, when the poly gate is doped at the time of source / drain impurity ion implantation, the concentration of the source / drain impurity must be higher than the usual concentration. That is, since the concentration of the source / drain impurity alone does not sufficiently satisfy the doping concentration of the poly gate, the concentration of the source / drain impurity must be higher than the conventional concentration to satisfy the doping concentration of the poly gate. do.

In the prior art, the poly gate is doped at the time of source / drain impurity implantation. As shown in FIG. 1A, after the poly gate 12 is formed, a region A on which the PMOS device is to be formed is exposed. 1 Mask 13 is formed.

That is, as shown in FIG. 1A, after forming the first mask 13 to expose only the region A in which the PMOS device is to be formed, the poly gate 12 and The first active region 11 is doped.

Accordingly, impurities are doped in the exposed poly gate 12, and impurities are also doped in the first active regions 11 on both sides thereof to form source / drain impurity regions 14 and 15 of the PMOS.

In this case, the implanted impurities use B or BF ₂ ions.

Thereafter, as shown in FIG. 1B, after the first mask 13 is removed, the second mask 16 is formed to expose only the portion B where the NMOS device is to be formed, and then an N conductive impurity ion implantation is formed on the entire surface. Next, the poly gate 12 and the second active region 11a of the exposed portion are doped.

Accordingly, an N conductive impurity is doped into the poly gate 12, and an impurity is doped into the second active region 11a to form source / drain impurity regions 17 and 18 of the NMOS.

In this case, the implanted impurity uses As or P ions.

FIG. 2A is a cross-sectional view taken along the line II ′ of FIG. 1A, and when the open region of the mask is formed as in the prior art when the poly gate is doped, an electric field is formed at the edge of the active region by the gate electrode. It shows the concentration.

FIG. 2B is a cross-sectional view taken along the line II-II ′ of FIG. 1A, and when the electric field is concentrated by the gate electrode at the edge portion of the active region, the channel is connected between the source and the drain by charges charged at the edge portion of the active region. This shows how it is formed.

The conventional method of manufacturing a semiconductor device as described above has the following problems.

As the device becomes smaller, the threshold voltage in the region becomes lower because the electric field by the gate becomes stronger in the other regions of the active region. Accordingly, current flows even when the voltage between the drain and the source is low, thereby increasing power consumption of the device. In particular, the smaller the channel width, the more serious this problem becomes.

The present invention has been made to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device suitable for inducing electric field reduction at the edge of the active region so that no current flows in the off state.

1A to 1B are layout process diagrams for explaining a method of manufacturing a semiconductor device according to the related art.

FIG. 2A is a cross-sectional view taken along line II ′ of FIG. 1A

FIG. 2B is a cross-sectional view taken along the line II-II 'of FIG. 1A

3 is a layout showing electric field generation at an edge portion of a gate;

4A to 4B are layout process diagrams for describing a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

5A through 5B are layout process diagrams for describing a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

Explanation of symbols for main parts of the drawings

31,31a: first and second active regions 32: poly gate

33,36: first and second masks 34,35: first source / drain regions

37,38: second source / drain region

A semiconductor device manufacturing method of the present invention for achieving the above object is a process for defining a semiconductor substrate as an active region and a field region, patterning a gate material layer on a predetermined portion of the active region, and the active region is exposed And forming a gate electrode, a source, and a drain region by doping the exposed gate material layer and the active region with an impurity of an opposite conductivity type to the semiconductor substrate.

First of all, the present invention is to prevent a phenomenon in which a current flows between a source and a drain even in an off state due to an increase in an electric field by a gate electrode in an active region. It is characterized by reducing the doping concentration of the gate of the region where the electric field is generated by making the mask almost the same size as the active region.

Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.

FIG. 3 is a schematic layout diagram illustrating a method of manufacturing a semiconductor device of the present invention in order to prevent an electric field from increasing in a dotted line shown in FIG. 3.

4A to 4B are layout process diagrams illustrating a method of fabricating a semiconductor device according to a first exemplary embodiment of the present invention, and relate to a method of doping polygates when forming a MOS device such as an NMOS or a PMOS or a CMOS.

For reference, the embodiment of the present invention uses a CMOS device as an example.

As shown in FIG. 4A, the semiconductor substrate is defined as a region A in which a PMOS is to be formed and a region B in which an NMOS is to be formed.

Thereafter, the device isolation region is formed using a trench isolation process to define an active region of each region, that is, a first active region 31 and a second active region 31a.

Thereafter, a polysilicon layer that is not doped with impurities is formed on the entire surface of the semiconductor substrate including the first and second active regions 31 and 31a, and then patterned to form the first active region 31 and the second active region 31a. To form a poly gate 32.

The first mask 33 is formed to dope the poly gate 32 in the region A in which the PMOS is to be formed.

In this case, an open portion of the first mask 33 exposes only the first active region 31 of the region A in which the PMOS is to be formed.

That is, in the related art, a mask is formed such that the area A including the active region and the field region on which the PMOS is to be formed is entirely exposed. Make it the same.

Of course, the open portion of the mask may be formed to be 0.1 μm larger or smaller than the size of the active region.

As described above, after the first mask 33 is formed, an impurity ion implantation of a P conductivity type is performed to dope the open poly gate 32, and the source impurity region 34 is formed in the first active region 31. And drain impurity region 35 is formed.

In this case, the implanted impurities use B or BF ₂ ions.

Subsequently, as shown in FIG. 4B, after the first mask 33 is removed, the second mask 36 is formed so that the second active region 31a of the region B in which the NMOS is to be formed is exposed. do.

Subsequently, after ion implanting impurities exposed to the second active region 31a and impurities opposite to that of the PMOS region, a diffusion process is performed to dope the poly gate 32 and simultaneously source impurity regions. 37 and the drain impurity region 38 are formed.

In this case, as the impurity implanted into the PMOS region, As or P ions are used.

Meanwhile, in the poly gate doping, it is possible to inject an impurity for poly gate doping into a region where the poly gate is to be formed before forming the polysilicon layer.

That is, the semiconductor substrate in the region where the poly gate is to be formed is previously doped with impurities, a poly gate is subsequently formed, and then the poly gate is doped by a diffusion process. Thereafter, source and drain regions are formed in the PMOS region and the NMOS region, respectively.

According to the first embodiment of the present invention as described above, impurities doped in the poly gate are laterally diffused during the diffusion process to lower the doping concentration of the poly gate edge portion.

Therefore, it is possible to prevent the formation of a channel between the source and the drain in the off state by reducing the electric field at the edge portion.

That is, conventionally, since the concentration of the poly gate is the same as that of the source / drain impurities, there is no change in the concentration at the poly gate edge even when diffusion is performed. Since the concentration of the / drain impurity diffusion region is lower, the diffusion process may cause impurities of the high concentration poly gate to diffuse toward the source or drain having a lower concentration, resulting in a lower doping concentration of the poly gate.

5A through 5B are layout process diagrams for describing a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

The second embodiment of the present invention is characterized by further reducing the open area of each mask to form a mask so that only the gate electrode on the active area is exposed.

As shown in FIG. 5A, a semiconductor substrate is defined as a region A in which a PMOS is to be formed and a region B in which an NMOS is to be formed.

Then, the first active region 31 and the second active region 31a are defined by forming the device isolation region using the trench isolation process.

Subsequently, a polysilicon layer without doping impurities is formed on the entire surface of the semiconductor substrate, and then patterned to form a poly gate 32.

The first mask 33 is formed to dope the poly gate 32 in the region A in which the PMOS is to be formed.

In this case, the first mask 33 forms an open region so that only the poly gate 32 on the first active region 31 of the region A in which the PMOS is to be formed is exposed.

That is, in the related art, a mask is formed such that an area in which a PMOS is to be formed, including an active region and a device isolation region, is completely exposed. In the first embodiment of the present invention, the open portion of the mask is substantially coincident with the active region. The second embodiment allows the open portion of the mask to be identical to the poly gate on the active region.

Of course, the open portion of the mask may be formed to be 0.1 μm larger or smaller than the exposed poly gate.

As described above, after the first mask 33 is formed, impurity ion implantation of P conductivity type is performed to dope the poly gate 32 in the open portion.

Subsequently, as shown in FIG. 5B, after the first mask 33 is removed, the poly gate 32 crossing the second active region 31a of the region B in which the NMOS is to be formed is exposed. The second mask 36 is formed.

Thereafter, the exposed poly gate is ion-implanted with impurities implanted in the PMOS region into an impurity, and a diffusion process is performed to dope the poly gate 32.

Next, although not shown in the drawing, source / drain regions are formed in the active region of the region where the PMOS is to be formed by impurity ion implantation using a mask.

After the mask is removed, an impurity is implanted into the active region of the region where the NMOS is to be formed to form a source / drain region. The semiconductor device manufacturing process according to the second embodiment of the present invention is completed.

On the other hand, the doping of the poly gate can be doped with impurities to the substrate in advance before forming the polysilicon layer.

That is, after the doping of the poly gate to the poly gate to be doped with the impurity for the poly gate, the poly gate is patterned, and then the diffusion process to diffuse the impurity into the poly gate, the source in the PMOS and NMOS region, respectively And a drain region may be formed.

As described above, the semiconductor device manufacturing method of the present invention has the following effects.

By reducing the concentration of the poly gate edge portion, the threshold voltage decreases and the electric field increases at the edge portion, thereby preventing current from flowing between the source and the drain in the off state. Therefore, power consumption can be minimized, and in particular, off current can be prevented in a device having a narrow width of the poly gate.

Claims (10)

delete delete delete delete delete Defining a first active region and a second active region in the semiconductor substrate; Patterning a gate material layer across the first active region and the second active region; Forming a first mask having an open area of the same size as the first active area so that the first active area is exposed; Implanting impurities of a first conductivity type into the exposed gate material layer and the first active region to form a first gate electrode, a first source and a drain region; After removing the first mask, forming a second mask having an open area having the same size as the second active area so that the second active area is exposed; And implanting impurities of a second conductivity type into the exposed gate material layer and the second active region to form the second gate electrode, the second source and the drain region. . delete Defining a first active region and a second active region in the semiconductor substrate; Patterning a gate material layer across the first and second active regions; Forming a first mask having an open region such that a gate material layer on the first active region is exposed; Forming a first gate electrode by doping the exposed gate material layer with impurities of a first conductivity type; After removing the first mask, forming a second mask having an open region to expose the gate material layer on the second active region; And forming a second gate electrode by doping the exposed gate material layer with a second conductivity type impurity. The method of claim 8, further comprising: forming a first source and a drain region in first active regions on both sides of the first gate electrode after forming the second gate electrode; And forming a second source and a drain region in the second active region on both sides of the second gate electrode. The semiconductor of claim 8, wherein the open regions of the first and second masks are formed to be 0.1 μm smaller or 0.1 μm larger than the size of the gate electrode on the first and second active regions, respectively. Device manufacturing method.