KR100353525B1 - Method for forming gate electrode in semiconductor device - Google Patents
Method for forming gate electrode in semiconductor device Download PDFInfo
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- KR100353525B1 KR100353525B1 KR1019990012946A KR19990012946A KR100353525B1 KR 100353525 B1 KR100353525 B1 KR 100353525B1 KR 1019990012946 A KR1019990012946 A KR 1019990012946A KR 19990012946 A KR19990012946 A KR 19990012946A KR 100353525 B1 KR100353525 B1 KR 100353525B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
- H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
- H10D64/664—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
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- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/671—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure
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Abstract
본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 고융점 금속 박막을 포함하는 게이트 전극에서, 게이트 전극 측벽에 노출된 고융점 금속 박막부분이 산화되는 것을 방지하는 반도체 소자의 게이트 전극 형성방법을 개시한다. 개시된 본 발명은, 반도체 기판 상에 게이트 절연막, 도핑된 폴리실리콘막, 확산 방지막, 고융점 금속 박막 및 난반사 방지용 산화막을 순차적으로 증착하는 단계와, 상기 난반사 방지용 산화막과 고융점 금속 박막, 확산 방지막 및 도핑된 폴리실리콘막을 소정 부분 패터닝하여 게이트 전극을 형성하는 단계와, 상기 게이트 전극의 측벽에 실리콘막과 제 1 질화막으로 된 제 1 스페이서를 형성하는 단계와, 상기 도핑된 폴리실리콘 측벽, 확산 방지막 측벽 및 난반사 방지용 산화막 측벽에 있는 실리콘막을 열산화되면서 고융점 금속 박막 측벽의 실리콘막은 실리사이드막으로 변화되도록, 반도체 기판 결과물을 열처리하는 단계와, 상기 노출된 반도체 기판에 소오스, 드레인용 저농도 불순물을 이온 주입하는 단계와, 상기 제 1 실리콘 질화막 양측에 제 2 실리콘 질화막으로 된 제 2 스페이서를 형성하는 단계, 및 상기 노출된 반도체 기판에 소오스, 드레인용 고농도 불순물을 이온 주입하는 단계를 포함한다.The present invention is to solve the above-described problems, and in the gate electrode including a high melting point metal thin film, a method of forming a gate electrode of a semiconductor device to prevent the high melting point metal thin film portion exposed to the sidewall of the gate electrode is oxidized. It starts. The present invention discloses sequentially depositing a gate insulating film, a doped polysilicon film, a diffusion barrier film, a high melting point metal thin film and an antireflective oxide film on a semiconductor substrate, the diffuse reflection prevention oxide film and a high melting point metal thin film, a diffusion prevention film and Forming a gate electrode by partially patterning the doped polysilicon film, forming a first spacer of a silicon film and a first nitride film on the sidewall of the gate electrode, and the doped polysilicon sidewall and the diffusion barrier sidewall. And heat-treating the semiconductor substrate resultant to thermally oxidize the silicon film on the sidewall of the anti-reflective oxide film so as to change the silicon film on the sidewall of the high melting point metal into a silicide film, and implanting low concentration impurities for source and drain into the exposed semiconductor substrate. And a second at both sides of the first silicon nitride film. Forming a second spacer of a silicon nitride film, and ion implanting a high concentration impurity for a source and a drain into the exposed semiconductor substrate.
Description
본 발명은 반도체 소자의 게이트 전극 형성방법에 관한 것으로 보다 구체적으로는 텅스텐 박막을 포함하는 게이트 전극 형성방법에 관한 것이다.The present invention relates to a method of forming a gate electrode of a semiconductor device, and more particularly, to a method of forming a gate electrode including a tungsten thin film.
일반적으로, 게이트 전극은 모스 트랜지스터를 셀렉팅하는 전극으로서, 주로 불순물이 도핑된 폴리실리콘막 구조가 이용되거나 또는 불순물이 도핑된 폴리실리콘막과 고융점 실리사이드막을 적층하는 구조(이하 폴리사이드 구조)가 이용된다.In general, the gate electrode is an electrode for selecting a MOS transistor, and a polysilicon film structure doped with an impurity is mainly used or a structure in which a polysilicon film doped with an impurity and a high melting point silicide film is laminated (hereinafter referred to as a polyside structure). Is used.
그러나, 반도체 소자의 집적도가 증가됨에 따라, 상기한 폴리사이드 구조의 게이트 전극 보다 더욱 우수한 전도 특성을 갖는 구조가 요구되었다.However, as the degree of integration of semiconductor devices is increased, a structure having better conductivity than the gate electrode of the polyside structure is required.
따라서, 종래에는 텅스텐 박막이 적층되어 전도 특성이 개선된 게이트 전극 구조가 제안되었고, 상기 구조에 대하여 도 1을 참조하여 설명한다.Therefore, conventionally, a gate electrode structure in which a tungsten thin film is stacked to improve conduction characteristics has been proposed. The structure will be described with reference to FIG. 1.
먼저, 도 1에 도시된 바와 같이, 반도체 기판(1) 상부에 열산화 방식에 의하에 게이트 절연막(2)을 형성한다. 이어, 게이트 절연막(2) 상부에 도핑된 폴리실리콘막(3)을 증착하고, 폴리실리콘막(3) 상부에 확산 방지막(4)을 증착한다. 그다음, 확산 방지막(4) 상부에 비저항성 고융점 금속 박막인 텅스텐 박막(5)을 증착하고, 이 텅스텐 박막(5) 상부에 마스크 산화막(6)을 증착한다. 여기서, 확산 방지막(4)은 폴리실리콘막(3)과 텅스텐 박막(5) 사이의 이온 확산을 방지하기 위한 막이고, 산화막(6)은 이후 패터닝 공정시 텅스텐의 난반사로 인하여 패턴 결함이 발생되는 것을 방지하기 위하여 형성하는 막이다.First, as shown in FIG. 1, the gate insulating film 2 is formed on the semiconductor substrate 1 by thermal oxidation. Next, a doped polysilicon film 3 is deposited on the gate insulating film 2, and a diffusion barrier 4 is deposited on the polysilicon film 3. Then, a tungsten thin film 5, which is a resistive high melting point metal thin film, is deposited on the diffusion barrier film 4, and a mask oxide film 6 is deposited on the tungsten thin film 5 above. Here, the diffusion barrier 4 is a film for preventing ion diffusion between the polysilicon layer 3 and the tungsten thin film 5, the oxide film 6 is a pattern defect due to the diffuse reflection of tungsten during the patterning process It is a film formed to prevent it.
그후, 공지의 포토리소그라피 공정 및 패터닝 공정에 의하여 산화막(6), 텅스텐 박막(5), 확산 방지막(4) 및 도핑된 폴리실리콘막(3)을 순차적으로 패터닝하여 게이트 전극을 형성한다.Thereafter, the oxide film 6, the tungsten thin film 5, the diffusion barrier film 4, and the doped polysilicon film 3 are sequentially patterned by a known photolithography process and a patterning process to form a gate electrode.
그러나, 상술한 텅스텐 박막을 포함하는 게이트 전극은 다음과 같은 문제점을 갖는다.However, the gate electrode including the tungsten thin film described above has the following problems.
게이트 전극을 형성하기 위한 패터닝 공정을 마치게 되면, 상기 텅스텐 박막(6)이 공기중에 노출된다. 이때, 텅스텐 박막(6)은 공기중의 산소와 쉽게 결합하여 산화막이 쉽게 발생되는 특징을 지니고 있다. 이에따라, 노출된 텅스텐 박막(6) 부분은 고온에서의 산화막 공정 진행중 산화가 이루어져, 도 1과 같이 텅스텐 박막(6)의 측벽에 텅스텐 산화막(7:WO3)이 발생된다. 이와같은 텅스텐 산화막(7)이 형성됨에 따라, 종래의 게이트 전극은 그 형상이 변형되어져, 후속으로 진행되는 소오스, 드레인용 불순물의 이온 주입이 어렵게 되고, 게이트 전극의 자체 저항이 증가된다.When the patterning process for forming the gate electrode is completed, the tungsten thin film 6 is exposed to air. At this time, the tungsten thin film 6 is easily combined with oxygen in the air and has an characteristic that an oxide film is easily generated. Accordingly, the exposed portion of the tungsten thin film 6 is oxidized during the oxide film process at a high temperature, so that the tungsten oxide film 7: WO 3 is generated on the sidewall of the tungsten thin film 6 as shown in FIG. 1. As such a tungsten oxide film 7 is formed, the shape of the conventional gate electrode is deformed, so that ion implantation of subsequent source and drain impurities is difficult, and the self-resistance of the gate electrode is increased.
이러한 문제점을 해결하기 위하여, 종래의 다른 방법으로는 H2O가 원하는 비율로 혼합된 분위기에서 실리콘에만 산화막이 형성되고 텅스텐막에는 산화막이 형성되지 않도록 선택적 산화하는 방법이 제안되었다.In order to solve this problem, another method of the related art has been proposed in which an oxide film is formed only on silicon and an oxide film is not formed on a tungsten film in an atmosphere in which H 2 O is mixed at a desired ratio.
그러나, 상기한 선택적 산화 방법은 950℃이상에서 150초 동안 열공정을 실시하여야 하므로 열적 부담이 가해지고, 부분적으로 텅스텐 박막이 산화되는 문제점이 있다.However, the selective oxidation method has a problem that the thermal burden is applied, and the tungsten thin film is partially oxidized because the thermal process must be performed for 150 seconds at 950 ° C. or higher.
따라서, 본 발명의 목적은 상기한 종래의 문제점을 해결하기 위한 것으로, 고융점 금속 박막을 포함하는 게이트 전극에서, 게이트 전극 측벽에 노출된 고융점 금속 박막부분이 산화되는 것을 방지하는 반도체 소자의 게이트 전극 형성방법을 제공하는 것이다.Accordingly, an object of the present invention is to solve the above-described problems, and in the gate electrode including the high melting point metal thin film, the gate of the semiconductor device which prevents the high melting point metal thin film portion exposed to the gate electrode sidewall from being oxidized. It is to provide an electrode forming method.
도 1은 종래의 게이트 전극 형성방법을 설명하기 위한 도면.1 is a view for explaining a conventional method for forming a gate electrode.
도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 각 공정별 단면도.2A to 2D are cross-sectional views of respective processes for explaining a method of forming a gate electrode of a semiconductor device according to the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 반도체 기판 12 : 게이트 절연막11 semiconductor substrate 12 gate insulating film
13 : 도핑된 폴리실리콘막 14 : 확산 방지막13: doped polysilicon film 14: diffusion barrier film
15 : 고융점 금속 박막 16 : 마스크 산화막15: high melting point metal thin film 16: mask oxide film
17 : 실리콘막 18 : 제 1 질화막17 silicon film 18 first nitride film
19a,19b : 열산화막 20 : 실리사이드19a, 19b: thermal oxide film 20: silicide
21 : 제 2 질화막21: second nitride film
상기한 본 발명의 목적을 달성하기 위하여, 본 발명의 일 실시예에 따르면, 본 발명은 반도체 기판 상에 게이트 절연막, 도핑된 폴리실리콘막, 확산 방지막, 고융점 금속 박막 및 난반사 방지용 산화막을 순차적으로 증착하는 단계와, 상기 난반사 방지용 산화막과 고융점 금속 박막, 확산 방지막 및 도핑된 폴리실리콘막을 소정 부분 패터닝하여 게이트 전극을 형성하는 단계와, 상기 게이트 전극의 측벽에 실리콘막과 제 1 질화막으로 된 스페이서를 형성하는 단계와, 상기 도핑된 폴리실리콘 측벽, 확산 방지막 측벽 및 난반사 방지용 산화막 측벽에 있는 실리콘막을 열산화되면서 고융점 금속 박막 측벽의 실리콘막은 실리사이드막으로 변화되도록, 반도체 기판 결과물을 열처리하는 단계와, 상기 노출된 반도체 기판에 소오스, 드레인용 저농도 불순물을 이온 주입하는 단계와, 상기 제 1 실리콘 질화막 양측에 제 2 실리콘 질화막으로 된 스페이서를 형성하는 단계, 및 상기 노출된 반도체 기판에 소오스, 드레인용 고농도 불순물을 이온 주입하는 단계를 포함한다.In order to achieve the above object of the present invention, according to an embodiment of the present invention, the present invention sequentially a gate insulating film, a doped polysilicon film, a diffusion barrier film, a high melting point metal thin film and an antireflection oxide film on a semiconductor substrate Forming a gate electrode by depositing a predetermined portion of the diffuse reflection prevention oxide film, the high melting point metal thin film, the diffusion barrier film, and the doped polysilicon film, and forming a gate electrode on a sidewall of the gate electrode; Thermally oxidizing the silicon films on the doped polysilicon sidewalls, the diffusion barrier sidewalls, and the diffuse reflection prevention oxide sidewalls, so that the silicon film on the sidewall of the high melting point metal thin film is changed to a silicide layer; Low concentration impurities for source and drain in the exposed semiconductor substrate Ion implantation, forming a spacer of a second silicon nitride film on both sides of the first silicon nitride film, and ion implanting a high concentration impurity for source and drain into the exposed semiconductor substrate.
여기서, 상기 확산 방지막은 텅스텐 나이트 라이드 또는 티타늄 나이트 라이드로 형성되고, 약 50 내지 300Å의 두께로 형성된다.Here, the diffusion barrier layer is formed of tungsten nitride or titanium nitride, it is formed to a thickness of about 50 to 300Å.
상기 고융점 금속 박막은 텅스텐, 탄탄륨 또는 몰리브덴 중 선택되는 하나로 형성되고, 약 500 내지 2000Å 두께로 형성된다.The high melting point metal thin film is formed of one selected from tungsten, tantalum or molybdenum, and is formed to a thickness of about 500 to 2000 microns.
또한, 상기 게이트 전극을 형성하는 방법은 상기 난반사 방지용 산화막 상부에 게이트 전극용 레지스트 패턴을 형성하는 단계와, 상기 레지스트 패턴을 마스크로 하여, 상기 산화막을 패터닝하는 단계와 상기 패터닝된 산화막을 마스크로 하여고융점 금속 박막, 확산 방지막 및 도핑된 폴리실리콘막을 건식 식각하는 단계를 포함한다.The method of forming the gate electrode may include forming a gate electrode resist pattern on the diffuse reflection prevention oxide film, patterning the oxide film using the resist pattern as a mask, and using the patterned oxide film as a mask. Dry etching the high melting point metal thin film, the diffusion barrier, and the doped polysilicon film.
본 발명에 의하면, 고융점 금속 박막을 포함하는 게이트 전극을 형성할 때, 게이트 전극 측벽 부분에 실리콘막, 제 1 질화막을 스페이서 형태로 형성한다음 열처리한다. 이에따라, 고융점 금속 박막이 실리콘막 및 제 1 질화막에 의하여 완전히 차단되어, 열처리 진행하여도 고융점 금속 박막은 산화가 일어나지 않는다.According to the present invention, when forming a gate electrode including a high melting point metal thin film, a silicon film and a first nitride film are formed in the form of a spacer on the sidewall portion of the gate electrode and then subjected to heat treatment. Accordingly, the high melting point metal thin film is completely blocked by the silicon film and the first nitride film so that the high melting point metal thin film does not oxidize even when the heat treatment is performed.
또한, 실리콘막이 제 1 질화막에 의하여 덮혀있으므로, 균일하게 열산화막 또는 실리사이드막으로 변화되어, 게이트 전극의 형상도 변형되지 않는다. 더욱이, 고융점 금속 박막 측벽에는 전도 특성이 우수한 실리사이드막이 둘러싸여 있으므로 전도 특성도 유지된다.In addition, since the silicon film is covered by the first nitride film, the silicon oxide film is uniformly changed into a thermal oxide film or a silicide film, and the shape of the gate electrode is not deformed. Further, the high melting point metal thin film sidewall is surrounded by a silicide film having excellent conductivity, so that the conductivity is also maintained.
(실시예)(Example)
이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 각 공정별 단면도이다.2A to 2D are cross-sectional views of respective processes for explaining a method of forming a gate electrode of a semiconductor device according to the present invention.
먼저, 도 2a를 참조하여, 반도체 기판(11) 상부에 표면 열산화 방식에 의하여 게이트 절연막(12)을 형성한다. 이어서, 게이트 절연막(12) 상부에 도핑된 폴리리콘막(13), 확산 방지막(14), 고융점 금속박막(15) 및 마스크 산화막(16)을 순차적으로 형성한다. 이때, 확산 방지막(14)은 텅스텐 나이트라이드(WN) 또는 티타늄 나이트라이드(TiN)등이 이용되고, 약 50 내지 300Å의 두께로 증착된다. 또한, 고융점 금속박막(15)은 텅스텐(W), 탄탈륨(Ta), 몰리브덴(Mo)등이 이용될 수 있고, 약 500 내지 2000Å 두께로 증착된다. 또한, 마스크 산화막(16)은 이후 포토리소그라피 공정시 난반사 방지 역할 및 게이트 전극 식각시 마스크로 이용되며, 예를들어 화학기상 증착법으로 형성한다. 다음으로, 마스크 산화막(16) 상부에 공지의 포토리소그라피 공정에 의하여 게이트 전극 형성용 레지스트 패턴(도시되지 않음)을 형성한다음, 이 레지스트 패턴을 마스크로 이용하여, 상기 마스크 산화막(16)을 패터닝한다. 그리고나서, 소정 부분 패터닝된 산화막(16)을 다시 마스크로 이용하여, 고융점 금속 박막(15)과, 확산 방지막(14)과 도핑된 폴리실리콘막(13)을 건식 식각하여 게이트 전극을 형성한다.First, referring to FIG. 2A, the gate insulating layer 12 is formed on the semiconductor substrate 11 by surface thermal oxidation. Subsequently, the doped polysilicon film 13, the diffusion barrier film 14, the high melting point metal thin film 15, and the mask oxide film 16 are sequentially formed on the gate insulating film 12. At this time, the diffusion barrier 14 is made of tungsten nitride (WN) or titanium nitride (TiN) and the like, and is deposited to a thickness of about 50 to 300 kPa. In addition, tungsten (W), tantalum (Ta), molybdenum (Mo), or the like may be used for the high melting point metal thin film 15, and is deposited to a thickness of about 500 to 2000 kPa. In addition, the mask oxide layer 16 is then used as a mask for preventing anti-reflection during the photolithography process and etching the gate electrode, and is formed by, for example, chemical vapor deposition. Next, a resist pattern (not shown) for forming a gate electrode is formed on the mask oxide film 16 by a known photolithography process, and then the mask oxide film 16 is patterned by using the resist pattern as a mask. do. Then, the gate electrode is formed by dry etching the high melting point metal thin film 15, the diffusion barrier 14, and the doped polysilicon film 13 by using the partially patterned oxide film 16 as a mask again. .
그리고나서, 도 2b에 도시된 바와 같이, 게이트 전극이 형성된 반도체 기판(11) 결과물 상부에 실리콘막(17) 및 제 1 실리콘 질화막(18)을 순차적으로 증착한다. 이때, 실리콘막(17)은 비도핑된 물질이든지, 그렇지 않은 물질이든지 상관없으며, 약 50 내지 200Å 두께로 증착한다. 또한, 제 1 실리콘 질화막(18)은 100 내지 200Å의 두께로, 저압 기상 증착 방식으로 형성한다, 그리고나서, 이 실리콘막(17)과 제 1 실리콘 질화막(18)을 비등방성 식각하여, 게이트 전극 측벽에 잔류시킨다.Then, as illustrated in FIG. 2B, the silicon film 17 and the first silicon nitride film 18 are sequentially deposited on the semiconductor substrate 11 formed with the gate electrode. At this time, the silicon film 17 may be a undoped material or a non-doped material, and is deposited to a thickness of about 50 to about 200 microseconds. In addition, the first silicon nitride film 18 is formed to have a thickness of 100 to 200 GPa by a low pressure vapor deposition method. Then, the silicon film 17 and the first silicon nitride film 18 are anisotropically etched to form a gate electrode. Remain on the sidewalls.
이어서, 도 2c에 도시된 바와 같이, 게이트 전극 및 그 측벽에 실리콘 스페이서(17)가 형성된 반도체 기판 구조물을 750 내지 950℃의 온도에서 열처리 한다. 상기의 열처리 공정으로 노출된 마스크 산화막(16) 양측의 실리콘막은 열산화막(19a)으로 변화되고, 텅스텐 박막(15) 양측의 실리콘막은 텅스텐 실리사이드막(20)으로 변화되며, 도핑된 폴리실리콘막(13) 양측의 실리콘막(17)은 그대로 남아있게 된다. 또한, 반도체 기판(11) 표면에도 일부 열산화막(19b)이 형성된다. 이때, 제 1 질화막(18)은 상기 열처리 공정으로 쉽게 산화되지 않으며, 상기 실리콘막(17)을 덮고있어, 실리콘막만으로 차단할 수 없었던 텅스텐 박막(15)의 산화를 완전히 차단할 수 있으며, 열처리시 실리콘막(17)이 균일하게 산화 또는 실리사이드화되도록 한다.Subsequently, as illustrated in FIG. 2C, the semiconductor substrate structure having the silicon spacers 17 formed on the gate electrode and the sidewall thereof is heat-treated at a temperature of 750 to 950 ° C. The silicon film on both sides of the mask oxide film 16 exposed by the heat treatment process is changed to the thermal oxide film 19a, and the silicon film on both sides of the tungsten thin film 15 is changed to the tungsten silicide film 20, and the doped polysilicon film ( 13) The silicon films 17 on both sides remain intact. In addition, some thermal oxide films 19b are formed on the surface of the semiconductor substrate 11. At this time, the first nitride film 18 is not easily oxidized by the heat treatment process, and covers the silicon film 17, thereby completely blocking the oxidation of the tungsten thin film 15 which could not be blocked by only the silicon film. The film 17 is allowed to be oxidized or silicided uniformly.
그 다음, 노출된 반도체 기판에 소오스, 드레인용 저농도 불순물을 이온 주입한다.Thereafter, ion-implanted low concentration impurities for source and drain are implanted into the exposed semiconductor substrate.
그후, 도 2d에 도시된 바와 같이, 반도체 기판(11) 결과물 상부에 제 2 질화막(21)을 증착한다. 그런다음, 제 2 질화막(21)을 비등방성 블랭킷 식각하여, 제 1 질화막(18)측벽에 스페이서를 형성한다. 이때, 제 2 질화막(21)의 비등방성 식각으로 반도체 기판(11)상의 열산화막(19)이 제거된다.Thereafter, as shown in FIG. 2D, a second nitride film 21 is deposited on the semiconductor substrate 11. Then, anisotropic blanket etching is performed on the second nitride film 21 to form a spacer on the sidewall of the first nitride film 18. At this time, the thermal oxide film 19 on the semiconductor substrate 11 is removed by anisotropic etching of the second nitride film 21.
이어서, 노출된 반도체 기판에 소오스, 드레인용 고농도 불순물을 이온 주입한다.Subsequently, high concentration impurities for source and drain are ion implanted into the exposed semiconductor substrate.
이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 고융점 금속 박막을 포함하는 게이트 전극을 형성할 때, 게이트 전극 측벽 부분에 실리콘막, 제 1 질화막을 스페이서 형태로 형성한다음 열처리한다. 이에따라, 고융점 금속 박막이 실리콘막 및 제 1 질화막에 의하여 완전히 차단되어, 열처리 진행하여도 산화가 일어나지 않는다.As described in detail above, according to the present invention, when forming a gate electrode including a high melting point metal thin film, a silicon film and a first nitride film are formed in the form of a spacer on the sidewall portion of the gate electrode and then heat-treated. Accordingly, the high melting point metal thin film is completely blocked by the silicon film and the first nitride film, so that oxidation does not occur even when the heat treatment proceeds.
또한, 실리콘막이 제 1 질화막에 의하여 덮혀있으므로, 균일하게 열산화막 또는 실리사이드막으로 변화되어, 게이트 전극의 형상도 변형되지 않는다. 더욱이, 고융점 금속 박막 측벽에는 전도 특성이 우수한 실리사이드막이 둘러싸여 있으므로 전도 특성도 유지된다.In addition, since the silicon film is covered by the first nitride film, the silicon oxide film is uniformly changed into a thermal oxide film or a silicide film, and the shape of the gate electrode is not deformed. Further, the high melting point metal thin film sidewall is surrounded by a silicide film having excellent conductivity, so that the conductivity is also maintained.
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