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KR100583494B1 - 반도체패키지 - Google Patents

반도체패키지 Download PDF

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Publication number
KR100583494B1
KR100583494B1 KR1020000015304A KR20000015304A KR100583494B1 KR 100583494 B1 KR100583494 B1 KR 100583494B1 KR 1020000015304 A KR1020000015304 A KR 1020000015304A KR 20000015304 A KR20000015304 A KR 20000015304A KR 100583494 B1 KR100583494 B1 KR 100583494B1
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KR
South Korea
Prior art keywords
semiconductor chip
mounting plate
chip
conductive
semiconductor
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1020000015304A
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English (en)
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KR20010090378A (ko
Inventor
서성민
정영석
백종식
구재훈
이재학
Original Assignee
앰코 테크놀로지 코리아 주식회사
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Application filed by 앰코 테크놀로지 코리아 주식회사 filed Critical 앰코 테크놀로지 코리아 주식회사
Priority to KR1020000015304A priority Critical patent/KR100583494B1/ko
Priority to US09/816,852 priority patent/US6858919B2/en
Priority to SG200101839A priority patent/SG91352A1/en
Publication of KR20010090378A publication Critical patent/KR20010090378A/ko
Priority to US10/944,241 priority patent/US6953988B2/en
Application granted granted Critical
Publication of KR100583494B1 publication Critical patent/KR100583494B1/ko
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

이 발명은 반도체패키지에 관한 것으로, 마이크로 리드프레임상에 반도체칩을 플립칩 기술을 이용하여 본딩함으로써 제조 공정수를 축소함은 물론 반도체패키지의 두께를 박형화하고, 또한 반도체칩의 그라운드/파워처리를 공통된 영역에 본딩하여 신호용 리드의 개수를 최대한 확보하며, 방열성능도 향상시키기 위해, 하면에 다수의 입출력패드가 구비된 반도체칩과; 상기 반도체칩의 하면에 위치된 칩탑재판과; 상기 칩탑재판의 외주연에 일정거리 이격되어 위치되며, 하면을 향하여 적어도 한 개이상의 돌기부가 형성된 다수의 리드와; 상기 반도체칩의 입출력패드와 리드를 상호 전기적으로 접속하는 다수의 도전성 접속수단와; 상기 반도체칩, 도전성 접속수단, 칩탑재판 및 내부리드를 봉지재로 봉지하되, 상기 칩탑재판의 저면 및 내부리드의 돌기부 저면은 외부로 노출되도록 봉지되어 형성된 패키지몸체를 포함하여 이루어진 것을 특징으로 함.

Description

반도체패키지{Semiconductor package}
도1은 종래의 반도체패키지를 도시한 단면도이다.
도2a 및 도2b는 본 발명의 제1실시예에 의한 반도체패키지를 도시한 단면도이다.
도3a 및 도3b는 본 발명의 제2실시예에 의한 반도체패키지를 도시한 단면도이다.
도4a 및 도4b는 본 발명의 제3실시예에 의한 반도체패키지를 도시한 단면도이다.
도5는 본 발명의 반도체패키지에 이용된 마이크로 리드프레임의 일부를 도시한 평면도이다.
- 도면중 주요 부호에 대한 설명 -
101,102,103; 본 발명에 의한 반도체패키지
2; 반도체칩 2a; 입출력패드
4; 칩탑재판 4a; 부분에칭부
6; 리드 6a; 부분에칭부
6b; 돌기부 8; 도전성 접속수단
10; 패키지몸체 12; 도전성볼
14; 열전도성접착제 16; 절연층
본 발명은 반도체패키지에 관한 것으로, 더욱 상세하게 설명하면 마이크로 리드프레임상에 반도체칩을 플립칩 기술을 이용하여 본딩함으로써 제조 공정수를 축소함은 물론 반도체패키지의 두께를 박형화하고, 또한 반도체칩의 그라운드/파워처리를 공통된 영역에 본딩하여 신호용 리드의 개수를 최대한 확보하며, 방열성능도 향상시킬 수 있는 MLF(Micro LeadFrame)형 반도체패키지에 관한 것이다.
최근의 전자기기 예를 들면, 휴대폰, 셀룰러 폰, 노트북 등의 마더보드에는 많은 수의 반도체칩들이 패키징되어 최소 시간내에 그것들이 다기능을 수행할 수 있도록 설계되는 동시에, 전자기기 자체가 초소형화 되어 가는 추세에 있다. 이에 따라 반도체칩이 고집적화됨은 물론, 이를 패키징한 반도체패키지의 크기도 축소되고 있으며, 또한 실장밀도도 고밀도화되어 가고 있다.
이러한 추세에 따라 최근에는 반도체칩의 전기적 신호를 마더보드로 전달해줌은 물론 마더보드(Mother Board) 상에서 일정한 형태로 지지되도록 하는 반도체패키지의 크기가 대략 1×1mm ~ 10×10mm 내외로 개발되고 있으며, 이러한 반도체패키지의 예로서 MLF(Micro LeadFrame)형 반도체패키지 등이 알려져 있다.
여기서 상기 MLF형 반도체패키지(100')의 통상적인 구조를 도1에 도시하였다.
도시된 바와 같이 상면에 다수의 입출력패드(2a')가 형성된 반도체칩(2')이 구비되어 있고, 상기 반도체칩(2')의 저면에는 접착제로 칩탑재판(4')이 접착되어 있다. 상기 칩탑재판(4')은 측면의 하부 둘레에 부분에칭부(4a')가 형성되어 있다. 상기 칩탑재판(4')의 외주연에는 방사상으로 배열되어 있으며 칩탑재판(4')을 향하는 단부의 하부에 부분에칭부(6a')가 형성된 다수의 리드(6')가 구비되어 있다. 상기 반도체칩(2')의 입출력패드(2a')와 리드(6')는 도전성와이어(8')에 의해 서로 전기적으로 접속되어 있다. 상기 반도체칩(2'), 도전성와이어(8'), 칩탑재판(4') 및 리드(6')는 봉지재로 봉지되어 소정의 패키지몸체(10')를 형성하고 있으며, 상기 칩탑재판(4'), 리드(6')의 저면은 패키지몸체(10') 저면으로 노출되어 있다. 상기와 같은 반도체패키지는 상기 리드의 저면이 마더보드에 솔더를 통하여 융착됨으로써 실장된다. 한편, 상기 반도체패키지는 반도체칩의 전기적 신호가 입출력패드, 도전성와이어 및 리드를 통해 마더보드와 교신된다.
그러나 상기와 같은 종래의 반도체패키지는 반도체칩과 리드가 도전성와이어로 본딩되기 때문에, 상기 와이어의 루프 하이트(Loop Height)로 인해 반도체패키지의 두께가 비교적 두꺼워지는 단점이 있다. 더불어 상기 와이어 본딩을 위해 반도체칩과 리드 사이에 일정영역의 공간이 항상 필요함으로써 축소될 수 있는 반도체패키지의 크기에 제한이 있다.
또한, 상기와 같은 반도체패키지는 열방출 경로가 반도체칩 저면의 칩탑재판에 편중됨으로써 열방출 성능이 저조한 문제점이 있다. 즉, 상기 도전성와이어를 통해 리드쪽으로도 열이 방출되지만 상기 도전성와이어의 두께는 μm 단위이기 때 문에 열 전달률이 좋지 않고, 또한 반도체칩의 상면도 완전히 봉지재로 봉지됨으로써 그 방열성능이 저하되는 문제점이 있다.
또한, 반도체칩의 그라운드/파워용 입출력패드도 도전성와이어에 의해 마이크로리드 프레임의 신호용 리드에 접속됨으로써 불필요하게 많은 신호용 리드가 낭비되는 단점이 있다. 즉, 반도체칩에는 신호용 입출력패드뿐만 아니라 많은 그라운드/파워용의 입출력패드가 형성되는데 이러한 모든 그라운드/파워용의 입출력패드는 공통 전위를 가짐에도 불구하고 다수의 신호용 리드에 접속됨으로써, 실제 반도체칩의 작동에 중요한 역할을 하는 신호용 입출력패드와 대응되는 신호용 리드가 부족해지는 문제점이 있다.
또한, 입출력패드가 파인피치(Fine Pitch)화한 반도체칩을 수용하기 위해서는 보다 큰 마이크로 리드프레임을 필요로 하며 이에 따라 마더보드에서의 실장밀도도 크게 저하되는 문제가 있다.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 마이크로 리드프레임상에 반도체칩을 플립칩 기술을 이용하여 본딩함으로써 제조 공정수를 축소함은 물론 반도체패키지의 두께를 박형화하고, 또한 반도체칩의 그라운드/파워처리를 공통된 영역에 본딩하여 신호용 리드의 개수를 최대한 확보하며, 방열성능도 향상시킬 수 있는 MLF(Micro LeadFrame)형 반도체패키지를 제공하는데 있다.
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 하면에 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 하면에 위치되며, 하면을 향하여 적어도 한 개이상의 돌기부가 형성된 다수의 리드와; 상기 반도체칩의 입출력패드와 리드를 상호 전기적으로 접속하는 다수의 도전성 접속수단과; 상기 반도체칩, 도전성 접속수단 및 내부리드를 봉지재로 봉지하되, 상기 내부리드의 돌기부 하면은 외부로 노출되도록 형성된 패키지몸체를 포함하여 이루어진 것을 특징으로 한다.
상기 반도체칩의 하면 중앙부에, 그리고 다수의 리드 사이에는 칩탑재판이 더 위치되어 있고, 상기 칩탑재판의 상면과 상기 반도체칩은 열전도성 접착제에 의해 서로 접착될 수 있다.
상기 반도체칩은 상면이 패키지몸체 외측으로 노출될 수도 있다.
상기 반도체칩은 하면 중앙부에 다수의 입출력패드가 구비되어 있고, 상기 입출력패드는 도전성 접속수단에 의해 상기 칩탑재판에 접속될 수도 있다.
상기 도전성 접속수단은 골드볼, 솔더볼 또는 이방성 전도필름중 선택된 어느 하나일 수 있다.
상기 도전성 접속수단으로서 골드볼 또는 솔더볼이 이용되었을 경우, 상기 접속수단과 접속되는 칩탑재판 또는 리드의 상면에는 상기 접속되는 영역의 외주연이 일정두께의 절연층으로 코팅됨이 바람직하다.
상기 리드는 돌기부가 열과 행으로 어레이되어 형성될 수 있다.
상기 리드는 돌기부 하면에 도전성볼이 융착될 수 있다.
또한, 상기 칩탑재판의 하면에는 도전성 페이스트 또는 다수의 도전성볼이 더 융착될 수 있다.
상기와 같이 하여 본 발명에 의한 반도체패키지에 의하면, 반도체칩과 리드가 도전성 접속수단에 의해 접속됨으로써 종래의 와이어 루프 하이트가 없어지고 따라서 반도체패키지의 두께가 더욱 박형화되는 장점이 있다.
또한, 종래의 와이어 본딩을 위한 공간이 필요없게 됨으로써 동일한 리드프레임상에 보다 큰 반도체칩을 탑재할 수 있게 된다.
또한, 반도체칩의 열방출 경로가 반도체칩 하면의 칩탑재판 뿐만 아니라, 그 외주연의 리드까지 확장됨으로써 방열성능이 향상된다. 더욱이, 반도체칩의 상면이 패키지몸체 외측으로 직접 노출될 수 있고, 또한 칩탑재판이 개재된 경우에는 상기 칩탑재판 하면에 도전성 페이스트 또는 도전성볼을 융착함으로써 그 방열 성능을 더욱 향상시킬 수 있게 된다.
또한, 모든 그라운드/파워용 입출력패드를 반도체칩 하면의 중앙부분에 형성하고, 이를 도전성 접속수단을 이용하여 칩탑재판에 접속함으로써 신호용 리드를 최대한 확보할 수 있는 장점이 있다. 따라서, 동일한 크기의 리드프레임에 파인피치화한 반도체칩을 탑재할 수 있게 된다.
또한, 상기 도전성 접속수단이 접속되는 칩탑재판 또는 리드의 소정 영역을 제외한 그 외주연을 일정두께의 절연층으로 코팅함으로써, 상기 도전성 접속수단을 상기 칩탑재판 또는 리드의 소정 영역에 융착시, 그 도전성 접속수단이 외측으로 흘러가지 않토록 함으로써 접속 작업이 보다 용이하게 수행되는 장점도 있다.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.
도2a 및 도2b는 본 발명의 반도체패키지(101)에 대한 제1실시예를 도시한 단면도이다.
도시된 바와 같이 하면의 둘레 부근에 다수의 입출력패드(2a)가 형성된 반도체칩(2)이 구비되어 있다. 상기 반도체칩(2)의 하면 중앙부 즉, 입출력패드(2a)가 형성되지 않은 하면에는 칩탑재판(4)이 위치되어 있고, 상기 칩탑재판(4)의 외주연으로는 일정 거리 이격되어 다수의 리드(6)가 위치되어 있다.
여기서, 상기 칩탑재판(4)이 반드시 필요한 것은 아니다.
상기 칩탑재판(4)의 하면 둘레에는 부분에칭부(4a)가 형성되어 있다. 또한, 상기 칩탑재판(4)을 향하는 리드(6)의 단부 하면에도 부분에칭부(6a)가 형성되어 있으며, 상기 리드(6)에 형성된 부분에칭부(6a)의 외주연에는 차후 마더보드와 접속되는 돌기부(6b)가 형성되어 있다.
또한 도2b에 도시된 바와 같이 상기 돌기부(6b)는 어레이되어 형성될 수 있으며, 따라서 종래에 비해 많은 입출력 수단을 확보할 수 있게 된다. 상기 도2b의 돌기부(6b)는 도시되지는 않았지만 저면에서 보았을 때 행과 열을 가지며 어레이된다.
상기 칩탑재판(4)의 상면과 반도체칩(2) 사이에는 열전도성접착제(14)가 개재되어 상기 반도체칩(2)을 칩탑재판(4)에 접착시키고 있다. 여기서, 상기 접착제(14)는 열은 전도하고 전기적으로 비도전성으로서 반도체칩(2)의 열을 칩탑재판(4)쪽으로 양호하게 전달시킨다. 더욱이, 도2b에서 칩탑재판(4)의 저면에 도전성 페이스트 또는 도전성볼을 융착하고, 이를 차후 마더보드에 접속시킴으로써 그 방열성능을 더욱 향상시킬 수도 있다.
한편, 상기 반도체칩(2)의 입출력패드(2a)와 리드(6)는 골드볼, 솔더볼 또는 이방성 전도필름과 같은 도전성접속수단(8)에 의해 상호 접속되어 있다.
여기서, 상기와 같이 반도체칩(2)의 입출력패드(2a)에 도전성 접속수단(8)으로서 골드볼 또는 솔더볼이 이용되었을 경우, 그 도전성 접속수단(8)이 접속되는 리드(6)의 표면에는 상기 도전성 접속수단(8)과 접속되는 영역의 외주연에 일정두께의 절연층(16)이 코팅되어 있다. 따라서 도전성 접속수단(8)의 융착시 상기 도전성 접속수단(8)이 외측으로 흘러가지 않게 되어 그 융착 작업이 용이하게 수행된다. 또한, 상기 반도체칩(2)과 리드(6)가 도전성 접속수단(8)에 의해 상호 접속됨으로써 신호 교환뿐만 아니라 반도체칩(2)의 열이 상기 도전성 접속수단(8)를 통해 리드(6)쪽으로도 방출된다. 여기서, 상기 절연층(16)은 다양한 물질들이 사용될 수 있으며, 솔더마스크(Solder Mask), 커버코트(Cover Coat) 또는 폴리이미드(Polyimide) 등을 사용함이 바람직하다.
여기서, 상기 도전성 접속수단(8)은 골드볼 또는 솔더볼 대신에 이방성전도필름(ACF; Anisotropic Conductive Film)을 이용할 수도 있다.
상기 이방성 전도 필름이란, 일반적인 접착 필름과 도전용금속알갱이가 혼합 된 것으로 상기 접착 필름의 두께는 약 50μm 정도이고 도전용금속알갱이의 지름은 약 5μm 정도이다. 또한 상기 도전용금속알갱이의 표면은 얇은 폴리머(Polymer)로 코팅되어 있으며, 이러한 이방성 전도 필름의 소정의 영역에 열 또는 압력을 가하게 되면 그 부분의 도전용금속알갱이를 감싸고 있는 폴리머가 녹게되어 도전성을 갖게 되고 그외의 부분은 확실한 절연성을 유지하는 특성을 가지고 있기 때문에 상호 접속될 부분의 위치 맞춤이 용이한 장점이 있다. 즉, 상기 도전성 접속수단으로서 골드볼 또는 솔더볼을 이용할 경우에는, 반도체칩 또는 리드의 특정 영역에 그 볼을 융착시킨 후, 상호 위치를 맞춘 상태에서 다시 리플로(Reflow) 과정을 거쳐야 하지만, 상기 도전성 접속수단으로 이방성 전도필름을 이용할 경우에는 반도체칩 또는 리드의 접속될 부분에 비교적 넓은 범위로 그 이방성 전도필름을 부착한 후, 단순히 상호 위치를 맞춘 상태에서 소정의 가압력만을 제공하면 특정 부분이 도전 가능하게 된다. 예를 들면, 상기 반도체칩(2)과 리드(6) 사이에 넓은 범위로 이방성 전도필름을 위치시키고, 상기 반도체칩(2) 또는 리드(6)를 서로 밀착시켜주면, 상기 반도체칩(2)의 입출력패드가 상기 이방성 전도필름의 특정영역에 압력을 제공하게 됨으로써, 상기 반도체칩의 입출력패드와 리드는 도전 가능하게 된다.(도면에서는 상기 도전성 접속수단으로서 골드볼 또는 솔더볼이 이용된 도면이 도시되어 있으나, 본 발명의 모든 실시예에서 상기 도전성 접속수단은 이방성 전도필름으로 대체될 수 있다)
상기 반도체칩(2), 도전성 접속수단(8), 칩탑재판(4) 및 리드(6)는 봉지재에 의해 봉지되어 있되, 상기 칩탑재판(4)의 하면 및 리드(6)중 돌기부(6b)의 하면은 봉지재 외측으로 노출되도록 봉지되어 소위 패키지몸체(10)를 형성하고 있다.
여기서, 상기 칩탑재판(4)의 하면 둘레 및 상기 칩탑재판(4)을 향하는 리드(6)의 단부 하면에는 부분에칭부(6a)(4a)가 형성됨으로써 상기 패키지몸체(10)와의 결합력이 향상되고, 따라서 상기 칩탑재판(4) 및 리드(6)가 패키지몸체(10)에서 수직 또는 수평방향으로 이탈되지 않게 된다.
이러한 반도체패키지(101)는 패키지몸체(10) 외측으로 노출된 돌기부(6b)에 솔더가 용융되어 마더보드에 실장된다.
또한 도2b에 도시된 바와 같이 돌기부(6b)에 솔더와 같은 도전성볼(12)을 미리 융착한 후 마더보드에 실장할 수도 있다. 이때에는 전술한 바와 같이 반도체패키지의 방열 성능을 향상시키기 위해, 상기 칩탑재판 저면에도 도전성페이스트 또는 다수의 도전성볼을 형성함이 바람직하다.
계속해서, 도3a 및 도3b에 도시된 반도체패키지(102)(제2실시예)는 상기 도2a 및 도2b의 반도체패키지(101)와 다르게 반도체칩(2)의 하면 중앙부에도 다수의 입출력패드(2a)가 형성되어 있다. 상기 입출력패드(2a)는 그라운드/파워용의 입출력패드(2a)가 되도록 함이 바람직하며, 이 입출력패드(2a) 역시 도전성 접속수단(8)에 의해 칩탑재판(4)에 접속되어 있다. 상기 도전성 접속수단(8)(특히, 골드볼 또는 솔더볼의 경우)이 융착되는 영역의 외주연인 칩탑재판(4) 표면에도 절연층이 코팅되어 있음으로써 상기 도전성 접속수단(8)의 융착 작업이 용이하게 수행되도록 되어 있다. 또한 전술한 바와 같이 상기 도전성 접속수단은 이방성 전도필름이 이용될 수도 있다.
상기와 같이 하여 그라운드/파워용의 입출력패드(2a)가 일체의 칩탑재판(4)에 접속됨으로써 많은 신호용 리드(6)를 확보할 수 있게 되며, 이에 따라 동일한 면적하에서 파인피치화한 반도체칩(2)을 탑재할 수 있게 된다.
더불어, 상기 칩탑재판(4)의 하면에는 도전성페이스트 또는 다수의 도전성볼을 더 형성시킬 수도 있다. 이와 같이 하여, 상기 도전성페이스트 또는 도전성볼이 차후 마더보드에 접속되면, 그 반도체칩의 방열성능 향상은 물론, 파워/그라운드 신호의 처리도 용이해진다.
한편, 도4a 및 도4b에 도시된 반도체패키지(103)(제3실시예)는 반도체칩(2)의 상면이 패키지몸체(10) 외측으로 노출되어 있다. 따라서 반도체칩(2)의 열이 상기 노출된 표면을 통해서 외부로 신속히 방출되어 방열 성능이 향상된다.
도5는 본 발명의 반도체패키지(101,102,103)에 이용된 마이크로 리드프레임의 일부를 도시한 평면도이다. 특히, 도3a에 이용된 마이크로 리드프레임이다.
도시된 바와 같이 중앙에 반도체칩(2)이 탑재되는 칩탑재판(4)이 구비되어 있고, 상기 칩탑재판(4)의 각 모서리에는 외측으로 연장되어 타이바가 형성되어 있다. 또한 상기 칩탑재판(4)의 외주연에는 대략 방사상으로 다수의 리드(6)가 형성되어 있다.
상기 칩탑재판(4)의 상면 전체에는 절연층(16)이 코팅되어 있되, 상기 칩탑재판(4)이 외부로 오픈되도록 다수의 개구(16a)가 형성되어 있다. 또한 상기 리드(6) 상면에도 일정 영역이 절연층(16)으로 코팅되어 있되, 리드(6)의 상면이 외부로 오픈되도록 소정 영역에 개구(16a)가 형성되어 있다. 상기 개구(16a)는 평 면상 대략 원형으로 형상함이 바람직하며, 크기는 도전성 접속수단(8)에 대응되는 크기로 함이 바람직하다. 또한, 상기 개구(16a)를 통해 외측으로 노출되는 칩탑재판(4) 및 리드(6)의 표면에는 상기 도전성 접속수단(8)와의 양호한 본딩을 위해 금(Au), 은(Ag), 니켈(Ni) 또는 팔라디움(Pd) 등을 도금함이 바람직하다.
상기 개구(16a)에는 차후 도전성 접속수단(8)가 위치되며, 상기 도전성 접속수단(8)에 의해 반도체칩(2)과 칩탑재판(4) 또는 리드(6)가 상호 전기적으로 접속된다. 상기 도전성 접속수단(8)는 통상 반도체칩(2)과 칩탑재판(4) 또는 리드(6)를 연결할 때에 녹아 있는 상태이기 때문에, 상기와 같이 웰(Well) 역할을 하는 개구(16a)가 상기 액체상태의 도전성 접속수단(8)가 외측으로 흘러가는 것을 막아주게 된다.
본 발명에서는 반도체칩과 리드를 상호 접속시켜주는 도전성 접속수단과 반도체칩과 칩탑재판을 상호 접속시켜주는 도전성 접속수단을 동일한 참조번호 8로서 나타내고 혼용하여 사용하였지만, 상기 두 도전성 접속수단을 구별하기 위해, 전자를 제 1 도전성 접속수단으로, 후자를 제 2 도전성 접속수단으로 명명할 수도 있다. 다만, 이는 형식적인 구분에 불과하고, 상기 두 접속수단의 형태나 재질이 달라야 함을 의미하는 것은 아니다.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기예만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.
따라서 본 발명에 의한 반도체패키지에 의하면, 반도체칩과 리드가 도전성 접속수단에 의해 접속됨으로써 종래의 와이어 루프 하이트가 없어지고 따라서 반도체패키지의 두께가 더욱 박형화되는 효과가 있다.
또한, 종래의 와이어 본딩을 위한 공간이 필요없게 됨으로써 동일한 리드프레임상에 보다 큰 반도체칩을 탑재할 수 있는 효과가 있다.
또한, 반도체칩의 열방출 경로가 반도체칩 하면의 칩탑재판 뿐만 아니라, 그 외주연의 리드까지 확장됨으로써 방열성능이 향상되며, 더욱이 반도체칩의 상면이 패키지몸체 외측으로 직접 노출될 수 있음으로써 상기 방열성능이 우수한 효과가 있다.
또한, 모든 그라운드/파워용 입출력패드를 반도체칩 하면의 중앙부분에 형성하고, 이를 도전성 접속수단를 이용하여 칩탑재판에 접속함으로써 신호용 리드를 최대한 확보할 수 있으며, 또한 동일한 크기의 리드프레임에 파인피치화한 반도체칩을 탑재할 수 있는 효과가 있다.
또한, 상기 도전성 접속수단가 접속되는 칩탑재판 또는 리드의 소정 영역을 제외한 그 외주연을 일정두께의 절연층으로 코팅함으로써, 상기 도전성 접속수단를 상기 칩탑재판 또는 리드의 소정 영역에 융착시, 그 도전성 접속수단가 외측으로 흘러가지 않토록 함으로써 접속 작업이 보다 용이하게 수행되는 효과도 있다.

Claims (11)

  1. 하면에 다수의 입출력패드가 형성된 반도체칩;
    상기 반도체칩 밑에 위치하며, 하방으로 적어도 하나의 돌기부가 형성된 다수의 리드;
    상기 반도체칩 밑에, 그리고 상기 다수의 리드 사이에 위치한 칩탑재판;
    상기 반도체칩 하면의 입출력패드와 상기 리드를 상호 전기적으로 접속하는 제 1 도전성 접속수단;
    상기 반도체칩 하면 중앙부에 형성된 다수의 입출력패드와 상기 칩탑재판을 상호 전기적으로 접속하는 제 2 도전성 접속수단; 및
    상기 반도체칩, 상기 리드, 상기 칩탑재판, 상기 제 1 및 제 2 도전성 접속수단을 봉지재로 봉지하되, 상기 리드의 상기 돌기부 하면과 상기 칩탑재판의 하면은 외부로 노출되도록 형성된 패키지몸체;를 포함하여 이루어진 것을 특징으로 하는 반도체패키지.
  2. 제 1 항에 있어서,
    상기 제 1 및 제 2 도전성 접속수단은 골드볼, 솔더볼 또는 이방성 전도필름 중 어느 하나인 것을 특징으로 하는 반도체패키지.
  3. 제 1 항에 있어서,
    상기 제 1 및 제 2 도전성 접속수단으로서 골드볼 또는 솔더볼이 이용되었을 경우, 상기 접속수단과 접속되는 칩탑재판의 상면 가운데 상기 접속되는 영역의 외주연이 일정두께의 절연층으로 코팅된 것을 특징으로 하는 반도체패키지.
  4. 제 1 항에 있어서,
    상기 칩탑재판의 하면에는 도전성 페이스트 또는 다수의 도전성볼이 더 형성된 것을 특징으로 하는 반도체패키지.
  5. 제 1 항에 있어서,
    상기 반도체칩은 상면이 패키지몸체 외측으로 노출된 것을 특징으로 하는 반도체패키지.
  6. 제 1 항에 있어서,
    상기 리드의 상기 돌기부는 열과 행으로 어레이되어 형성된 것을 특징으로 하는 반도체패키지.
  7. 제 1 항에 있어서,
    상기 리드의 상기 돌기부 하면에 도전성볼이 융착된 것을 특징으로 하는 반도체패키지.
  8. 삭제
  9. 삭제
  10. 삭제
  11. 삭제
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US09/816,852 US6858919B2 (en) 2000-03-25 2001-03-23 Semiconductor package
SG200101839A SG91352A1 (en) 2000-03-25 2001-03-23 Semiconductor package
US10/944,241 US6953988B2 (en) 2000-03-25 2004-09-17 Semiconductor package

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