KR100687331B1 - Thin Film Transistor Manufacturing Method - Google Patents

Abstract

The present invention discloses a method for manufacturing a thin film transistor. The configuration of the present invention comprises the steps of: forming a gate and a TFT portion on a transparent insulating substrate using a first mask process; Forming a gate insulating film on the gate; Sequentially forming a source / drain metal and a first ITO film on the gate insulating film, and forming a source / drain portion of the data signal line and the TFT portion using a second mask process; Forming an a-Si channel layer on the first ITO surface; Forming a protective film on an upper surface of the entire structure and exposing the first ITO using a fourth mask and an etching process; And forming a second ITO connected to the first ITO through an exposed portion of the first ITO using a fifth mask process. Therefore, by forming an ohmic layer without forming n + a-Si, a thin film transistor can be manufactured without a separate back channel without an etching process, and thus the thickness of the a-Si channel layer can be reduced compared to the conventional method, thereby reducing production costs. .

Description

Method for manufacturing Thin Film Transistor

1A to 1F are cross-sectional views of a TFT manufacturing process according to an embodiment of the present invention.

     <Description of Symbols for Main Parts of Drawings>

1: glass substrate 2: gate

3: gate insulator 4a: source (S)

4b: drain (D) 5: first ITO

6: a-Si 7: PVX (protective film)

8: second ITO (pixel electrode)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor liquid crystal display (TFT-LCD) manufacturing method, and in particular, an ohmic layer is formed without forming n + a-Si in a manufacturing process using 5 masks. The present invention relates to a thin film transistor (TFT) manufacturing method capable of manufacturing a thin film transistor (TFT) without etching a back channel.

In general, in a conventional TFT-LCD manufacturing process, a technology of fabricating a thin film transistor (TFT) by forming an ohmic layer by forming n + a-Si and etching a back channel is performed. Apply.

In the existing 5Mask manufacturing technology, a process of etching back channel is applied to etch n + a-Si, which is an ohmic layer, and a-Si, which is an active channel layer. It is a technique for manufacturing a thin film transistor (TFT) by separating the drain portion (Drain). In this case, since a-Si is damaged by the plasma during back channel etching, the characteristics of the thin film transistor TFT are degraded.

For reference, the leakage current of a TFT manufactured by using the 7 Mask process is about 1 pA, whereas the back channel etching type TFT manufactured by the conventional 5 Mask process has a high leakage current of about 20 to 30 pA. Has

In order to prevent deterioration of the characteristics of the thin film transistor, the thickness of a-Si is reduced to about 2000Å to minimize damage, but the thin film transistor according to the position of the panel due to the uneven thickness of the film and the etching unevenness ), And leakage current increases due to plasma damage caused by back channel etching, causing TFT characteristics to deteriorate and panel quality. There is a problem.

Accordingly, the present invention has been made to solve the problems of the prior art, an object of the present invention can suppress the rise of the leakage current (back current) due to back channel (Back Channel) etching, Ohh layer (Ohmic Layer) It is to provide a thin film transistor manufacturing method that can simplify the process by eliminating the film forming and etching process.

The present invention for achieving the object of the present invention, forming a gate and a TFT portion on the transparent insulating substrate using a first mask process; Forming a gate insulating film on the gate; Sequentially forming a source / drain metal and a first ITO film on the gate insulating film, and forming a source / drain portion of the data signal line and the TFT portion using a second mask process; Forming an a-Si channel layer on the first ITO surface; Forming a protective film on an upper surface of the entire structure and exposing the first ITO using a fourth mask and an etching process; And forming a second ITO connected to the first ITO through an exposed portion of the first ITO by using a fifth mask process.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1F are cross-sectional views of a thin film transistor fabrication process without an ohmic layer film formation and etching process according to an embodiment of the present invention.

In the method of manufacturing a thin film transistor according to the present invention, as shown in FIG. 1A, a gate of molybdenum tungsten alloy (MoW) 2 is formed on a glass substrate 1 for a lower substrate in a first deposition process. ) Is deposited and patterned in the first mask process to form the gate signal line and the TFT portion 2.

Next, as shown in FIG. 1B, a gate insulator 3 is formed on the gate deposited on the glass substrate in the second deposition process.

Subsequently, as shown in FIG. 1C, in a third deposition process, a source / drain (4a / 4b) metal is formed on the gate insulating film 3, and the first indium tin oxide is successively formed. (5). Then, the source / drain portions 4a and 4b of the data signal line and the TFT portion are formed by the second mask process.

Then, as shown in FIG. 1D, in the third process, phosphorus hydride (PH3) plasma is treated on the surface of the first ITO 5 to indium phosphate (InPOx) on the surface of the first ITO 5. By forming the a-Si channel layer 6 on ohmic contact with the a-Si channel layer 6 to be laminated later, the a-Si channel layer 6 is formed on the first ITO 5.

Subsequently, as illustrated in FIG. 1E, an active area is defined in a third mask process, a passivation layer 7 is deposited in a fourth process, and a fourth mask and an etching is performed. & Via process to form a via hole (not shown).

Next, as shown in FIG. 1F, a second ITO (Pixel electrode) is deposited on the upper right side of the drain of the TFT 2 in the fifth process, and then an ITO pixel pattern is formed through a mask and etching process. (pixel pattern) (8) is formed.

In the TFT-LCD manufacturing process as described above, the gate of the first deposition process is molybdenum (Mo), molybdenum tungsten alloy (MoW), upper molybdenum / lower aluminum (neodymium alloy) (Mo / Al (Nd)) or molybdenum / aluminum / molybdenum alloy (Mo / Al / Mo) can be used as the wiring metal. Further, the a-Si channel layer 6 is treated with phosphorus hydride (PH3) plasma to form an n + a-Si ohmic layer, whereby the ITO pixel pattern 8 and ohmic stacked later are formed. You can make contact.

In the fifth mask structure, the source / drain (S / D) metal and the ITO pixel pattern are simultaneously formed, and the S / D metal is a data signal line, and the first ITO (top) of the S / D metal is formed. 5) forms an indium phosphate (InPOx) on the surface of the first ITO (5) by treating with a phosphorous (PH3) plasma to form an a-Si channel layer 6 to be laminated later and ohmic; The first ITO is patterned in an ohmic area of the S / D so as to be used as an ohmic layer to be brought into contact, and as the gate and passivation insulator, SiN, SiON, SiO2, etc. Single films or films of SiN / SiON, SiN / SiO ₂ multilayers can be applied.

At this time, the phosphorus hydride (PH3) plasma treatment conditions are applied to the phosphorus hydride (PH3) power 500 ~ 1500W, the plasma treatment temperature is 250 to 350 ℃, the plasma treatment time is 10 seconds to 60 seconds.

In the subsequent formation of the a-Si channel layer 6 after the phosphorus hydride (PH3) plasma treatment before the formation of the a-Si channel layer 6, the phosphorus hydride (PH3) plasma treatment is performed on the first ITO 5. After forming the ohmic layer (Ohmic Layer) to form a-Si channel layer 6 to a thickness of 100 ~ 1000 kPa.

Here, as shown in FIG. 1D, before forming the a-Si channel layer 6 in the fourth process, phosphorus hydride (PH3) plasma treatment is performed to break oxygen bonds of ITO by H radicals of phosphorus hydride (PH3). P and In are combined.

At this time, since the bonding force of indium-oxygen (In-O) is smaller than that of indium-phosphorus oxide (In-POx), phosphorus hydride (PH3) plasma treatment to form a thin layer of indium phosphate (InPOx) on the surface of the ITO. Thereafter, the a-Si channel layer 6 is successively formed. In addition, indium phosphide (InPOx) bonds on the surface of the first ITO 5 are etched by H radicals of silicon hydride (SiH 4) during a-Si formation. That is, indium phosphate (InPOx) formed on the surface of the first ITO (5) is etched by H radicals of silicon hydride (SiH4) in an a-Si film forming atmosphere, and phosphorus (PH, PH2) radicals and hydrogenation The ohmic layer is formed in the form of a phosphorus (PH3) molecule to give an effect of doping the amorphous silicon layer to the a-Si and ITO interface.

As illustrated in FIG. 1E, the insulator of the via-hole and the insulator of the gate and the data pad part for connecting the pixel part of the source are etched and opened. As shown in FIG. 1F, after forming the second ITO 8, the ITO pixel pattern 8 is patterned by a fifth mask process.

Therefore, a thin film transistor can be fabricated without an additional back channel by etching by forming an ohmic layer without forming n + a-Si in a manufacturing process using 5 masks, thereby reducing the thickness of the a-Si channel layer. It can further reduce the production cost.

As described above, the thin film transistor manufacturing method without the ohmic layer forming and etching process according to the present invention does not apply the forming process of the n + a-Si film, which is an ohmic layer. The thickness of the a-Si channel layer can be reduced compared to the conventional method, thereby reducing the production cost.

In addition, since an ohmic layer is formed without n + a-Si film formation, no separate back channel etching is required, and since back channel etching is not performed, plasma damage generated during etching is eliminated. Therefore, the thickness of a-Si, which is a channel layer, can be reduced, thereby reducing the production cost.

In the present invention, since the n + a-Si film forming and etching process can be omitted, and a thin a-Si channel layer can be applied, the thin film transistor (TFT) process can be expected to be improved and the TFT performance can be expected. In addition, the use of ITO instead of n + a-Si, which has poor film uniformity, is advantageous for large-sized LCD panels.

Claims (7)

Forming a gate and a TFT portion on the transparent insulating substrate using a first mask process; Forming a gate insulating film on the gate; Sequentially forming a source / drain metal and a first ITO film on the gate insulating film, and forming a source / drain portion of the data signal line and the TFT portion using a second mask process; Before forming the a-Si channel layer on the surface of the first ITO and after forming the source / drain portion and the first ITO of the data signal line and the TFT portion by using the second mask process, the first ITO is a phosphorus hydride (PH3) plasma (Plasma). Treating with; Forming an a-Si channel layer on the first ITO surface; Forming a protective film on an upper surface of the entire structure and exposing the first ITO using a fourth mask and an etching process; Forming a second ITO connected to the first ITO through an exposed portion of the first ITO using a fifth mask process. The gate of claim 1 wherein the gate is molybdenum (Mo), molybdenum tungsten alloy (MoW), upper molybdenum / lower aluminum (neodymium alloy) (Mo / Al (Nd)), or molybdenum / aluminum / mol A thin film transistor manufacturing method using any one of lead denium (Mo / Al / Mo). delete The method of claim 1, wherein an interface between the first ITO and the a-Si channel layer is used as an ohmic layer. The method of claim 1, wherein the passivation layer is formed of a single layer of SiN, SiON, SiO _2, or a multilayer of SiN / SiON, SiN / SiO _2, or the like. The phosphorus hydride (PH3) plasma treatment conditions of claim 3 wherein the phosphorus hydride (PH3) power is applied at 500 to 1500 W, the plasma treatment temperature is 250 to 350 ° C., and the plasma treatment time is 10 to 60 seconds. Thin film transistor manufacturing method, characterized in that. The method of claim 1, wherein the thickness of the a-Si channel layer is 100 to 1000 GPa.

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