KR101884796B1 - Thin film transistor, Flat display device, and Method for fabricating the same - Google Patents

Abstract

The present invention relates to a thin film transistor in which the impurity concentration of the ohmic contact layer located between the source and drain electrodes and the intrinsic semiconductor layer has a slope in which the impurity concentration decreases from the source and drain electrodes toward the intrinsic semiconductor layer, A method of manufacturing a thin film transistor, comprising: forming a gate electrode on a substrate; Forming a gate insulating layer on the substrate including the gate electrode; And a second semiconductor layer formed on the first semiconductor layer and doped with an impurity; a source connected to the active layer; and a second semiconductor layer formed on the gate electrode, Wherein the doping concentration of the second semiconductor layer is higher than the doping concentration of the source in the interface with the first semiconductor layer by forming the second semiconductor layer by sequentially increasing the supply amount of the impurity, And the contact surface of the drain electrode.

Description

TECHNICAL FIELD [0001] The present invention relates to a thin film transistor (TFT), a liquid crystal display device including the thin film transistor, and a method of fabricating the thin film transistor,

The present invention relates to a thin film transistor in which the impurity concentration of the ohmic contact layer located between the source and drain electrodes and the intrinsic semiconductor layer has a slope in which the impurity concentration decreases from the source and drain electrodes toward the intrinsic semiconductor layer, ≪ / RTI >

In general, a liquid crystal display device is driven by using optical anisotropy and polarization properties of a liquid crystal. Since liquid crystal has a long structure, it has directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal. Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

More specifically, the liquid crystal panel includes a liquid crystal layer interposed between lower and upper substrates and lower and upper substrates bonded together with a space. A plurality of pixel electrodes formed on the plurality of pixel regions, and a plurality of data lines connected to the plurality of gate and data lines, the data signals being applied to the pixel regions, A plurality of thin film transistors are formed. A common electrode for generating an electric field for driving the liquid crystal layer together with a plurality of pixel electrodes, a black matrix for blocking light in a portion excluding the pixel region, and a color filter layer for realizing R, G, and B color are formed on the upper substrate .

Hereinafter, a method of manufacturing an array substrate of a liquid crystal display according to the related art will be described in detail with reference to the drawings.

FIGS. 1A to 1D are process cross-sectional views illustrating steps of manufacturing an array substrate of a liquid crystal display device including a thin film transistor according to the related art.

1A, a gate insulating layer 30 is formed on a substrate 10 including a gate electrode 20 and a gate electrode 20 on a substrate 10, and impurities are implanted into the gate insulating layer 30 The undoped first amorphous silicon layer 40 and the N-type impurity-doped second amorphous silicon layer 42 are sequentially formed and the metal material layer 50 is formed on the second amorphous silicon layer 42 do. A second amorphous silicon layer 42 is N-type impurity with a silicon source is formed by supply of 500sccm for 20 seconds, a PH ₃ gas.

A first photosensitive layer pattern 60a and a second photosensitive layer pattern 60b having a smaller thickness than the first photosensitive layer pattern 60 are formed on the metal material layer 50 as shown in FIG.

The first and second photosensitive layer patterns 60a and 60b are formed by forming a photosensitive layer (not shown) on the metal material layer 50 and exposing and developing the photosensitive layer to which a halftone mask is applied. The thickness of the first photosensitive layer pattern 60a is thicker than that of the second photosensitive layer pattern 60b.

When the first and second amorphous silicon layers 40 and 42 and the metal material layer 50 are etched using the first and second photosensitive layer patterns 60a and 60b as an etching mask, A pattern composed of the first and second amorphous silicon layers 40 and 42 and the metal material layer 50 is formed on the gate insulating layer 30 corresponding to the gate electrodes 20 and 20. In the process of etching the first and second amorphous silicon layers 40 and 42 and the metal material layer 50 using the first and second photosensitive layer patterns 60a and 60b as etching masks, The second photosensitive layer patterns 60a and 60b become thinner than the original thickness and completely remove the second photosensitive layer pattern 60b by the progress of the continuous etching process.

The metal material layer 50 and the first and second amorphous silicon layers 40 and 42 corresponding to the channel region CH are etched by using the first photosensitive layer pattern 60a as an etch mask, (70) and source and drain electrodes (80a, 80b). 1D, the formation of the thin film transistor T composed of the gate electrode 20, the gate insulating layer 30, the active layer 70, and the source and drain electrodes 80a and 80b is completed on the substrate 10 do. 1D, a protective layer 82 is formed on the gate insulating layer 30 including the thin film transistor T, and the protective layer 82 is selectively etched to expose the drain electrode 80b The pixel electrode 90 connected to the drain electrode 80b through the contact hole 84 is formed on the protective layer 82 after the contact hole 84 is formed.

In the thin film transistor T, the active layer 70 is composed of the first and second amorphous silicon layers 40 and 42, and the first amorphous silicon layer 40, which is an intrinsic semiconductor layer without doping the impurity, The second amorphous silicon layer 40 doped with the N-type impurity is used as the channel region CH between the electrodes 80a and 80b and the source and drain electrodes 80a and 80b formed of a metal material Which acts as an ohmic contact layer. However, if the second amorphous silicon layer 42 doped with an impurity exists in a portion corresponding to the channel region CH, the thin film transistor T is difficult to perform the switching function. Therefore, the second amorphous silicon layer 42 corresponding to the channel region CH must be removed.

1A, a portion of the N-type impurity is diffused into the first amorphous silicon layer 40, which is an intrinsic semiconductor layer, in the process of forming the second amorphous silicon layer 42. [ 1D, a portion of the first amorphous silicon layer 40 is formed together with the second amorphous silicon layer 42 in the channel region CH to form a first amorphous silicon layer 40. In order to remove the impurity-diffused first amorphous silicon layer 40, And then performing an overetching process. If the N-type impurity supplied from the second amorphous silicon layer 42 remains in the first amorphous silicon 40 without overetching the first amorphous silicon layer 40 in the channel region CH, The source and drain electrodes 80a and 80b may be electrically connected to each other through the channel region CH to cause a current to flow even in an off-state.

1A to 1D illustrate that a single thin film transistor T is formed on a substrate 10 but a plurality of thin film transistors T are actually formed and a uniform etching is performed according to the position of the substrate 10. [ It is difficult to ensure uniformity. In other words, even if the first amorphous silicon layer 40 is etched under the same process conditions, the etching rate of the first amorphous silicon layer 40 is different depending on the position of the substrate 10. For example, when the etching rate of the first amorphous silicon layer 40 is larger at the peripheral portion than at the central portion of the substrate 10, the first amorphous silicon layer 40 is excessively etched based on the peripheral portion having the lowest etching rate .

Therefore, since the transient etching is performed not only in the portion where the impurity is diffused in the first amorphous silicon layer 40 but also in the etching uniformity, the thickness of the first amorphous silicon layer 40 must be sufficiently secured. However, when the thickness of the first amorphous silicon layer 40 is increased, the deposition time and the etching time are increased, and the resistance is increased in proportion to the thickness of the first amorphous silicon layer 40, This degradation is problematic.

In order to solve the above problems, the present invention has a doping profile in which the impurity concentration of the ohmic contact layer located between the source and drain electrodes and the intrinsic semiconductor layer decreases in the direction of the intrinsic semiconductor layer from the source and drain electrodes, A thin film transistor for improving switching characteristics by reducing a thickness of a semiconductor layer, a liquid crystal display device including the thin film transistor, and a manufacturing method thereof.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a gate electrode on a substrate; Forming a gate insulating layer on the substrate including the gate electrode; An active layer including a first semiconductor layer, which is an intrinsic semiconductor layer, and a second semiconductor layer, which is formed on the first semiconductor layer and is doped with an impurity, on a gate insulating layer corresponding to the gate electrode; Wherein the doping concentration of the second semiconductor layer is higher than the doping concentration of the source and the drain in the interface with the first semiconductor layer by forming the second semiconductor layer by sequentially increasing the supply amount of the impurity, Drain electrode and the contact surface of the drain electrode.

Wherein the doping concentration of the second semiconductor layer is minimum at the interface with the first semiconductor layer and maximum at the interface between the source and drain electrodes.

Wherein a doping concentration of the second semiconductor layer increases linearly from a contact surface with the first semiconductor layer to a contact surface between the source and drain electrodes.

The forming of the active layer and the source and drain electrodes may include sequentially forming the first semiconductor layer, the second semiconductor layer, and the metal material layer on the gate insulating layer; Forming a first photosensitive layer pattern corresponding to the source and drain electrodes on the metal material layer and a second photosensitive layer pattern having a thickness smaller than the thickness of the first photosensitive layer pattern and corresponding to between the source and drain electrodes step; Etching the first and second semiconductor layers and the metal material layer using the first and second photosensitive layer patterns as an etching mask; And removing the second photosensitive layer pattern and etching the first and second semiconductor layers between the source and drain electrodes using the first photosensitive layer pattern as an etching mask. .

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a gate electrode on a substrate; Forming a gate insulating layer on the substrate including the gate electrode; An active layer including a first semiconductor layer, which is an intrinsic semiconductor layer, and a second semiconductor layer, which is formed on the first semiconductor layer and is doped with an impurity, on a gate insulating layer corresponding to the gate electrode; Forming an electrode; Forming a protective layer on the active layer and the gate insulating layer including the source and drain electrodes; And forming a pixel electrode connected to the drain electrode on the passivation layer, wherein the doping concentration of the second semiconductor layer is increased by sequentially increasing the amount of impurities supplied to the pixel electrode, Wherein the source electrode and the drain electrode are sequentially increased from a contact surface with the first semiconductor layer to a contact surface between the source electrode and the drain electrode.

According to an aspect of the present invention, A gate electrode; A gate insulating layer on the substrate including a gate electrode; An active layer formed on the gate insulating layer corresponding to the gate electrode and including a first semiconductor layer not doped with an impurity and a second semiconductor layer formed on the first semiconductor layer and doped with an impurity; And a source and drain electrode connected to the active layer, wherein the doping concentration of the second semiconductor layer is increased linearly from a contact surface with the first semiconductor layer to a contact surface between the source and drain electrodes do.

According to an aspect of the present invention, A gate electrode; A gate insulating layer on the substrate including a gate electrode; An active layer formed on the gate insulating layer corresponding to the gate electrode and including a first semiconductor layer not doped with an impurity and a second semiconductor layer formed on the first semiconductor layer and doped with an impurity; Source and drain electrodes connected to the active layer; A protective layer on the active layer and the source and drain electrodes; And a pixel electrode formed on the protection layer and connected to the drain electrode, wherein a doping concentration of the second semiconductor layer is linearly increased from a contact with the first semiconductor layer to a contact with the source and drain electrodes There is provided an array substrate of a liquid crystal display device.

The present invention has a doping profile in which the impurity concentration of the ohmic contact layer located between the source and drain electrodes and the intrinsic semiconductor layer decreases in the direction of the intrinsic semiconductor layer from the source and drain electrodes, Can be reduced. The thickness of the intrinsic semiconductor layer is minimized according to the reduction of the depth of the over-etching, and thus the deposition time for etching the intrinsic semiconductor layer and the etching time for etching are minimized, and the overall process time can be reduced. Also, when the thickness of the intrinsic semiconductor layer is reduced, the resistance of the channel region CH is decreased, and the mobility of electrons moving in the channel region CH is increased to improve the characteristics of the TFT.

FIGS. 1A to 1D are cross-sectional views showing steps of a manufacturing process for an array substrate of a liquid crystal display device including a thin film transistor according to the related art
FIGS. 2A to 2D are process cross-sectional views showing steps of manufacturing an array substrate of a liquid crystal display device including the thin film transistor according to the present invention
3 is a graph showing the doping profile of the ohmic contact layer according to the present invention and the related art

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Hereinafter, a method of manufacturing an array substrate of a liquid crystal display device according to the present invention will be described in detail with reference to the drawings.

FIGS. 2A to 2D are process cross-sectional views showing steps of manufacturing an array substrate of a liquid crystal display device including a thin film transistor according to the present invention.

2A, a gate insulating layer 130 is formed on a substrate 110 including a gate electrode 120 and a gate electrode 120 on a substrate 110. Referring to FIG. The substrate 110 is a glass substrate and the gate insulating layer 130 is formed using an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x), for example, by a method such as PECVD.

The gate electrode 120 may be formed of a single layer, a double layer, or a triple layer using a conductive metal such as copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd), and chromium have. When the gate electrode 120 is formed as a double layer, it may include a lower layer made of molybdenum (Mo) or titanium (Ti) or an alloy thereof and an upper layer made of copper (Cu).

The method of forming the gate electrode 120 includes forming a first metal material layer (not shown) on the substrate 110, forming a first photosensitive layer (not shown) on the first metal material layer Forming a first photosensitive layer pattern (not shown) on exposure and development of a first photosensitive layer to which a first mask (not shown) is applied, forming a first photosensitive layer pattern And patterning the layer. A gate wiring (not shown) is formed at the same time as the gate electrode 120.

A first semiconductor layer 140, a second semiconductor layer 142 and a second metal material layer 150 are sequentially formed on the gate insulating layer 130 and the second metal material layer 150 The first and second photosensitive layer patterns 160a and 160b are formed.

The first semiconductor layer 140 is an intrinsic semiconductor layer and is formed of amorphous silicon that is not doped with impurities. The second semiconductor layer 142 is an ohmic contact layer and is an N-type impurity, for example, For example, amorphous silicon doped with phosphorus (P). Phosphorus (P) uses PH ₃ as a doping source. The first semiconductor layer 140 is formed to a thickness of approximately 1700 ANGSTROM and the second semiconductor layer 142 is formed to a thickness of approximately 300 ANGSTROM.

The first semiconductor layer 140 is formed by a PECVD method by supplying a silicon source, for example SiH ₄ , without supplying an impurity source, and the second semiconductor layer 142 is formed by a PECVD method by supplying an impurity and a silicon source do. The process of forming the second semiconductor layer 142 is divided into the first to the n-th sections R1 to Rn and the supply amount of the impurity source from the first section R1 to the n-th section Rn is It increases sequentially. In other words, the supply amount of the impurity source is minimum in the first section R1 and becomes maximum in the nth section Rn.

For example, when the second semiconductor layer 142 is formed by supplying PH ₃ to the silicon source and the doping source for 20 seconds, the deposition process is divided into the first to fourth sections R1 to R4, PH ₃ is supplied at 100, 200, 300, 400 and 500 sccm for 4 seconds to each of the first to fourth sections R1 to R4. When the second semiconductor layer 142 is formed under such a condition, the second semiconductor layer 142 that is in contact with the first semiconductor layer 140 is doped with the lowest concentration, The upper portion of the second semiconductor layer 142 that is in contact is doped to the highest concentration.

The second metal material layer 150 may be formed of a single layer, a double layer, or a triple layer using a conductive metal such as copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd) .

The thickness of the first photosensitive layer pattern 160a formed on the second metal material layer 150 is greater than the thickness of the second photosensitive layer pattern 160b. The first and second photosensitive layer patterns 10a and 10b may be formed by forming a second photosensitive layer (not shown) on the second metal material layer 150 and exposing and developing the second photosensitive layer using a halftone mask . Although not shown in the drawing, the halftone mask includes a transmission region for transmitting all the irradiation light, a blocking region for completely blocking the irradiation light, and a semi-transmission region for transmitting a part of the irradiation light, and corresponds to the blocking region of the halftone mask The thickness of the first photosensitive layer pattern 160a formed to be thicker than the thickness of the second photosensitive layer pattern 160b formed to correspond to the transflective region of the halftone mask. Then, the second photosensitive layer corresponding to the transmission region of the halftone mask is removed, and the gate insulating layer 130 is exposed.

When the first and second semiconductor layers 140 and 142 and the second metal material layer 150 are etched using the first and second photosensitive layer patterns 160a and 160b as an etching mask, A pattern composed of the first and second semiconductor layers 140 and 142 and the second metal material layer 150 is formed on the gate insulating layer 130 corresponding to the first insulating layer 120. In the process of etching the first and second semiconductor layers 140 and 142 and the second metal material layer 150 using the first and second photosensitive layer patterns 160a and 160b as an etching mask, The thickness of the first and second photosensitive layer patterns 160a and 160b is reduced and the first photosensitive layer pattern 160b is completely removed as shown in FIG.

The first metal material layer 150 and the first and second semiconductor layers 140 and 142 corresponding to the channel region CH are etched using the first photosensitive layer pattern 160a as an etching mask, The active layer 170 and the source and drain electrodes 180a and 180b are formed. 2D, the second semiconductor layer 142 corresponding to the channel region CH is completely removed, and the first semiconductor layer 140 is partially removed. The first semiconductor layer 140 formed to a thickness of approximately 1700 ANGSTROM is etched to a depth of approximately 700 to 900 ANGSTROM. The concentration and depth of the impurity diffused in the first semiconductor layer 140 can be minimized in the step of forming the second semiconductor layer 142 and the thickness of the first semiconductor layer 140 can be reduced.

If the active layer 170 and the source and drain electrodes 180a and 180b are formed by etching the first and second semiconductor layers 140 and 142 corresponding to the channel region CH as shown in FIG. The formation of the thin film transistor T including the gate insulating layer 120, the gate insulating layer 130, the active layer 170, and the source and drain electrodes 180a and 180b is completed. A protective layer 182 is formed on the gate insulating layer 130 including the thin film transistor T and a contact hole 184 is formed to selectively etch the protective layer 182 to expose the drain electrode 180b. A pixel electrode 190 connected to the drain electrode 180b through the contact hole 184 is formed on the passivation layer 182. [

The protective layer 182 may be used by selecting the organic insulating material including an inorganic insulating material or an acrylic photo-benzo cyclo butene and comprises silicon dioxide (SiO ₂₎ and silicon nitride (SiNx). The pixel electrode 190 is formed of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO).

2 (d), the impurity concentration of the second semiconductor layer 142 becomes maximum at the upper surface in contact with the source and drain electrodes 180a and 180b, and becomes minimum at the lower surface in contact with the first semiconductor layer 140. [ Therefore, the concentration of the impurity is minimized at the lower surface of the second semiconductor layer 142, so that the concentration of the impurity diffused into the first semiconductor layer 140 can be minimized.

2D, the diffusion depth of the first semiconductor layer 140 corresponding to the channel region CH is minimized because the diffusion of the impurity into the first semiconductor layer 140 is minimized, Can be minimized. The thickness of the first semiconductor layer 140 is determined in consideration of the transient etching depth. When the depth of the transient etching is minimized, the thickness of the first semiconductor layer 140 can be minimized. When the thickness of the first semiconductor layer 140 is minimized, the deposition time for depositing the first semiconductor layer 140 and the etching time for etching the first semiconductor layer 140 corresponding to the channel region CH are minimized Thereby reducing the overall process time. When the thickness of the first semiconductor layer 140 is reduced, the resistance of the channel region CH is decreased and the mobility of electrons moving in the channel region CH increases, Improvement.

The characteristics of the thin film transistor of the present invention and the prior art are shown in Table 1. In the present invention and the prior art, the intrinsic semiconductor layer has a thickness of 300 angstroms. An ohmic contact layer of the present invention is the first to the fourth vapor deposition zone interval (R1 ... R4) to the segment, and the first to fourth sections (R1..R4) the PH ₃ to 100, 200, 300, respectively, 400 and 500 sccm for 4 seconds in total for 20 seconds, and the prior art ohmic contact layer is formed by supplying PH ₃ gas at a rate of 500 sccm for 20 seconds at a time.

division Invention Conventional technology Threshold voltage (V) 1.49 1.48 Mobility m < 2 > / (V * sec) 0.26 0.29 Subthreshold swing (mV / decade) 1033.01 934.87 Off current 38.51 31.28 On current 1.78 2.05

Comparing the present invention with the prior art, it can be seen that although the threshold voltage of the thin film transistor is almost unchanged, the mobility of the electrons, the sub threshold swing and the off current are increased and the on-current is decreased to improve the characteristics of the thin film transistor have.

3 is a graph showing the doping profile of the ohmic contact layer according to the present invention and the related art.

The x-axis represents the diffusion depth, and the y-axis represents the doping concentration. and the thicknesses of the source and drain electrodes, the ohmic contact layer, and the intrinsic semiconductor layer which are sequentially arranged in the x-axis. The red color represents the doping concentration of the present invention, and the black color represents the doping concentration of the prior art. An ohmic contact layer of the present invention is the first to the fourth vapor deposition zone interval (R1 ... R4) to the segment, and the first to fourth sections (R1..R4) the PH ₃ to 100, 200, 300, respectively, 400, and 500 sccm for 4 seconds, respectively, and the prior art ohmic contact layer is formed by supplying PH ₃ gas at 500 sccm for 20 seconds.

The doping concentration of the impurity in the ohmic contact layer of the present invention decreases linearly from the upper surface in contact with the source and drain electrodes to the lower surface in contact with the intrinsic semiconductor layer. That is, the concentration of the impurity of the ohmic contact layer are sequentially increased to 4E21 atoms / cm ³ from 1E20 atoms / cm ³ to the abutment surfaces of the source and drain electrodes on the contact face of the intrinsic semiconductor layer. At this time, it can be seen that the first diffusion depth D1 in which the impurity is diffused into the intrinsic semiconductor layer of the present invention is reduced by about half compared with the second diffusion depth D2 in which the impurity is diffused in the intrinsic semiconductor layer of the prior art . However, in the conventional ohmic contact layer, the doping concentration remains almost uniform from the upper surface in contact with the source and drain electrodes to the lower surface in contact with the intrinsic semiconductor layer, and the second diffusion depth D2 ) Is relatively longer than the first diffusion depth D1 of the present invention.

As the depth of diffusion of the impurity into the intrinsic semiconductor layer becomes deeper, the depth of the excessive etching of the intrinsic semiconductor layer must be deepened, and the thickness of the intrinsic semiconductor layer must be increased in consideration of the depth of transient etching. However, since the diffusion depth of the impurity diffused in the intrinsic semiconductor layer is reduced in comparison with the prior art, the depth of the transient etching can be reduced and thus the thickness of the intrinsic semiconductor layer can be reduced.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

Claims (7)

Forming a gate electrode on the substrate;
Forming a gate insulating layer on the substrate including the gate electrode; And
An active layer including a first semiconductor layer, which is an intrinsic semiconductor layer, and a second semiconductor layer, which is formed on the first semiconductor layer and is doped with an impurity, on a gate insulating layer corresponding to the gate electrode; Forming an electrode;
Lt; / RTI >
The doping concentration of the impurity of the second semiconductor layer is set so that the doping concentration of the impurity of the second semiconductor layer is higher than that of the source and drain electrodes at the interface with the first semiconductor layer to the contact face from 1E20 atoms / cm ³ the method of the thin film transistor which sequentially increased to 4E21 atoms / cm ^3.
The method according to claim 1,
Wherein the doping concentration of the impurity in the second semiconductor layer is minimum at the interface with the first semiconductor layer and maximum at the interface between the source and drain electrodes.
The method according to claim 1,
Wherein the doping concentration of the impurity of the second semiconductor layer increases linearly from the interface with the first semiconductor layer to the interface between the source and drain electrodes.
Forming a gate electrode on the substrate;
Forming a gate insulating layer on the substrate including the gate electrode; And
An active layer including a first semiconductor layer, which is an intrinsic semiconductor layer, and a second semiconductor layer, which is formed on the first semiconductor layer and is doped with an impurity, on a gate insulating layer corresponding to the gate electrode; Forming an electrode;
Lt; / RTI >
The doping concentration of the impurity in the second semiconductor layer is gradually increased from the contact face with the first semiconductor layer to the contact face with the source and drain electrodes by sequentially increasing the impurity supply amount to form the second semiconductor layer However,
Wherein forming the active layer and the source and drain electrodes comprises:
Sequentially forming the first semiconductor layer, the second semiconductor layer, and the metal material layer on the gate insulating layer;
Forming a first photosensitive layer pattern corresponding to the source and drain electrodes on the metal material layer and a second photosensitive layer pattern having a thickness smaller than the thickness of the first photosensitive layer pattern and corresponding to between the source and drain electrodes step;
Etching the first and second semiconductor layers and the metal material layer using the first and second photosensitive layer patterns as an etching mask; And
Removing the second photosensitive layer pattern and etching the first and second semiconductor layers between the source and drain electrodes using the first photosensitive layer pattern as an etching mask;
Wherein the step of forming the thin film transistor comprises the steps of:
Forming a gate electrode on the substrate;
Forming a gate insulating layer on the substrate including the gate electrode;
An active layer including a first semiconductor layer, which is an intrinsic semiconductor layer, and a second semiconductor layer, which is formed on the first semiconductor layer and is doped with an impurity, on a gate insulating layer corresponding to the gate electrode; Forming an electrode;
Forming a protective layer on the active layer and the gate insulating layer including the source and drain electrodes; And
Forming a pixel electrode connected to the drain electrode on the protective layer;
Lt; / RTI >
The doping concentration of the impurity of the second semiconductor layer is set so that the doping concentration of the impurity of the second semiconductor layer is higher than that of the source and drain electrodes at the interface with the first semiconductor layer Wherein the interface is sequentially increased from 1E20 atoms / cm < ³ > to 4E21 atoms / cm < ³ >
Board;
A gate electrode;
A gate insulating layer on the substrate including a gate electrode;
An active layer formed on the gate insulating layer corresponding to the gate electrode and including a first semiconductor layer not doped with an impurity and a second semiconductor layer formed on the first semiconductor layer and doped with an impurity; And
Source and drain electrodes connected to the active layer;
/ RTI >
An ohmic contact layer of the second doping concentration of the impurity in the semiconductor layer is the first in the contact face between the semiconductor layer to increase linearly up to the contacting surface of the source and drain electrodes from 1E20 atoms / cm ³ to 4E21 atoms / cm ³ Thin film transistor.
Board;
A gate electrode;
A gate insulating layer on the substrate including a gate electrode;
An active layer formed on the gate insulating layer corresponding to the gate electrode and including a first semiconductor layer not doped with an impurity and a second semiconductor layer formed on the first semiconductor layer and doped with an impurity;
Source and drain electrodes connected to the active layer;
A protective layer on the active layer and the source and drain electrodes; And
A pixel electrode formed on the protective layer and connected to the drain electrode,
/ RTI >
An ohmic contact layer of the second doping concentration of the impurity in the semiconductor layer is the first in the contact face between the semiconductor layer to increase linearly up to the contacting surface of the source and drain electrodes from 1E20 atoms / cm ³ to 4E21 atoms / cm ³ An array substrate of a liquid crystal display device.

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