KR100771889B1 - Split gate type flash memory device and manufacturing method thereof - Google Patents

Abstract

A split gate flash memory device and a method of manufacturing the same are provided. The flash memory device has a floating gate disposed on the active region. A control gate overlapping one side wall and an upper portion of the floating gate is disposed. An edge oxide film formed by selectively oxidizing an upper edge not overlapping with the control gate of the floating gate is disposed.

Description

Split gate type flash memory device and method of manufacturing the same

1 is a plan view illustrating a split gate type flash memory device according to an exemplary embodiment of the present invention.

2A to 2F illustrate a method of manufacturing a split gate type flash memory device according to an exemplary embodiment of the present invention, which are cross-sectional views taken along a cutting line II-II ′ of FIG.

The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly to a split gate type flash memory device and a method of manufacturing the same.

The nonvolatile memory device can electrically write and erase data and retain data even when power is not supplied. Due to these characteristics, applications are currently increasing in various fields including mobile communication systems, memory cards, and the like. Among such nonvolatile memory devices, a flash memory device is a memory device that can be programmed in a cell unit and can be erased in block or sector units. Flash memory devices include a floating gate type and an electron trap layer type according to the type of the gate of the transistor. Examples of the flash gate device include a stack gate type and a split gate type.

The split gate type flash memory device includes a floating gate, a control gate covering a sidewall and an upper portion of the floating gate, and an interpoly dielectric between the floating gate and the control gate. The channel region under the floating gate and the channel region under the control gate are connected in series. The data write of the split gate type flash memory device is performed by injecting hot electrons generated in the channel region into the floating gate, that is, by Hot Electron Injection (HEI), and data erasing is performed. The charge stored in the floating gate is tunneled to the control gate through the inter-gate insulating layer, that is, FN tunneling (Fowler-Nordheim tunneling) method.

In the split gate type flash memory device, the edge of the floating gate overlapping the control gate may be sharply formed to reduce the erase voltage and increase the erase efficiency when data is erased. The corners of the floating gate are also pointed. The sharp edges of the floating gate not overlapping with the control gate may be a path for dissipating the charge stored in the floating gate. In this case, the data retention capability of the split gate type flash memory device can be reduced.

An object of the present invention is to provide a split gate type flash memory device having improved data retention capability and a method of manufacturing the same.

One aspect of the present invention to achieve the above technical problem provides a split gate type flash memory device. The flash memory device has a floating gate disposed on the active region. A control gate overlapping one side wall and an upper portion of the floating gate is disposed. An edge oxide film formed by selectively oxidizing an upper edge not overlapping with the control gate of the floating gate is disposed.

In order to achieve the above technical problem, another aspect of the present invention provides a method of manufacturing a split gate type flash memory device. The manufacturing method includes forming an isolation layer in a substrate to define an active region. A floating gate is formed on the active region. A control gate overlapping the sidewall and the upper portion of one side of the floating gate is formed on the floating gate. An upper edge not overlapping with the control gate of the floating gate is selectively oxidized to form a corner oxide film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. Like reference numerals refer to like elements throughout.

1 is a plan view illustrating a split gate type flash memory device according to an embodiment of the present invention, and FIGS. 2A to 2F illustrate a method of manufacturing a split gate type flash memory device according to an embodiment of the present invention. Sections taken along the cutting line II-II 'of each step.

1 and 2A, an isolation layer 105 is formed in the substrate 100 to define the active region 103. The device isolation layer 105 may be formed using conventional trench device isolation techniques. The active region 103 includes a plurality of common source line active regions 102 parallel to each other and a plurality of cell active regions 101 disposed to cross the common source line active regions 102. .

A gate insulating layer 110 is formed on the active region 103. The gate insulating layer 110 may be a silicon oxide layer, and preferably, a thermal oxide layer formed by thermally oxidizing the substrate 100. The floating gate conductive layer 120 and the hard mask layer 130 are sequentially stacked on the gate insulating layer 110. Preferably, the floating gate conductive layer 120 is a polysilicon layer, and the hard mask layer 130 is a silicon nitride layer.

A photoresist pattern (not shown) is formed on the hard mask layer 130, and the hard mask layer 130 is etched using the photoresist pattern as a mask to form the floating gate conductive layer in the hard mask layer 130. Openings 130a exposing the film 120 are formed. Thereafter, the photoresist pattern is removed.

The floating gate conductive layer 120 exposed in the openings 130a is thermally oxidized to form intergate oxide layers 125 in the openings 130a, respectively. The inter-gate oxide film 125 is elliptical in cross section. Specifically, the edge region of the inter-gate oxide film 125 is formed thinner than the center portion.

1 and 2B, after removing the hard mask layer 130, the floating gate conductive layer 120 is etched using the inter-gate oxide layer 125 as a mask to form a lower portion of the inter-gate oxide layer 125. The floating gate 121 is formed in the hole. As a result, a pair of floating gates 121 spaced apart from each other are disposed on the cell active region 101. The floating gates 121 are disposed to be adjacent to the common source line active regions 102, respectively.

Subsequently, a photoresist pattern (not shown) is formed to expose the common source line active region 102, and a conductive impurity is implanted into the exposed common source line active region 102 using the photoresist pattern as a mask. do. Thereafter, the photoresist pattern is removed. The conductive impurity may be P or As. The substrate 100 into which the conductive type impurity is implanted is heat-treated to diffuse the implanted ions to form a common source region 102a overlapping the floating gate 121. The common source region 102a extends along the common source line active region 102 to define a common source line.

1 and 2C, a tunnel insulating layer 135 is formed on a substrate 100 including the floating gate 121, and a control gate conductive layer is formed on the tunnel insulating layer 135. The control gate conductive layer may be a polysilicon layer or a metal layer, and the tunnel insulating layer 135 may be a silicon oxide layer.

Subsequently, the control gate conductive layer is patterned to form the control gates 140. Each control gate 140 covers an upper portion of the floating gate 121 and one side of the floating gate 121. As a result, the inter-gate insulating film 125 and the tunnel insulating film 135 are interposed between the floating gate 121 and the control gate 140. Specifically, the inter-gate insulating film 125 is disposed in an upper region of the floating gate 121 among regions where the floating gate 121 and the control gate 140 overlap, and the floating gate 121 and the floating gate 121 are disposed on the floating gate 121. The tunnel insulating layer 135 is disposed in a side region of the floating gate 121 among regions where the control gate 140 overlaps.

The control gates 140 are disposed in pairs between the common source line active regions 102 to extend in a direction parallel to the common source line active regions 102. The extended control gate 140 may be defined as a word line. The word lines 140 cross the upper portions of the cell active regions 101 and the floating gates 121, and the cell active regions 101 are exposed between the word lines 140.

Subsequently, a photoresist pattern (not shown) exposing the cell active regions 101 is formed, and conductive impurities are implanted into the cell active region 101 using the photoresist pattern as a mask. Thereafter, the photoresist pattern is removed. The conductive impurity may be P or As. As a result, the drain region 101a is formed in the cell active region 101 exposed between the control gates 140.

1 and 2D, a spacer insulating film is stacked on a substrate 100 including the control gate 140, and the spacer insulating film is anisotropically etched to control the control gate 140 of the floating gate 121. The insulating layer spacers 145 are formed on sidewalls not overlapping with each other and sidewalls of the control gate 140. When the flash memory device and the logic device are formed at the same time, the insulating film spacer 145 is formed to introduce a normal LDD structure into the logic device. However, the present invention is not limited thereto, and the LDD structure may be formed in the flash memory device using the insulating layer spacer 145.

The spacer insulating layer may be formed of a film having an etch selectivity with respect to the control gate 140, the floating gate 121, and the inter-gate oxide layer 125. In example embodiments, the spacer insulating layer may be a silicon nitride layer or a silicon oxynitride layer. However, even when the spacer insulating layer is formed using a material having an etching selectivity, the inter-gate oxide layer may be formed in a transient etching process in which a residue is not formed when the insulating layer spacer 145 is formed. The edge region 125t of the inter-gate oxide layer 125 that is not overlapped by the control gate 140 may be etched and damaged. In other words, since the edge region 125t of the inter-gate oxide layer 125 is thinner than a center portion, insulation may be deteriorated or contaminated due to etching damage during the formation of the insulating film spacer 145. Can even be removed. Therefore, the inter-gate oxide film 125 that is damaged or contaminated may remain unevenly on the upper edge of the floating gate 121 not overlapped by the control gate 140.

1 and 2E, the edge region 125t of the inter-gate oxide layer 125, that is, the damaged gate oxide layer 125 that remains unevenly on the upper edge of the floating gate 121 may be selectively removed. Can be. To this end, a photoresist pattern 190 is formed on the substrate 100 to expose the edge region 125t of the common source line active region 102 and the gate oxide layer 125 adjacent thereto. The edge region 125t of the inter-gate oxide layer 125 is removed using the pattern 190 as a mask. Removing the edge region 125t of the damaged gate oxide layer 125 may be performed using a wet etching method having an excellent selectivity. As a result, the upper edge of the floating gate 121 under the edge region 125t of the gate oxide film 125, that is, the upper edge not overlapping with the control gate 140 of the floating gate 121 is exposed.

1 and 2F, the edge oxide layer 127 may be removed by removing the photoresist pattern (190 of FIG. 2E) and oxidizing an upper edge not overlapping with the control gate 140 of the floating gate 121. To form. The corner oxide film 127 is formed adjacent to an edge not overlapped by the control gate 140 of the inter-gate oxide film 125. It is preferable to oxidize the upper edge using a thermal oxidation method. As a result, a corner oxide film 127 having excellent insulation characteristics while containing almost no impurities can be obtained. In this case, an upper edge not overlapping with the control gate 140 of the floating gate 121 is blunt than the upper edge T overlapping with the control gate 140.

Subsequently, an interlayer insulating film 150 is laminated on the substrate 100 including the corner oxide film 127. The interlayer insulating film 150 may be a CVD oxide film using a chemical vapor deposition method. The interlayer insulating film 150 may contain impurities such as alkali ions in the film. The charge stored in the floating gate 121 in the device operation process may be lost by the alkali ions through an upper edge not overlapping with the control gate 140 of the floating gate 121. However, in the present embodiment, the corner oxide film 127 sufficiently protects the upper edge of the floating gate 121 that does not overlap with the control gate 140 to prevent loss of charge stored in the floating gate 121. have. Therefore, the data retention capability of the split gate type flash memory device can be improved.

As described above, according to the present invention, by forming a corner oxide film on the upper edge not overlapping with the control gate of the floating gate, the upper edge not overlapping with the control gate of the floating gate is sufficiently protected so that the loss of charge stored in the floating gate is reduced. Can be prevented. Therefore, the data retention capability of the split gate type flash memory device can be improved.

Claims (7)

An isolation layer formed in the substrate to define an active region; A floating gate disposed on the active region; A control gate overlapping one sidewall and an upper portion of the floating gate; And And a corner oxide layer formed by selectively oxidizing an upper corner not overlapping the control gate of the floating gate. The method of claim 1, And an interpoly oxide layer disposed between the floating gate and the control gate. And the edge oxide film is formed adjacent to an edge not overlapped by the control gate of the inter-gate oxide film. The method according to claim 1 or 2, And sidewalls not overlapping the control gate of the floating gate and insulating layer spacers formed on the sidewalls of the control gate. Forming an isolation layer in the substrate to define an active region, Forming a floating gate on the active region, Forming a control gate on the floating gate, the control gate overlapping one sidewall and an upper portion of the floating gate; And selectively oxidizing an upper edge not overlapping with the control gate of the floating gate to form a corner oxide layer. The method of claim 4, wherein The floating gate is formed by stacking a floating gate conductive film on the active region, locally oxidizing the floating gate conductive film to form an inter-gate oxide film, and etching the floating gate conductive film using the inter-gate oxide film as a mask. That includes, And the edge oxide film is formed adjacent to an edge not overlapped by the control gate of the inter-gate oxide film. The method of claim 5, And selectively removing a non-overlapping edge region by the control gate of the inter-gate oxide film before forming the corner oxide film. The method according to any one of claims 4 to 6, After forming the control gate and before forming the corner oxide layer, a spacer insulating layer is stacked on the floating gate and the control gate, and the spacer insulating layer is anisotropically etched to form sidewalls that do not overlap the control gate of the floating gate; And forming insulating film spacers on sidewalls of the control gate.

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