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KR100953022B1 - Method for forming contact plug of semiconductor device - Google Patents

Method for forming contact plug of semiconductor device Download PDF

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KR100953022B1
KR100953022B1 KR1020070025499A KR20070025499A KR100953022B1 KR 100953022 B1 KR100953022 B1 KR 100953022B1 KR 1020070025499 A KR1020070025499 A KR 1020070025499A KR 20070025499 A KR20070025499 A KR 20070025499A KR 100953022 B1 KR100953022 B1 KR 100953022B1
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contact hole
forming
stop layer
diffusion stop
semiconductor substrate
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KR20080084176A (en
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조직호
한세진
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 콘택 플러그 형성방법에 관한 것으로, 반도체 기판 상부에 형성된 절연막 내에 콘택 홀을 형성하는 단계와, 상기 콘택 홀을 포함한 상기 반도체 기판 상부에 제1 확산 정지막을 형성하는 단계와, 상기 콘택 홀의 상부 측벽 및 상기 절연막 상에 형성된 상기 제1 확산 정지막을 제거하는 단계와, 상기 콘택 홀 내부의 보우잉이 발생한 영역까지 상기 절연막을 식각하는 단계와, 상기 콘택 홀을 포함한 상기 반도체 기판 상부에 제2 확산 정지막을 형성하는 단계와, 상기 콘택 홀 내부에 콘택 플러그를 형성하는 단계를 포함한다. The present invention relates to a method of forming a contact plug of a semiconductor device, the method comprising: forming a contact hole in an insulating film formed on an upper surface of a semiconductor substrate, forming a first diffusion stop layer on the semiconductor substrate including the contact hole; Removing the first diffusion stop layer formed on the upper sidewall of the contact hole and the insulating film, etching the insulating film to an area where bowing occurs inside the contact hole, and forming an upper portion of the semiconductor substrate including the contact hole. Forming a second diffusion stop layer, and forming a contact plug in the contact hole.

드레인 콘택 홀, 보우잉, 포지티브 슬로프 Drain Contact Holes, Bowing, Positive Slope

Description

반도체 소자의 콘택 플러그 형성방법{Method of forming a contact plug in semiconductor device}Method of forming a contact plug in semiconductor device

도 1a 내지 도 1f는 본 발명의 일 실시 예에 따른 반도체 소자의 콘택 플러그 형성방법을 설명하기 위해 도시한 소자의 단면도이다.1A to 1F are cross-sectional views illustrating a device for explaining a method for forming a contact plug of a semiconductor device according to an embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

100 : 반도체 기판 102 : 식각 방지막100 semiconductor substrate 102 etching prevention film

104 : 층간 절연막 106 : 포토레지스트 패턴104: interlayer insulating film 106: photoresist pattern

108 : 콘택 홀 110 : 제2 확산 정지막108: contact hole 110: second diffusion stop film

112 : 제2 확산 정지막 114 : 콘택 플러그112: second diffusion stop film 114: contact plug

본 발명은 반도체 소자의 콘택 플러그 형성방법에 관한 것으로, 특히, 콘택 홀 갭필(gap-fill) 특성을 향상시키기 위한 반도체 소자의 콘택 플러그 형성방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact plug of a semiconductor device, and more particularly, to a method of forming a contact plug of a semiconductor device for improving contact hole gap-fill characteristics.

플래시 메모리는 휴대폰, PDA, 카메라, 게임기 그리고 MP3 등과 같은 휴대기기의 출현으로 지난 몇 년간 폭발적인 성장을 하고 있다. 또한, IT 기술과 가전 기술의 발달과 더불어서 플래시 메모리는 이들 분야의 저장 매체로서 지속적인 각광을 받고 있다. 특히, 플래시 메모리는 비휘발성 및 저 전력 소모 특성으로 이런 응용에 적합하여 각종 휴대기기의 주 기억 소자로 사용되기 시작하였으며 최근의 수요에 부응하여 플래시 메모리의 집적도를 향상시키는 연구를 많이 하고 있다. 최근에는 70nm급 또는 그 이하의 채널 길이를 갖는 플래시 메모리 소자 기술을 개발하여 4Gb 또는 그 이상의 집적도를 갖는 플래시 메모리가 개발되고 있다.Flash memory has exploded in the last few years with the advent of mobile devices such as mobile phones, PDAs, cameras, game consoles and MP3s. In addition, with the development of IT technology and consumer electronics technology, flash memory is in the spotlight as a storage medium in these fields. In particular, the flash memory is suitable for such applications due to its non-volatile and low power consumption characteristics, and is being used as a main memory device of various portable devices. Recently, a flash memory device having a channel length of 70 nm or less has been developed, and a flash memory having a density of 4 Gb or more has been developed.

소자가 고집적화되어 감에 따라 하부소자와 상부 배선 사이의 다층 구조로 인하여 콘택의 높이가 증가하게 된다. 이에 대한 반도체 소자의 제조방법을 설명하면 다음과 같다.As the device becomes more integrated, the height of the contact increases due to the multilayer structure between the lower device and the upper wiring. Hereinafter, a method of manufacturing a semiconductor device will be described.

소정의 구조가 형성된 반도체 기판 상부에 층간 절연막 및 포토레지스트 패턴을 형성한 후 포토레지스트 패턴을 마스크로 층간 절연막을 식각하여 콘택 홀을 형성한다. 이때, 식각 공정 시 콘택 홀 상부 측면에 남아 있는 폴리머(polymer)로 인하여 이온 결함이 발생하고, 이로 인하여 폴리머 하부 영역의 층간 절연막을 과도 식각하게 되어 콘택 홀 내에 보우잉(bowing)이 발생하게 된다. 보우잉이 발생된 콘택 홀 내부의 상부 영역은 네거티브 프로파일(negative profile)을 갖는다. 이는 층간 절연막의 두께를 낮게 증착하여도 콘택 홀 형성시 콘택 홀 상부 측면에 잔류하는 폴리머로 인하여 상기와 같이 동일하게 보우잉 현상이 발생된다. After forming the interlayer insulating film and the photoresist pattern on the semiconductor substrate having a predetermined structure, the contact hole is formed by etching the interlayer insulating film using the photoresist pattern as a mask. At this time, an ion defect occurs due to the polymer remaining on the upper side of the contact hole during the etching process, thereby over-etching the interlayer insulating layer in the lower region of the polymer, thereby causing bowing in the contact hole. The upper region inside the contact hole where bowing has occurred has a negative profile. This is the same as described above due to the polymer remaining on the upper side of the contact hole when forming the contact hole even if the thickness of the interlayer insulating film is deposited.

그런 다음, 포토레지스트 패턴을 제거한 후 콘택 홀을 포함한 반도체 기판 상부에 확산 방지막을 형성한다. 이때, 확산 방지막은 티타늄 질화막(TiN)으로 형성한다. 콘택 홀이 채워지도록 전체 구조 상부에 텅스텐(W)을 형성한다. 이때, 텅스텐(W)은 스텝 커버리지(step coverage) 특성이 우수한 CVD(Chemical Vapor Deposition) 방법을 이용하여 형성한다. 콘택 홀을 채우기 전에 확산 방지막을 먼저 형성하는 것은 텅스텐(W) 형성 공정 시 사용되는 반응 가스인 WF6에 의해 반도체 기판, 알루미늄(Al), 티타늄(Ti) 또는 콘택 플러그가 어택(attack)을 받는 것을 방지하기 위해서이다. Thereafter, after removing the photoresist pattern, a diffusion barrier layer is formed on the semiconductor substrate including the contact hole. In this case, the diffusion barrier is formed of titanium nitride (TiN). Tungsten (W) is formed on the entire structure to fill the contact holes. In this case, tungsten (W) is formed by using a chemical vapor deposition (CVD) method having excellent step coverage. Forming the diffusion barrier first before filling the contact hole is performed by WF 6 , a reaction gas used in the tungsten (W) forming process, in which the semiconductor substrate, aluminum (Al), titanium (Ti), or contact plug are attacked. To prevent that.

상기에 언급했듯이, 콘택 홀 하부에 적정 두께의 확산 방지막을 증착하기 위해 스텝 커버리지 특성을 고려하고 있으며, 확산 방지막 증착 공정 시 원자층 증착(Atomic Layer Deposition; ALD) 방법을 제외한 스텝 커버리지 특성이 우수한 CVD 방법을 이용하여 티타늄 질화막(TiN)을 형성하고 있다. As mentioned above, the step coverage characteristics are considered to deposit an appropriate thickness diffusion barrier layer under the contact hole, and the CVD process has excellent step coverage characteristics except for atomic layer deposition (ALD) in the diffusion barrier deposition process. A titanium nitride film TiN is formed using the method.

그러나, CVD 방식을 이용한 티타늄 질화막(TiN) 형성 공정은 60% 정도의 스텝 커버리지를 나타내고 있다. 즉, 콘택 홀 하부에 증착되는 두께보다 콘택 홀 상부에 증착되는 두께가 더 두껍게 증착되어 콘택 홀 상부 폭이 급격하게 감소하게 된다는 것이다. 이로 인하여, 콘택 홀 내에 보우잉을 갖는 상태에서 콘택 홀을 채우기 위한 텅스텐(W) 형성 공정 시 콘택 홀 하부 영역이 채워지지 않은 상태에서 콘택 홀 상부 영역이 먼저 텅스텐(W)으로 채워져 콘택 홀 갭필 불량이 발생하게 된다. However, the titanium nitride film (TiN) formation process using the CVD method exhibits about 60% step coverage. That is, the thickness deposited on top of the contact hole is deposited thicker than the thickness deposited on the bottom of the contact hole, thereby rapidly decreasing the width of the top of the contact hole. As a result, during the tungsten (W) forming process for filling the contact hole with bowing in the contact hole, the contact hole upper region is first filled with tungsten (W) without the contact hole lower region being filled, so that the contact hole gap fill is poor. This will occur.

또한, 콘택 홀 내부의 상부 영역이 포지티브 프로파일(positive profile)을 갖는다 해도 확산 방지막 형성 공정 시 콘택 홀 하부에 증착되는 두께보다 콘택 홀 상부에 증착되는 두께가 더 두껍게 증착되어 콘택 홀 내부가 네거티브 프로파일을 갖게 될 뿐만 아니라, 콘택 홀 상부 폭이 급격하게 감소하게 된다. 이로 인하여 콘택 홀 갭필 불량이 발생하게 된다. In addition, even if the upper region inside the contact hole has a positive profile, the thickness deposited on the contact hole is thicker than the thickness deposited on the bottom of the contact hole during the diffusion barrier film forming process, so that the inside of the contact hole may have a negative profile. In addition to this, the contact hole upper width is drastically reduced. This causes contact hole gapfill failure.

본 발명은 콘택 홀 상부 영역에 형성된 확산 정지막을 제거한 후 식각 공정으로 콘택 홀 내부의 보우잉(bowing)이 발생한 영역까지 절연막을 식각하여 콘택 홀 갭필(gap-fill) 특성을 향상시킬 수 있다. The present invention can improve the contact hole gap-fill characteristics by removing the diffusion stop layer formed in the upper region of the contact hole and etching the insulating film to the area where bowing occurs inside the contact hole by an etching process.

본 발명의 실시 예에 따른 반도체 소자의 콘택 플러그 형성방법은, 반도체 기판 상부에 형성된 절연막 내에 콘택 홀을 형성한다. 콘택 홀을 포함한 반도체 기판 상부에 제1 확산 정지막을 형성한다. 콘택 홀의 상부 측벽 및 상기 절연막 상에 형성된 제1 확산 정지막을 제거한다. 콘택홀 내부에 제1 확산 정지막이 잔여하는 상태에서 콘택 홀 내부의 보우잉이 발생한 영역까지 절연막을 식각한다. 콘택 홀을 포함한 반도체 기판 상부에 제2 확산 정지막을 형성한다. 콘택 홀 내부에 콘택 플러그를 형성한다. In the method for forming a contact plug of a semiconductor device according to an embodiment of the present invention, a contact hole is formed in an insulating film formed on an upper portion of a semiconductor substrate. A first diffusion stop layer is formed on the semiconductor substrate including the contact hole. An upper sidewall of the contact hole and a first diffusion stop layer formed on the insulating layer are removed. The insulating layer is etched to a region where bowing occurs in the contact hole while the first diffusion stop layer remains in the contact hole. A second diffusion stop layer is formed on the semiconductor substrate including the contact hole. A contact plug is formed inside the contact hole.

상기에서, 보우잉이 발생된 콘택 홀 내부의 상부 영역은 네거티브 프로파일을 갖는다. 제1 확산 정지막은 CVD(Chemical Vapor Deposition) 방법을 이용하여 티타늄(Ti) 및 티타늄 질화막(TiN)을 적층된 구조로 형성한다. 제1 확산 정지막은 블랭킷 식각(blanket etch) 공정을 이용하여 선택적으로 제거한다. In the above, the upper region inside the contact hole where bowing has occurred has a negative profile. The first diffusion stop layer is formed of a stacked structure of titanium (Ti) and titanium nitride (TiN) by using a chemical vapor deposition (CVD) method. The first diffusion stop layer is selectively removed using a blanket etch process.

보우잉이 제거된 콘택 홀 내부의 상부 영역은 포지티브 프로파일(positive profile)을 갖는다. 절연막은 산화막 습식 에천트(oxide wet etchant)를 이용하여 식각하거나, 건식 플라즈마(dry plasma)를 이용하여 식각한다. 제2 확산 정지막은 PVD(Physical Vapor Deposition) 방법을 이용하여 형성한다. 콘택 홀은 CVD 방법을 이용하여 텅스텐(W)으로 채운다. The upper region inside the contact hole from which bowing was removed has a positive profile. The insulating layer is etched using an oxide wet etchant or etched using a dry plasma. The second diffusion stop layer is formed by using a physical vapor deposition (PVD) method. Contact holes are filled with tungsten (W) using the CVD method.

이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1f는 본 발명의 일 실시 예에 따른 반도체 소자의 콘택 플러그 형성방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1A through 1F are cross-sectional views of devices sequentially illustrated to explain a method for forming a contact plug of a semiconductor device according to an embodiment of the present invention.

도 1a를 참조하면, 소자분리막, 트랜지스터 또는 플래시 메모리 셀과 같은 반도체 소자(미도시)가 형성된 반도체 기판(100) 상부에 식각 정지막(102) 및 층간 절연막(104)을 형성한 후 화학적 기계적 연마(Chemical Mechanical Polishing; CMP) 공정을 실시하여 층간 절연막(104)을 평탄화시킨다. 이때, 식각 정지막(102)은 질화막으로 형성하고, 층간 절연막(104)은 산화막 또는 고밀도 플라즈마(High Density Plasma; HDP) 산화막으로 형성한다. 층간 절연막(104) 상부에 포토레지스트 패턴(106)을 형성한 후 포토레지스트 패턴(106)을 식각 마스크로 층간 절연 막(104) 및 식각 정지막(102)을 식각하여 콘택 홀(108)을 형성한다. 이때, 식각 공정 시 콘택 홀(108) 상부 측면에 남아 있는 폴리머(polymer)로 인하여 이온 결함이 발생하고, 이로 인하여 폴리머 하부 영역의 층간 절연막(104)을 과도 식각하게 되어 콘택 홀(108) 내에 보우잉(bowing)이 발생하게 된다. 보우잉이 발생된 콘택 홀(108) 내부의 상부 측벽은 네거티브 프로파일(negative profile)을 갖는다. Referring to FIG. 1A, after the etching stop layer 102 and the interlayer insulating layer 104 are formed on a semiconductor substrate 100 on which a semiconductor device (not shown) such as an isolation layer, a transistor, or a flash memory cell is formed, chemical mechanical polishing A chemical mechanical polishing (CMP) process is performed to planarize the interlayer insulating film 104. In this case, the etch stop film 102 is formed of a nitride film, and the interlayer insulating film 104 is formed of an oxide film or a high density plasma (HDP) oxide film. After the photoresist pattern 106 is formed on the interlayer insulating film 104, the contact hole 108 is formed by etching the interlayer insulating film 104 and the etch stop layer 102 using the photoresist pattern 106 as an etching mask. do. At this time, an ion defect occurs due to a polymer remaining on the upper side of the contact hole 108 during the etching process, thereby over-etching the interlayer insulating layer 104 in the lower region of the polymer, thereby protecting the inside of the contact hole 108. Bowing will occur. The upper sidewall inside the contact hole 108 from which bowing has occurred has a negative profile.

도 1b를 참조하면, 포토레지스트 패턴(106)을 제거한 후 콘택 홀(108)을 포함한 반도체 기판(100) 상부에 제1 확산 정지막(110)을 형성한다. 이때, 제1 확산 정지막(110)은 스텝 커버리지(step coverage) 특성이 우수한 CVD(Chemical Vapor Deposition) 방법을 이용하여 티타늄(Ti) 및 티타늄 질화막(TiN)을 적층된 구조로 형성한다. 제1 확산 정지막(110)은 콘택 홀(108) 하부에 증착되는 두께보다 콘택 홀(108) 상부에 증착되는 두께가 더 두껍게 증착되어 콘택 홀(108) 상부 영역에 오버행(overhang)이 발생한다. 이로 인하여 콘택 홀(108) 상부 폭이 급격하게 감소하게 된다. Referring to FIG. 1B, after removing the photoresist pattern 106, a first diffusion stop layer 110 is formed on the semiconductor substrate 100 including the contact hole 108. In this case, the first diffusion stop layer 110 is formed of a stacked structure of titanium (Ti) and titanium nitride (TiN) by using a chemical vapor deposition (CVD) method having excellent step coverage. The first diffusion stop layer 110 is thicker than the thickness deposited on the bottom of the contact hole 108, and the thickness of the first diffusion stop layer 110 is formed to overhang in the upper region of the contact hole 108. . As a result, the upper width of the contact hole 108 is drastically reduced.

도 1c를 참조하면, 층간 절연막(104) 상부와 콘택 홀(108) 상부 측벽에 형성된 제1 확산 정지막(110)을 제거한다. 이때, 제1 확산 정지막(110)은 블랭킷 식각(blanket etch) 공정을 이용하여 선택적으로 제거한다. 콘택 홀(108)의 상부 측벽에 형성된 제1 확산 정지막(110)을 제거함으로써 콘택 홀(108) 상부 영역의 오버행을 제거할 수 있다. Referring to FIG. 1C, the first diffusion stop layer 110 formed on the upper sidewall of the interlayer insulating layer 104 and the upper sidewall of the contact hole 108 is removed. In this case, the first diffusion stop layer 110 is selectively removed using a blanket etch process. The overhang of the upper region of the contact hole 108 may be removed by removing the first diffusion stop layer 110 formed on the upper sidewall of the contact hole 108.

도 1d를 참조하면, 식각 공정으로 콘택 홀(108) 내부의 보우잉이 발생한 영역까지 층간 절연막(104)을 식각하여 콘택 홀(108) 내부의 측벽이 포지티브 프로파 일(positive profile)을 갖도록 한다. 예를 들어, 콘택 홀(108) 내부에서 폭이 가장 넓은 영역까지 층간 절연막(104)을 식각한다. 이때, 층간 절연막(104)은 산화막 습식 에천트(oxide wet etchant)를 이용하여 식각하거나, 건식 플라즈마(dry plasma)를 이용하여 식각한다. Referring to FIG. 1D, the interlayer insulating film 104 is etched to the area where the bowing occurs in the contact hole 108 by the etching process, so that the sidewall inside the contact hole 108 has a positive profile. . For example, the interlayer insulating layer 104 is etched to the widest region within the contact hole 108. In this case, the interlayer insulating layer 104 is etched using an oxide wet etchant or etched using a dry plasma.

도 1e를 참조하면, 콘택 홀(108)을 포함한 반도체 기판(100) 상부에 제2 확산 정지막(112)을 형성한다. 이때, 제2 확산 정지막(112)은 콘택 홀(108) 측벽과 하부 영역에 증착되는 양을 감소시키기 위해 스텝 커버리지 특성이 좋지 않은 PVD(Physical Vapor Deposition) 방법을 이용하여 형성한다. 제2 확산 정지막(112)은 콘택 홀(108) 측벽과 하부 영역보다 콘택 홀(108) 상부 영역에 주로 형성된다. Referring to FIG. 1E, a second diffusion stop layer 112 is formed on the semiconductor substrate 100 including the contact hole 108. In this case, the second diffusion stop layer 112 is formed by using a physical vapor deposition (PVD) method having poor step coverage characteristics in order to reduce the amount of deposition on the sidewalls and the lower region of the contact hole 108. The second diffusion stop layer 112 is mainly formed in the upper region of the contact hole 108 than the sidewalls and the lower region of the contact hole 108.

도 1f를 참조하면, 콘택 홀(108)이 채워지도록 콘택 홀(108)을 포함한 반도체 기판(100) 상부에 제2 도전막을 형성한다. 이때, 제2 도전막은 스텝 커버리지 특성이 우수한 CVD 방법을 이용하여 텅스텐(W)으로 형성한다. 제2 도전막을 형성하기 전에 층간 절연막(104) 상부에 제2 확산 정지막(112)을 형성함으로써 층간 절연막(104)과 제2 도전막 사이에 들뜨는(lifting) 현상이 발생하지 않는다. 층간 절연막(104) 상부가 노출될 때까지 화학적 기계적 연마(CMP) 공정 또는 에치백(etchback) 공정을 실시하여 콘택 플러그(114)를 형성한다. Referring to FIG. 1F, a second conductive layer is formed on the semiconductor substrate 100 including the contact hole 108 to fill the contact hole 108. At this time, the second conductive film is formed of tungsten (W) using a CVD method having excellent step coverage characteristics. By forming the second diffusion stop layer 112 over the interlayer insulating layer 104 before forming the second conductive layer, the phenomenon of lifting between the interlayer insulating layer 104 and the second conductive layer does not occur. The contact plug 114 is formed by performing a chemical mechanical polishing (CMP) process or an etchback process until the upper portion of the interlayer insulating layer 104 is exposed.

상기와 같이, 콘택 홀(108) 상부 영역에 형성된 제1 확산 정지막(110)을 제거함으로써 콘택 홀(108) 상부 영역에 형성된 오버행을 제거할 수 있다. 또한, 식각 공정으로 콘택 홀(108) 내부의 보우잉이 발생한 영역까지 층간 절연막(104)을 식각함으로써 콘택 홀(108) 내부의 측벽이 포지티브 프로파일을 갖도록 한다. 이렇 게 콘택 홀(108) 내부의 측벽이 포지티브 프로파일을 갖도록 함으로써 콘택 홀(108) 갭필 특성이 향상되며, 콘택 플러그(114)의 저항을 낮춰 소자의 신뢰성을 확보할 수 있다. As described above, the overhang formed in the upper region of the contact hole 108 may be removed by removing the first diffusion stop layer 110 formed in the upper region of the contact hole 108. In addition, by etching the interlayer insulating film 104 to the region where the bowing occurs in the contact hole 108 in the etching process, the sidewall inside the contact hole 108 has a positive profile. As such, the sidewall inside the contact hole 108 has a positive profile, thereby improving contact gap 108 gapfill characteristics, and reducing the resistance of the contact plug 114 to secure device reliability.

본 발명의 기술 사상은 상기 바람직한 실시 예에 따라 구체적으로 기술되었으나, 상기한 실시 예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주지하여야 한다. 또한, 본 발명의 기술 분야에서 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시 예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같이 본 발명에 의한 효과는 다음과 같다. As described above, the effects of the present invention are as follows.

첫째, 콘택 홀 상부 영역에 형성된 제1 확산 정지막을 제거함으로써 콘택 홀 상부 영역에 형성된 오버행(overhang)을 제거할 수 있다. First, an overhang formed in the upper region of the contact hole may be removed by removing the first diffusion stop layer formed in the upper region of the contact hole.

둘째, 식각 공정으로 콘택 홀 내부의 보우잉(bowing)이 발생한 영역까지 층간 절연막을 식각함으로써 콘택 홀 내부의 상부 영역을 포지티브 프로파일(positive profile)을 갖도록 할 수 있다.Second, the interlayer insulating layer may be etched to an area where bowing occurs in the contact hole by an etching process, so that the upper region inside the contact hole may have a positive profile.

셋째, 콘택 홀 내부의 상부 영역을 포지티브 프로파일을 갖도록 함으로써 콘택 홀 갭필(gap-fill) 특성이 향상되며, 콘택 플러그의 저항을 낮춰 소자의 신뢰성을 확보할 수 있다. Third, the contact hole gap-fill characteristics are improved by making the upper region inside the contact hole have a positive profile, and the reliability of the device can be secured by lowering the resistance of the contact plug.

Claims (8)

반도체 기판 상부에 형성된 절연막 내에 콘택 홀을 형성하는 단계;Forming a contact hole in the insulating film formed on the semiconductor substrate; 상기 콘택 홀을 포함한 상기 반도체 기판 상부에 제1 확산 정지막을 형성하는 단계;Forming a first diffusion stop layer on the semiconductor substrate including the contact hole; 상기 콘택 홀의 상부 측벽 및 상기 절연막 상에 형성된 상기 제1 확산 정지막을 제거하는 단계; Removing the first diffusion stop layer formed on the upper sidewall of the contact hole and the insulating layer; 상기 콘택 홀 내부에 상기 제1 확산 정지막이 잔여하는 상태에서 상기 콘택 홀 내부의 보우잉이 발생한 영역까지 상기 절연막을 식각하는 단계;Etching the insulating layer to a region where bowing occurs in the contact hole while the first diffusion stop layer remains in the contact hole; 상기 콘택 홀을 포함한 상기 반도체 기판 상부에 제2 확산 정지막을 형성하는 단계; 및Forming a second diffusion stop layer on the semiconductor substrate including the contact hole; And 상기 콘택 홀 내부가 채워지도록 상기 콘택 홀을 포함한 상기 반도체 기판 상에 도전막을 형성한 후, 상기 절연막이 노출될 때까지 연마 공정 또는 에치 백 공정을 실시하여 콘택 플러그를 형성하는 단계를 포함하고,Forming a contact plug by forming a conductive film on the semiconductor substrate including the contact hole so that the inside of the contact hole is filled, and then performing a polishing process or an etch back process until the insulating film is exposed; 상기 보우잉은 상기 콘택 홀을 형성하는 단계에서 상기 콘택 홀의 상부에 발생하는 반도체 소자의 콘택 플러그 형성방법. And the bowing is formed on the contact hole at the step of forming the contact hole. 제1항에 있어서, The method of claim 1, 상기 보우잉이 발생된 상기 콘택 홀 내부의 상부 영역은 네거티브 프로파일을 갖는 반도체 소자의 콘택 플러그 형성방법.The upper region inside the contact hole where the bowing is generated has a negative profile. 제1항에 있어서, The method of claim 1, 상기 제1 확산 정지막은 CVD(Chemical Vapor Deposition) 방법을 이용하여 티타늄(Ti) 및 티타늄 질화막(TiN)을 적층된 구조로 형성하는 반도체 소자의 콘택 플러그 형성방법.The method of claim 1, wherein the first diffusion stop layer is formed by stacking titanium (Ti) and titanium nitride (TiN) using a chemical vapor deposition (CVD) method. 제1항에 있어서,  The method of claim 1, 상기 제1 확산 정지막은 블랭킷 식각(blanket etch) 공정을 이용하여 선택적으로 제거하는 반도체 소자의 콘택 플러그 형성방법.The method of claim 1, wherein the first diffusion stop layer is selectively removed by using a blanket etch process. 제1항에 있어서, The method of claim 1, 상기 보우잉이 제거된 상기 콘택 홀 내부의 상부 영역은 포지티브 프로파일(positive profile)을 갖는 반도체 소자의 콘택 플러그 형성방법.And an upper region in the contact hole from which the bowing is removed, has a positive profile. 제1항에 있어서, The method of claim 1, 상기 절연막은 산화막 습식 에천트(oxide wet etchant)를 이용하여 식각하거 나, 건식 플라즈마(dry plasma)를 이용하여 식각하는 반도체 소자의 콘택 플러그 형성방법.The insulating layer is etched using an oxide wet etchant (etch wet), or a method of forming a contact plug of a semiconductor device by etching using a dry plasma (dry plasma). 제1항에 있어서, The method of claim 1, 상기 제2 확산 정지막은 PVD(Physical Vapor Deposition) 방법을 이용하여 형성하는 반도체 소자의 콘택 플러그 형성방법.And forming the second diffusion stop layer by using a physical vapor deposition (PVD) method. 제1항에 있어서,The method of claim 1, 상기 콘택 홀은 CVD 방법을 이용하여 텅스텐(W)으로 채우는 반도체 소자의 콘택 플러그 형성방법. The contact hole is a contact plug forming method of a semiconductor device filled with tungsten (W) by using a CVD method.
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US10377948B2 (en) 2016-11-29 2019-08-13 Samsung Electronics Co., Ltd. Etching composition and method for fabricating semiconductor device by using the same
US10800972B2 (en) 2016-11-29 2020-10-13 Samsung Electronics Co., Ltd. Etching composition and method for fabricating semiconductor device by using the same

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