KR101152822B1 - Fabricating method for wafer - Google Patents

Abstract

Method of forming a wafer according to the invention comprises the steps of forming through electrodes on a carrier wafer; Forming an adhesive layer on the carrier wafer surface between the through electrodes on a carrier wafer including the through electrodes; Forming a silicon layer between the through electrodes including the adhesive layer; Forming a semiconductor circuit layer on the silicon layer including the through electrodes; Separating a carrier wafer from the through electrodes, the silicon layer and the semiconductor circuit layer; And protruding a portion of the through electrodes by removing the adhesive layer attached to the through electrodes and the silicon layer.

Description

Fabrication Method for Wafer

The present invention relates to a method of forming a wafer, and more particularly, to a method of forming a wafer capable of improving the production yield through a simplified process.

In the semiconductor industry, packaging technology for integrated circuits has continually evolved to meet the demand for miniaturization and mounting reliability. For example, the demand for miniaturization is accelerating the development of technology for packages that are close to chip size, and the demand for mounting reliability highlights the importance of packaging technologies that can improve the efficiency of mounting operations and mechanical and electrical reliability after mounting. I'm making it.

A stack package is classified into a method of packaging individual semiconductor chips after stacking individual semiconductor chips according to a manufacturing technique, and stacking and forming packaged individual semiconductor chips.

Such a stack package includes a bonding method using a metal wire and a bonding method using a through electrode. Recently, research on stack packages using through silicon vias (TSVs) has been actively conducted to overcome the problems of stack packages using metal wires and to prevent and reduce the electrical characteristics of the stack packages. have.

Hereinafter, a stack type semiconductor package using a through electrode will be described with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a stack-type semiconductor package using a through electrode according to the related art.

As shown, the stacked semiconductor package 105 using the through electrode is a redistribution line 140 connecting the through electrode 130 and the through electrode 130 and the bonding pad 112 on the substrate 101. Is formed. In this case, the semiconductor chips 150 are stacked to correspond to the through electrodes 130.

Unexplained reference numeral 145 denotes an insulating film, 108a, 108b a metal seed film, 114 a buried material, and 170 a solder ball, respectively.

In the stack-type semiconductor package 105 using the through electrode, since electrical connection is made through the through electrode 130, electrical deterioration is prevented and the operation speed of the semiconductor chip 150 is not only improved, but also active in miniaturization. There is an advantage to cope with.

However, in the case of a stack package using a conventional through electrode, a manufacturing cost due to the complexity of the process is required as the through holes for forming through electrodes are formed in one-to-one correspondence with the bonding pads in the semiconductor chip and connected by redistribution. Is on the rise.

In particular, during the step of forming the through-holes in the wafer, it may affect the semiconductor circuit in the wafer to inhibit the production yield. In addition, in the etching process for forming the through-hole, the depth between the through-holes is formed differently due to the difference in the etching rate between the center and the edge of the wafer, it may affect the subsequent process.

Furthermore, in the formation of the through-electrode embedded in the through-hole, the filling process without the generation of voids is a situation that acts as a major factor that inhibits the production yield with a high difficulty technology that takes a long time.

The present invention provides a method of forming a wafer which can improve the production yield by simplifying the manufacturing process of the wafer including the through electrode.

Method of forming a wafer according to an embodiment of the present invention comprises the steps of forming through electrodes on a carrier wafer; Forming an adhesive layer on the carrier wafer surface between the through electrodes on a carrier wafer including the through electrodes; Forming a silicon layer between the through electrodes including the adhesive layer; Forming a semiconductor circuit layer on the silicon layer including the through electrodes; Separating a carrier wafer from the through electrodes, the silicon layer and the semiconductor circuit layer; And protruding a portion of the through electrodes by removing the adhesive layer attached to the through electrodes and the silicon layer.

The forming of the through electrodes may include forming a seed metal layer on the carrier wafer; Forming a mask pattern on a carrier wafer including the seed metal layer; Forming a metal material layer on the mask pattern; Etching back the surface of the metal material layer to remove some thickness; And removing the mask pattern and etching the exposed seed metal layer.

The forming of the through electrodes may include mounting a stencil mask on the carrier wafer; Embedding a metal material in the stencil mask; Separating the stencil mask from the carrier wafer; And curing the metal material.

The through electrodes are formed of metal pins.

The carrier wafer is characterized in that made of silicon or glass.

Between the forming of the adhesive layer and the step of forming the silicon layer, further comprising the step of forming an insulating layer on the inner wall of the through electrodes.

The insulating layer is characterized in that formed of polyimide or silicon oxide.

According to another aspect of the present invention, a method of forming a wafer includes forming through electrodes on a carrier wafer; Bonding a wafer including via holes formed on the carrier wafer to correspond to the through electrodes and an adhesive layer formed on a bottom surface of the via holes; Removing the carrier wafer from a wafer including through electrodes inserted into the via holes and an adhesive layer; And removing the adhesive layer attached to the bottom surface between the through electrodes.

The present invention has the effect of improving the production yield by simplifying the process by eliminating the etching process for forming the through-hole in the wafer, or the backgrinding process to remove the back surface of the wafer.

(First embodiment)

Hereinafter, a method of forming a wafer according to a first embodiment of the present invention will be described with reference to the accompanying drawings.

2A to 2F are cross-sectional views sequentially illustrating a method of forming a wafer according to a first embodiment of the present invention in order of processing.

As shown in FIG. 2A, the seed metal layer 210 is formed on the carrier wafer 200. The carrier wafer 200 may be formed of any one of silicon or glass. Next, a mask pattern 222 is formed on the carrier wafer 200 including the seed metal layer 210.

Next, a metal material layer 220 is formed on the carrier wafer 200 including the mask pattern 222. The seed metal layer 210 and the metal material layer 220 may be formed of any one of copper (Cu), aluminum (Al), nickel (Ni), tin (Sn), gold (Au), and platinum (Pt). Among these, it is preferable to form with copper (Cu).

The seed metal layer 210 and the metal material layer 220 may be formed through electrolytic plating or electroless plating.

Next, the exposed surface of the metal material layer 220 is removed by an etch back process. In this case, the metal material layer 220 is etched back to a thickness corresponding to the mask pattern 222.

Next, as shown in FIG. 2B, the exposed mask pattern (222 of FIG. 2A) is removed by a strip process and the seed metal layer (210 of FIG. 2A) exposed to the outside of the metal material layer (220 of FIG. 2A) is etched. Thus, through electrodes 230 are formed on the carrier wafer 200, respectively.

In the above-described process, although not shown in the drawings, seed metal patterns (not shown) having a width corresponding thereto are formed on the bottom surfaces of the through electrodes 230.

In this case, a method of forming through electrodes 230 by directly attaching a metal pin to the carrier wafer 200 may be applied. When using the metal pin, the step of forming the seed metal layer and the mask pattern can be omitted. The metal pin may be the same material as the metal material layer.

Next, as shown in FIG. 2C, an adhesive layer 242 is formed on the surface of the carrier wafer 200 between the through electrodes 230 on the carrier wafer 200 on which the through electrodes 230 are formed. The adhesive layer 242 may be formed to a thickness corresponding to the thickness of exposing the through electrodes 230 by a conventional backgrinding process.

That is, since the thickness of the adhesive layer 242 has a close correlation with the thickness of the through electrodes 230 finally exposed, it is preferable to determine the thickness of the adhesive layer 242 in consideration of this.

Next, an insulating layer 245 is formed on the inner walls of the through electrodes 230. The insulating layer 245 may be formed of polyimide or silicon oxide (SiO 2). The insulating layer 245 functions to electrically insulate the through electrodes 230 from the silicon layer to be formed in a subsequent process.

Conventionally, the insulating layer 245 has been formed prior to forming the through electrodes 230, but in the present invention, since the insulating layer 245 is formed after the through electrodes 230 are formed, the thickness of the insulating layer 245 can be easily controlled. The process can be simplified and further shorten the process time.

Next, as shown in FIG. 2D, the silicon layer 232 is formed by applying and curing silicon to the inner walls of the through electrodes 230 without gaps.

The silicon layer 232 is preferably formed at the same height as the upper surface of the silicon semiconductor layer 232 facing the lower surface of the through electrodes 230 contacting the carrier wafer 200. In particular, the silicon layer 232 is preferably formed so that the surface of the through electrodes 230 located on the upper surface of the silicon layer 232 is exposed to the outside.

Next, the semiconductor circuit layer 234 is formed on the upper surface of the silicon layer 232 including the through electrodes 230. The semiconductor circuit layer 234 may include a transistor, a capacitor, a resistor, and the like.

Although not shown in the drawings, the semiconductor circuit layer may be formed to electrically correspond to each of the through electrodes 230, and may have bonding pads (not shown) at one end thereof.

As shown in FIG. 2E, the carrier wafer (200 of FIG. 2D) is separated from the through electrodes 230, the silicon layer 232, and the semiconductor circuit layer 234. Next, as shown in FIG. 2F, the through electrodes 230 and the adhesive layer 242 attached to the silicon layer 232 are removed to protrude some of the through electrodes 230.

As described above, the wafer according to the first embodiment of the present invention can be formed.

Therefore, in the present invention, the back surface of the wafer is removed by a backgrinding process in order to expose the through electrodes to the outside, and there is an advantage of not requiring a process of removing the spaced apart between the through electrodes by an etching process. In this case, the carrier wafer separated from the through electrodes, the silicon layer and the semiconductor circuit layer may be reused.

(2nd Example)

Hereinafter, a method of forming a wafer according to a second embodiment of the present invention will be described with reference to the accompanying drawings. In particular, according to the second embodiment of the present invention, there is a difference in a method of forming the through electrode on the carrier wafer.

3A to 3C are cross-sectional views illustrating a part of a method of forming a wafer according to a second embodiment of the present invention. 4 is a cross-sectional view showing a modification of the second embodiment of the present invention.

As shown in FIG. 3A, a stencil mask 304 having an opening pattern 302 is mounted on a carrier wafer 300.

Next, as shown in FIG. 3B, the metal material 330a is screen printed on the upper surface of the stencil mask 304 and embedded in the opening pattern 302.

The metal material 330a may be any one of copper (Cu), aluminum (Al), nickel (Ni), tin (Sn), gold (Au), and platinum (Pt) paste, of which copper (Cu ) Is preferably formed into a paste.

Next, as shown in FIG. 3C, the stencil mask 304 (FIG. 3B) is separated from the carrier wafer 300, and then the metal material (330a of FIG. 3B) is cured. When the curing process is completed, through electrodes 330 are formed on the carrier wafer 300.

In this case, as shown in FIG. 4, the redistribution line 340 may be formed simultaneously with the through electrodes 330 by changing the shape of the opening pattern in the design of the stencil mask. The design arrangement of the redistribution 340 may be variously changed.

Since the process is the same as the first embodiment, duplicate description will be omitted.

(Third Embodiment)

Hereinafter, a method of forming a wafer according to a third embodiment of the present invention will be described with reference to the accompanying drawings.

5A through 5C are cross-sectional views sequentially illustrating a method of forming a wafer according to a third exemplary embodiment of the present invention, in order of process order.

As shown in FIG. 5A, through electrodes 430 are formed on the carrier wafer 400. The through electrodes 430 may be formed by any one of the methods according to the first and second embodiments described above.

Next, the wafer 401 including the via holes 460 formed on the carrier wafer 400 to correspond to the through electrodes 430 and the adhesive layer 442 formed on the bottom surface of the via holes 460 is aligned. do.

In this case, the wafer 401 may further include an insulating layer 445 formed on the inner wall of the via hole 460 in addition to the via hole 460 formed to correspond to the through electrodes 430. have. Alternatively, although not shown in the drawings, an adhesive layer 442 may be formed on the surface of the carrier wafer 400 between the through electrodes 430 on the carrier wafer 400.

Next, as shown in FIG. 5B, the carrier wafer 400 including the through electrodes 430 and the wafer 401 including the via holes (460 of FIG. 5A) and the adhesive layer 442 are bonded to each other.

As shown in FIG. 5C, the carrier wafer (400 of FIG. 5B) is removed from the wafer 400 including the through electrodes 430 inserted into the via holes and the adhesive layer 442 of FIG. 5B. In this case, the through electrodes 430 are inserted into the via holes, respectively, and transferred to the wafer 401.

Next, the adhesive layer attached to the bottom surface between the through electrodes 430 is removed to protrude some of the through electrodes 430.

As described above, the wafer according to the third embodiment of the present invention can be formed.

Accordingly, in the third embodiment of the present invention, since the wafer having the manufacturing process is used, there is an advantage that the manufacturing process can be simplified compared to the first and second embodiments.

Hereinbefore, the present invention has been illustrated and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications and variations can be made.

1 is a cross-sectional view showing a stack-type semiconductor package using a through electrode according to the prior art.

2A to 2F are cross-sectional views sequentially showing a method of forming a wafer according to a first embodiment of the present invention in the order of processes.

3A to 3C are cross-sectional views showing a part of a method of forming a wafer according to a second embodiment of the present invention.

4 is a cross-sectional view showing a modification of the second embodiment of the present invention.

5A to 5C are cross-sectional views sequentially illustrating a method of forming a wafer according to a third embodiment of the present invention in the order of processes.

Claims (8)

Forming through electrodes on a carrier wafer; Forming an adhesive layer on the carrier wafer surface between the through electrodes on a carrier wafer including the through electrodes; Forming a silicon layer between the through electrodes including the adhesive layer; Forming a semiconductor circuit layer on the silicon layer including the through electrodes; Separating a carrier wafer from the through electrodes, the silicon layer and the semiconductor circuit layer; And Protruding a portion of the through electrodes by removing the adhesive layer attached to the through electrodes and the silicon layer; Forming a wafer comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, wherein forming the through electrodes comprises: Forming a seed metal layer on the carrier wafer; Forming a mask pattern on a carrier wafer including the seed metal layer; Forming a metal material layer on the mask pattern; Etching back the surface of the metal material layer to remove some thickness; And Removing the mask pattern and etching the exposed seed metal layer; Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, wherein forming the through electrodes comprises: Mounting a stencil mask on the carrier wafer; Embedding a metal material in the stencil mask; Separating the stencil mask from the carrier wafer; And Curing the metal material; Forming a wafer comprising a. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, wherein the through electrodes are formed of metal pins. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, wherein the carrier wafer is made of silicon or glass. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, further comprising forming an insulating layer on the inner walls of the through electrodes between the forming of the adhesive layer and the forming of the silicon layer. Claim 7 was abandoned upon payment of a set-up fee. 7. The method of claim 6, wherein the insulating layer is formed of polyimide or silicon oxide. Forming through electrodes on a carrier wafer; Bonding a wafer including via holes formed on the carrier wafer to correspond to the through electrodes and an adhesive layer formed on a bottom surface of the via holes; Removing the carrier wafer from a wafer including through electrodes inserted into the via holes and an adhesive layer; And Removing the adhesive layer attached to the bottom surface between the through electrodes; Forming a wafer comprising a.

Images