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KR101432481B1 - Stacked package - Google Patents

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Publication number
KR101432481B1
KR101432481B1 KR1020120126676A KR20120126676A KR101432481B1 KR 101432481 B1 KR101432481 B1 KR 101432481B1 KR 1020120126676 A KR1020120126676 A KR 1020120126676A KR 20120126676 A KR20120126676 A KR 20120126676A KR 101432481 B1 KR101432481 B1 KR 101432481B1
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Prior art keywords
circuit board
printed circuit
chip
bonding
stacked
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KR20140060054A (en
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김성산
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에스티에스반도체통신 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 집적회로 패키지 및 그 제조방법에 관한 것으로, 본 발명의 집적회로 패키지는 회로패턴을 구비하는 인쇄회로기판과; 상기 회로패턴과 전기적으로 연결되도록 상기 인쇄회로기판 상에 실장되며, 양단부가 일측 방향을 항하도록 구부러진 플렉서블 기판과; 상기 구부러진 플렉서블 기판의 내측에서 서로 대향하는 면들에 계단형태로 적층되며 본딩 와이어에 의해 상기 플렉서블 기판과 전기적으로 연결된 복수의 반도체 칩을 구비하는 제1 및 제2 칩 적층부와; 상기 제1 및 제2 칩 적층부 사이에 형성된 접착층; 및 상기 플렉서블 기판과, 상기 제1 및 제2 칩 적층부를 포함하는 상기 인쇄회로기판의 일면을 밀봉하는 몰딩부를 포함하는 것을 특징으로 한다. The present invention relates to an integrated circuit package and a method of manufacturing the same, the integrated circuit package comprising: a printed circuit board having a circuit pattern; A flexible board mounted on the printed circuit board so as to be electrically connected to the circuit pattern, the both ends of the flexible board bent to face one direction; First and second chip stacking portions stacked in a stepwise manner on surfaces facing each other on the inside of the bent flexible substrate and having a plurality of semiconductor chips electrically connected to the flexible substrate by bonding wires; An adhesive layer formed between the first and second chip stacked portions; And a molding part sealing the one surface of the printed circuit board including the flexible substrate and the first and second chip stacked parts.

Description

스택 패키지{STACKED PACKAGE} Stack package {STACKED PACKAGE}

본 발명은 스택 패키지 및 그 제조 방법에 관한 것으로서, 보다 구체적으로는 복수개의 반도체 칩이 적층된 스택 패키지, 및 이러한 스택 패키지를 제조하는 방법에 관한 것이다.
The present invention relates to a stack package and a method of manufacturing the same, and more particularly, to a stack package in which a plurality of semiconductor chips are stacked, and a method of manufacturing such stack package.

최근 반도체 산업의 발전과 사용자의 요구에 따라 전자기기는 더욱 소형화 및 경량화되고 있으며 전자기기의 핵심 부품인 패키지 또한 소형화 및 경량화되고 있다. 이와 같은 추세에 따라 개발된 패키지로서 복수의 반도체칩을 수직으로 적층하여 하나의 단위 반도체 칩 패키지로 구현된 스택 패키지가 널리 사용되고 있다.Recently, according to the development of the semiconductor industry and the demands of users, electronic devices have become smaller and lighter, and packaging, which is a core component of electronic devices, has also become smaller and lighter. As a package developed according to this trend, a stack package in which a plurality of semiconductor chips stacked vertically and implemented as one unit semiconductor chip package is widely used.

도 1은 종래의 스택 패키지를 개략적으로 나타낸 단면도이다. 도 1에 도시된 바와 같이, 종래의 스택 패키지는 기판(10), 적층된 다수의 반도체 칩(20, 21), 제1 및 제2 본딩 와이어(30, 31)를 포함한다.1 is a schematic cross-sectional view of a conventional stack package. 1, a conventional stack package includes a substrate 10, a plurality of stacked semiconductor chips 20, 21, and first and second bonding wires 30, 31.

기판(10)상에는 다수의 반도체 칩(20, 21)이 계단형태(cascade)로 적층 부착되어 있고, 각각의 반도체 칩(20)은 제1 본딩 와이어(30)에 의해 기판(10)과 전기적으로 연결되어 있다. 또한, 최상층에 위치하는 반도체 칩(21)은 제2 본딩 와이어(31)에 의해 기판(10)과 전기적으로 연결되어 있다. A plurality of semiconductor chips 20 and 21 are stacked on a substrate 10 in a cascade manner and each semiconductor chip 20 is electrically connected to the substrate 10 by a first bonding wire 30 It is connected. Further, the semiconductor chip 21 located on the uppermost layer is electrically connected to the substrate 10 by the second bonding wire 31.

그러나 종래의 스택 패키지는 다수의 반도체 칩을 적층하는 고단 스택시 먼저 반도체 칩을 적층한 다음 본딩 와이어를 일괄적으로 형성하기 때문에 상단 본딩 와이어에서 와이어가 한쪽으로 쏠리는 와이어 스위핑(wire sweeping)이 발생한다. 또한, EMC(Epoxy Molding Compound)몰딩시 액상 봉지재의 유동으로 인해서도 와이어 스위핑(wire sweeping)이 자주 발생한다. However, in the conventional stack package, when high-speed stacking of a plurality of semiconductor chips is carried out, the semiconductor chips are stacked first, and then the bonding wires are collectively formed, so that wire sweeping occurs in which the wires are tilted to one side in the upper bonding wires . Also, wire sweeping frequently occurs due to the flow of the liquid encapsulant during the molding of EMC (Epoxy Molding Compound).

이러한 와이어 스위핑은 와이어 쇼트(short), 워페이지(warpage) 등을 초래하며 이로 인해 스택 패키지의 수율이 저하되는 문제점이 있다.
Such wire sweeping results in wire shorts, warpage, and the like, which results in a problem of lowering the yield of the stack package.

따라서, 본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 일반적인 목적은 종래 기술에서의 한계와 단점에 의해 발생되는 다양한 문제점을 실질적으로 보완할 수 있는 스택 패키지 및 그 제조방법을 제공하는 것이다. SUMMARY OF THE INVENTION Accordingly, it is a general object of the present invention to provide a stack package capable of substantially completing various problems caused by limitations and disadvantages of the prior art, And a method for manufacturing the same.

본 발명의 보다 구체적인 다른 목적은 와이어 스위핑을 초래하지 않으면서 많은 수의 반도체 칩을 적층 할 수 있는 스택 패키지 및 그 제조방법을 제공하는 것이다. It is still another specific object of the present invention to provide a stack package and a manufacturing method thereof capable of stacking a large number of semiconductor chips without causing wire sweeping.

본 발명의 보다 구체적인 다른 목적은 최상단에 적층되는 반도체 칩으로부터 기판까지의 본딩 와이어의 길이를 최소화할 수 있는 스택 패키지 및 그 제조방법을 제공하는 것이다.
Another object of the present invention is to provide a stack package capable of minimizing the length of a bonding wire from a semiconductor chip stacked on a top end to a substrate, and a manufacturing method thereof.

이를 위해 본 발명의 일 실시예에 따른 스택 패키지는 서로 대향하는 제1 표면 및 제2 표면과, 상기 제2 표면상에 형성된 본딩핑거와, 상기 제1 표면으로부터 상기 제2 표면까지 관통하도록 형성된 개구부를 구비하는 인쇄회로기판과; 상기 인쇄회로기판의 상기 제1 표면상에 적층되며, 와이어에 의해 상기 본딩핑거와 본딩되어 상기 인쇄회로기판과 전기 접속되는 적어도 하나의 제1 반도체 칩을 구비하는 제1 칩 적층부와; 상기 인쇄회로기판의 상기 제2 표면상에 적층되며, 상기 개구부를 관통하는 와이어에 의해 상기 본딩핑거와 본딩되어 상기 인쇄회로기판과 전기 접속되는 적어도 하나의 제2 반도체 칩을 구비하는 제2 칩 적층부를 포함하는 것을 특징으로 한다. To this end, a stack package according to an embodiment of the present invention includes a first surface and a second surface opposed to each other, a bonding finger formed on the second surface, an opening formed to penetrate from the first surface to the second surface, A printed circuit board (PCB) A first chip stacking portion stacked on the first surface of the printed circuit board and having at least one first semiconductor chip bonded to the bonding finger by a wire and electrically connected to the printed circuit board; A second chip stacked on the second surface of the printed circuit board and having at least one second semiconductor chip bonded to the bonding finger by a wire passing through the opening and electrically connected to the printed circuit board, And the like.

본 발명의 일 실시예에 따른 스택 패키지에서, 상기 제1 반도체 칩은 상면 일측 단부에 제1 본딩패드를 구비하며, 복수 개의 상기 제1 반도체 칩은 상기 제1 본딩패드가 노출되도록 계단형태로 적층될 수 있다. In the stack package according to an embodiment of the present invention, the first semiconductor chip may have a first bonding pad at one side of its upper surface, and a plurality of the first semiconductor chips may be stacked in a stepwise manner to expose the first bonding pad. .

본 발명의 일 실시예에 따른 스택 패키지에서, 상기 제2 반도체 칩은 상면 일측 단부에 제2 본딩패드를 구비하며, 복수 개의 상기 제2 반도체 칩은 상기 제2 본딩패드가 노출되도록 계단형태로 적층될 수 있다. In the stack package according to an embodiment of the present invention, the second semiconductor chip may have a second bonding pad at one side of its upper surface, and a plurality of the second semiconductor chips may be stacked in a stepwise manner to expose the second bonding pad. .

본 발명의 일 실시예에 따른 스택 패키지 제조방법은 (a) 서로 대향하는 제1 표면 및 제2 표면을 갖는 인쇄회로기판에 상기 제1 표면으로부터 상기 제2 표면까지 관통하도록 개구부를 형성하는 과정과; (b) 상기 제2 표면에 본딩핑거를 형성하는 과정과; (c) 제1 본딩패드를 구비하는 적어도 하나의 제1 반도체 칩을 상기 제1 표면에 적층하되, 적어도 하나의 상기 제1 본딩패드가 상기 개구부 내에 위치하도록 적층하는 과정과; (d) 제2 본딩패드를 구비하는 적어도 하나의 제2 반도체 칩을 적층하는 과정; 및 (e) 상기 제1 본딩패드 및 상기 제2 본딩패드와 상기 본딩핑거를 와이어 본딩으로 접속하는 과정을 포함하는 것을 특징으로 한다. According to an aspect of the present invention, there is provided a stack package manufacturing method comprising the steps of: (a) forming an opening in a printed circuit board having first and second surfaces opposed to each other from the first surface to the second surface; ; (b) forming a bonding finger on the second surface; (c) stacking at least one first semiconductor chip having a first bonding pad on the first surface such that at least one of the first bonding pads is located in the opening; (d) stacking at least one second semiconductor chip having a second bonding pad; And (e) connecting the first bonding pad and the second bonding pad with the bonding finger by wire bonding.

본 발명의 일 실시예에 따른 스택 패키지 제조방법에서, 상기 (b) 과정은 일측 단부에 상기 제1 본딩패드를 구비하는 1차 반도체 칩을, 상기 제1 본딩패드가 상기 개구부 내에 위치하도록 상기 1차 반도체 칩을 상기 인쇄회로기판의 상기 제1 표면에 부착하는 단계와; 상기 1차 반도체 칩의 배면에 2차 반도체 칩, 3차 반도체 칩 및 4차 반도체 칩을 차례로 적층 부착하되, 각 반도체 칩의 일측 단부에 구비된 상기 제1 본딩패드가 상기 개구부 내에 위치하도록 계단형태로 적층하는 단계를 포함할 수 있다. In the method of manufacturing a stack package according to an embodiment of the present invention, the step (b) includes a step of bonding the first semiconductor chip having the first bonding pad at one end thereof to the first semiconductor chip, Attaching a secondary semiconductor chip to the first surface of the printed circuit board; A second semiconductor chip, a third semiconductor chip, and a fourth semiconductor chip are stacked in this order on the back surface of the first semiconductor chip, and the first bonding pad provided at one end of each semiconductor chip is arranged in a stepped shape As shown in FIG.

본 발명의 일 실시예에 따른 스택 패키지 제조방법에서, 상기 (d) 과정은 일측 단부에 상기 제2 본딩패드를 구비하는 복수의 제2 반도체 칩을 차례로 적층 부착하되, 각 반도체 칩의 일측 단부에 구비된 상기 제2 본딩패드가 노출되도록 계단형태로 적층하는 단계를 포함할 수 있다.
In the method of manufacturing a stack package according to an embodiment of the present invention, the step (d) includes sequentially stacking a plurality of second semiconductor chips having the second bonding pads at one end thereof, And stacking the second bonding pads in a stepwise manner to expose the second bonding pads.

본 발명에 따른 스택 패키지 및 그 제조방법에 의하면, 이와 같이 본 발명의 실시예에 따른 스택 패키지 및 그 제조방법은 인쇄회로기판에 개구부를 형성하고, 인쇄회로기판의 상면 및 배면의 양면에 다수의 반도체 칩을 적층한 다음 이 개구부를 통과하도록 본딩 와이어를 형성함으로써 인쇄회로기판의 일면에만 반도체 칩을 적층하는 구조에 비해 최상단 반도체 칩과 인쇄회로기판 간의 본딩 와이어의 길이를 최소화하고, 본딩 페일 등의 고단 적층에 따른 문제점을 개선할 수 있다. According to the stack package and the method of manufacturing the same of the present invention, the stack package and the method of manufacturing the same according to the embodiment of the present invention can form an opening in the printed circuit board, The length of the bonding wire between the uppermost semiconductor chip and the printed circuit board is minimized compared to a structure in which the semiconductor chips are stacked only on one side of the printed circuit board by stacking the semiconductor chips and then forming the bonding wires so as to pass through the openings, The problems caused by the high-temperature lamination can be improved.

또한, 본 발명에 따른 스택 패키지 및 그 제조방법에 의하면, 인쇄회로기판에 개구부를 형성함으로써 리플로우 진행시 열에 대한 인쇄회로기판의 휨을 감소시키고, 반도체 칩과 인쇄회로기판 각각의 열팽창 계수(CTE: Coefficient of Thermal Expansion)의 차이로 인한 반도체 칩과 인쇄회로기판의 접합면에서의 스트레스(Stress) 발생을 감소시켜 범프 크랙(Bump Crack) 및 오픈(Open) 등의 불량발생이나 워페이지(warpage) 발생을 최소화할 수 있다.
According to the stack package and the method of manufacturing the same according to the present invention, it is possible to reduce the warpage of the printed circuit board against heat during the reflow process by forming openings in the printed circuit board, Due to the difference of the coefficient of thermal expansion, the occurrence of stress on the junction surface between the semiconductor chip and the printed circuit board is reduced to cause defects such as bump crack and open, and warpage Can be minimized.

도 1은 종래의 스택 패키지를 개략적으로 나타낸 단면도이다.
도 2는 본 발명의 일 실시예에 따른 스택 패키지의 구조를 개략적으로 나타낸 도면이다.
도 3a 내지 도 3f는 본 발명의 일 실시예에 따른 스택 패키지의 제조방법을 설명하기 위한 공정 단면도이다. 1 is a schematic cross-sectional view of a conventional stack package.
2 is a schematic diagram illustrating the structure of a stack package according to an embodiment of the present invention.
3A to 3F are cross-sectional views illustrating a method of manufacturing a stack package according to an embodiment of the present invention.

이하, 첨부 도면을 참조하여 본 발명의 실시 예를 상세히 설명하면 다음과 같다. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명을 설명함에 있어서, 관련된 공지기능 혹은 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우 그 상세한 설명은 생략한다. 또한, 후술되는 용어들은 본 발명에서의 기능을 고려하여 정의된 용어들로서 이는 사용자의 의도 또는 판례 등에 따라 달라질 수 있다. 그러므로 그 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the terms described below are defined in consideration of the functions of the present invention, and these may vary depending on the intention or precedent of the user. Therefore, the definition should be based on the contents throughout this specification.

도 2는 본 발명의 일 실시예에 따른 집적회로 패키지의 구조를 개략적으로 나타낸 도면으로, 도 2의 (a)는 단면도이고, 도 2의 (b)는 평면도이다. 2 is a schematic view of a structure of an integrated circuit package according to an embodiment of the present invention, wherein FIG. 2A is a cross-sectional view, and FIG. 2B is a plan view.

도 2를 참조하면, 본 실시예에 따른 집적회로 패키지(1)는 인쇄회로기판(100)과, 제1 칩 적층부(140) 및 제2 칩 적층부(160)와, 제1 내지 제3 본딩 와이어(150, 170, 190)를 포함한다. 2, the integrated circuit package 1 according to the present embodiment includes a printed circuit board 100, a first chip stacking unit 140 and a second chip stacking unit 160, first through third And bonding wires 150, 170, and 190.

상기 인쇄회로기판(100)은 서로 대향하는 제1 표면(배면)(101) 및 제2 표면(상면)(102)과, 상기 제1 표면으로부터 상기 제2 표면까지 관통하도록 형성된 개구부(110)와, 상기 제2 표면상에 형성된 본딩핑거(120)를 구비한다. 이러한 인쇄회로기판(100)은 예를 들어 폴리이미드(polyimide) 등의 고분자 물질로 형성될 수 있으며, 표면 또는 내부에 회로 배선이 형성되어 있을 수 있으며, 이 경우 상기 개구부(110)는 회로 배선이 형성되어 있지 않은 부분에 마련된다. The printed circuit board 100 includes a first surface (back surface) 101 and a second surface (upper surface) 102 facing each other, an opening 110 formed to penetrate from the first surface to the second surface, And bonding fingers 120 formed on the second surface. The printed circuit board 100 may be formed of a polymer material such as polyimide or the like, and circuit wiring may be formed on the surface or inside. In this case, And is provided in a portion where it is not formed.

상기 개구부(110)는 인쇄회로기판(100)의 배면(101)에 실장되는 제1 칩 적층부(140)를 구성하는 각각의 제1 반도체 칩(140A~140D)과 인쇄회로기판(100)과의 전기적 접속을 위한 통로역할을 한다. 즉, 제1 반도체 칩(140A~140D)과 인쇄회로기판(100)을 전기적으로 연결하는 제1 본딩 와이어(150)가 인쇄회로기판(100)의 배면(101)에서 상면(102)으로(아래쪽에서 위쪽으로) 개구부(110)를 통과하여 연결될 수 있도록 한다.The opening 110 is formed in the first semiconductor chip 140A to 140D and the printed circuit board 100 and the second semiconductor chip 140A to 140D constituting the first chip stacking unit 140 to be mounted on the back surface 101 of the printed circuit board 100, As shown in FIG. That is, a first bonding wire 150 for electrically connecting the first semiconductor chips 140A to 140D and the printed circuit board 100 is electrically connected from the back surface 101 of the printed circuit board 100 to the top surface 102 So that they can be connected to each other through the opening 110.

여기서, 개구부(110)의 크기는 인쇄회로기판(100)의 배면(101)에 적층되는 제1 칩 적층부(140)의 적층구조, 제1 반도체 칩(140A~140D)의 크기나 본딩패드(141a~141d)의 위치 등 필요에 따라 적정 크기로 선택할 수 있다. 즉, 개구부(110)의 크기를 도 2에 도시된 바와 같이 인쇄회로기판(100) 배면(101)에 위치하는 본딩패드(141A~141D)가 모두 노출될 수 있도록 할 수도 있고, 본딩패드(141A~141D) 중 일부가 노출되도록 할 수도 있다. The sizes of the openings 110 are determined by the stacking structure of the first chip stacking unit 140 stacked on the back surface 101 of the printed circuit board 100 and the size of the first semiconductor chips 140A to 140D, 141a to 141d and the like. That is, the size of the opening 110 may be such that the bonding pads 141A to 141D located on the back surface 101 of the printed circuit board 100 are all exposed as shown in FIG. 2, To 141D may be exposed.

상기 본딩핑거(120)는 인쇄회로기판(100) 상면(102)상의 제2 칩 적층부(160)와 개구부(110) 사이에 형성되며, 제1 칩 적층부(140)를 이루는 제1 반도체 칩(141~145) 및 제2 칩 적층부(160)를 이루는 제2 반도체 칩(160A~160D, 160T)과 제 및 제2 본딩 와이어(141A~141D, 161A~16D)에 의해 연결된다.The bonding finger 120 is formed between the second chip stacking portion 160 on the upper surface 102 of the printed circuit board 100 and the opening 110 and the first chip stacking portion 140, The second semiconductor chips 160A to 160D and 160T and the second and third bonding wires 141A to 141D and 161A to 16D constituting the first chip stacking part 141 to 145 and the second chip stacking part 160 are connected.

상기 제1 칩 적층부(140)는 인쇄회로기판(100)의 배면에 2 이상 다단으로 적층된 복수 개의 제1 반도체 칩(140A~140D)을 포함한다. 이러한 복수 개의 제1 반도체 칩(140A~140D)은 상면 오른쪽(일측) 단부(가장자리)에 제1 본딩패드(141A~141D)를 구비하며, 제1 본딩패드(141A~141D)가 노출되도록 왼쪽에서 계단형태로 적층되어 있다. The first chip stacking part 140 includes a plurality of first semiconductor chips 140A to 140D stacked in two or more stages on the back surface of the printed circuit board 100. [ The plurality of first semiconductor chips 140A to 140D are provided with first bonding pads 141A to 141D on the upper right side (one side) of the upper surface and the first bonding pads 141A to 141D And are stacked in a stepped shape.

상기 제2 칩 적층부(160)는 인쇄회로기판(100)의 상면에 2 이상 다단으로 적층된 복수 개의 제2 반도체 칩(160A~160D, 160T)을 포함한다. 이러한 복수 개의 제2 반도체 칩(160A~160D, 160T)은 제1 반도체 칩(140A~140D)과 마찬가지로 상면 오른쪽(일측) 단부(가장자리)에 제2 본딩패드(161A~161D)를 구비하며, 제2 본딩패드가 노출되도록 계단형태로 적층되어 있다. 다만, 최상층에 적층되는 반도체 칩(160T)은 칩의 크기나, 형태, 적층 위치에 따라 본딩패드(161T)가 임의의 적정 위치에 배치될 수 있다. The second chip stacking unit 160 includes a plurality of second semiconductor chips 160A to 160D and 160T stacked on the upper surface of the printed circuit board 100 in two or more stages. The plurality of second semiconductor chips 160A to 160D and 160T may include second bonding pads 161A to 161D on the right side (one side) of the top surface in the same manner as the first semiconductor chips 140A to 140D, 2 bonding pads are exposed. However, the semiconductor chip 160T stacked on the uppermost layer may be disposed at any suitable position depending on the size, shape, and stacking position of the chip.

여기서, 상기 제1 칩 적층부(140)와 상기 제2 칩 적층부(160)를 이루는 각각의 반도체 칩(140A~140D, 160A~160D, 160T)은 접착층(미도시) 예를 들면, 접착테이프에 의해 하부 및 상부의 인홰회로기판(100) 또는 반도체 칩과 부착되어 있다. 다른 예로, 접착층으로 본딩 와이어(150, 170, 190)가 침투할 수 있는 침투테이프(penetration tape)를 사용할 수 있으며, 이 경우 반도체 칩(140A~140D, 160A~160D, 160T)상에 본딩 와이어를 형성하기 위한 스페이서를 필요로 하지 않으며, 본딩 와이어가 쓰러지거나 눌리는 등의 불량을 억제할 수 있다. Each of the semiconductor chips 140A to 140D, 160A to 160D and 160T constituting the first chip stacking part 140 and the second chip stacking part 160 is bonded to an adhesive layer (not shown) And is attached to the upper and lower circuit board 100 or the semiconductor chip. As another example, a penetration tape capable of penetrating the bonding wires 150, 170, and 190 into the adhesive layer may be used. In this case, bonding wires may be formed on the semiconductor chips 140A to 140D, 160A to 160D, It is not necessary to provide a spacer for forming the wiring, and it is possible to suppress defects such as collapsing or pressing of the bonding wire.

이들 반도체 칩(140A~140D, 160A~160D, 160T)은 서로 동일한 구조의 칩일 수도 서로 다른 구조의 칩일 수도 있으며, 반도체 칩에는 메모리소자, 로직로자, 광전소자 또는 파워소자 등의 반도체 소자가 형성될 수 있으며, 반도체 소자에는 저항, 콘덴서 등의 각종 수동소자가 포함될 수 있다. These semiconductor chips 140A to 140D, 160A to 160D, and 160T may be chips having the same structure or different structures, and semiconductor devices such as a memory device, a logic device, a photoelectric device, or a power device may be formed on the semiconductor chip And semiconductor elements may include various passive elements such as resistors and capacitors.

상기 제1 및 제2 본딩 와이어(150, 170)는 제1 반도체 칩(140A~140D) 및 제2 반도체 칩(160A~160D)과 인쇄회로기판(100)을 전기적으로 연결하기 위한 것으로, 본딩패드가 노출된 각 반도체 칩의 단부쪽에서 인쇄회로기판(110) 및 각각의 반도체 칩(140A~140D, 160A~160D)이 순차적으로 본딩되어 있다. The first and second bonding wires 150 and 170 electrically connect the first semiconductor chips 140A to 140D and the second semiconductor chips 160A to 160D to the printed circuit board 100, The printed circuit board 110 and the respective semiconductor chips 140A to 140D and 160A to 160D are sequentially bonded to the ends of the exposed semiconductor chips.

여기서, 제1 본딩 와이어(150)는 인쇄회로기판(100)의 배면(101)에 위치하는 본딩패드(141A~141D)로부터 개구부(110)를 통과하여 인쇄회로기판(100)의 상면(102)에 위치하는 본딩핑거(120)와 연결되어 있다. The first bonding wire 150 passes through the opening 110 from the bonding pads 141A to 141D located on the back surface 101 of the printed circuit board 100 and passes through the upper surface 102 of the printed circuit board 100, And is connected to a bonding finger 120 located at a predetermined position.

상기 제3 본딩 와이어(190)는 제2 칩 적층부(160)의 최상단에 위치하는 탑 반도체 칩(160T)와 인쇄회로기판(100)을 전기적으로 연결하기 위한 것으로, 본딩패드가 노출된 각 반도체 칩의 단부쪽에서 인쇄회로기판(110) 및 각각의 반도체 칩(140A~140D, 160A~160D)이 순차적으로 본딩되어 있다. The third bonding wire 190 is for electrically connecting the top semiconductor chip 160T positioned at the uppermost end of the second chip stacking unit 160 to the printed circuit board 100, The printed circuit board 110 and the respective semiconductor chips 140A to 140D and 160A to 160D are sequentially bonded from the end of the chip.

전술한 구성을 갖는 본 발명의 스택 패키지의 제조방법을 설명하면 다음과 같다. A method of manufacturing the stack package of the present invention having the above-described structure will be described below.

도 3a 내지 도 3f는 본 발명의 일 실시예에 따른 스택 패키지(1)의 제조방법을 설명하기 위한 공정 단면도이다. 3A to 3F are cross-sectional views illustrating a method of manufacturing a stack package 1 according to an embodiment of the present invention.

먼저, 도 3a에 도시된 바와 같이 인쇄회로기판(100)의 일측(오른쪽) 가장자리 부분에 개구부(110)를 형성하고, 그 안쪽에 본딩핑거(120)를 패터닝 한다. 여기서, 개구부(110)를 통해 인쇄회로기판(100) 배면에 적층되는 제1 칩 적층부와 인쇄회로기판(100) 상면에 위치하는 본딩핑거(120)가 제1 본딩 와이어에 의해 전기적으로 접속되므로 인쇄회로기판(100)의 배면에 적층되는 제1 칩 적층부의 적층구조, 제1 반도체 칩(140A~140D)의 크기나 본딩패드(141a~141d)의 위치 등을 고려하여 개구부(110)의 위치 및 크기를 선택할 수 있다. 즉, 개구부(110)의 크기를 도 2에 도시된 바와 같이 인쇄회로기판(100) 배면(101)에 위치하는 본딩패드(141A~141D)가 모두 노출될 수 있도록 할 수도 있고, 본딩패드(141A~141D) 중 일부가 노출되도록 할 수도 있다. First, as shown in FIG. 3A, an opening 110 is formed at one edge (right side) of the printed circuit board 100, and a bonding finger 120 is patterned inside the opening 110. Here, since the first chip stacked portion stacked on the back surface of the printed circuit board 100 through the opening 110 and the bonding fingers 120 positioned on the upper surface of the printed circuit board 100 are electrically connected by the first bonding wire The position of the opening 110 is determined in consideration of the stacked structure of the first chip stacked portion stacked on the back surface of the printed circuit board 100 and the size of the first semiconductor chips 140A to 140D and the positions of the bonding pads 141a to 141d, And size. That is, the size of the opening 110 may be such that the bonding pads 141A to 141D located on the back surface 101 of the printed circuit board 100 are all exposed as shown in FIG. 2, To 141D may be exposed.

다음으로, 도 3b에 도시된 바와 같이 인쇄회로기판(100)의 배면에 1차 반도체 칩(140A)을 부착한다. 여기서, 1차 반도체 칩(140A)은 오른쪽 단부에 본딩패드(141A)를 구비하고 있으며, 이 본딩패드(141A)가 개구부(110) 내에 위치하도록 1차 반도체 칩(140A)의 위치를 설정한 다음 접착층을 매개로 인쇄회로기판(100)의 배면에 부착한다. Next, the primary semiconductor chip 140A is attached to the back surface of the printed circuit board 100 as shown in FIG. 3B. The first semiconductor chip 140A is provided with a bonding pad 141A at the right end and the position of the first semiconductor chip 140A is set so that the bonding pad 141A is positioned within the opening 110 And adheres to the back surface of the printed circuit board 100 via an adhesive layer.

계속해서, 도 3c에 도시된 바와 같이 1차 반도체 칩(140A)의 배면에 2차 반도체 칩(140B), 3차 반도체 칩(140C), 4차 반도체 칩(140D)을 차례로 적층 부착한다. 2차 내지 4차 반도체 칩(140B~140D) 또한 오른쪽 단부에 본딩패드(141B~141D)를 구비하고 있으며, 이 본딩패드(141B~141D)가 개구부(110) 내에서 노출되도록 각 반도체 칩(141B~141D)을 접착층을 매개로 부착한다. 이 경우, 제1 칩 적층부(140)는 전체적으로 계단형태를 이룬다. 한편, 이러한 계단형태의 제1 칩 적층부(140)는 일 실시예에 불과하며 제1 칩 적층부(140)의 적층 형태는 다양하게 구현할 수 있다. 예를 들면, 접착층으로 본딩 와이어가 침투할 수 있는 침투테이프(penetration tape)를 사용할 수 있으며, 이 경우 2차 내지 4차 반도체 칩(140B~140D)의 상부에 구비된 본딩패드(141B~141D)를 노출시키지 않고 포개어서 부착할 수 있다. Subsequently, as shown in Fig. 3C, the secondary semiconductor chip 140B, the tertiary semiconductor chip 140C, and the quaternary semiconductor chip 140D are stacked in order on the back surface of the primary semiconductor chip 140A. The second to fourth semiconductor chips 140B to 140D are also provided with bonding pads 141B to 141D at the right end and are electrically connected to the semiconductor chips 141B to 141D so that the bonding pads 141B to 141D are exposed in the opening 110. [ To 141D) are attached via an adhesive layer. In this case, the first chip stacking portion 140 has a stepped shape as a whole. Meanwhile, the first chip stacking unit 140 having a step shape is merely an embodiment, and the stacking configuration of the first chip stacking unit 140 can be variously implemented. For example, a penetration tape capable of penetrating the bonding wire with the adhesive layer can be used. In this case, the bonding pads 141B to 141D provided on the upper part of the second to fourth semiconductor chips 140B to 140D, So that they can be attached without being exposed.

다음으로, 도 3d에 도시된 바와 같이 인쇄회로기판(100)의 상면에 제2 칩 적층부(160)를 구성하는 반도체 칩(160A~160D)을 부착한다. 여기서, 반도체 칩(160A~160D)은 오른쪽 단부에 본딩패드(161A~161D)를 구비하고 있으며, 이 본딩패드(161A~161D)가 본딩핑거(120) 주변에 위치하도록, 먼저 1차 반도체 칩(160A)의 위치를 설정한 다음 2차 내지 4차 반도체 칩(160B~160D)을 차례로 계단형태로 적층 부착한다. Next, as shown in FIG. 3D, the semiconductor chips 160A to 160D constituting the second chip stacking portion 160 are attached to the upper surface of the printed circuit board 100. Next, as shown in FIG. Here, the semiconductor chips 160A to 160D are provided with bonding pads 161A to 161D at the right end, and the bonding pads 161A to 161D are disposed on the first semiconductor chip 160A are set, and then the second to fourth semiconductor chips 160B to 160D are stacked in a stepwise manner.

다음으로, 도 3e에 도시된 바와 같이 제2 칩 적층부(160)의 최상단 즉, 4차 반도체 칩(160D) 위에 탑 반도체 칩(160T)을 부착한다. Next, as shown in FIG. 3E, the top semiconductor chip 160T is attached to the uppermost end of the second chip stacking portion 160, that is, the fourth semiconductor chip 160D.

다음으로, 도 3f에 도시된 바와 같이 와이어 본딩 공정을 진행하여 제1 칩 적층부(140)와 상기 제2 칩 적층부(160)를 이루는 각각의 반도체 칩(140A~140D, 160A~160D, 160T)과 인쇄회로기판(100)을 전기적으로 접속하는 제1 내지 제3 본딩 와이어(150, 170, 190)를 형성한다. Next, as shown in FIG. 3F, the semiconductor chips 140A to 140D, 160A to 160D, and 160T (160A to 160D) that constitute the first chip stacking unit 140 and the second chip stacking unit 160 And the first to third bonding wires 150, 170, and 190 that electrically connect the printed circuit board 100 and the printed circuit board 100 are formed.

여기서, 제1 본딩 와이어(150)는 인쇄회로기판(100)의 배면(101)에 위치하는 본딩패드(141A~141D)로부터 개구부(110)를 통과하여 인쇄회로기판(100)의 상면(102)에 위치하는 본딩핑거(120)와 연결되어 있다. The first bonding wire 150 passes through the opening 110 from the bonding pads 141A to 141D located on the back surface 101 of the printed circuit board 100 and passes through the upper surface 102 of the printed circuit board 100, And is connected to a bonding finger 120 located at a predetermined position.

또한, 본 실시예에서 제2 적층부(160)는 전체적으로 계단형태를 이루고 있으나 이러한 계단형태의 제2 칩 적층부(160)는 일 실시예에 불과하며 제2 칩 적층부(160)의 적층 형태는 다양하게 구현할 수 있음은 물론이다. In this embodiment, the second laminated portion 160 has a stepped shape as a whole, but the stepped second chip laminated portion 160 is only an example, and the laminated type of the second chip laminated portion 160 But may be implemented in various ways.

이와 같이 본 발명의 실시예에 따른 스택 패키지 및 그 제조방법은 인쇄회로기판에 개구부를 형성하고, 인쇄회로기판의 상면 및 배면의 양면에 다수의 반도체 칩을 적층한 다음 이 개구부를 통과하도록 본딩 와이어를 형성함으로써 인쇄회로기판 배면에 적층된 다수의 반도체 칩과 인쇄회로기판을 전기적으로 연결할 수 있도록 한다. 이에 따라, 인쇄회로기판의 일면에만 반도체 칩을 적층하는 구조에 비해 최상단 반도체 칩과 인쇄회로기판 간의 본딩 와이어의 길이를 최소화하고, 본딩 페일 등의 고단 적층에 따른 문제점을 개선할 수 있다. As described above, the stack package and the method of manufacturing the same according to the embodiment of the present invention are characterized in that an opening is formed in a printed circuit board, a plurality of semiconductor chips are stacked on both sides of a top surface and a back surface of a printed circuit board, So that the plurality of semiconductor chips stacked on the back surface of the printed circuit board can be electrically connected to the printed circuit board. Accordingly, the length of the bonding wire between the uppermost semiconductor chip and the printed circuit board can be minimized, and the problems caused by the high-speed stacking of the bonding pads and the like can be improved as compared with the structure in which the semiconductor chips are stacked on only one side of the printed circuit board.

또한, 인쇄회로기판에 개구부를 형성함으로써 리플로우 진행시 열에 대한 인쇄회로기판의 휨을 감소시키고, 반도체 칩과 인쇄회로기판 각각의 열팽창 계수(CTE: Coefficient of Thermal Expansion)의 차이로 인한 반도체 칩과 인쇄회로기판의 접합면에서의 스트레스(Stress) 발생을 감소시켜 범프 크랙(Bump Crack) 및 오픈(Open) 등의 불량발생을 줄일 수 있다.In addition, by forming openings in the printed circuit board, it is possible to reduce the warpage of the printed circuit board with respect to heat during the progress of the reflow process and to reduce the warpage of the semiconductor chip and the printed circuit board due to the difference in the coefficient of thermal expansion (CTE) It is possible to reduce the occurrence of stress on the joint surface of the circuit board and to reduce the occurrence of defects such as bump crack and open.

또한, 몰딩 공정(Molding Process)에서 발생할 수 있는 보이드(Void)를 관통홀을 통해 진공으로 빼줄 수 있기 때문에 인쇄회로기판과 반도체 칩 사이를 채우는 봉지재 내부에서 보이드 결함(Void Defect)이 발생하는 것을 억제할 수 있다.In addition, since voids that can occur in a molding process can be removed through a through hole, void defects may be generated in the encapsulating material filling the space between the printed circuit board and the semiconductor chip. .

한편, 본 발명의 상세한 설명 및 첨부도면에서는 구체적인 실시예에 관해 설명하였으나, 본 발명은 개시된 실시예에 한정되지 않고 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다. 따라서, 본 발명의 범위는 설명된 실시예에 국한되어 정해져서는 안되며 후술하는 특허청구범위뿐만 아니라 이 특허청구범위와 균등한 것들을 포함하는 것으로 해석되어야 할 것이다.
While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and similarities. Accordingly, the scope of the present invention should be construed as being limited to the embodiments described, and it is intended that the scope of the present invention encompasses not only the following claims, but also equivalents thereto.

100 : 인쇄회로기판 110 : 개구부
120 : 본딩핑거 140, 160 : 칩 적층부
140A~140D, 160A~160D, 160T : 반도체 칩
130, 150, 170 : 본딩 와이어100: printed circuit board 110: opening
120: bonding finger 140, 160: chip stacking part
140A to 140D, 160A to 160D, and 160T: semiconductor chips
130, 150, 170: Bonding wire

Claims (6)

서로 대향하는 제1 표면 및 제2 표면과, 상기 제2 표면상에 형성된 본딩핑거와, 상기 제1 표면으로부터 상기 제2 표면까지 관통하도록 형성된 개구부를 구비하는 인쇄회로기판과;
상기 인쇄회로기판의 상기 제1 표면상에 적층되며, 상기 개구부를 관통하는 제1 와이어에 의해 상기 본딩핑거와 본딩되어 상기 인쇄회로기판과 전기 접속되는 적어도 하나의 제1 반도체 칩을 구비하는 제1 칩 적층부와;
상기 인쇄회로기판의 상기 제2 표면상에 적층되며, 제2 와이어에 의해 상기 본딩핑거와 본딩되어 상기 인쇄회로기판과 전기 접속되는 적어도 하나의 제2 반도체 칩을 구비하는 제2 칩 적층부를 포함하며,
상기 개구부, 상기 제1 와이어 및 상기 제2 와이어는 상기 기판의 왼쪽 또는 오른쪽 중 어느 일측에만 존재하는 것을 특징으로 하는 스택 패키지.
A printed circuit board having a first surface and a second surface opposite to each other, a bonding finger formed on the second surface, and an opening formed to penetrate from the first surface to the second surface;
A first semiconductor chip stacked on the first surface of the printed circuit board and having at least one first semiconductor chip bonded to the bonding finger by a first wire penetrating the opening and electrically connected to the printed circuit board, A chip stacking portion;
And a second chip stacking portion stacked on the second surface of the printed circuit board and having at least one second semiconductor chip bonded to the bonding finger by a second wire and electrically connected to the printed circuit board, ,
Wherein the opening, the first wire, and the second wire are present only on either side of the left or right side of the substrate.
제 1 항에 있어서, 상기 제1 반도체 칩은 상면 일측 단부에 제1 본딩패드를 구비하며, 복수 개의 상기 제1 반도체 칩은 상기 제1 본딩패드가 노출되도록 계단형태로 적층된 것을 특징으로 하는 스택 패키지.
2. The semiconductor device according to claim 1, wherein the first semiconductor chip has a first bonding pad at one end of its top surface, and a plurality of the first semiconductor chips are stacked in a stepwise manner such that the first bonding pad is exposed. package.
제 1 항 또는 제 2 항에 있어서, 상기 제2 반도체 칩은 상면 일측 단부에 제2 본딩패드를 구비하며, 복수 개의 상기 제2 반도체 칩은 상기 제2 본딩패드가 노출되도록 계단형태로 적층된 것을 특징으로 하는 스택 패키지.
3. The semiconductor device according to claim 1 or 2, wherein the second semiconductor chip has a second bonding pad at one end of its upper surface, and the plurality of second semiconductor chips are stacked in a stepwise manner to expose the second bonding pad Features a stack package.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010061886A (en) * 1999-12-29 2001-07-07 윤종용 Stack chip package
KR20080077566A (en) * 2007-02-20 2008-08-25 가부시끼가이샤 도시바 Semiconductor device and semiconductor module using same
KR20110086407A (en) * 2010-01-22 2011-07-28 삼성전자주식회사 Stacked Package of Semiconductor Devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010061886A (en) * 1999-12-29 2001-07-07 윤종용 Stack chip package
KR20080077566A (en) * 2007-02-20 2008-08-25 가부시끼가이샤 도시바 Semiconductor device and semiconductor module using same
KR20110086407A (en) * 2010-01-22 2011-07-28 삼성전자주식회사 Stacked Package of Semiconductor Devices

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