KR102164539B1 - Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices - Google Patents

Abstract

Methods of manufacturing semiconductor devices including an interposer, including formation of conductive vias penetrating through a material layer on a recoverable substrate, are provided. A carrier substrate is bonded over the material layer, and then the recoverable substrate is separated from the material layer to restore the recoverable substrate. A detachable interface may be provided between the material layer and the recoverable substrate to facilitate the separation. Electrical contacts in electrical communication with the conductive vias may be formed on the material layer opposite the carrier substrate. Semiconductor structures and devices are formed using these methods.

Description

TECHNICAL FIELD [Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices]

The present invention relates to methods of forming and using interposers in the manufacture of semiconductor devices, and to structures and devices manufactured using such methods.

The technical features of the present application are "Methods of forming bonded semiconductor structures including two or more processed semiconductor structures transferred by a common substrate, and methods of forming bonded semiconductor structures including Two or more processed semiconductor structures carried by a common substrate, and semiconductor structures formed by such methods), which is related to the technical features of US Patent Application No. 13/077,365 filed March 31, 2011.

Electronic signal processors, memory devices and photoactive devices (e.g., LEDs, laser diodes, photocells, photoactive devices) In the manufacture of semiconductor devices including integrated circuits such as photodetectors, etc.), between two devices (e.g., two integrated circuit elements), between devices and structures (e.g. For example, between an integrated circuit device and a package substrate such as a circuit board or layer), or between two structures, it is often required to employ what is referred to in the industry as an “interposer”. Such an interposer is disposed between two elements and/or structures and can be used to provide structural and electrical interconnection between the two elements and/or structures.

In some cases, an interposer may be used to redistribute the electrical connection pattern. For example, the integrated circuit device may have an array of electrical contact features arranged in a first pattern, and other devices or structures to which the integrated circuit device is coupled may have a different second It can have an array of electrical contact features arranged in a pattern. Thus, in order to establish an electrical connection between the electrical contact features of the integrated circuit device and the electrical contact features of another device and structure, the integrated circuit device is not simply abutted against or bonded to another device or structure. May not.

In order to facilitate electrical interconnection, the interposer is a first set of electrical contact features on a first side arranged in a pattern that is a mirror image of a pattern of electrical contact features of an integrated circuit device, and other devices or structures. May be fabricated to include a second set of electrical contact features on an opposing second side, arranged in another pattern, which is a mirror image of the pattern of electrical contact features of. The interposer may include one or more electrically conductive vias extending vertically through at least a portion of the interposer perpendicular to a major plane of the interposer, and the interposer It may include electrically conductive traces extending horizontally across the interposer in parallel to the main surface of the integrated circuit device and defining a location where electrical connection will be established with other devices or structures. It may include electrically conductive contact pads. Conductive vias and traces may be used to "redistribute" the pattern of contact pads on the first side of the interposer to another pattern of the contact pads on the opposite second side of the interposer. In this configuration, the contact pads on the first side of the interposer can be structurally and electrically coupled to the electrical contact features of the integrated circuit device, and the contact pads on the opposite second side of the interposer are It may be structurally and electrically coupled to electrical contact features of another structure or device, thereby providing an electrical interconnection between the integrated circuit device and the other structure or device through the interposer.

In general, interposers are relatively thick so that the interposers can be handled and manipulated by conventional semiconductor manufacturing process equipment. For example, interposers may have an average layer thickness of 200 micrometers (200 μm) or more.

Features of semiconductor devices continue to shrink to smaller dimensions. When the average cross-sectional dimension (eg, average diameter) of the conductive vias formed through the interposers decreases, the aspect ratios of the conductive vias increase. The aspect ratio of the conductive via is defined by the length of the conductive via (a vertical dimension perpendicular to the major surface of the interposer) divided by the average cross-sectional dimension of the conductive via. For example, a conductive via with a length of 200 microns (200 microns) and an average cross-sectional dimension of 40 microns (40 microns) has an aspect ratio of 5 (ie, 200/40=5).

Conductive vias with high aspect ratios are difficult to form. In order to form conductive vias in interposers, holes may first be formed through the interposer, and then one or more plating processes (e.g., first electroless It can be filled with a conductive metal using an electrolytic plating process followed by an electroless plating process. Because it is necessary to deposit metal without good step coverage and voids, holes with high aspect ratios in the plating process are difficult to fill with metal. For example, prior to completely filling the area of the hole close to the center of the interposer, the areas in the holes adjacent to the opposite major surfaces of the interposer may be plugged with metal, whereby more metal is deposited into the hole. And causes voids in the resulting conductive vias. These voids can render the conductive vias inoperable. Also, larger conductive vias require the use of more metal, which adds cost and increases the metal deposition process time. Larger conductive vias also occupy a larger area on the interposer, which limits the number of conductive vias that can be formed within a given area of the interposer, which allows the overall drive of any semiconductor device with such an interposer. Bandwidth (operational bandwidth) can be limited.

The technical idea of the present invention is to provide a method of manufacturing a semiconductor device using an interposer including conductive vias having a relatively low aspect ratio.

This summary is provided to introduce a selection of inventive concepts in a simplified form. These concepts will be described in more detail in the detailed description of the exemplary embodiments disclosed below. This summary is not intended to identify key features or essential features of the claimed technical idea, nor is it intended to be used to limit the scope of the claimed technical idea.

In one embodiment, the present invention includes methods of manufacturing a semiconductor device including an interposer. According to this method, conductive vias are formed through the material layer on the recoverable substrate. A carrier substrate is bonded over the material layer on the opposite side of the recoverable substrate, and the recoverable substrate is separated from the material layer to recover the recoverable substrate. Electrical contacts in electrical communication with the conductive vias are formed on the material layer on the opposite side of the carrier substrate.

In further manufacturing methods of semiconductor devices including interposers, a detachable interface is formed between the semiconductor layer and the recoverable substrate. The detachable interface includes a bond of controlled mechanical strength between the semiconductor layer and the recoverable substrate. Conductive vias are formed to penetrate the semiconductor layer on the recoverable substrate. A carrier substrate is bonded over the semiconductor layer on the opposite side of the recoverable substrate, and the recoverable substrate is separated from the semiconductor layer to separate the recoverable substrate. Thereafter, electrical contacts in electrical communication with the conductive vias may be formed on the semiconductor layer on the opposite side of the carrier substrate.

Still other embodiments of the present invention include intermediate and fully fabricated semiconductor structures and devices formed using the methods described herein.

For example, in one embodiment, the intermediate structure formed in the manufacturing process of the semiconductor device is a semiconductor layer adhered to the top of the recoverable substrate, and desorption of controlled mechanical strength between the semiconductor layer and the recoverable substrate The semiconductor layer having a possible interface, and conductive vias extending through the semiconductor layer. A carrier substrate may be bonded to an upper portion of the semiconductor layer on the opposite side of the recoverable substrate.

According to the present invention, an interposer including conductive vias having a relatively low aspect ratio can be provided.

This specification clearly indicates what is regarded as embodiments of the present invention and ends with the claims specifically claimed, but the advantages of the embodiments in the present disclosure are the embodiments of the present disclosure when read in conjunction with the accompanying drawings. More immediately from the descriptions of specific examples of
1 is a simplified cross-sectional view of a material layer used to form an interposer having a detachable interface between a material layer and a resilient substrate on a resilient substrate;
FIG. 2 is a simplified cross-sectional view showing conductive vias formed through a layer of material of the structure shown in FIG. 1 to form at least a portion of an interposer;
FIG. 3 is a simplified cross-sectional view showing a redistribution layer formed on a material layer opposite to a resilient substrate on a material layer of the interposer shown in FIG. 2;
FIG. 4 is a simplified cross-sectional view showing a carrier substrate temporarily bonded onto a material layer opposite to the resilient substrate on a material layer of the interposer shown in FIG. 3;
5 is a simplified cross-sectional view showing the separation of a material layer of the interposer along a detachable interface between the interposer and the resilient substrate from the resilient substrate shown in FIG. 4;
FIG. 6 is a simplified cross-sectional view showing another redistribution layer formed on the material layer opposite the carrier substrate on the material layer of the interposer shown in FIG. 5;
FIG. 7 is a simplified cross-sectional view showing electrical contacts formed on the material layer opposite the carrier substrate on the material layer of the interposer shown in FIG. 6;
8 is a simplified cross-sectional view showing an integrated circuit element structurally and electrically coupled on an interposer opposite a carrier substrate of the structure shown in FIG. 7;
9 shows the removal of the carrier substrate from the structure of FIG. 8; And
10 shows another structure or device structurally and electrically coupled on an interposer opposite the integrated circuit device.

The illustrations shown below are not meant to be actual drawings of any particular semiconductor material, structure, device, or method, but are merely ideal representative diagrams used to describe embodiments of the present disclosure. No table of contents used herein may be considered as limiting the scope of the embodiments of the present invention as defined by the following claims and their legal equivalents. The concepts described within a particular table of contents are generally applicable in other sections throughout the entire specification. A plurality of references are cited herein and, irrespective of how they are characterized herein, none of the references are to be admitted as prior art related to the claimed subject matter.

Methods of manufacturing semiconductor devices including an interposer described herein may provide a relatively thin interposer including conductive vias having relatively low aspect ratios. As described in more detail below, the methods generally include forming conductive vias through a layer of material on a substrate, which may be a resilient substrate. The carrier substrate is bonded to the upper portion of the material layer opposite the recovery substrate, and thereafter, the recoverable substrate may be separated from the material layer to restore the recoverable substrate. Thereafter, electrical contacts in electrical communication with the conductive vias may be formed on the material layer opposite the carrier substrate.

A structure 100 including a recoverable substrate 102 is shown in FIG. 1. The material layer 104 is disposed on the recoverable substrate 102. In some embodiments, the detachable interface 106 may be formed or provided between the material layer 104 and the recoverable substrate 102. The detachable interface 106 may provide a bond of controlled mechanical strength between the material layer 104 and the recoverable substrate 102, and the material layer after a subsequent process to be described below. It can be used to remove the recoverable substrate 102 from 104.

The material layer 104 may include a semiconductor material layer in some embodiments. In other words, the material layer 104 may include a semiconductor layer. As non-limiting examples, the material layer 104 includes at least one of silicon, germanium, silicon carbide, diamond, and III-V semiconductor material. Can include. In some embodiments, the material layer 104 is essentially composed of silicon, and the silicon may be polycrystalline or monocrystalline.

The recoverable substrate 102 is a semiconductor material (e.g., silicon (prime grade or mechanical grade for low acquisition cost), germanium, III-V semiconductor material, etc.) or oxide ) (E.g. aluminum oxide, silicon oxide, zirconium oxide, etc.), nitride (e.g. silicon nitride) or carbide (e.g. For example, it may include a ceramic material such as silicon carbide).

The detachable interface 106 between the recoverable substrate 102 and the material layer 104 is described, for example, in Aspar et al., US Patent Application Publication No. 2004/0222500, published on November 11, 2004, Martinez disclosed in any of U.S. Patent Application Publication No. 2007/0122926 published on May 3, 2007 by Faure et al., and International Patent Application Publication No. WO2010/015878 published on February 11, 2010 by Faure et al. Can be formed as

In some embodiments, the detachable interface 106 may include a direct molecular bond between the material layer 104 and the recoverable substrate 102. In other embodiments, the detachable interface 106 as shown in FIG. 1 may include an intermediate material 107 disposed between the material layer 104 and the recoverable substrate 102. have. Such an intermediate material 107 may include one or more of a semiconductor material, a dielectric material, or a ceramic material, such as any one of the foregoing. In other embodiments, the intermediate material 107 may comprise a metal. In still other embodiments, the intermediate material 107 may comprise a multi-layer structure comprising two or more of these materials.

As a non-limiting example, prior to bonding the material layer 104 over the recoverable substrate 102, as described in U.S. Patent Publication No. 2004/0222500, the material layer 104 and the recoverable substrate ( The mechanical strength of the detachable interface 106 may be adjusted by adjusting at least one of roughness and hydrophilicity of the facing surfaces of 102 ). For example, if one or both of the opposing faces comprise, for example, SiO ₂ , the SiO ₂ surface can be etched using hydrofluoric acid to control the surface roughness. Other chemical treatments may be used depending on the nature of the material to be etched. For example, phosphoric acid (H ₃ PO ₄ ) can be used to etch and roughen silicon nitride (Si ₃ N ₄ ), ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H). A solution of ₂ O ₂ ) and water can be used to etch and roughen the silicon. In additional techniques, optionally controlled heat treatments can be used to control the mechanical strength of the molecular bond between the material layer 104 and the recoverable substrate 102.

Thus, in one embodiment, voids 108 may be present in the detachable interface 106. Voids 108 may be due to the roughness of the initial surface between adjacent bonded surfaces and may be randomly located across the detachable interface 106. In other embodiments, voids 108 may be formed in one or both of adjacent bonded surfaces prior to the bonding step, and may be located at predetermined and selected locations across the removable interface 106. I can. The number and size of voids 108 can be used to selectively control the mechanical strength of the bond between material layer 104 and recoverable substrate 102.

In embodiments in which the material layer 104 comprises a semiconductor material and the detachable interface 106 comprises an intermediate material 107 comprising an electrically insulating material, the structure 100 of FIG. 1 ) Is a "semiconductor-on-insulator" in the industry, such as a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. , SeOI)" type substrate may be included. In these embodiments, the recoverable substrate 102 forms the base of the SeOI-type substrate, and the intermediate material 107 forms the material layer 104 and an insulating layer between the base.

In one embodiment, the recoverable substrate 102 may be selected to include a material exhibiting a coefficient of thermal expansion that is closely matched with the coefficient of thermal expansion exhibited by the material layer 104. have. For example, the recovery substrate 102 may exhibit a coefficient of thermal expansion that is within about 10% from the coefficient of thermal expansion exhibited by the material layer 104, and within about 5% from the coefficient of thermal expansion exhibited by the material layer 104, Alternatively, it may represent up to about 2.5% from the coefficient of thermal expansion indicated by the material layer 104. Closely matching the coefficients of thermal expansion of the recoverable substrate 102 and the material layer 104 is due to thermal stresses close to the detachable interface 106 as the temperature of the structure 100 changes in a subsequent process. stresses) can be reduced or minimized, and inadvertent premature separation of the material layer 104 from the resilient substrate 102 can be prevented.

The recoverable substrate 102 may be thicker than the material layer 104. As non-limiting examples, the material layer 104 may be about 200 micrometers (200 μm) or less, about 50 μm (50 μm) or less, about 1 micrometer (1 μm) or less, or about 100 nanometers (100 nm). It may have the following average layer thickness (T). In some embodiments, the average layer thickness T may be between about 15 nanometers (15 nm) and about 100 micrometers (100 μm). The recoverable substrate 102 may have an average layer thickness of about 200 micrometers (200 μm) or more, about 500 μm (500 μm) or more, or about 700 micrometers (700 μm) or more. In embodiments where the detachable interface 106 includes an intermediate material 107, the intermediate material 107 may be thinner than the material layer 104, for example, about 100 nanometers (100 nm). Hereinafter, it may have an average layer thickness of about 50 nanometers (50 nm) or less, or about 25 nanometers (25 nm) or less.

The material layer 104 having such a thin layer thickness T may be provided on top of the resilient substrate 102 using, for example, what is called a trademark SMART-CUT® process in the industry. The registered trademark smart cut process is, for example, U.S. Patent No. RE39,484 (issued February 6, 2007) to Bruel, U.S. Patent No. 6,303,468 (October 16, 2001) awarded to Aspar et al. Publication), U.S. Patent No. 6,335,258 awarded to Aspar et al. (issued on January 1, 2002), U.S. Patent No. 6,756,286 awarded to Moriceau et al. (issued on June 29, 2004), Aspar et al U.S. Patent No. 6,809,044 (issued Oct. 26, 2004) issued to. And U.S. Patent No. 6,946,365 (issued Sep. 20, 2005) to Aspar et al.

In short, the trademark smart cut process involves implanting ions into a relatively thick layer of material to form a generally planar weakened ion implant plane within this layer of material. Include. A relatively thick material layer may be bonded on top of the recoverable substrate 102. The relatively thick material layer is then fractured along the embrittled ion implantation surface, leaving a material layer 104 having the desired average layer thickness T bonded on top of the resilient substrate 102. Optionally, in order to provide the material layer 104 having the required average layer thickness (T), an additional semiconductor material (with a polycrystalline or amorphous microstructure) is selectively selected after the trademark smart cut process. It may be deposited over the transferred material layer 104.

In additional embodiments, a relatively thick material layer is first bonded to the top of the recovery substrate 102, and subsequently one or more of a grinding process, a polishing process, and an etching process is performed. This thin average layer thickness (T) by thinning the material layer to an average layer thickness (T) using (e.g., using a chemical-mechanical polishing (CMP) process) A material layer 104 having a may be provided on the recoverable substrate 102. Such bonding and flaking processes may be desirable to provide a layer of material 104 having an average layer thickness (T) of at least about 150 micrometers (150 μm), while the trademark smartcut process may be about 1.5 micrometers ( It may be desirable to provide a material layer 104 having an average layer thickness (T) of 1.5 μm) or less.

Referring to FIG. 2, the material layer 104 is formed on the recoverable substrate 102 and the conductive vias 110 are formed to penetrate the material layer 104 to form the structure 112 of FIG. 2. have. The conductive vias 110 may be formed using techniques known in the art.

For example, a patterned mask may be provided on the exposed main surface 114 of the material layer 104. At locations where the conductive vias 110 are to be formed in the material layer 104, apertures may extend through the patterned mask layer. Holes through and into the material layer 104 through the apertures extending through the mask layer by an anisotropic etching process such as a dry reactive ion etching (RIE) process It can be used to etch holes, the mask layer shielding other parts of the material layer 104 from the etchant and preventing removal of these parts.

After formation of the holes through the material layer 104, a dielectric material (e.g. oxide) may be deposited into the holes 104 to provide isolation, after which the holes ( 104 may be filled with a conductive material such as a metal to form conductive vias 110 in the holes. For example, the metal may include one or more of copper, aluminum, silver, tungsten, titanium, nickel, and the like. In some embodiments, the conductive vias 110 may include a plurality of metal layers having two or more different compositions. The metal may be deposited in the holes using one or more plating processes. For example, a first electroless plating process may be used to deposit a relatively thin metal seed layer on the surfaces of the material layer 104 in the holes. These processes can provide a relatively dense and thin metal layer with good step coverage, thus allowing at least a substantially continuous metal layer to be deposited on all surfaces inside the holes. After depositing such a seed layer, another plating process, such as an electroplating process, is used to deposit an additional metal on the seed layer at a relatively high rate until the holes are at least substantially filled with the metal. Vias 110 may be formed. Other deposition processes such as physical vapor deposition (PVD) processes and/or chemical vapor deposition (CVD) processes may be used to deposit a conductive material inside the holes in additional embodiments. have.

As shown in FIG. 2, the conductive vias 110 may extend through the material layer 104 entirely from the exposed main surface 114 to the detachable interface 106. Accordingly, in embodiments in which the material layer 104 includes silicon, the conductive vias 110 are through-wafer vias (TWVs) or through-silicon vias (TSVs) in the industry. It may include what is collectively referred to as.

The conductive vias 110 may be formed to have aspect ratios of about 2.5 or less, or, in some embodiments, up to about 1.6 or less. By forming the conductive vias 110 to have relatively low aspect ratios, problems associated with formation of conductive vias having high aspect ratios previously discussed herein can be alleviated.

In addition, embodiments of the methods as described herein do not include any significant flaking of the material layer 104 on which the conductive vias 110 are formed after formation of the conductive vias 110 in the material layer 104. May not.

Referring to FIG. 3, after formation of the conductive vias 110, a selective redistribution layer 118 is formed on the material layer 104 opposite the recovery substrate 102, and the structure 120 of FIG. 3 Can be formed. The locations and patterns of the conductive vias 110 may not be complementary to electrical contact features of another structure or device to be coupled thereto. Thus, redistribution layer 118 can be used to redistribute electrical contact patterns. The redistribution layer 118 may include one or more of vertically extending conductive vias 122, laterally extending conductive traces 124, and conductive contact pads 126. Conductive vias 122 and traces 124 will be used to redistribute the pattern of conductive vias 110 of material layer 104 from material layer 104 to another pattern on the opposite phase of redistribution layer 118. I can. The redistribution layer 118 may be formed in a layer-by-layer lithography process using techniques known in the art.

As shown in FIG. 4, the carrier substrate 130 may be temporarily bonded on the material layer 104 opposite the recovery substrate 102 to form the structure 132 of FIG. 4. Carrier substrate 130 may be generally flat and may include any of a plurality of materials. For example, the carrier substrate 130 may include any of the materials described above in connection with the resilient substrate 102. The carrier substrate 130 may have an average layer thickness sufficient to allow handling and manipulation of the structure 132 by a semiconductor manufacturing facility during subsequent processing. For example, the carrier substrate 130 may have an average layer thickness of about 200 micrometers (200 μm) or more, about 500 μm (500 μm) or more, or up to about 700 μm (700 μm) or more. The carrier substrate 130 may be bonded to the top of the material layer 104 using a direct molecular bonding process, or by using an adhesive or other bonding material between the surfaces to which the carrier substrate 130 is to be bonded. Can be bonded on top of layer 104

In embodiments in which the redistribution layer 118 is formed on the material layer 104 opposite the recovery substrate 102, the carrier substrate 130 is bonded to the redistribution layer 118 on the material layer 104. I can. In embodiments in which the redistribution layer 118 is not formed, the carrier substrate 130 may be bonded to the material layer 104.

Referring to FIG. 5, after bonding the carrier substrate 130 on the material layer 104 (as described with reference to FIG. 4), the recovery substrate 102 is It can be separated from 104 to recover the recoverable substrate 102 and to form the structure 138 disclosed in FIG. 5. In particular, the recoverable substrate 102 may be separated from the material layer 104 along the detachable interface 106. If desired, the resilient substrate 102 can then be reused. In other words, the recoverable substrate 102 may be recyclable. Recycling of the recoverable substrate 102 can reduce waste and manufacturing costs.

The resilient substrate 102 may be formed by using the equipment and methods described in US Patent Application Publication No. 2007/0122926 published May-31, 2007 by Martinez et al. ) Can be separated from. As described herein, a fixed positioning member may be employed to stabilize the structure 132 of FIG. 4, and cleaving propagate across the detachable interface 106 A cutting mechanism including a blade may be used to connect the structure 132 in a way to induce a cleaving wave. In one embodiment, a notch may be formed on the side surface of the structure 132 of FIG. 4, and the blade of the cutting mechanism is inserted into the notch with force to allow the recovery substrate 102 and The cleaving wave may be induced along the detachable interface 106 between the material layers 104.

As shown in FIG. 5, after separating the recoverable substrate 102 from the material layer 104, the crack surface 140 of the structure 138 may be relatively rough, and in one embodiment remains Intermediate material 107 may be included. Thus, the uniform surface 140 can be cleaned and/or smoothed as desired. For example, one or more of an etching process, a grinding process, and a polishing process (eg, a chemical mechanical polishing (CMP) process) may be used to smooth the crack surface 140. After smoothing the crack surface 140, a standard cleaning process can be used to remove unwanted material remaining thereon.

As shown in FIG. 6, an optional redistribution layer 144 may be formed on the material layer 104 opposite the carrier substrate 130 to form the structure 146 of FIG. 6. As described above, the locations and patterns of conductive vias 110 may not be complementary to electrical contact features of other structures or devices to be coupled thereto. Thus, like redistribution layer 118, redistribution layer 144 can be used to redistribute electrical contact patterns. The redistribution layer 144 may include one or more of vertically extending conductive vias 150, laterally extending conductive traces 152, and conductive contact pads 154. The conductive vias 150 and traces 152 are used to redistribute the pattern of the conductive vias 110 of the material layer 104 from the material layer 104 to another pattern on the opposite side of the redistribution layer 144. Can be used. The redistribution layer 144 may be formed in a layer-by-layer lithography process using techniques known in the art.

Referring to FIG. 7, electrical contacts 160 may be formed on the material layer 104 opposite the carrier substrate 130 to form the structure 162 of FIG. 7. The electrical contacts 160 are in electrical communication with the conductive vias 110. In embodiments where structure 162 includes an optional redistribution layer 144, electrical contacts 160 are conductive vias 150, traces 152 and pads 154 of redistribution layer 144. ) In electrical communication with the conductive vias 110. In embodiments that do not include the optional redistribution layer 144, electrical contacts 160 may be formed directly on the conductive vias 110 to establish direct electrical communication with the conductive vias 110. have.

Various types of electrical contacts 160 are known in the art and may be employed within embodiments of the present invention. As a non-limiting example, the electrical contacts 160 may include conductive bumps formed on the material layer 104. As is well known, a dielectric material 164 may be provided over the material layer 104 and an aperture may be formed to penetrate the dielectric material 164 at locations desired to form the conductive bumps. Thereafter, so-called “under-bump metallurgy (UBM)” processes may be used to deposit one or more layers of conductive metal 166 within the apertures. The conductive bumps may then be formed on the conductive metal 166 deposited inside the apertures extending through the dielectric material 164.

Thus, as described above, an interposer including a material layer 104 having conductive vias 110 (eg, through wafer vias TWVs) extending through the material layer 104 ( 170) is formed. The interposer 170 may also include an optional redistribution layer 118 on the first side of the material layer 104, and/or an optional redistribution layer 118 on the opposite second side of the material layer 104. I can. In the state of FIG. 7 in which the interposer 170 remains temporarily bonded to the carrier substrate 130, the interposer 170 includes electrical contacts 160 on the material layer 104 opposite the carrier substrate 130. ) Can be included. As will be described further below, additional electrical contacts are subsequently formed on the interposer 170 on the opposite side of the material layer 104 after the carrier substrate 130 is removed from the interposer 170. I can.

Referring to FIG. 8, prior to removing the carrier substrate 130 from the material layer 104, the conductive features 171 of the first structure or device, such as the integrated circuit device 172, are formed of the interposer 170. The electrical contacts 160 may be structurally and electrically coupled to form the structure 174 of FIG. 8. The integrated circuit device 172 may be selected to include one or more of an electronic signal processing device, a memory device, and a photoactive device (eg, a light-emitting device (LED), a laser diode, a photovoltaic cell, a photodetector, etc.). .

As shown in FIG. 9, the carrier substrate 130 may then be separated from the material layer 104 to form the structure 176, which includes an interposer 170 and an integrated circuit device 172. After removing the carrier substrate 130, the structure 176 of FIG. 9 is structurally and electrically coupled to the conductive features 180 of another structure or device 182 to form the structure 184 of FIG. 10. can do. Other structures or devices 182 may include, for example, other integrated circuit devices such as any of the foregoing, printed circuit boards, and the like. Thus, an electrical connection can be established between the conductive vias 110 of the material layer 104 of the interposer 170 and the conductive features 180 of the structure or device 182. In addition, the electrical connection between the integrated circuit element 172 and the structure or element 182 is the conductivity of the material layer 104 of the interposer 170 interposed between the integrated circuit element 172 and the structure or element 182. It may be established through vias 110.

Various techniques known in the art can be used to structurally and electrically couple the structure 176 of FIG. 9 to the conductive features 180 of the structure or device 182. As a non-limiting example, conductive bumps 186 are on conductive features 180, or such as exposed ends of conductive vias 110 (if the interposer is optional redistribution layer 144) may be formed on the complementary conductive features of the interposer 170, or on the conductive pads 154 of the optional redistribution layer 144. As a non-limiting example, conductive bumps 186 may be formed over material layer 104 using techniques such as those described above in connection with electrical contacts 160. In further embodiments, conductive bumps may be formed on conductive features 180 of structure or device 182.

Although interposers 170 may be intended to be used with a number of different structures and devices having varying connection feature patterns, multiple interposers 170 are common using the techniques described herein. It may be manufactured to have conductive vias 110 manufactured in a comprehensive and comprehensive pattern. Redistribution layers 118, 144 may be constructed and fabricated differently for different subsets of interposers 170 to customize different subsets for use with different structures and devices. I can.

Additional and non-limiting embodiments of the invention are described below:

Example 1: A method of manufacturing a semiconductor device including an interposer, comprising: forming conductive vias penetrating a material layer on a recoverable substrate; Bonding a carrier substrate to an upper portion of the material layer opposite the recoverable substrate; Separating the recoverable substrate from the material layer to recover the recoverable substrate; And forming electrical contacts in electrical communication with the conductive vias on the material layer opposite the carrier substrate.

Example 2: The method according to Example 1, further comprising selecting the material layer to have an average layer thickness of about 100 micrometers (100 μm) or less.

Example 3: The method according to Example 2, further comprising selecting the material layer to have an average layer thickness between about 15 nanometers (15 nm) and about 100 micrometers (100 μm).

*Example 4: A method according to any one of Examples 1 to 3, further comprising selecting the material layer to include a semiconductor material.

Example 5: The method according to Example 4, further comprising selecting the material layer to include at least one of silicon, germanium and III-V semiconductor materials.

Example 6: The method according to Example 5, further comprising selecting the material layer to contain silicon.

Example 7: The method according to any one of Examples 1 to 6, wherein the forming of conductive vias penetrating the material layer on the recovery substrate comprises: a semiconductor material layer having a semiconductor-on-insulator (SeOI) structure. Forming the conductive vias therethrough, wherein the SeOI structure includes a base including the recoverable substrate and an insulating layer between the base and the semiconductor material layer.

Example 8: The method according to Example 7, wherein the base includes a material exhibiting a coefficient of thermal expansion closely matched with the coefficient of thermal expansion exhibited by the layer of semiconductor material.

Example 9: The method according to Example 7 or 8, wherein separating the recoverable substrate from the material layer to recover the recoverable substrate comprises: the semiconductor material layer from the base along the insulating layer It includes the step of separating.

Example 10: The method according to any of Examples 1 to 9, further comprising forming the conductive vias to have an aspect ratio of about 2.5 or less.

Example 11: A method according to Example 10, further comprising forming the conductive vias to have an aspect ratio of about 1.6 or less.

Example 12: The method according to any one of Examples 1 to 11, wherein prior to the step of separating the recoverable substrate from the material layer to recover the recoverable substrate, between the recoverable substrate and the material layer And forming a detachable interface, wherein the detachable interface includes bonding of controlled mechanical strength between the material layer and the recoverable substrate.

Example 13: The method according to any one of Examples 1 to 12, wherein prior to bonding the carrier substrate on the material layer opposite the recovery substrate, redistribution on the material layer opposite the recovery substrate It further includes forming a layer.

Embodiment 14: The method according to Embodiment 13, further comprising forming another redistribution layer on the material layer on the opposite side of the carrier substrate, prior to forming electrical contacts on the material layer on the opposite side of the carrier substrate. And the electrical contacts are in electrical communication with the conductive vias through the other redistribution layer.

Embodiment 15: The method according to any one of Embodiments 1 to 12, wherein before forming electrical contacts on the material layer opposite the carrier substrate, another redistribution layer is formed on the material layer opposite the carrier substrate. And forming the electrical contacts in electrical communication with the conductive vias through the other redistribution layer.

Embodiment 16: The method according to any one of Embodiments 1 to 15, wherein forming electrical contacts on the material layer opposite the carrier substrate includes forming conductive bumps on the material layer.

Embodiment 17: A method according to any of Embodiments 1 to 16, further comprising structurally and electrically coupling conductive features of an integrated circuit device to the electrical contacts.

Embodiment 18: The method according to embodiment 17, further comprising selecting the integrated circuit device to include at least one of an electronic signal processing device, a memory device, and a photoactive device.

Embodiment 19: The method according to Embodiment 17 or Embodiment 18, further comprising: establishing electrical contact between the conductive vias and conductive features of the structure or device on the material layer opposite to the integrated circuit device. The material layer and the conductive vias are interposed between the integrated circuit device and another structure or device.

Example 20: The method according to any one of Examples 1 to 19, further comprising separating the carrier substrate from the material layer.

Example 21: As an intermediate structure formed in the process of manufacturing a semiconductor device, the intermediate structure is: a semiconductor layer adhered on a recovery substrate, a detachable interface of controlled mechanical strength between the semiconductor layer and the recovery substrate The semiconductor layer having a; Conductive vias extending through the semiconductor layer; And a carrier substrate bonded to an upper portion of the semiconductor layer opposite the recovery substrate.

Example 22: The intermediate structure according to Example 21, wherein the semiconductor layer has an average layer thickness of between about 15 nanometers (15 nm) and about 100 micrometers (100 μm).

Example 23: The intermediate structure according to Example 21 or 22, wherein the semiconductor layer comprises silicon.

Example 24: The intermediate structure according to any one of Examples 21 to 23, wherein the conductive vias have aspect ratios of about 2.5 or less.

Example 25: The intermediate structure according to any one of Examples 21 to 24, further comprising a redistribution layer on the semiconductor layer between the carrier substrate and the semiconductor layer.

Example 26: A method of manufacturing a semiconductor device including an interposer, wherein a detachable interface comprising a controlled level of mechanical strength between the semiconductor layer and the recoverable substrate is formed between the semiconductor layer and the recoverable substrate. step; Forming conductive vias passing through the semiconductor layer on the recoverable substrate; Bonding a carrier substrate to an upper portion of the semiconductor layer opposite the recoverable substrate; Separating the recoverable substrate from the semiconductor layer to recover the recoverable substrate; And forming electrical contacts in electrical communication with the conductive vias on the semiconductor layer opposite the carrier substrate.

Example 27: The method according to Example 26, further comprising selecting the semiconductor layer to have an average layer thickness between about 15 nanometers (15 nm) and about 100 micrometers (100 μm).

Example 28: The method according to Example 26 or 27, further comprising selecting the semiconductor layer to include silicon.

Example 29: A method according to any of Examples 26 to 28, further comprising forming the conductive vias to have an aspect ratio of about 2.5 or less.

Example 30: The method according to Example 29, further comprising forming the conductive vias to have an aspect ratio of about 1.6 or less.

Example 31: The method according to any one of Examples 26 to 30, wherein prior to bonding the carrier substrate to an upper portion of the semiconductor layer opposite the recoverable substrate, redistribution to the upper portion of the semiconductor layer opposite the recoverable substrate It further includes forming a layer.

Example 32: The method according to any one of Examples 26 to 31, wherein before forming electrical contacts on the semiconductor layer opposite the carrier substrate, forming a redistribution layer on the semiconductor layer opposite the carrier substrate And the electrical contacts are in electrical communication with the conductive vias through the redistribution layer.

Embodiment 33: A method according to any of Embodiments 26 to 32, comprising structurally and electrically coupling conductive features of an integrated circuit device to the electrical contacts; And separating the carrier substrate from the semiconductor layer.

Embodiment 34: The method according to embodiment 33, further comprising selecting the integrated circuit device to include at least one of an electronic signal processing device, a memory device, and a photoactive device.

Embodiment 35: The method according to Embodiment 33 or Embodiment 34, further comprising: establishing electrical connection between the conductive vias and conductive features of the structure or device on the semiconductor layer opposite the integrated circuit device. The semiconductor layer and the conductive vias are interposed between the integrated circuit device and another structure or device.

The above-described exemplary embodiments of the present invention do not limit the scope of the present invention, since these embodiments are merely examples of embodiments of the present invention, but rather by the appended claims and the scope of their legal equivalents. Limited. Any equivalent embodiments are intended to be within the scope of the present invention. Indeed, various improvements of the embodiments as well as those shown and described herein, such as alternative useful combinations of components described herein, will now become apparent to those skilled in the art from this detailed description. In other words, one or more features of one example embodiment described herein may be combined with one or more features of other example embodiments described herein to provide additional embodiments of the present disclosure. These improvements and embodiments are also intended to fall within the scope of the appended claims.

102: recovery substrate 104: material layer
106: detachable interface 108: voids
110, 150: conductive vias 114: main surface
118, 144: redistribution layer 122: conductive vias
124, 152: conductive traces 126, 154: conductive contact pads
130: carrier substrate 160: electrical contacts
164: genetic material 170: interposer
171, 180: conductive features 172: integrated circuit device
182: structure or device 186: conductive bumps

Claims (15)

As a method for manufacturing a semiconductor device including an interposer,
Providing a semiconductor-on-insulator (SeOI) structure, wherein the SeOI structure comprises a base recoverable substrate, a material layer, and between the base recoverable substrate and the material layer. Providing a SeOI structure comprising an insulating layer, the material layer comprising a semiconductor material;
Forming a detachable interface between the base recoverable substrate and the material layer, wherein the detachable interface includes the insulating layer, and the detachable interface includes the base recoverable substrate and the material layer Forming a detachable interface comprising a bond of controlled mechanical strength therebetween;
Forming conductive vias passing through the material layer;
Bonding a carrier substrate on the material layer opposite the base recovery substrate;
Separating the base recoverable substrate from the material layer to recover the base recoverable substrate; And
Forming electrical contacts on the material layer opposite the carrier substrate in electrical communication with the conductive vias. The method of claim 1,
The method further comprising selecting the material layer to have an average layer thickness of 100 micrometers or less. The method of claim 1,
The method further comprising selecting the semiconductor material to include at least one of silicon, germanium, and III-V semiconductor material. The method of claim 3,
The method further comprising selecting the semiconductor material to include silicon. The method of claim 1,
A method, characterized in that voids are present at the detachable interface. The method of claim 1,
The method of claim 1, wherein the base recovery substrate comprises a material exhibiting a coefficient of thermal expansion in the range of 90% to 110% of the coefficient of thermal expansion exhibited by the material layer. The method of claim 1,
Separating the base recovery substrate from the material layer to recover the base recovery substrate,
And separating the material layer along the insulating layer from the base resilient substrate. The method of claim 1,
The method further comprising forming the conductive vias to have aspect ratios of 2.5 or less. The method of claim 1,
Before the step of bonding a carrier substrate on the material layer opposite the base recovery substrate,
And forming a redistribution layer on the material layer opposite the base resilient substrate. The method of claim 9,
Before the step of forming electrical contacts on the material layer opposite the carrier substrate,
Further comprising the step of forming another redistribution layer on the material layer opposite the carrier substrate,
Wherein the electrical contacts are in electrical communication with the conductive vias through the other redistribution layer. The method of claim 1,
Before the step of forming electrical contacts on the material layer opposite the carrier substrate,
Further comprising the step of forming a redistribution layer on the material layer opposite the carrier substrate,
The electrical contacts are in electrical communication with the conductive vias through the redistribution layer. The method of claim 1,
Forming electrical contacts on the material layer opposite the carrier substrate,
And forming conductive bumps on the material layer. The method of claim 1,
Structurally and electrically coupling conductive features of an integrated circuit device to the electrical contacts, and at least one of an electronic signal processor, a memory device, and a photoactive device And selecting the integrated circuit device to include one. The method of claim 13,
And separating the carrier substrate from the material layer. The method of claim 14,
Further comprising the step of establishing electrical connection between the conductive vias and conductive features of another structure or device on the material layer opposite the integrated circuit device,
Wherein the layer of material and the conductive vias are interposed between the integrated circuit device and the other structure or device.

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