KR102298315B1 - Display Device - Google Patents

Abstract

The liquid crystal display device of the present invention generates a common voltage based on a liquid crystal panel in which a gate line, a dummy data line and a data line are formed, a timing controller for outputting common voltage data, and the common voltage data, and provides it to the dummy data line and provides image data It includes a data driver for providing a data voltage to the data line based on the , and a common line formed in a horizontal line direction to provide a common voltage received through the dummy data line to each pixel formed on the horizontal line.

Description

Liquid crystal display device {Display Device}

The present invention relates to a liquid crystal display device.

An active matrix driving type liquid crystal display uses a thin film transistor (hereinafter referred to as "TFT") as a switching element to display a moving picture. This liquid crystal display device can be miniaturized compared to a cathode ray tube (CRT), so it is not only applied to display devices in portable information devices, office devices, computers, etc.

Pixels of the liquid crystal display device include a thin film transistor connected to a data line and a gate line crossing each other, and connected to the crossing part. The thin film transistor supplies a data voltage supplied through the data line to the pixel electrode of the liquid crystal cell in response to a gate pulse from the gate line. The liquid crystal cell is rotated by an electric field generated according to a voltage difference between the voltage of the pixel electrode and the common voltage Vcom applied to the common electrode to adjust the amount of light passing through the polarizing plate. That is, the liquid crystal display device maintains a constant potential of the common voltage Vcom and expresses a desired gradation while varying the data voltage. However, as time passes, the potential of the common voltage v is shifted, and when the common voltage Vcom is shifted, the desired image quality cannot be properly expressed.

In order to improve the shift phenomenon of the common voltage Vcom, a common voltage feedback (Vcom Feedback) compensation circuit is generally used. The common voltage feedback compensation circuit includes an operational amplifier (OP-Amp) that receives a feedback of the common voltage supplied to the panel and outputs the compensated common voltage by inputting the feedback voltage and the reference common voltage as inputs. However, this method of using the common voltage feedback compensation circuit not only requires an additional circuit, but also has disadvantages in that it does not reflect the difference in delay (RC delay) according to the position of each common electrode in the panel. In particular, in order to reduce the bezel, since the width of the common electrode is reduced, the resistance of the common electrode is increased, and accordingly, the RC delay difference is further increased, so the efficiency of the conventional common voltage compensation method is decreasing.

An object of the present invention is to provide a liquid crystal display capable of efficiently compensating for a common voltage.

The liquid crystal display device of the present invention generates a common voltage based on a liquid crystal panel in which a gate line, a dummy data line and a data line are formed, a timing controller for outputting common voltage data, and the common voltage data to provide it to the dummy data line and provide image data. It includes a data driver for providing a data voltage to the data line based on , and a common line formed in a horizontal line direction to provide a common voltage received through the dummy data line to each pixel formed on the horizontal line.

In the present invention, a circuit for generating and compensating for a common voltage can be omitted, and since the common voltage is supplied through the dummy data line, the common line or common electrode passing through the bezel in the liquid crystal panel can be omitted, and thus the bezel can be removed. can be made narrower.

In addition, since the present invention provides a common voltage for each horizontal line in response to a gate pulse, problems such as horizontal crosstalk caused by the delay of the common electrode can be improved.

In addition, since the present invention compensates for the common voltage provided to each horizontal line based on image data, it is possible to provide a common voltage capable of preventing ripple from occurring in advance.

1 is a view showing the configuration of a liquid crystal display device according to the present invention.
2 is a diagram showing the configuration of a data driver according to the present invention.
3 is a view showing a pixel array area according to the first embodiment;
4 is a view showing a planar structure of a pixel and a holding capacitor according to the first embodiment;
5 is a diagram illustrating output timing of a gate pulse and a common voltage according to the first embodiment;
6 is an equivalent circuit diagram of the pixel and the holding capacitor shown in FIG. 4;
7 is a view showing a cross-section taken along the cutting line I-I' shown in FIG.
8 is a diagram illustrating a procedure for compensating common voltage data according to the present invention.
9 is a diagram illustrating a principle in which common voltage data is compensated.
10 is a diagram illustrating a pixel array area according to a second embodiment;
11 is a diagram illustrating a planar structure of a pixel and a holding capacitor according to a second embodiment;
12 is a diagram illustrating output timing of a gate pulse and a common voltage according to the second embodiment;
13 is a view showing a pixel array area according to a third embodiment;

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

1 is a view showing a liquid crystal display device according to the present invention.

Referring to FIG. 1 , the liquid crystal display of the present invention includes a liquid crystal panel 100 , a timing controller 210 , a power module 220 , a gate driver 230 , and a data driver 240 .

The liquid crystal panel 100 includes a thin film transistor array substrate on which a thin film transistor array is formed and a color filter substrate on which a color filter is formed, and a liquid crystal layer is formed between the thin film transistor array substrate and the color filter substrate. In addition, in the liquid crystal panel 100 , a region in which the pixels P are arranged on the thin film transistor array substrate is defined as a pixel array region 100A.

A pixel array is formed on the lower glass substrate of the liquid crystal display panel 100 . The pixel array includes liquid crystal cells Clc formed at intersections of data lines DL and gate lines GL, first transistors T1 connected to the pixel electrode 1 of the liquid crystal cells, and a pixel electrode ( 17) and a common electrode 15 and a storage capacitor Cst opposite to each other. The liquid crystal cells Clc are connected to the TFT and are driven by an electric field between the pixel electrodes 17 and the common electrode 15 . A dummy data line DDL is formed outside the pixel array region 100A, and the dummy data line DDL receives a common voltage Vcom from the data driver 240 .

The timing controller 210 receives digital video data (RGB) from an external host (not shown), a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), and a main clock A timing signal such as (CLK) is received. The timing controller 210 transmits digital video data RGB to the source drive ICs 240 . The timing controller 210 includes a source timing control signal for controlling the operation timing of the data driver 240 using the timing signals Vsync, Hsync, DE, and CLK, and a source timing control signal for controlling the operation timing of the gate driver 230 . Generates a gate timing control signal.

Also, the timing controller 210 generates common voltage data VCDATA. The common voltage data VCDATA is output as a common voltage Vcom through the data driver 240 .

The power module 220 receives the power supply voltage VCC and outputs a gate high voltage VGH, a gate low voltage VGL, a high potential voltage VDD, and the like. The gate high voltage VGH is a high level voltage of the scan pulse supplied to the gate line GL, and the gate low voltage VGL is a low level voltage of the scan pulse supplied to the gate line GL.

The GIP-type gate driver 230 includes a level shifter 231 and a shift register 233 mounted on the PCB 200 .

The level shifter 231 receives driving voltages such as the gate high voltage VGH and the gate low voltage VGL, and receives the start signal ST and the gate clock signal GCLK from the timing controller 210, A start pulse VST and a clock signal CLK swinging between the voltage VGH and the gate low voltage VGL are output. The clock signals CLK output from the level shifter 26 are sequentially shifted in phase and transmitted to the shift register 233 formed in the display panel 100 .

The shift register 233 is connected to the gate line GL of the display panel 100 . The shift register 233 includes a plurality of cascadingly connected stages. The shift register 233 shifts the start pulse VST input from the level shifter 231 according to the clock signal CLK and sequentially supplies the gate pulses to the gate lines GL.

The data driver 240 receives digital video data RGB and common voltage data VCDATA from the timing controller 210 . The data driver 240 converts digital video data RGB into positive/negative analog data voltages in response to a source timing control signal from the timing controller 210 , and then synchronizes the data voltages with the gate pulses on the display panel It is supplied to the data lines DL1 to DLn of (100). The data driver 240 converts the common voltage data VCDATA into the common voltage Vcom, and then supplies the common voltage Vcom to the dummy data line DDL.

To this end, as shown in FIG. 2 , the data driving unit 240 includes a register unit 241 , a first latch 243 , a second latch 245 , and a digital-to-analog converter (DAC). 247 and an output unit 249 . The register unit 241 samples the RGB digital video data bits of the input image using the data control signals SSC and SSP provided from the timing controller 210 , and provides them to the first latch 243 . Also, the register unit 241 provides the common voltage data VCDATA received from the timing controller 210 to the first latch 243 . The first latch 243 samples and latches common voltage data VCDATA and digital video data bits according to a clock sequentially provided from the register unit 241, and latches the latched common voltage data VCDATA and data DATA. outputs at the same time. The second latch 235 latches the common voltage data VCDATA and the data provided from the first latch 243 , and simultaneously outputs the latched data in response to the source output enable signal SOE. The DAC 247 converts the common voltage data VCDATA and video data input from the second latch unit 245 into a gamma compensation voltage GMA to generate a common voltage Vcom and a data voltage ADATA. The output unit 249 provides the common voltage Vcom output from the DAC 247 to the dummy data line DDL during the low logic period of the source output enable signal SOE, and applies the data voltage ADATA to the data It is provided to the lines DL1 to DLn.

3 is a diagram illustrating a pixel array substrate of the liquid crystal panel 100 according to the first embodiment, and FIG. 4 is a diagram illustrating the structure of a pixel P and a holding capacitor Cgc.

3 and 4 , the thin film transistor array substrate of the liquid crystal panel 100 according to the first embodiment has pixels defined by gate lines GL1 to GLm and data lines DL1 to DLn arranged vertically and horizontally. (P) are arranged in a matrix form. A dummy data line DDL and a holding capacitor Cgc formed in parallel with the first data line DL1 are formed at a position outside the pixel array region 100A.

Each of the gate lines GL1 to GLm receives a gate pulse from the gate driver 230 and supplies it to the first and second gate electrodes 41 and 42 . The ith gate line GLi is formed under the pixels P arranged on the ith horizontal line HLi.

In one horizontal line, n pixels P are formed, and each pixel P receives a data voltage ADATA through data lines DL1 to DLn connected one-to-one. A first transistor T1 is formed in a region where the data line DL and the gate line GL intersect. The first transistor T1 is disposed adjacent to the first gate electrode 41 branched from the gate line GL, the first drain electrode 21 branched from the data line DL, and the first drain electrode 21 . The first source electrode 31 is formed. The first transistor T1 supplies the data voltage ADATA received from the data line DL to the first source electrode 31 in response to a gate pulse input through the gate line GL.

Each common line VCL receives the common voltage Vcom from the dummy data line DDL and supplies it to the common electrodes 17 . The ith (i is a natural number less than or equal to m) common line VCLi is formed above the pixels P arranged on the ith horizontal line HLi.

The holding capacitors Cgc1 to Cgcm include the metal pattern 50 and the source pattern 32, are charged by receiving the common voltage Vcom through the dummy data line DDL, and are charged with the charged common voltage Vcom. is maintained for 1 frame. The ith holding capacitor Cgc is formed on the ith horizontal line HLi at a position outside the pixel array region 100A. Each of the holding capacitors Cgc receives a common voltage from the dummy data line DDL through the second transistor T2 in response to the gate pulse.

The second transistor T2 has a second gate electrode 42 branched from the gate line GL, a second drain electrode 22 protruding from the dummy data line DDL, and adjacent to the second drain electrode 22 . It includes a source pattern (32). The second transistor T2 has a second gate electrode width GW, a second drain electrode width DW, and a source pattern width VW so that the common voltage Vcom can be supplied smoothly. Set it as large as possible within the range. Since the second gate electrode 42 formed on the ith horizontal line HLi should not contact the ith common line VCL, the width of the second gate electrode GW is less than the pixel width d. In consideration of the process margin, it may be formed with the maximum width.

FIG. 5 is a diagram illustrating timing for switching the common voltage Vcom using a gate pulse, and FIG. 6 illustrates an equivalent circuit of the pixel and the holding capacitor Cgc shown in FIG. 4 according to charging of the common voltage.

5 and 6 , when the ith gate pulse Gi is supplied to the ith gate line GLi during the ith horizontal period iH, it is formed on the ith horizontal line HLi. The first and second transistors T1 and T2 are turned on. While the first transistor T1 is turned on, the data voltage ADATA provided through the data lines DL1 to DLn is charged to the pixels P. And while the second transistor T2 is turned on, the i-th common voltage Vcomi provided through the dummy data line DDL is provided to the i-th common line VCLi through the source pattern 32 . Since the source pattern 32 forms the facing metal pattern 50 and the holding capacitor Cgci, the common voltage Vcom provided to the source pattern 32 is charged in the i-th holding capacitor Cgci. The ith common voltage charged in the ith holding capacitor Cgci during the ith horizontal period iH is maintained for one frame period, that is, until a new common voltage Vcom is provided in the next frame.

Similarly, by the (i+1)th gate pulse (G[i+1]) provided during the (i+1)th horizontal period ([i+1]H), the (i+1)th horizontal line The pixels P are charged with the data voltage ADATA. In addition, the (i+1)th common voltage Vcom[i+1] is provided to the (i+1)th common line VCL[i+1], and the (i+1)th holding capacitor Cgc[ i+1]), the (i+1)th common voltage Vcom[i+1] is charged.

As described above, the liquid crystal display according to the first embodiment provides a common voltage to the pixels P without using a separate common voltage generating circuit. In particular, in the liquid crystal display according to the first embodiment, since the common voltage Vcom is provided in synchronization with a gate pulse for scanning each horizontal line, a phenomenon in which the common voltage is delayed can be prevented.

In addition, even when the second transistor T2 is turned off after the horizontal period in which the common voltage Vcom is provided, the common voltage Vcom is stably used for one frame period using the common voltage Vcom charged in the holding capacitor Cgc. (Vcom) can be provided. In addition, the holding capacitor Cgc may prevent the potential of the common voltage Vcom from changing due to a kick back voltage at the turn-off moment of the second transistor T2 . At the moment when the potential of the gate pulse is inverted to the low potential, the charge is instantaneously redistributed, and as shown by the dotted line in FIG. 6 , the voltage greatly fluctuates, resulting in a difference in the kick-back voltage ΔVkb. However, since the holding capacitor Cgc maintains the voltage constant, it is possible to suppress the occurrence of the kick-back voltage at the moment the gate pulse is inverted to the low potential.

One end of the metal pattern 50 of the holding capacitor Cgc is connected to a reference voltage source. The reference voltage source stably maintains the potential of the common voltage Vcom charged in the holding capacitor Cgc for each frame. The reference voltage source may use a low potential voltage source GND or a gate low voltage VGL.

FIG. 7 is a cross-sectional view taken along the line I-I' shown in FIG. 4 .

A process of forming the pixel array substrate according to the first embodiment will be briefly described with reference to FIGS. 4 and 7 .

A gate line GL, first and second gate electrodes 41 and 42, and a common line VCL are formed on a substrate using a gate electrode material. A gate insulating layer GI is formed on the gate line GL, the first and second gate electrodes 41 and 42 , and the common line VCL. The common line VCL forms a third contact hole CT3 by patterning a portion of the gate insulating layer GI. The data line DL, the dummy data line DDL, the first and second drain electrodes 21 and 22, the first source electrode 31 and the source pattern 32 are formed on the gate insulating layer GI using a data metal material. ) to form The data metal material is buried in the third contact hole CT3 to electrically connect the metal pattern 50 and the common line VCL. Next, the passivation layer PAS is formed, and the pixel electrode 17 , the common electrode 15 , and the metal pattern 50 are formed on the passivation layer PAS.

8 is a flowchart illustrating a process in which the timing controller 210 generates common voltage data VCDATA and compensation common voltage data VCDATA.

Referring to FIG. 8 , the timing controller 210 calculates the data change amount of each pixel P between horizontal lines based on input image data RGB. To this end, the timing controller 210 controls the sum of the n image data of the i-th horizontal line HLi and the n image data of the (i+1)-th horizontal line HL[i+1] stored in the line memory. Calculate the difference of the total. (S801)

In addition, the timing controller 210 determines whether the amount of change in the image data is greater than or equal to a threshold value. The threshold value may be set based on the amount of change in image data in which the ripple of the common voltage may occur. The ripple of the common voltage increases as the amount of change in the image data increases. In addition, when a ripple occurs in the common voltage, image quality defects such as horizontal dimming or horizontal crosstalk occur. The threshold value may be set as an amount of change in image data within a range in which ripple of the common voltage may affect image quality (S803).

The timing controller 210 generates compensation common voltage data by compensating the common voltage data when the amount of change in the image data is greater than or equal to a threshold value. For example, when the amount of change between the i-th image data and the (i+1)-th image data is equal to or greater than the threshold, the timing controller 210 supplies the (i+1)-th image data to the (i+1)-th horizontal line to be charged. compensating the common voltage. (S805)

9 is a diagram illustrating an example of generating compensation common voltage data according to a data change amount. In FIG. 9 , the threshold value data_ref will be described by taking as an example a range larger than Δdata1 and smaller than Δdata2.

9 shows an example in which the sum of the image data of the first horizontal line is 127 grayscales of positive polarity, and the sum of the image data of the second horizontal line is 127 grayscales of the negative polarity. That is, the amount of change in the image data of the second horizontal line is 256 grayscales of negative polarity. Since the amount of change Δdata1 of the image data of the second horizontal line compared to the image data of the first horizontal line is greater than or equal to the threshold value, the timing controller 210 controls the common voltage data VCDATA for generating the second common voltage Vcom. ) outputs the uncompensated common voltage data VCDATA to the data driver 240 .

In addition, if the total image data of the third horizontal line is 255 grayscales of positive polarity, the amount of change (Δdata2) of the image data of the third horizontal line is greater than or equal to the threshold value compared to the image data of the second horizontal line, so the timing controller 210 is In order to generate the third common voltage Vcom, the compensating common voltage data VCDATA obtained by compensating the common voltage data VCDATA is output to the data driver 240 . In order to generate the compensation common voltage data VCDATA, the timing controller 210 may store compensation values according to the amount of change in the image data in advance in a look-up table (not shown). The compensation value is a value capable of reducing ripple based on panel characteristics and the like, and may be determined by an experimental value. And, since the image data change amount Δdata2 of the third horizontal line indicates the direction of the positive polarity, the ripple is generated in the positive polarity. Accordingly, the timing controller 210 selects a negative polarity compensation value for generating the compensation common voltage data VCDATA for the third common voltage Vcom.

Since the amount of change in the image data Δdata3 of the fourth horizontal line compared to the third horizontal line is also greater than or equal to the threshold, the timing controller 210 generates the compensation common voltage data VCDATA to output the fourth common voltage Vcom. compensate At this time, since the amount of change of image data Δdata3 of the fourth horizontal line compared to the third horizontal line is larger than the amount of change of image data of the third horizontal line Δdata2 with respect to the second horizontal line, it is compensated with a larger compensation value. do. In addition, since the image data change amount Δdata3 of the fourth horizontal line has a negative polarity compared to the third horizontal line, the compensation common voltage data VCDATA of the fourth horizontal line is obtained by using a positive compensation value. compensated

10 is a diagram illustrating a pixel array substrate of the liquid crystal panel 100 according to the second embodiment, and FIG. 11 is a diagram illustrating the structure of a pixel P and a holding capacitor Cgc. In the second embodiment, a detailed description of a configuration that is substantially the same as or very similar to the above-described embodiment will be omitted.

10 and 11 , the thin film transistor array substrate of the liquid crystal panel 100 according to the second embodiment has pixels defined by gate lines GL1 to GLm and data lines DL1 to DLn arranged vertically and horizontally. (P) are arranged in a matrix form. A dummy data line DDL and a holding capacitor Cgc formed in parallel with the first data line DL1 are formed at a position outside the pixel array region 100A.

Each of the gate lines GL1 to GLm receives a gate pulse from the gate driver 230 and supplies it to the first and second gate electrodes 41 and 42 . The ith gate line GLi is formed on the pixels P arranged on the ith horizontal line HLi.

In one horizontal line, n pixels P are formed, and each pixel P receives a data voltage ADATA through data lines DL1 to DLn connected one-to-one. A first transistor T1 is formed in a region where the data line DL and the gate line GL intersect.

Each common line VCL receives the common voltage Vcom from the dummy data line DDL and supplies it to the common electrodes 17 . The ith (i is a natural number less than or equal to (m-1)) common line VCLi is formed under the pixels P arranged on the ith horizontal line HLi. The i-th common line VCLi is connected to the source pattern 32 formed on the (i+1)-th horizontal line HL[i+1].

The holding capacitors Cgc1 to Cgcm include the metal pattern 50 and the source pattern 32, are charged by receiving the common voltage Vcom through the dummy data line DDL, and are charged with the charged common voltage Vcom. is maintained for 1 frame. The ith holding capacitor Cgci is formed on the ith horizontal line HLi at a position out of the pixel array region 100A. Each of the holding capacitors Cgc1 to Cgcm receives a common voltage from the dummy data line DDL through the second transistor T2 in response to a gate pulse.

12 is a diagram illustrating timing of switching the common voltage Vcom using a gate pulse.

10 to 12 , when the i-th gate pulse Gi is supplied to the i-th gate line GLi during the (i-1)-th and the i-th horizontal periods (iH,[i+1]H), The first and second transistors T1 and T2 formed on the ith horizontal line HLi are turned on. While the first transistor T1 is turned on, the data voltage ADATA provided through the data lines DL1 to DLn during the ith horizontal period iH is applied to the pixel P of the ith horizontal line HLi. ) are charged in And while the second transistor T2 is turned on, the common voltage Vcom provided through the dummy data lines DL1 to DLn is applied to the (i-1)th common line VCL through the source pattern 32 . [i-1]). Since the source pattern 32 of the ith horizontal line HLi forms the ith holding capacitor Cgci with the metal pattern 50 facing each other, the common voltage Vcom provided to the source pattern 32 is the ith The holding capacitor (Cgci) is charged. The ith common voltage Vcomi charged in the ith holding capacitor Cgc during the (i-1) and ith horizontal periods iH is maintained until the end of the frame.

Similarly, (i+1)th provided to the (i+1)th gate line GL[i+1] during the i-th and (i+1)-th horizontal periods (iH, [i+1]H) The pixels P on the (i+1)th horizontal line are charged with the data voltage ADATA by the gate pulse G[i+1]. In addition, the (i+1)th common voltage Vcom provided to the i-th common line VCL is maintained during the i-th and (i+1)-th horizontal periods.

As described above, the liquid crystal display of the second embodiment controls the i-th common voltage supplied to the i-th horizontal line, which is the previous stage, by using the (i+1)th gate pulse. And in the second embodiment, since the holding capacitor Cgc is maintained for two horizontal periods 2H, it is possible to more stably provide the common voltage Vcom.

In the liquid crystal display of the first and second embodiments, the holding capacitor may be formed as a pair as shown in FIG. 13 . That is, first and second dummy data lines DDL1 and DDL2 are formed on both sides of the pixel array region 100A, and the first holding capacitor Cgc_L is connected to a common voltage through the first dummy data line DDL1. Vcom is provided, and the second holding capacitor Cgc_R receives the common voltage Vcom through the second dummy data line DDL2. As in FIG. 13 , the common voltage Vcom is charged using the first and second holding capacitors Cgc_L and Cgc_R and provided to the common line VCL, thereby reducing the delay difference between the horizontal lines while reducing the common voltage Vcom. The voltage Vcom can be provided more efficiently.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (8)

a liquid crystal panel on which a gate line, a dummy data line, and a data line are formed;
a timing controller for outputting common voltage data;
a data driver generating a common voltage based on the common voltage data, providing it to the dummy data line, and providing a data voltage to the data line based on image data;
a common line formed in a horizontal line direction to provide the common voltage received through the dummy data line to each pixel formed in the horizontal line; and
a transistor including a gate electrode branched from the gate line, a drain electrode protruding from the dummy data line, and a source pattern adjacent to the drain electrode and electrically connected to the common line;
and the transistor supplies the common voltage received through the dummy data line to the source pattern connected to the common line in response to a gate pulse provided to the gate line.
delete The method of claim 1,
A metal pattern formed with an insulating layer interposed therebetween is further formed on the source pattern, so that the source pattern and the metal pattern form a holding capacitor that maintains the common voltage provided to the source pattern for one frame. .
4. The method of claim 3,
The source pattern of the transistor turned on by a gate pulse provided to an i-th (i is a natural number equal to or smaller than the number of the gate lines) gate lines is electrically connected to the i-th common line, and the i-th common line The line is a liquid crystal display device that provides a common voltage supplied to pixels formed on the ith horizontal line in the ith horizontal period.
4. The method of claim 3,
The source pattern of the transistor turned on by a gate pulse provided to the (i+1)th (i is a natural number less than or equal to (m-1) when the number of the gate lines is m) is the i-th A liquid crystal display device electrically connected to a common line, wherein the i-th common line provides a common voltage supplied in an i-th horizontal period to pixels formed on the i-th horizontal line.
6. The method of claim 5,
The gate pulse provided to the (i+1)th gate line is output during i-th and (i+1)-th horizontal periods.
The method of claim 1,
the timing controller
A liquid crystal display device for calculating the amount of change in the image data between horizontal lines, and compensating for the common voltage data with a polarity opposite to the polarity of the change amount of the image data when the amount of change in the image data is greater than or equal to a threshold value.
4. The method of claim 3,
The metal pattern is connected to a low potential voltage or a gate low voltage.

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