KR20050001516A - Thin Film Transistor Array Type Liquid Crystal Display Device and a Method for manufacturing the same - Google Patents

Abstract

An object of the present invention is to provide a method for manufacturing a thin film transistor for an NSA structure liquid crystal display device which can omit a separate alignment key manufacturing process, and for this purpose includes a thin film transistor and a pixel electrode on a substrate on which a color filter is formed. By using a thin film transistor on color filter (TOC) liquid crystal display device having a structure for forming an array element to form an alignment key at the same time in the manufacturing process of the color filter, a separate alignment key manufacturing process is omitted. By providing the aligned NSA structure thin film transistor, the alignment key is formed simultaneously in the color filter manufacturing process, so that the NSA structure thin film transistor having excellent device characteristics and reliability can be manufactured in a simplified process, and as the color filter layer exists under the buffer layer, The thermal conductivity can be improved, and the crystallinity of the semiconductor layer can be improved.

Description

Thio Film Transistor Array Type Liquid Crystal Display Device and a Method for manufacturing the same

The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing a thin film transistor for a liquid crystal display device.

Recently, with the rapid development of the information society, there is a need for a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption. displays are actively being developed.

In general, a liquid crystal display device is formed by arranging two substrates on which electric field generating electrodes are formed so that the surfaces on which two electrodes are formed face each other, inserting a liquid crystal material between the two substrates, and then applying voltage to the two electrodes. It is a device that expresses an image by the transmittance of light that varies depending on the movement of liquid crystal molecules by moving the liquid crystal molecules by an electric field.

In the above-described liquid crystal display device, an active matrix type liquid crystal display device having a thin film transistor, which is a switching element for turning on / off a voltage for each pixel that is a minimum unit for displaying a screen, is mainly used. Recently, liquid crystal display devices employing thin film transistors using poly-silicon (poly-Si) have been widely researched and developed. In a liquid crystal display using polycrystalline silicon, the thin film transistor and the driving circuit can be formed on the same substrate, and the process of connecting the thin film transistor and the driving circuit is unnecessary, thereby simplifying the process. In addition, since polycrystalline silicon has a field effect mobility of about 100 to 200 times larger than amorphous silicon, the response speed is fast and the stability of temperature and light is excellent.

Crystallization to polycrystalline silicon is the mainstream of the laser heat treatment process through the laser beam irradiation. However, since the surface temperature of the silicon film irradiated with the laser beam is about 1400 ° C., the surface of the silicon film is easily oxidized. In particular, in the laser heat treatment crystallization method, since the laser beam is irradiated many times, when the laser heat treatment is performed in the air, the surface of the silicon film irradiated with the laser beam is oxidized to generate SiO ₂ . Therefore, laser heat treatment should be carried out in a vacuum of about 10 ^-7 to 10 ^-6 torr.

In order to make up for the shortcomings of the crystallization method by laser heat treatment, a method of crystallizing by sequential lateral solidification (hereinafter referred to as SLS method) using a laser has recently been proposed and widely studied.

The SLS method takes advantage of the fact that the grain of silicon grows in the direction perpendicular to the interface at the interface between the silicon liquid region and the solid state region of the silicon, and moves the grain according to the size of the laser energy and the irradiation range of the laser beam. Crystallization method of the amorphous silicon thin film which can improve the size of the silicon grain by lateral growth by a predetermined length (Robert S. Sposilli, MA Crowder, and James S. Im, Mat. Res. Soc. Symp. Proc. Vol. 452, 956 to 957, 1997). The SLS method enables the fabrication of a thin film transistor having a single crystal silicon channel region by forming an SLS silicon thin film on the substrate with a significantly large size of silicon grain.

The above-mentioned crystalline silicon materials such as polycrystalline silicon and single crystal silicon have higher field effect mobility than amorphous silicon, so that a driving circuit can be made on the substrate. If the driving circuit is directly made on the substrate, the IC cost can be reduced. It is easy to mount.

1 is a schematic diagram of a general liquid crystal display device integrated with a driving circuit unit.

As shown in the drawing, the driving circuit section 3 and the pixel section 4 are formed on the same substrate 2.

The pixel portion 4 is located at the center of the substrate 2, and gates and data driving circuit portions 3a and 3b are positioned on the left and upper portions of the pixel portion 4, respectively.

In the pixel portion 4, a pixel area defined as an area where a plurality of gate wires 6 connected to the gate driving circuit part 3a and a plurality of data wires 8 connected to the data driving circuit part 3b intersect. The pixel electrode 10 is formed, and the thin film transistor T is formed in connection with the pixel electrode 10.

The gate and data driving circuit portions 3a and 3b are devices for supplying a scan signal and a data signal to the pixel electrode 10 through the gate and the data lines 6 and 8, respectively.

In addition, the gate and data driving circuit units 3a and 3b are connected to an external signal input terminal 12 to adjust an external signal input through the external signal input terminal 12 and output the same to the pixel electrode 10. Do it.

2A through 2D are cross-sectional views illustrating a conventional step in fabricating a crystalline silicon thin film transistor, and are mainly illustrated in the process of manufacturing a semiconductor layer.

2A illustrates forming a buffer layer 22 on a substrate 20 and forming a semiconductor layer 24 made of a crystalline silicon material on the buffer layer 22.

For example, the crystalline silicon material may correspond to a material formed through a crystallization process of an amorphous silicon material.

FIG. 2B illustrates a step of sequentially forming a gate insulating layer 26 and a gate electrode 28 in a central portion of the semiconductor layer 24. FIG. 2C illustrates an exposed semiconductor layer using the gate electrode 28 as a mask. 24) Doping the region.

In this step, a central portion of the undoped semiconductor layer 24 may be defined as an active region i, and both regions of the doped semiconductor layer 24 may be defined as a source region ii and a drain region iii, respectively. .

2D is a step of activating the source region (ii) and the drain region (iii) of the semiconductor layer 24. This step is a step of activating the amorphous source region (ii) and the drain region (iii) through the doping treatment step of FIG. 2c, which includes a heat treatment process as in the crystallization process, and typically includes laser energy. Is used.

As described above, in the manufacturing process of the conventional semiconductor layer, the process for defining the source region and the drain region is by a self-aligning process using a gate electrode without a separate mask process, and manufactured by such a process. The thin film transistor may be defined as a self-aligned thin film transistor (hereinafter, abbreviated to SA structure thin film transistor).

However, in the SA structure thin film transistor, first, an activation process is added separately from the crystallization process, and a second gate electrode is doped by using a mask as a kind of mask, and as the activation process proceeds in a state where the gate electrode is masked, The junction part (iv; juction part) of the semiconductor layer 24 positioned at the boundary with the electrode 28 is inferior in crystallization characteristics, and thus causes deterioration of device characteristics such as leakage current. There was a disadvantage working.

In order to remedy this drawback, recently, a non self-align (NSA) process has been proposed, which can omit a separate activation process by performing a crystallization process after a doping process based on an alignment key.

3A through 3E are cross-sectional views illustrating a conventional manufacturing process of a thin film transistor for an NSA structure liquid crystal display device.

In FIG. 3A, the buffer layer 32 is formed on the substrate 30, and the alignment key 34 is formed on both sides of the substrate 30.

For example, the alignment key 34 may be formed using chromium (Cr), and although not shown in the drawings, the alignment key 34 may be formed on the four corners of the substrate.

3B illustrates forming an amorphous silicon layer 36 in an area covering the alignment key 34, and placing the alignment key 34 in the first region v on the substrate on which the amorphous silicon layer 36 is formed. As a reference, the dummy pattern 38 is formed.

The first region v corresponds to a channel region defined as a movement path of a carrier.

3C illustrates a step of doping the exposed amorphous silicon layer 36 using the dummy pattern 38 as a mask.

In this step, it can be made by an n + doping process using Group 5 elements as doping ions.

The doped amorphous silicon layer 36 region is defined as a second region vi for convenience of description.

3D illustrates removing the dummy pattern 38 and crystallizing the exposed amorphous silicon layer 36.

The crystallization step may be selected from one of a laser crystallization process or an SLS crystallization process, and is characterized in that it is possible to omit a separate activation process because the crystallization process is performed after the doping process.

FIG. 3E shows a patterned silicon layer crystallized based on the alignment key 34 to form an active region vii located in the center, a source region viii and a drain forming both sides of the active region vii. In this step, the semiconductor layer 40 including the region ix is formed.

The active region vii corresponds to the first region (v in FIG. 3C), and the source region viii and the drain region ix are included in the second region (vi in FIG. 3C). It is an area.

Such a thin film transistor for an NSA structure liquid crystal display device has an advantage of simultaneously activating a silicon layer in a crystallization process. However, the additional alignment key process has been added, which increases the manufacturing cost and processing time.

In order to solve this problem, an object of the present invention is to provide a method for manufacturing a thin film transistor for an NSA structure liquid crystal display device which can omit a separate alignment key manufacturing process.

To this end, in the present invention, a thin film transistor on color filter (TOC) liquid crystal display having a structure in which an array element including a thin film transistor and a pixel electrode is formed on a substrate on which a color filter is formed. By forming an alignment key at the same time, an object of the present invention is to provide an NSA structure thin film transistor in which a separate alignment key manufacturing process is omitted.

The TOC liquid crystal display can prevent the aperture ratio loss due to mis-alignment by forming the color filter and the array element on the same substrate, and as the array element is positioned above the color filter, the array element Since the wiring portions (gate wirings and data wirings) are positioned at the color boundary of the color filter, the black matrix manufacturing process can be omitted in the manufacturing process of the color filter.

1 is a schematic diagram of a general liquid crystal display device integrated with a driving circuit unit;

Figure 2a to 2d is a cross-sectional view showing a step of manufacturing a conventional crystalline silicon thin film transistor.

3A through 3E are cross-sectional views illustrating a manufacturing process of a thin film transistor for a conventional NSA structure liquid crystal display.

4A to 4H are process diagrams showing step-by-step manufacturing processes of an NSA structure thin film transistor for a TOC liquid crystal display device according to a first embodiment of the present invention;

5 is a plan view of a liquid crystal display (TOC) device including an alignment key according to a second exemplary embodiment of the present invention.

6 is a cross-sectional view of a TOC liquid crystal display device according to a third embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

110 substrate 112 color filter layer

114: alignment key I: first area

II: second area

In order to achieve the above object, in a first aspect of the present invention, there is provided a method of forming a color filter and an alignment key at a periphery of the color filter by using a color resin material on a substrate; Forming a buffer layer in an area covering the color filter and the alignment key; Forming an amorphous silicon layer in an area covering the buffer layer; Forming a dummy pattern in the first region of the amorphous silicon layer based on the alignment key; Doping the exposed amorphous silicon layer region by using the dummy pattern as a mask to define the doped amorphous silicon layer region as a source region and a drain region; Removing the dummy pattern; Crystallizing an amorphous silicon layer in which the source and drain regions are defined; Provided is a method of manufacturing a substrate for a liquid crystal display device, the method comprising patterning the crystallized silicon layer into a semiconductor layer based on the alignment key.

The forming of the color filter may include sequentially forming red, green, and blue color filters, wherein the color filter is positioned in a display area defined as an area for implementing a screen, and the alignment key is not displayed. Located in an area, the buffer layer is formed to a thickness value that can have a step at a position corresponding to the alignment key, the first area is a channel area that is a passage for moving a carrier (carrier), the doping treatment The step is characterized in that the n + doping step using a Group 5 element.

The patterning of the semiconductor layer may include forming a gate electrode, a source electrode, and a drain electrode.

According to a second aspect of the present invention, there is provided a semiconductor device comprising: a first substrate formed by the manufacturing method according to the first aspect; A second substrate disposed to face the first substrate; A liquid crystal display device including a liquid crystal layer interposed between the first and second substrates is provided.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

First Embodiment

4A to 4H are process diagrams illustrating step-by-step manufacturing processes of an NSA structure thin film transistor for a TOC liquid crystal display according to a first embodiment of the present invention.

FIG. 4A illustrates a second embodiment in which a color filter layer 112 is formed in a first region I by using a color resin material on a substrate 110 and located at both sides of the first region I. Referring to FIG. The alignment key 114 is formed in the region II.

The first area I corresponds to the screen display area, and the second area II corresponds to the non-display area.

Although not shown in detail in the drawings, the color resin corresponds to a red, green, and blue color resin, and the color filter layer 112 has a structure in which red, green, and blue color filters are sequentially arranged in order.

The alignment key 114 may be formed of a single color resin or a combination of a plurality of color resins.

For example, the color resin may correspond to a color resin having any one of red, green, and blue color resins, and the color filter layer and the alignment key may correspond to each pattern formed of a single color color resin.

4B illustrates forming a buffer layer 116 in an area covering the color filter layer 112 and an alignment key 114, and forming an amorphous silicon layer 118 in an area covering the buffer layer 116. .

The buffer layer 116 is selected from a silicon insulating material, and is formed of, for example, a silicon oxide film (SiO 2), and is formed to a thickness value that may have a stepped pattern of the alignment key 114 as it is, and thus the buffer layer 116. In the state covered by), the step of the alignment key 114 may be recognized as it is to proceed with the process.

FIG. 4C is a step of forming a dummy pattern 120 on the alignment key 114 in the third region III on the buffer layer 116. The third region III corresponds to a channel region. Next, in FIG. 4D, the exposed amorphous silicon layer region is doped by masking the third region III of the amorphous silicon layer 118 with the dummy pattern 120.

The doping treatment corresponds to either an n + doping process using Group 5 ions or a p + doping process using Group 3 ions.

4E illustrates removing the dummy pattern 120 and crystallizing the doped amorphous silicon layer 118.

The crystallization step may be selected from any one of a laser heat treatment process or an SLS crystallization process.

In FIG. 4F, the crystallized silicon layer is patterned into a semiconductor layer 124, wherein the semiconductor layer 124 includes an undoped active region IV, a doped source region V, and a drain region. (VI).

In this step, the semiconductor layer 124 is patterned based on the alignment key 114 used in the patterning process of the dummy pattern (120 of FIG. 4E). As the patterning process is performed based on the alignment key 114, the doped semiconductor layer 124 may be precisely defined as the source region V and the drain region VI.

FIG. 4G illustrates a step of sequentially forming the gate insulating layer 126 and the gate electrode 128 at positions corresponding to the active region IV of the semiconductor layer 124, and FIG. 4H illustrates a position covering the gate electrode 128. Forming an interlayer insulating film 134 having first and second contact holes 130 and 132 exposing a portion of the source region V and the drain region VI of the semiconductor layer 124, and the interlayer insulating film 134. The semiconductor layer 124 is connected to the source electrode 136 through the first contact hole 130 and the drain region VI through the second contact hole 132. The drain electrode 138 is formed.

The semiconductor layer 124, the gate electrode 128, the source electrode 136, and the drain electrode 138 form a thin film transistor (T).

Second Embodiment

FIG. 5 is a plan view of a TOC liquid crystal display including an alignment key according to a second exemplary embodiment of the present invention. As shown in FIG. 5, a non-display area forming a display area I and a periphery of the display area I is shown. On the substrate having (II), the color filter layer 210 located in the display area I and the alignment key 212 located in the non-display area II are formed, respectively.

The color filter layer 210 and the alignment key 212 are made in the same process using a color resin material. That is, the alignment key 212 according to the present embodiment is characterized in that it is formed in the color filter manufacturing process without additional process.

The color filter layer 210 has a structure in which the red, green, and blue color filters 210a, 210b, and 210c are sequentially arranged in sequence, and the alignment keys 212 are located at the corners, respectively.

In the drawing, region "III" corresponds to one pixel region, and the number of pixel regions can be variously changed.

The pattern shape and the stacked structure of the alignment key 212 may be variously changed.

In addition, the color filter layer 210 serves as a heat preservation layer of the semiconductor layer (not shown), thereby improving the crystallinity of the silicon layer.

Third Embodiment

6 is a cross-sectional view of a TOC liquid crystal display device according to a third embodiment of the present invention, which includes a thin film transistor formed according to a manufacturing process of the NSA structure thin film transistor according to the first embodiment.

As illustrated, the first and second substrates 310 and 350 are disposed to face each other, the color filter layer 312 is formed on the first substrate 310, and the color boundary of the color filter layer 314 is defined. And a planarization layer 316 is formed on the upper portion. The planarization layer 316 corresponds to a pattern for enhancing planarization characteristics of the color filter layer 314, and may be omitted in some cases. Although not shown in detail in the drawings, the color filter layer 312 has a structure in which red, green, and blue color filters are sequentially arranged in sequence, and is illustrated with an area including blue and red color filters on the drawing.

A buffer layer 318 is formed on the planarization layer 316, and a thin film transistor including a semiconductor layer 320, a gate electrode 322, a source electrode 324, and a drain electrode 326 on the buffer layer 318. (T) is formed. A protective layer 330 having a drain contact hole 328 partially exposing the drain electrode 326 is formed at a position covering the thin film transistor T, and a drain contact hole 328 is formed on the protective layer 330. The pixel electrode 332 connected to the drain electrode 326 is formed, and the first alignment layer 334 is formed in the region covering the pixel electrode 332.

The semiconductor layer 320 includes an active region IV corresponding to the gate electrode 322, and a source region V and a drain region VI located at both sides of the active region IV. The source region V and the drain region VI are doped regions, which are not shown in the drawing but doped by an NSA process using an alignment key made of the same material in the same process as the color filter layer 312. It features.

The common electrode 352 and the second alignment layer 354 are sequentially formed on the inner surface of the second substrate 350, and the liquid crystal layer 360 is interposed between the first and second alignment layers 334 and 354. It is.

The present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention.

As described above, according to the manufacturing method of the NSA structure thin film transistor for TOC liquid crystal display according to the present invention, since the alignment key is formed at the same time in the color filter manufacturing process, the NSA structure thin film transistor having excellent device characteristics and reliability can be simplified. It is possible to fabricate, and the presence of the color filter layer under the buffer layer improves the thermal conductivity, thereby improving the crystallinity of the semiconductor layer.

Claims (8)

Using a color resin material on the substrate to form a color filter and an alignment key in the periphery of the color filter; Forming a buffer layer in an area covering the color filter and the alignment key; Forming an amorphous silicon layer in an area covering the buffer layer; Forming a dummy pattern in the first region of the amorphous silicon layer based on the alignment key; Doping the exposed amorphous silicon layer region by using the dummy pattern as a mask to define the doped amorphous silicon layer region as a source region and a drain region; Removing the dummy pattern; Crystallizing an amorphous silicon layer in which the source and drain regions are defined; Patterning the crystallized silicon layer into a semiconductor layer based on the alignment key Method of manufacturing a substrate for a liquid crystal display device comprising a. The method of claim 1, The forming of the color filter may include forming red, green, and blue color filters in order. The method of claim 1, And the color filter is in a display area defined as an area for implementing a screen, and the alignment key is in a non-display area. The method of claim 1, And the buffer layer is formed to a thickness value having a step at a position corresponding to the alignment key. The method of claim 1, The first region is a channel region, which is a channel for moving a carrier. The method of claim 1, The doping treatment step is a n + doping treatment step using a Group 5 element manufacturing method for a liquid crystal display device substrate. The method of claim 1, And forming a gate electrode, a source electrode, and a drain electrode after patterning the semiconductor layer. A first substrate formed by the manufacturing method according to claim 1; A second substrate disposed to face the first substrate; Liquid crystal layer interposed between the first and second substrates Liquid crystal display comprising a.