KR20150131455A - Gate driving circuit - Google Patents

Abstract

The gate driving circuit is connected to the timing signal input terminal of the first stage and the timing signal output terminal of the third stage among the plurality of stages including any three consecutive stages, The second stage includes an input for receiving a carry signal from the first stage, a clock signal of a first voltage level according to the level of the carry signal to the first node, A bootstrapping unit connected to the first node and the first ground terminal for raising the voltage of the second node above the first voltage level and for pulling down the output signal of the output terminal to the first ground voltage according to the voltage level of the first node, And a first pull-down section connected to the first node for pulling down the output signal of the carry terminal and the timing signal output terminal to the first or second ground voltage Down portion includes a first transistor coupled to the timing signal output terminal by a diode-connection, and a second transistor coupled to the carry terminal and the first ground terminal, wherein the first pull-down portion includes a second pull-down portion, When the second transistor is in the turn-off state, the carry terminal and the timing signal output terminal are pulled down to the second ground voltage, and when the second transistor is in the turn-on state, Down to a ground voltage, and applies a discharge voltage applied from the second node of the third stage to the carry terminal, to the first ground terminal, and the first transistor prevents the discharge voltage from being applied to the output terminal. Therefore, the gate drive circuit can improve the efficiency of the output signal by reducing the ripple phenomenon in the output signal. Further, according to the embodiment of the present invention, the carry signal outputted from the previous stage can be effectively transmitted to the input terminal of the next stage.

Description

[0001] GATE DRIVING CIRCUIT [0002]

The present invention relates to a display device, and more particularly to a gate drive circuit using an oxide thin film transistor.

A display device is a device that visually transmits information through a display panel. There are various types of display devices such as a liquid crystal display (LCD), a light emitting diode (LED), and a plasma display panel (PDP).

In order to drive the display panel of the display device, a gate driving circuit is required. For cost reduction of the display device and simplification of the structure, the gate drive circuit includes a thin film transistor. In particular, the oxide thin film transistor is superior to the conventional silicon thin film transistor in current drive capability and is suitable for use in a gate drive circuit. In addition, the oxide thin film transistor has a low manufacturing cost.

However, oxide thin film transistors can have a negative threshold voltage due to process variations due to voltage and light. Therefore, if an oxide thin film transistor is used in a gate driving circuit including a conventional silicon thin film transistor, normal circuit operation is impossible because the oxide thin film transistor is not completely turned off.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a gate drive circuit including an oxide thin film transistor which removes a ripple component of an output voltage and improves a drive ratio even at a negative threshold voltage. Circuit.

The gate driving circuit according to the embodiment of the present invention is configured such that the timing signal input terminal of the first stage and the timing signal output terminal of the third stage are connected to each other among a plurality of stages including any three consecutive stages, A second stage having an input for receiving a carry signal from the first stage and a second stage for receiving a carry signal of a first voltage level according to the level of the carry signal, A bootstrapping unit for applying a voltage to the first node and for raising a voltage of the second node to a first voltage level; a bootstrapping unit connected to the first node and the first ground terminal for applying an output signal of the output terminal according to a voltage level of the first node; Down to a first ground voltage and a second pull-down section connected to the first node, wherein the output signal of the carry terminal and the timing signal output terminal is connected to the first or second ground Down portion includes a first transistor coupled to the timing signal output terminal by a diode-connection, and a second transistor coupled to the carry terminal and the first ground terminal, the second pull- When the first node is at the second voltage level, the carry terminal and the timing signal output terminal are pulled down to the second ground voltage when the second transistor is in the turn-off state, and when the second transistor is in the turn- The timing signal output terminal is pulled down to a first ground voltage and a discharge voltage applied to the carry terminal from the second node of the third stage is applied to the first ground terminal, .

According to the embodiment of the present invention, the gate drive circuit can improve the efficiency of the output signal by reducing the ripple phenomenon in the output signal. Further, according to the embodiment of the present invention, the carry signal outputted from the previous stage can be effectively transmitted to the input terminal of the next stage.

1 is a block diagram showing a display device according to an embodiment of the present invention.
2 is a block diagram showing the gate driving circuit shown in FIG. 1 according to an embodiment of the present invention.
Fig. 3 is a circuit diagram showing each stage shown in Fig. 2. Fig.
FIG. 4 is a signal diagram showing input and output clock signals of the circuit shown in FIG.
5A and 5B are graphs showing the efficiency of the output signal of the present invention.
6 is a graph of an output signal of an output terminal according to a change in a threshold voltage.
FIG. 7 is a block diagram of each stage shown in FIG. 2. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention. The same elements will be referred to using the same reference numerals. Similar components will be referred to using similar reference numerals. The gate drive circuit according to the present invention to be described below and the operation performed thereby are merely described by way of example, and various changes and modifications are possible without departing from the technical idea of the present invention.

1 is a block diagram showing a display device according to an embodiment of the present invention. Referring to FIG. 1, a display device 100 includes a timing controller 110, a gate driving circuit 120, a data driver 130, and a display panel 140.

The timing control unit 110 outputs a gate control signal GCS for controlling the output of a plurality of gate control signals of the gate driving circuit 120. [ The timing controller 110 receives the input video signals from the outside and outputs the converted video data IDATA in accordance with the operation mode of the display panel 140.

The gate driving circuit 120 receives the gate control signal GCS from the timing control unit 110. [ The gate drive circuit 120 may generate a plurality of gate signals in response to the gate control signal GCS. The gate signals are sequentially applied to the display panel 140 through the plurality of lines GL1 to GLn.

The data driver 130 receives the converted image data IDATA from the timing controller 110. The data driver 130 generates a plurality of data signals in response to the converted image data IDATA. The data signals are applied to the display panel 140 through the plurality of data lines DL1 to DLm.

The display panel 140 is electrically connected to the gate driving circuit 120 through a plurality of gate lines GL1 to GLn. The display panel 140 is electrically connected to the data driver 120 through the plurality of data lines DL1 to DLn. The display panel 140 is connected to a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLn and includes a plurality of pixels. The display panel 140 operates according to a data voltage transmitted through the data driver 130 and a gate voltage transmitted through the gate driving circuit 120.

2 is a block diagram showing the gate driving circuit shown in FIG. 1 according to an embodiment of the present invention. Referring to FIG. 2, the gate driving circuit 120 (see FIG. 1) includes a shift register 121. The shift register 121 includes first through (n + 2) -th stages SRC1 through SRCn which are connected in a dependent manner. The first to nth stages SRC1 to SRCn are defined as a driving stage and the n + 1 and n + 2 stages SRCn + 1 and SRCn + 2 are defined as a dummy stage.

The first through n-th stages SRC1 through SRCn include first through third clock signal terminals CK1 through CK3, an input terminal IN, a timing signal output terminal JIN, a timing signal input terminal JIN, A carry terminal CR, and an output terminal OUT. Signals having mutually opposite phases are input to the first clock signal terminal CK1 of the odd-numbered stages SRC1 to SRCn-1 and the even-numbered stages SRC2 to SRCn. Specifically, the first clock signal CK is applied to the first clock signal terminal CK1 of the odd-numbered stages SRC1 to SRCn-1. In addition, the second clock signal CKB is applied to the first clock signal terminal CK1 of the even-numbered stages SRC2 to SRCn.

Clock signals having opposite phases are applied to the second and third clock signal terminals CK2 and CK3 of the first to n-th stages SRC1 to SRCn. Specifically, the third clock signal CKL is applied to the second clock signal terminal CK2 of the odd-numbered stages SRC1 to SRCn-1 and the fourth clock signal CK2, which is opposite in phase to the third clock signal terminal CK3, The signal CKLB is applied. Conversely, the fourth clock signal CKLB is applied to the second clock signal terminal CK2 of the even-numbered stages SRC2 to SRCn and the third clock signal CKL is applied to the third clock signal terminal CK3 do.

Carry signals output from the carry terminals CR of the previous stage are applied to the input terminals IN of the second to n-th stages SRC2 to SRCn, respectively. The carry signal output from the carry terminal CR serves to drive the next stage. The vertical start signal STV is applied to the input terminal IN of the first stage SRC1 instead of the carry signal. Thus, the first stage SRC1 is driven by the vertical start signal STV.

The timing signal output from the timing signal output terminal JOUT of the next odd-numbered stage is applied to each timing signal input terminal JIN of the odd-numbered stages SRC1 to SRCn-1. Specifically, the timing signal output from the timing signal output terminal JOUT of the third stage SRC3 is applied to the timing signal input terminal JIN of the first stage SRC1.

The timing signal output from the timing signal output terminal JOUT of the next even-numbered stage is applied to each timing signal input terminal JIN of the even-numbered stages SRC2 to SRCn. Specifically, the timing signal output from the timing signal output terminal JOUT of the fourth stage SRC4 is applied to the timing signal input terminal JIN of the second stage SRC2.

The timing signal output terminal JOUT of the first and second stages SRC1 and SRC2 outputs a timing signal. However, since there is no previous stage for applying the timing signal, the output signal is not displayed separately.

The first to nth stages SRC1 to SRCn are electrically connected to the display panel 140 (see FIG. 1) through the first to nth gate lines GL1 to GLn. The output terminal OUT of the first to nth stages SRC1 to SRCn sequentially outputs the first to nth gate signals G1 to Gn through the first to nth gate lines GL1 to GLn, do.

The n + 1 and n + 2 stages SRCn + 1 and SRCn + 2 are dummy stages and do not apply a gate signal to the display panel. The n + 1 and n + 2 stages SRCn + 1 and SRCn + 2 apply timing signals to the respective timing signal input terminals JIN of the n-1 and n-th stages SRCn-1 and SRCn To be. The n + 1 and n + 2 stages SRCn + 1 and SRCn + 2 output timing signals. However, the timing signal is not applied through the timing signal input terminal JIN.

3 is a circuit diagram constituting the stage of Fig. 2 and 3, the first to n-th stages SRC1 to SRCn include first to tenth TFTs M1 to M10 and first to third capacitors C1 to C3, . The first to tenth thin film transistors M1 to M10 may be oxide thin film transistors. However, the first to tenth thin film transistors M1 to M10 are not limited to the oxide thin film transistor. The present invention is based on the assumption that the first to tenth thin film transistors M1 to M10 are oxide thin film transistors.

The gate terminal of the first thin film transistor M1 is connected to the third clock signal terminal CK3. The gate terminal of the first thin film transistor M1 receives the third and fourth clock signals CKL and CKLB from the third clock signal terminal CK3. The third and fourth clock signals CKL and CKLB are also applied to the first capacitor C1. The first capacitor C1 prevents the sixth thin film transistor M6 from being turned on or off by the third and fourth clock signals CKL and CKLB.

And the third clock signal CKL is applied to the third clock signal terminal CK3 of the even-numbered stages SRC2 to SRCn. And the fourth clock signal CKLB is applied to the third clock signal terminal CK3 of the odd-numbered stages SRC1 to SRn-1. The third and fourth clock signals CKL and CKLB have phases opposite to each other. The drain terminal of the first thin film transistor M1 is connected to the input terminal IN and the source terminal thereof is connected to the gate terminal of the second thin film transistor M2.

The carry signal and the vertical start signal STV output from the carry terminal CR of the previous stage are applied to the input terminal IN. The first thin film transistor M1 is controlled such that the carry signal and the vertical start signal STV are applied to the gate terminal of the second thin film transistor M2 according to the third and fourth clock signals CKL and CKLB input to the gate terminal do.

The second capacitor C2 connected to the first node n1 may be charged by the carry signal and the vertical start signal STV. A second capacitor C2 may be disposed between the first and second nodes n1 and n2. The second capacitor C2 is used to implement bootstrapping.

The carry signal and the vertical start signal STV output from the first thin film transistor M1 are applied to the gate terminal of the second thin film transistor M2. The drain terminal of the second thin film transistor M2 is connected to the first clock signal terminal CK1, and the source terminal thereof is connected to the first node n1. The first and second clock signals CK and CKB are applied to the first clock signal terminal CK1. The first clock signal CK is input to the first clock signal terminal CK1 of the odd-numbered stages SRC1 to SRn-1. The second clock signal CKB is applied to the first clock signal terminal CK1 of the even-numbered stages SRC2 to SRCn. The first and second clock signals CK and CKB have phases opposite to each other.

The second thin film transistor M2 applies the first and second clock signals CK and CKB to the first node n according to the input voltage inputted to the gate terminal. The drain terminal and the output terminal OUT of the second capacitor C2, the third, sixth and seventh thin film transistors M3, M6 and M7 are connected to the first node n1.

The drain terminal of the third thin film transistor M3 is connected to the first node n1, and the source terminal is connected to the first ground terminal. The first ground terminal has a first ground voltage (VSS, e.g., 0V). And the gate terminal of the third thin film transistor M3 is connected to the third clock signal terminal CK3. The third clock signal terminal CK3 outputs the third and fourth clock signals CKL and CKLB. The third thin film transistor M3 applies the first and second clock signals CK and CKB received from the second node n2 to the ground terminal in accordance with the third and fourth clock signals CKL and CKLB .

And the gate terminal of the fourth thin film transistor M4 is connected to the second clock signal terminal CK2. The drain terminal of the fourth thin film transistor M4 is connected to the power source terminal, and the source terminal is connected to the third node n3. The second clock signal terminal CK2 outputs the third and fourth clock signals CKL and CKLB. And the third clock signal CKL is applied to the second clock signal terminal CK2 of the odd-numbered stages SRC1 to SRn-1. And the fourth clock signal CKLB is applied to the second clock signal terminal CK2 of the even-numbered stages SRC2 to SRCn.

The fourth thin film transistor M4 applies the power supply voltage VDD output from the power supply terminal to the third node n3 in accordance with the third and fourth clock signals CKL and CKLB. The drain terminal of the fifth thin film transistor M5, the third capacitor C3 and the gate terminals of the sixth thin film transistor M6 are connected to the third node n3.

The gate terminal of the fifth thin film transistor M5 is connected to the second node n2. The drain terminal of the fifth thin film transistor M5 is connected to the third node n3, and the source terminal is connected to the first ground terminal.

And the gate terminal of the sixth thin film transistor M6 is connected to the third node n3. The drain terminal of the sixth thin film transistor M6 is connected to the first node n1, and the source terminal is connected to the first ground terminal. The sixth thin film transistor M6 pulls down the voltage of the output signal of the output terminal OUT to the first ground voltage VSS (for example, 0 V) in accordance with the power source voltage VDD input to the gate terminal.

And the gate terminal of the seventh thin film transistor M7 is connected to the second clock signal terminal CK2. The drain terminal of the seventh thin film transistor M7 is connected to the first node n1 and the source terminal is connected to the fourth node n4. The seventh thin film transistor M7 supplies the first and second clock signals CK and CKB applied to the drain terminal to the fourth node (CK and CKB) according to the third and fourth clock signals CKL and CKLB applied to the gate terminal n4. A timing signal output terminal JOUT and a drain terminal and a gate terminal of the eighth thin film transistor M8 are connected to the fourth node n4.

The gate terminal and the drain terminal of the eighth thin film transistor M8 are connected to the fourth node n4 and the source terminal is connected to the fifth node n5. The eighth thin film transistor M8 is connected by a diode-connection. Therefore, when the voltage of the signal on the output terminal OUT side is higher than the voltage of the signal on the carry terminal CR, the first and second clock signals CK and CKB turn on the eighth thin film transistor M8 . At the same time, the first and second clock signals CK and CKB are applied to the fifth node n5 through the drain terminal of the eighth thin film transistor M8. The fifth node n5 is connected to a carry terminal CR, a drain terminal of the ninth thin film transistor M9, and a drain terminal of the tenth thin film transistor M10.

And the gate terminal of the ninth thin film transistor M9 is connected to the third clock signal terminal CK3. The drain terminal of the ninth thin film transistor M9 is connected to the fifth node n5, and the source terminal is connected to the second ground terminal. The second ground terminal has a second ground voltage (VSSL, e.g., -5V). The ninth thin film transistor M9 is supplied with the third and fourth clock signals CKL and CKLB at its gate terminal. Thus, the carry signal of the carry terminal CR is pulled down to the second ground voltage (VSSL, for example, -5 V). The second ground voltage (VSSL, e.g., -5V) is always lower than the first ground voltage (VSS, e.g., 0V).

The gate terminal of the tenth thin film transistor M10 is connected to the timing signal input terminal JIN. The drain terminal of the tenth thin film transistor M10 is connected to the fifth node n5, and the source terminal is connected to the first ground terminal. As the timing signal is input to the gate terminal of the tenth thin film transistor M10, the carry signal of the carry terminal CR is pulled down to the first ground voltage VSS (for example, 0 V).

4 is a signal diagram showing a clock signal input or output in the circuit diagram shown in FIG. 4 is a signal diagram for a clock signal input to or outputted from odd-numbered stages SRC1 to SRCn-1 in the shift register of FIG. The first to fourth clock signals CK, CKB, CKL and CKLB have a first voltage level L1 according to a high state and a second voltage level L2 according to a low state.

IN denotes a carry signal applied to an input terminal IN, and CR denotes a carry signal outputted through a carry terminal CR. n1 denotes a voltage level at the first node n1. JOUT denotes the output signal of the timing signal output terminal (JOUT), and JIN denotes the input signal of the timing signal input terminal (JIN). Finally, G denotes the output signal of the output terminal OUT.

3 and 4, at the first time t1, the fourth clock signal CKLB of the first voltage level L1 is input to the third clock signal terminal CK3. The fourth clock signal CKLB of the first voltage level L1 is applied to the gate terminals of the first, third, and ninth transistors M1, M3, and M9 to turn on. And charges the first capacitor C1.

The carry signal of the first voltage level L1 is input to the input terminal IN. Alternatively, the vertical timing signal STV of the first voltage level L1 is input to the input terminal IN of the first stage SRC1. The carry signal of the first voltage level L1 or the vertical timing signal STV turns on the gate terminal of the second thin film transistor M2 through the turned-on first thin film transistor M1. Further, the carry signal or the vertical timing signal STV of the first voltage level L1 is applied to the second node n2.

And the gate terminal of the second capacitor C2 and the fifth thin film transistor M5 are connected to the second node n2. Therefore, the carry signal or the vertical timing signal STV of the first voltage level L1 charges the second capacitor C2 and turns on the fifth thin film transistor M5. Due to the turn-on of the third thin film transistor M3, the voltage of the output terminal OUT can be maintained at the first ground voltage VSS (for example, 0 V).

At the second time t2, the first clock signal CK of the first voltage level L1 is applied to the first clock signal terminal CK1. And the activated signal generated by the energy stored in the second capacitor C2 is applied to the second node n2. The activated signal is applied to the gate terminals of the second and fifth thin film transistors M2 and M5. Therefore, the second and fifth thin film transistors M2 and M5 are turned on.

The first clock signal CK of the first voltage level L1 is applied to the first node n1 through the second thin film transistor M2. The second capacitor C2, the drain terminal and the output terminal OUT of the third thin film transistor M3 are connected to the first node n1.

The second capacitor C2 is charged by the first clock signal CK of the first voltage level L1 applied through the first node n1. Therefore, the turn-on state of the second thin film transistor M2 can be maintained. The second capacitor C2 implements bootstrapping. Bootstrapping means that the first clock signal CK of the first voltage level L1 is added to the energy charged in the second capacitor C2. Therefore, the voltage level of the second node n2 can be raised to twice the first voltage level L1. By bootstrapping, the first clock signal CK of the first voltage level L1 is applied to the output terminal OUT without loss. And the output terminal OUT outputs the output signal G of the first voltage level L1.

And the third clock signal CKL of the first voltage level L1 is applied to the second clock signal terminal CK2. Therefore, the fourth and seventh thin film transistors M4 and M7 to which the second clock signal terminal CK2 and the gate terminal are connected are turned on. The first clock signal CK of the first voltage level L1 is applied to the fourth node n4 through the seventh thin film transistor M7. A timing signal output terminal JOUT and a gate terminal and a drain terminal of the eighth thin film transistor M8 are connected to the fourth node n4.

The activated first clock signal CK output through the timing signal output terminal JOUT is applied to the timing signal input terminal JIN of the previous odd-numbered stage. The eighth thin film transistor M8 is connected by a diode-connection. Therefore, the gate terminal of the eighth thin film transistor M8 is turned on by the first clock signal CK of the first voltage level L1. At the same time, the eighth thin film transistor M8 applies the first clock signal CK of the first voltage level L1 to the fifth node n5. The fifth node n5 is connected to a carry terminal CR, a drain terminal of the ninth thin film transistor M9, and a drain terminal of the tenth thin film transistor M10.

The signal of the second voltage level L2 is applied to the timing signal input terminal JIN and the third clock signal terminal CK3. Therefore, the tenth and ninth thin film transistors M9 and M10 are turned off. The first clock signal CK1 of the first voltage level L1 is output to the next stage via the control terminal CR.

The power supply voltage VDD is applied to the third node n3 through the fourth thin film transistor M4. The drain terminal of the fifth thin film transistor M5 and the gate terminal of the sixth thin film transistor M6 are connected to the third node n3. Therefore, the power supply voltage VDD is applied to the first ground terminal through the fifth thin film transistor M5. In addition, the sixth thin film transistor M6 is turned on by the power supply voltage VDD. Therefore, the first clock signal CK of the first voltage level L1 is applied to the first ground terminal through the sixth thin film transistor M6.

At the third time t3 0, the fourth clock signal CKLB of the first voltage level L1 is applied to the third clock signal terminal CK3. Accordingly, the first, third, and eighth thin film transistors M1, M3, and M8 are turned on. The input terminal IN is connected to the control terminal CR of the previous stage. Thus, the activated signal output by the energy remaining in the second capacitor C2 is discharged through the previous stage. The eighth thin film transistor M8 of the previous stage is turned off and the tenth thin film transistor M1O is turned on.

The activated signal generated in the second capacitor C2 is applied to the first ground terminal through the tenth thin film transistor M10 of the previous stage. The eighth thin film transistor M8 of the previous stage is connected by a diode-connection. Therefore, the activated signal generated in the second capacitor C2 can not be applied to the output terminal OUT of the previous stage. Due to the diode-connection connection of the eighth thin film transistor M8, the ripple signal at the output terminal OUT can be reduced.

Due to the turn-on of the third thin film transistor M3, the voltage of the output terminal OUT can be pulled-down to the first ground voltage VSS, for example, 0V. Further, due to the turn-on of the eighth thin film transistor M8, the voltage of the carry terminal CR can be pulled-down to the second ground voltage VSSL, for example, -5V.

At the fourth time t4, the fourth clock signal CKLB of the second voltage level L2 is applied to the third clock signal terminal CK3. The carry signal of the second voltage level L2 and the vertical start signal STV are applied to the input terminal IN. Therefore, the second, third, fifth and ninth thin film transistors M2, M3, M5 and M9 are turned off. The first clock signal CK of the first voltage level L1 is applied to the drain terminal of the second thin film transistor M2. However, since the second thin film transistor M2 is in the turn-off state, the first clock signal CK of the first voltage level L1 can not be applied to the first node n1.

 And the first voltage level L1 and the third clock signal CKL are applied to the second clock signal terminal CK2. The second clock signal terminal CK2 is connected to the gate terminals of the fourth and seventh thin film transistors M4 and M7. Therefore, the fourth and seventh thin film transistors M4 and M7 are turned on.

When the fourth thin film transistor M4 is turned on, the power source voltage VDD is applied to the third node n3. The drain terminal of the fifth thin film transistor M5 and the gate terminal of the sixth thin film transistor M6 are connected to the third node n3. Since the fifth thin film transistor M5 is turned off, the power source voltage VDD is applied to the gate terminal of the sixth thin film transistor M6 through the third node n3. Thus, the sixth thin film transistor M6 is turned on. And the output terminal OUT is connected to the first ground terminal through the sixth thin film transistor M6. Thus, the output terminal OUT is pulled-down to the first ground voltage VSS (for example, 0 V).

An activated timing signal is applied to the timing signal input terminal JIN connected to the gate terminal of the tenth thin film transistor M10. Thus, the tenth thin film transistor M10 is turned on. The carry terminal CR is connected to the first ground terminal through the tenth thin film transistor M10 so that the carry terminal CR is connected to the input terminal IN of the next stage with the first ground voltage VSS, .

Thus, the ripple signal at the output terminal OUT can be reduced through the diode-connection connection of the eighth thin-film transistor M8. Also, through the bootstrapping implementation of the second capacitor C2, the first clock signal CK1 of the first voltage level L1 is applied to the output terminal OUT without loss.

5A and 5B are graphs showing the efficiency of the output signal of the present invention. 5A is a graph showing output signals of stages of a conventional gate driving circuit. 5A is a graph of the third, sixth and ninth output signals G3, G6 and G9 output in the third, sixth and ninth stages. 5A and 5B indicate the unit time (s), and the vertical axis indicates the magnitude (V) of the output signal output per unit time. Referring to FIG. 5A, it can be confirmed that ripple components exist in the third, sixth, and ninth output signals G3, G6, and G9.

Referring to FIG. 5B in comparison with FIG. 5A, the output signals of the third, sixth and ninth stages SRC3, SRC6 and SRC9 of the gate drive circuit 120 (see FIG. 2) It can be confirmed that there is almost no existence. To illustrate the present invention, the third, sixth and ninth output signals G3, G6 and G9 of the third, sixth and ninth stages SRC3, SRC6 and SRC9 are exemplified. The present invention will have almost no ripple component even in output signals other than the third, sixth and ninth output signals G3, G6 and G9.

The discharge voltage is not applied to the output terminal OUT due to the diode-connection of the eighth thin film transistor M8 (see Fig. 3) and the tenth thin film transistor M10 (see Fig. 3) of the stage 200 Do not. Therefore, the ripple signal can be reduced.

6 is a graph of the output signal of the output terminal according to the change of the threshold voltage VT. In FIG. 6, the horizontal axis represents unit time (s), and the vertical axis represents output voltage output per unit time. Referring to FIG. 6, it can be seen that a stable output signal is output at the output terminal OUT regardless of the change from the first threshold voltage VT1 to the eighth threshold voltage VT8.

FIG. 7 is a block diagram of each stage shown in FIG. 2. FIG. The stage 300 of FIG. 7 is the same as the stage 200 of FIG. Referring to FIG. 7, the stage 300 includes an input 310, a bootstrapping portion 320, a first pull-down portion 330, and a second pull-down portion 340.

The input unit 310 includes a first thin film transistor M1 and is capable of receiving a carry signal and a vertical start signal STV received from an input terminal IN. The first and second clock signals CK and CKB can be applied to the output terminal OUT.

The bootstrapping portion 320 may include a second thin film transistor M2 and a second capacitor C2. The second thin film transistor M2 is driven by the carry signal switched by the first thin film transistor M1 and the vertical start signal STV. The voltage of the first node n1 can be further raised by the boost trapping implementation of the second capacitor C2.

The first pull-down section 330 includes third through sixth thin film transistors M3 through M6, and a third capacitor C3. The first pull-down unit 330 sets the signal level of the output terminal OUT to a first ground voltage (VSS, for example, 0 V) when the signal output to the output terminal OUT is a first ground voltage VSS, e.g., 0V).

The second pull-down portion 340 includes seventh to tenth thin film transistors M7 to M10. The second pull-down unit 340 outputs the output of the carry terminal CR and the timing signal output terminal JOUT to a first ground voltage VSS (for example, 0 V) and a second ground voltage VSSL (for example, 5V). ≪ / RTI >

The embodiments have been disclosed in the drawings and specification as described above. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (1)

The timing signal input terminal of the first stage and the timing signal output terminal of the third stage are connected to each other among a plurality of stages including any three consecutive stages and the carry terminal of the second stage and the input terminal In the gate driving circuit,
The second stage comprising:
An input for receiving a carry signal from the first stage;
A bootstrapping unit applying a clock signal of a first voltage level to the first node according to the level of the carry signal and raising a voltage of the second node to a level higher than the first voltage level;
A first pull-down section coupled to the first node and a first ground terminal for pulling-down the output signal of the output terminal to a first ground voltage according to the voltage level of the first node; And
And a second pull-down portion connected to the first node for pulling-down the output signal of the carry terminal and the timing signal output terminal to a first or second ground voltage,
Down portion includes a first transistor connected in a diode-connection to the timing signal output terminal, and a second transistor coupled to the carry terminal and the first ground terminal,
When the first node is at a second voltage level, the carry terminal and the timing signal output terminal are pulled down to the second ground voltage when the second transistor is in a turn-off state,
Wherein the timing signal output terminal is pulled down to the first ground voltage when the second transistor is in a turn-on state, and a discharge voltage applied to the carry terminal from a second node of the third stage is applied to the first ground And the first transistor prevents the discharge voltage from being applied to the output terminal.

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