KR20250020083A - Fabrication method of resistance variable memory device - Google Patents

Abstract

A method for manufacturing a memory device according to one embodiment of the present invention includes a first step of forming a first insulating layer on a substrate, a second step of forming a first conductive line on the first insulating layer, a third step of forming a laminated structure including a lower electrode, a selection element, an intermediate electrode, a variable resistor, and an upper electrode that are sequentially laminated on the first conductive line, a fourth step of forming a second insulating layer between the laminated structures to cover sidewalls of the laminated structures, a fifth step of forming a second conductive line on the laminated structure, and a sixth step of subjecting the memory device manufactured by the first to fifth steps to a low-temperature treatment at a temperature of -270 degrees to -100 degrees for a predetermined period of time and then leaving it at room temperature for a predetermined period of time.

Description

{Fabrication method of resistance variable memory device}

The present invention relates to a method for manufacturing a variable resistance memory element, and more particularly, to a method for manufacturing a variable resistance memory element having a cross-point structure.

Recently, with the spread of portable digital devices and the increasing need to store digital data, interest in nonvolatile memory devices that do not lose stored data even when power is turned off is increasing.

As semiconductor devices, flash memory devices are widely used because they can be manufactured at low cost based on silicon processes, such as DRAM memory devices. However, flash memory devices have the disadvantages of having relatively low integration, slow operation speed, and requiring relatively high voltage for data storage compared to DRAM memory devices, which are volatile memory devices.

To overcome the shortcomings of such flash memory devices, various next-generation semiconductor devices such as phase changeable RAM (PRAM), magnetic RAM (MRAM), and resistance changeable RAM (RRAM) have been proposed. Such next-generation nonvolatile memory devices can operate at relatively low voltages and have fast access times, which significantly offsets the shortcomings of flash memory devices.

In particular, research on next-generation nonvolatile memory devices having a three-dimensional cross-point array structure has been actively conducted recently in response to high integration demands. The cross-point array structure is a structure in which a plurality of upper electrodes and a plurality of lower electrodes are arranged to intersect each other, and memory cells are arranged at the cross points of the upper and lower electrodes, so that random access to each memory cell is possible, making it easy to implement data storage (program) and reading (read).

Such a cross-point array structure can be easily formed into a three-dimensional structure by forming unit cells in a stacked structure along the vertical direction between the upper and lower electrodes, and stacking a plurality of single cross-point array structures along the vertical direction. Accordingly, next-generation non-volatile memory elements can be integrated at a high density.

The background technology of this application is disclosed in Patent Publication No. 10-2017-0108599.

The technical problem to be solved by the present invention is to provide a variable resistance memory device which minimizes the delay constant of the memory device by using a nano fiber material as the insulating layer, thereby improving the operating speed and reducing the amount of heat generated, and prevents a change in the composition of the phase change material layer by stacking a capping layer made of a metal material on the upper and lower portions of the variable resistor.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A method for manufacturing a variable resistance memory device according to one embodiment of the present invention includes a first step of forming a first insulating layer on a substrate, a second step of forming a first conductive line on the first insulating layer, a third step of forming a laminated structure including a lower electrode, a selection element, an intermediate electrode, a variable resistor, and an upper electrode that are sequentially laminated on the first conductive line, a fourth step of forming a second insulating layer between the laminated structures to cover sidewalls of the laminated structures, a fifth step of forming a second conductive line on the laminated structure, and a sixth step of subjecting the memory device manufactured by the first to fifth steps to a low-temperature treatment at a temperature of -270 degrees Celsius to -100 degrees Celsius for a predetermined period of time and then leaving it at room temperature for a predetermined period of time.

In the process of forming the lower electrode, the selection element, the middle electrode, the variable resistor, and the upper electrode in the third step, low-temperature treatment is performed at a temperature between -270 and -100 degrees.

The coolant used for the low-temperature treatment in the sixth step is any one of liquid nitrogen, liquid helium, liquid oxygen, and liquid hydrogen.

The memory element of the present invention is subjected to cryogenic treatment by being immersed in a coolant for 1 to 60 minutes, and after the cryogenic treatment is completed, is left at room temperature for 1 to 120 minutes, and through a process in which the temperature gradually increases, the crystals of the memory element are rearranged according to the increase in temperature, the stress inside the element is removed, and furthermore, the mobility of holes and electrons increases, so that the performance of the memory element can be improved.

FIG. 1 is a perspective view schematically illustrating a variable resistance memory element according to embodiments of the present invention.
FIG. 2 is a plan view showing a variable resistance memory element according to one embodiment of the present invention.
Figure 3 is a cross-sectional view taken along line I-I' of Figure 2.
FIG. 4 is a flowchart of a method for manufacturing a variable resistance memory element according to embodiments of the present invention.

The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and the present embodiments are provided only to make the disclosure of the present invention complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

In this specification, when it is said that an element is “on” another element, this includes not only cases where the element is in contact with the other element, but also cases where another element exists between the two elements. Also, in this specification, when it is said that a part “includes” a certain element, this does not mean that the other element is excluded, but rather that the other element can be included, unless otherwise specifically stated.

The terms “about,” “substantially,” and the like, as used throughout this specification, are used in a meaning that is at or near the numerical value when manufacturing and material tolerances inherent in the meanings referred to are presented, and are used to prevent unscrupulous infringers from unfairly exploiting the disclosure, which states precise or absolute values to aid understanding of this specification.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

FIG. 1 is a perspective view schematically illustrating a variable resistance memory element according to embodiments of the present invention.

Referring to FIG. 1, first conductive lines (CL1) extending in a first direction (D1) and second conductive lines (CL2) extending in a second direction (D2) intersecting the first direction (D1) may be provided. The second conductive lines (CL2) may be spaced apart from the first conductive lines (CL1) along a third direction (D3) perpendicular to the first direction (D1) and the second direction (D2). A memory cell stack (MCA) may be provided between the first conductive lines (CL1) and the second conductive lines (CL2). The memory cell stack (MCA) may include memory cells (MC) provided at each of the intersections of the first conductive lines (CL1) and the second conductive lines (CL2). The memory cells (MC) may be arranged two-dimensionally to form rows and columns. Although one memory cell stack (MCA) is illustrated in the present embodiment, embodiments of the present invention are not limited thereto. Memory cell stacks (MCAs) can be provided in multiples and stacked vertically.

Each of the memory cells (MC) may include a variable resistance pattern (VR) and a switching pattern (SW). The variable resistance pattern (VR) and the switching pattern (SW) may be connected in series with each other between a pair of conductive lines (CL1, CL2) connected thereto.

For example, a variable resistance pattern (VR) and a switching pattern (SW) included in each of the memory cells (MC) may be connected in series with each other between a corresponding first conductive line (CL1) and a corresponding second conductive line (CL2). Here, the first conductive line (CL1) may be a bit line, and the second conductive line (CL2) may be a word line, or vice versa. In addition, although FIG. 1 illustrates that the switching pattern (SW) is provided on the variable resistance pattern (VR), embodiments of the present invention are not limited thereto. Unlike FIG. 1, the variable resistance pattern (VR) may also be provided on the switching pattern (SW).

Voltage is applied to the variable resistance pattern (VR) of the memory cell (MC) through the first challenge line (CL1) and the second challenge line (CL2), so that current can flow through the variable resistance pattern (VR), and the resistance of the variable resistance pattern (VR) of the selected memory cell (MC) can change depending on the applied voltage.

According to the change in resistance of the variable resistance pattern (VR), the memory cell (MC) can store digital information such as "0" or "1", and the digital information can be erased from the memory cell (MC). For example, data can be written in the memory cell (MC) in a high resistance state "0" and a low resistance state "1". Here, writing from the high resistance state "0" to the low resistance state "1" can be called a "set operation", and writing from the low resistance state "1" to the high resistance state "0" can be called a "reset operation". However, the memory cell (MC) according to the embodiments of the present invention is not limited to the digital information of the exemplified high resistance state "0" and low resistance state "1", and can store various resistance states.

For example, the variable resistance pattern (VR) may include a transition metal oxide, in which case at least one electrical passage may be created or destroyed within the variable resistance pattern (VR) by a program operation. When the electrical passage is created, the variable resistance pattern (VR) may have a low resistance value, and when the electrical passage is destroyed, the variable resistance pattern (VR) may have a high resistance value. By utilizing the difference in resistance values of the variable resistance pattern (VR), the variable resistance memory element may store data.

As another example, the variable resistance pattern (VR) may include a phase change material layer that can reversibly transition between a first state and a second state. However, the variable resistance pattern (VR) is not limited thereto, and may include any variable resistor whose resistance value changes depending on an applied voltage.

The switching pattern (SW) may be a current control element capable of controlling the flow of current. In the present invention, the switching pattern (SW) may be a switching element having ovonic threshold switching (OTS) characteristics.

That is, the switching pattern (SW) may include a material having an ovonic threshold switching characteristic in which the resistance can change depending on the magnitude of the voltage applied to both ends of the switching pattern (SW). Accordingly, when a voltage smaller than the threshold voltage is applied to the switching pattern (SW), the switching pattern (SW) is in a high resistance state, and when a voltage larger than the threshold voltage is applied to the switching pattern (SW), it is in a low resistance state and current starts to flow. In addition, when the current flowing through the switching pattern (SW) becomes smaller than the holding current, the switching pattern (SW) can change to a high resistance state.

Any memory cell (MC) can be addressed by selecting a first challenge line (CL1) and a second challenge line (CL2), and by applying a predetermined signal between the first challenge line (CL1) and the second challenge line (CL2), the memory cell (MC) is programmed, and by measuring a current value through the first challenge line (CL1), information according to the resistance value of a variable resistor constituting the corresponding memory cell (MC) can be read.

Referring to FIGS. 2 and 3 below, a variable resistance memory element according to one embodiment of the present invention will be described.

FIG. 2 is a plan view showing a variable resistance memory element according to one embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along line I-I' of FIG. 2.

Referring to FIGS. 2 and 3, first conductive lines (CL1) and second conductive lines (200) may be sequentially provided on a substrate. The first conductive lines (CL1) may extend in a first direction (D1) substantially parallel to a top surface of the substrate (100) and may be spaced apart from each other in a second direction (D2) substantially parallel to the top surface of the substrate (100) and intersecting the first direction (D1). The second conductive lines (200) may extend in the second direction (D2) and be spaced apart from each other in the first direction (D1). The first conductive lines (CL1) and the second conductive lines (200) may be spaced apart from each other in a third direction (D3) perpendicular to the top surface of the substrate (100).

The substrate (100) may include a semiconductor substrate, such as a Si substrate, a Ge substrate, a Si-Ge substrate, a Silicon-on-Insulator (SOI) substrate, a Germanium-On-Insulator (GOI) substrate, etc. The substrate (100) may also include a III-V group compound, such as InP, GaP, GaAs, GaSb, etc. Meanwhile, although not shown, a p-type or n-type impurity may be injected into the upper portion of the substrate (100) to form a well.

Each of the first and second challenge lines (CL1, CL2) may include a metal (e.g., copper, tungsten, or aluminum) and/or a metal nitride (e.g., tantalum nitride, titanium nitride, or tungsten nitride).

A first insulating layer (101) may be interposed on the substrate (100). In this case, a first conductive line (102) may be formed on the first insulating layer (101). In addition, a peripheral circuit (not shown) including a transistor, a contact, a wiring, etc. may be formed on the substrate (100).

Memory cells (MC) may be arranged between first conductive lines (102) and second conductive lines (200), and may be located at intersections of the first conductive lines (102) and second conductive lines (200), respectively. The memory cells (MC) may be two-dimensionally arranged along a first direction (D1) and a second direction (D2). The memory cells (MC) may form one memory cell stack (MCA). For convenience of explanation, only one memory cell stack (MCA) is illustrated, but a plurality of memory cell stacks (MCAs) may be stacked on a substrate (100) along a third direction (D3). In this case, structures corresponding to the first conductive lines (102), the second conductive lines (200), and the memory cells (MC) may be repeatedly stacked on the substrate (100).

Each of the memory cells may include a stacked structure (ST), and the stacked structure (ST) may be connected in series between a pair of conductive lines (102, 200) connected thereto. In the present embodiment, the first and second conductive lines (102, 200), the variable resistor (180), and the selection element (135) may correspond to the first and second conductive lines (CL1, CL2), the variable resistor pattern (VR), and the switching pattern (SW) of FIG. 1.

The laminated structure (ST) may include a lower electrode (125), a selection element (135), a middle electrode (145), a variable resistor (180), and an upper electrode (195) that are sequentially laminated on a first challenge line (102).

The lower electrode (125) can be in contact with the upper surface of the first conductive line (102).

The selection element (135) may be placed on the lower electrode (125) in contact with the upper surface of the lower electrode (125), and the middle electrode (145) may be placed on the selection element (135) in contact with the upper surface of the selection element (135).

A variable resistor (180) and an upper electrode (195) can be laminated on the middle electrode (145).

In one embodiment of the present invention, the lower electrode (125), the middle electrode (145), and the upper electrode (195) may be formed of a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. At least one of the lower electrode (125), the middle electrode (145), and the upper electrode (195) may include a conductive film formed of a metal or a conductive metal nitride, and at least one conductive barrier film covering at least a portion of the conductive film. The conductive barrier film may be formed of, but is not limited to, a metal oxide, a metal nitride, or a combination thereof.

In one embodiment of the present invention, the upper electrode (195) or the middle electrode (145) may include a conductive material capable of generating sufficient heat to phase-change the variable resistor (180). For example, the upper electrode (195) or the middle electrode (145) may be made of a high-melting-point metal, such as TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, C, SiC, SiCN, CN, TiCN, TaCN, or a combination thereof, or a nitride thereof, or a carbon-based conductive material. Although not shown in the drawing, a heater electrode (not shown) may be interposed between the variable resistor (180) and the upper electrode (195), or between the variable resistor (180) and the middle electrode (145), and the heater electrode may include a conductive material capable of generating heat sufficient to phase-change the variable resistor (180). For example, the heater electrode (170) may be made of a high-melting-point metal, such as TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, C, SiC, SiCN, CN, TiCN, TaCN, or a combination thereof, or a nitride thereof, or a carbon-based conductive material.

The selection element (135) may be a current regulating element capable of controlling the flow of current. The selection element (135) may be, for example, a current regulating element having ovonic threshold switching (OTS) characteristics.

The selection element (135) may include a material whose resistance can change depending on the magnitude of the voltage applied across the selection element (135), and may include, for example, a material having an ovonic threshold switching characteristic. For example, when a voltage smaller than the threshold voltage is applied to the selection element (135), the selection element (135) is in a high resistance state, and when a voltage larger than the threshold voltage is applied to the selection element (135), it is in a low resistance state and current starts to flow. In addition, when the current flowing through the selection element (135) becomes smaller than the holding current, the selection element (135) may change to a high resistance state.

In one embodiment of the present invention, the selection element (135) can include silicon (Si), tellurium (Te), arsenic (As), germanium (Ge), indium (In), or a combination of these elements. For example, the selection element (135) can include silicon (Si) at a concentration of about 14%, tellurium (Te) at a concentration of about 39%, arsenic (As) at a concentration of about 37%, germanium (Ge) at a concentration of about 9%, and indium (In) at a concentration of about 1%.

Here, the percentage ratio is the atomic percentage ratio where the atomic components total 100%, and the same applies hereinafter. The selection element (135) may include silicon (Si), tellurium (Te), arsenic (As), germanium (Ge), sulfur (S), selenium (Se), or a combination of these elements. For example, the selection element (135) may include silicon (Si) at a concentration of about 5%, tellurium (Te) at a concentration of about 34%, arsenic (As) at a concentration of about 28%, germanium (Ge) at a concentration of about 11%, sulfur (S) at a concentration of about 21%, and selenium (Se) at a concentration of about 1%.

Furthermore, the selection element (135) may include silicon (Si), tellurium (Te), arsenic (As), germanium (Ge), sulfur (S), selenium (Se), antimony (Sb), or a combination of these elements. For example, the selection element (135) may include sulfur (S) at a concentration of about 2%, selenium (Se) at a concentration of about 50%, and antimony (Sb) at a concentration of about 2%.

In one embodiment of the present invention, the variable resistor (180) may include a phase change material that reversibly changes between an amorphous state and a crystalline state depending on a heating time. For example, the variable resistor (180) may include a material whose phase may be reversibly changed by Joule heat generated by a voltage applied to both ends of the variable resistor (180), and whose resistance may be changed by this phase change. Specifically, the phase change material may become a high resistance state in an amorphous phase, and a low resistance state in a crystalline phase. By defining a high resistance state as “0” and a low resistance state as “1”, data may be stored in the variable resistor (180).

In some embodiments of the present invention, the variable resistor (180) can include one or more elements (chalcogen elements) from Group VI of the Periodic Table and optionally one or more chemical modifiers from Groups III, IV or V. For example, the variable resistor (180) can include Ge-Sb-Te. The hyphenated chemical composition notation used herein indicates an element included in a particular mixture or compound and can represent any chemical formula structure that includes the indicated element. For example, Ge-Sb-Te can be a material such as Ge2Sb2Te5, Ge2Sb2Te7, Ge1Sb2Te4, Ge1Sb4Te7, etc.

The variable resistor (180) may include various phase change materials in addition to the aforementioned Ge-Sb-Te. For example, the variable resistor 180 may be Ge-Te, Sb-Te, In-Se, Ga-Sb, In-Sb, As-Te, Al-Te, Bi-Sb-Te(BST), In-Sb-Te(IST), Ge-Sb-Te, Te-Ge-As, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, In-Ge-Te, Ge-Sn-Te, Ge-Bi-Te, Ge-Te-Se, As-Sb-Te, Sn-Sb-Bi, Ge-Te-O, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, It may include at least one or a combination of Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, Ge-Te-Sn-Pt, In-Sn-Sb-Te, and As-Ge-Sb-Te.

Each element forming the variable resistor (180) may have a variety of chemical composition ratios (stoichiometry). Depending on the chemical composition ratio of each element, the crystallization temperature, melting temperature, phase change speed according to crystallization energy, and data retention characteristics of the variable resistor (180) may be controlled.

The variable resistor (180) may further include at least one impurity among carbon (C), nitrogen (N), silicon (Si), oxygen (O), bismuth (Bi), and tin (Sn). The driving current of the memory element may be changed by the impurity. In addition, the variable resistor (180) may further include a metal. For example, the variable resistor (180) may include at least one among aluminum (Al), gallium (Ga), zinc (Zn), titanium (Ti), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), ruthenium (Ru), palladium (Pd), hafnium (Hf), tantalum (Ta), iridium (Ir), platinum (Pt), zirconium (Zr), thallium (Tl), lead (Pd), and polonium (Po). These metal materials can increase the electrical conductivity and thermal conductivity of the variable resistor (180), thereby increasing the crystallization speed and thus increasing the set speed. In addition, the metal materials can improve the data retention characteristics of the variable resistor (180).

The variable resistor (180) may have a multilayer structure in which two or more layers having different properties are laminated. The number or thickness of the plurality of layers may be freely selected. A barrier layer may be further formed between the plurality of layers. The barrier layer may play a role in preventing material diffusion between the plurality of layers. That is, the barrier layer may reduce diffusion of a preceding layer when forming a subsequent layer among the plurality of layers.

In addition, the variable resistor (180) may have a super-lattice structure in which a plurality of layers including different materials are alternately laminated. For example, the variable resistor (180) may include a structure in which a first layer made of Ge-Te and a second layer made of Sb-Te are alternately laminated. However, the materials of the first layer and the second layer are not limited to Ge-Te and Sb-Te, and may each include various materials described above.

Above, a phase change material is exemplified as a variable resistor (180), but the technical idea of the present invention is not limited thereto. The variable resistor (180) of the memory element may include various materials having resistance change characteristics.

In some embodiments of the present invention, when the variable resistor (180) includes a transition metal oxide, the memory element may be a ReRAM (Resistive RAM). The variable resistor (180) including the transition metal oxide may have at least one electrical passage created or destroyed within the variable resistor (180) by a program operation. When the electrical passage is created, the variable resistor (180) may have a low resistance value, and when the electrical passage is destroyed, the variable resistor (180) may have a high resistance value. The memory element may store data by utilizing the difference in resistance value of the variable resistor (180).

When the variable resistor (180) is made of a transition metal oxide, the transition metal oxide may include at least one metal selected from Ta, Zr, Ti, Hf, Mn, Y, Ni, Co, Zn, Nb, Cu, Fe, or Cr. For example, the transition metal oxide may be made of a single layer or multiple layers made of at least one material selected from Ta2O5-x, ZrO2-x, TiO2-x, HfO2-x, MnO2-x, Y2O3-x, NiO1-y, Nb2O5-x, CuO1-y, or Fe2O3-x. In the exemplified materials, x and y may be selected within the ranges of 0≤x≤1.5 and 0≤y≤0.5, respectively, but are not limited thereto.

In other embodiments of the present invention, when the variable resistor (180) has a MTJ (Magnetic Tunnel Junction) structure including two electrodes made of a magnetic material and a dielectric interposed between the two magnetic material electrodes, the memory element can be an MRAM (Magnetic RAM).

The two electrodes may be a magnetized pinned layer and a magnetized free layer, respectively, and the dielectric interposed between them may be a tunnel barrier layer. The magnetized pinned layer may have a magnetization direction fixed in one direction, and the magnetized free layer may have a magnetization direction that can be changed to be parallel or antiparallel to the magnetization direction of the magnetized pinned layer. The magnetization directions of the magnetized pinned layer and the magnetized free layer may be parallel to one surface of the tunnel barrier layer, but is not limited thereto. The magnetization directions of the magnetized pinned layer and the magnetized free layer may be perpendicular to one surface of the tunnel barrier layer.

When the magnetization direction of the magnetized free layer is parallel to the magnetization direction of the magnetized fixed layer, the variable resistor (180) can have a first resistance value. On the other hand, when the magnetization direction of the magnetized free layer is anti-parallel to the magnetization direction of the magnetized fixed layer, the variable resistor (180) can have a second resistance value. The memory element can store data by utilizing the difference in these resistance values. The magnetization direction of the magnetized free layer can be changed by the spin torque of electrons in the program current.

The magnetized pinned layer and the magnetized free layer may include a magnetic material. In this case, the magnetized pinned layer may further include an antiferromagnetic material that fixes the magnetization direction of the ferromagnetic material in the magnetized pinned layer. The tunnel barrier may be formed of an oxide of any one material selected from Mg, Ti, Al, MgZn, and MgB, but is not limited to the examples.

A capping wall (105a, 105b) may be formed on the sidewalls of the variable resistor (180) and the selection element (135) of the memory element according to the present invention, and a second insulating layer (122) may be formed between the laminated structures (ST). The second insulating layer (122) may be formed to cover the sidewalls of the laminated structures (ST).

As an example of the present invention, the first insulating layer (101) and the second insulating layer (122) may include silicon nitride or silicon oxide.

In addition, the present invention can prevent a change in the composition of a phase change material layer by stacking a first capping layer (106a) made of a metal material between an intermediate electrode (145) and a variable resistor (180), and a second capping layer (106b) made of a metal material between a variable resistor (180) and an upper electrode (195), thereby ensuring the characteristics of a stable phase change memory device.

FIG. 4 is a flowchart of a method for manufacturing a variable resistance memory element according to embodiments of the present invention.

In Fig. 4, any parts that overlap with the previous explanation are omitted.

A method for manufacturing a memory device according to an embodiment of the present invention comprises: a first step (S11) of forming a first insulating layer (101) on a substrate; a second step (S12) of forming a first conductive line (102) on the first insulating layer (101); a third step (S13) of forming a laminated structure (ST) including a lower electrode (125), a selection element (135), an intermediate electrode (145), a variable resistor (180), and an upper electrode (195) sequentially laminated on the first conductive line (102); a fourth step (S14) of forming a second insulating layer (123) between the laminated structures (ST) to cover side walls of the laminated structures (ST); a fifth step (S15) of forming a second conductive line (200) on the laminated structure (ST); and a sixth step of subjecting the memory device manufactured by the first to fifth steps (S11 to S15) to a low-temperature treatment at a temperature between -270 degrees Celsius and -100 degrees Celsius for a predetermined period of time and then leaving it at room temperature for a predetermined period of time. It may include step (S16).

In step 6 (S16), the coolant used for low-temperature treatment may be any one of liquid nitrogen, liquid helium, liquid oxygen, and liquid hydrogen, and it is preferable to use liquid nitrogen or liquid helium that has high stability in a liquid state.

In addition, during the process of forming the lower electrode (125), selection element (135), middle electrode (145), variable resistor (180), and upper electrode (195) in the third stage, low-temperature treatment can be performed at a temperature between -270 and -100 degrees.

In step 6 (S16), the memory element is subjected to cryogenic treatment by being immersed in a coolant for 1 to 60 minutes, and after the cryogenic treatment is completed, it is left at room temperature for 1 to 120 minutes, and through a process in which the temperature gradually increases, the crystals of the memory element are rearranged according to the increase in temperature, the stress inside the element is removed, and furthermore, the mobility of holes and electrons increases, so that the performance of the memory element can be improved.

Although the embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features thereof. Therefore, it should be understood that the embodiments and application examples described above are exemplary in all respects and are not limiting.

Claims (3)

A first step of forming a first insulating layer on a substrate;
A second step of forming a first conductive line on the first insulating layer;
A third step of forming a laminated structure including a lower electrode, a selection element, an intermediate electrode, a variable resistor, and an upper electrode, which are sequentially laminated on the first challenge line;
A fourth step of forming a second insulating layer between the laminated structures to cover the side walls of the laminated structures;
Step 5 of forming a second challenge line on the laminated structure; and
A method for manufacturing a memory device, comprising a sixth step of subjecting the memory device manufactured through the first to fifth steps to a low-temperature treatment at a temperature between -270 degrees and -100 degrees for a predetermined period of time and then leaving it at room temperature for a predetermined period of time. In the first paragraph,
A method for manufacturing a memory element, characterized in that, in the process of forming the lower electrode, the selection element, the middle electrode, the variable resistor, and the upper electrode in the third step, low-temperature treatment is performed at a temperature between -270 and -100 degrees. In the second paragraph,
A method for manufacturing a memory element, characterized in that the coolant used for the low-temperature treatment in the sixth step is any one of liquid nitrogen, liquid helium, liquid oxygen, and liquid hydrogen.