KR20250034850A - Apparatus and method for encoding and decoding of data in communication or broadcasting system - Google Patents

Abstract

The present disclosure relates to a 5G or 6G communication system for supporting higher data transmission rates than a 4G communication system such as LTE.

Description

{APPARATUS AND METHOD FOR ENCODING AND DECODING OF DATA IN COMMUNICATION OR BROADCASTING SYSTEM}

The present disclosure relates to a method and device for encoding and decoding data in a communication or broadcasting system.

Looking back at the development process over the generations of wireless communication, technologies have been developed primarily for human-targeted services such as voice, multimedia, and data. After the commercialization of the 5G (5th Generation) communication system, it is expected that connected devices, which are increasing explosively, will be connected to the communication network. Examples of objects connected to the network include vehicles, robots, drones, home appliances, displays, smart sensors installed in various infrastructures, construction equipment, and factory equipment. Mobile devices are expected to evolve into various form factors such as augmented reality glasses, virtual reality headsets, and holographic devices. In the 6G (6th Generation) era, efforts are being made to develop an improved 6G communication system in order to connect hundreds of billions of devices and objects and provide various services. For this reason, the 6G communication system is called a system beyond 5G.

The maximum transmission speed in the 6G communication system, which is expected to be realized around 2030, is tera (i.e., 1,000 giga) bps (bits per second), and the wireless delay time is 100 microseconds (μsec). In other words, the transmission speed in the 6G communication system is 50 times faster than that of the 5G communication system, and the wireless delay time is reduced to one-tenth.

To achieve such high data rates and ultra-low latency, 6G communication systems are being considered for implementation in the terahertz (THz) band (e.g., from 95 gigahertz (GHz) to 3 terahertz (THz) band). Compared to the millimeter wave (mmWave) band introduced in 5G, the terahertz band is expected to have more serious path loss and atmospheric absorption phenomena, and thus the importance of technologies that can guarantee signal reach, or coverage, is expected to increase. Key technologies to ensure coverage include RF (Radio Frequency) components, antennas, new waveforms that are better than OFDM (Orthogonal Frequency Division Multiplexing) in terms of coverage, beamforming, and multiple antenna transmission technologies such as massive Multiple-Input and Multiple-Output (MIMO), Full Dimensional MIMO (FD-MIMO), array antennas, and large scale antennas. In addition, new technologies such as metamaterial-based lenses and antennas, high-dimensional spatial multiplexing technology using Orbital Angular Momentum (OAM), and Reconfigurable Intelligent Surfaces (RIS) are being discussed to improve the coverage of terahertz band signals.

In addition, in order to improve frequency efficiency and system network, 6G communication systems are being developed with full duplex technology that utilizes the same frequency resources at the same time for uplink and downlink, network technology that comprehensively utilizes satellites and HAPS (High-Altitude Platform Stations), network structure innovation technology that supports mobile base stations and enables optimization and automation of network operation, dynamic spectrum sharing technology through collision avoidance based on spectrum usage prediction, AI-based communication technology that utilizes AI (Artificial Intelligence) from the design stage and internalizes end-to-end AI support functions to realize system optimization, and next-generation distributed computing technology that realizes services with complexity that exceeds the limits of terminal computing capabilities by utilizing ultra-high-performance communication and computing resources (Mobile Edge Computing (MEC), cloud, etc.). In addition, efforts are being made to further strengthen connectivity between devices, further optimize networks, promote softwareization of network entities, and increase the openness of wireless communications by designing new protocols to be used in 6G communication systems, implementing hardware-based security environments, developing mechanisms for safe use of data, and developing technologies for maintaining privacy.

These research and developments in 6G communication systems are expected to enable the next hyper-connected experience through the hyper-connectivity of 6G communication systems that include not only connections between things but also connections between people and things. Specifically, 6G communication systems are expected to enable the provision of services such as truly immersive eXtended Reality (XR), high-fidelity mobile holograms, and digital replicas. In addition, services such as remote surgery, industrial automation, and emergency response through enhanced security and reliability will be provided through 6G communication systems, which will be applied in various fields such as industry, medicine, automobiles, and home appliances.

The present disclosure provides algebraic characteristics that a parity check matrix of an LDPC code must satisfy in order to reduce decoding latency and lower encoding complexity. In addition, an efficient encoding and decoding method and device using an LDPC code having the algebraic characteristics are provided.

The present disclosure provides algebraic characteristics that a parity check matrix of an LDPC code must satisfy in order to reduce a Block Error Rate (BLER). In addition, an efficient encoding and decoding method and device using an LDPC code having the algebraic characteristics are provided.

The present disclosure provides algebraic features that a parity check matrix of an LDPC code must satisfy by appropriately combining the above algebraic features to simultaneously reduce decoding latency, encoding complexity and BLER. In addition, an efficient encoding and decoding method and device using an LDPC code having the combined algebraic features are provided.

A data transmission method of a base station or a terminal in a communication system according to one embodiment of the present disclosure may include a step of LDPC encoding data based on a base matrix and/or a parity check matrix, a step of applying appropriate rate matching to the encoded data, a step of modulating the rate-matched encoded data, and a step of transmitting the modulated signal through a transmission device, wherein the base matrix or the parity check matrix or the weight matrix corresponding thereto is characterized in that it satisfies a specific algebraic condition.

In a communication system according to one embodiment of the present disclosure, a method for receiving data by a base station or a terminal may include the steps of receiving a modulated signal through a receiving device, performing demodulation to determine values for decoding based on the received signal, performing LDPC decoding based on the determined values and a base matrix and/or a parity check matrix, appropriately applying rate dematching to the LDPC decoded result, and determining data from the rate dematched result, wherein the base matrix or the parity check matrix or the weight matrix corresponding thereto is characterized in that it satisfies a specific algebraic condition.

According to the present disclosure, by providing algebraic characteristics of a parity check matrix for reducing latency and BLER, LDPC codes can be effectively supported for variable length and variable rate.

Figure 1 is a diagram of a systematic LDPC codeword structure.
Figure 2 is a diagram illustrating a method for representing a graph of an LDPC code.
Figure 3a is an example diagram explaining the cycle characteristics of a QC-LDPC code.
Figure 3b is an example diagram explaining the cycle characteristics of a QC-LDPC code.
FIG. 4 is a transmission block structure diagram according to an embodiment of the present disclosure.
FIG. 5 is an exemplary diagram of an LDPC encoding process according to an embodiment of the present disclosure.
FIG. 6 is an exemplary diagram of an LDPC decoding process according to an embodiment of the present disclosure.
FIG. 7 is a block diagram of a transmitter according to an embodiment of the present disclosure.
FIG. 8 is a block diagram of a receiving device according to an embodiment of the present disclosure.
FIG. 9 is a structural diagram of an LDPC decoding unit according to an embodiment of the present disclosure.
Figure 10 is an example diagram of the structure of a parity check matrix of an LDPC code.
FIG. 11a and FIG. 11b are examples of parity check matrices for LDPC codes satisfying the characteristics proposed in the present disclosure.

Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the attached drawings. In addition, when describing the present disclosure, if it is determined that a specific description of a related known function or configuration may unnecessarily obscure the gist of the present disclosure, the detailed description will be omitted. In addition, the terms described below are terms defined in consideration of the functions in the present disclosure, and these may vary depending on the intention or custom of the user or operator. Therefore, the definitions should be made based on the contents throughout this specification.

The main gist of the present disclosure can be applied to other systems having similar technical backgrounds with slight modifications within a scope that does not significantly deviate from the scope of the present disclosure, and this can be done at the discretion of a person skilled in the technical field of the present disclosure. For reference, a communication system is a term that generally includes the meaning of a broadcasting system, but in the present disclosure, if a broadcasting service is the main service among the communication systems, it can be more clearly named as a broadcasting system.

The advantages and features of the present disclosure, and the methods for achieving them, will become apparent by referring to the embodiments described in detail below together with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below and may be implemented in various different forms, and the embodiments are provided only to make the disclosure of the present disclosure complete and to fully inform those skilled in the art of the scope of the invention, and the present disclosure is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Low Density Parity Check (LDPC) codes, first introduced by Gallager in the 1960s, were long forgotten due to their complexity that was difficult to implement with the technology at the time. However, when the turbo code proposed by Berrou, Glavieux, and Thitimajshima in 1993 showed performance approaching the Shannon channel capacity, many analyses of the performance and characteristics of turbo codes were conducted, and many studies on iterative decoding and graph-based channel coding were conducted. This led to the re-study of LDPC codes in the late 1990s, and it was found that when decoding is performed by applying iterative decoding based on the sum-product algorithm on the Tanner graph corresponding to the LDPC code, the LDPC code also has performance approaching the Shannon channel capacity.

LDPC codes are generally defined by a parity-check matrix and can be represented using a bipartite graph, commonly referred to as a Tanner graph. In general, LDPC codes are a type of parity-check codes, and are called 'low-density' parity-check codes because they have the characteristic that the ratio of the number of 1s (i.e., density) in the parity-check matrix for very long cases is very low. Therefore, the techniques proposed in this disclosure based on LDPC codes for convenience can be easily extended to general parity-check matrix codes.

Figure 1 is a diagram illustrating a systematic LDPC codeword structure.

According to Fig. 1, a device that performs LDPC encoding receives an information word (102) composed of K _ldpc bits or symbols and performs encoding to generate a codeword (100) composed of N _ldpc bits or symbols. For the convenience of the following description, it is assumed that an information word (102) including K _ldpc bits is received and a codeword (100) composed of N _ldpc bits is generated. That is, an information word having K _ldpc input bits (102) When LDPC encoded, the codeword (100) is generated. That is, the information word and the code word are bit strings composed of a number of bits, and the information word bit and the code word bit mean each bit that constitutes the information word and the code word. Typically, the LDPC encoding bit

If it contains information words such as , it is called a systematic code. Here, is a parity bit (104), and the number of parity bits N _parity can be expressed as N _parity = N _ldpc - K _ldpc .

LDPC code is a type of linear block code and includes a process of determining a codeword that satisfies the condition in mathematical expression 1 below.

[Mathematical Formula 1]

Here, am.

는 패리티 검사 행렬(H)의 i번째 열(column)을 의미한다.In mathematical expression 1, H is a parity check matrix, c is a codeword, c _i is the i-th bit of the codeword, and N _ldpc is the LDPC codeword length.

represents the i-th column of the parity check matrix (H).

)과 i 번째 부호어 비트 c_i의 곱들의 합이 '0'이 됨을 의미하므로, i 번째 열(

)은 i 번째 부호어 비트 c_i와 관계가 있음을 의미한다.The parity check matrix H consists of N _ldpc columns, which is the same number of bits as the LDPC codeword. Mathematical expression 1 is the i-th column of the parity check matrix (

) and the i-th code word bit c _i means that the sum of the products is '0', so the i-th column (

) means that it is related to the i-th code word bit c _i .

Figure 2 is a diagram illustrating a method for representing a graph of an LDPC code.

Referring to Fig. 2, we will explain the graph representation method of LDPC codes.

Fig. 2 is a diagram illustrating an example of a parity check matrix H ₁ of an LDPC code consisting of 4 rows and 8 columns and its representation as a Tanner graph. Referring to Fig. 2, since the parity check matrix H ₁ has 8 columns, a codeword of length 8 is generated, and the code generated through H ₁ means an LDPC code, and each column corresponds to 8 encoded bits.

Referring to Fig. 2, the Tanner graph of an LDPC code that encodes and decodes based on a parity check matrix H ₁ consists of eight variable nodes, namely x ₁ (202), x ₂ (204), x ₃ (206), x ₄ (208), x ₅ (210), x ₆ (212), x ₇ (214), x ₈ (216), and four check nodes (218, 220, 222, 224). Here, the i-th column and the j-th row of the parity check matrix H ₁ of the LDPC code correspond to the variable node x _i and the j-th check node, respectively. In addition, the meaning of the value of 1, that is, a non-zero value, at the point where the ith column and the jth row of the parity check matrix H ₁ of the LDPC code intersect means that there is an edge connecting the variable node x _i and the jth check node on the Tanner graph, as shown in Fig. 2.

In the Tanner graph of an LDPC code, the degree of a variable node and a check node refers to the number of segments connected to each node, which is equal to the number of non-zero elements (entries) in the column or row corresponding to the corresponding node in the parity check matrix of the LDPC code. For example, in Fig. 2, the degrees of variable nodes x ₁ (202), x ₂ (204), x ₃ (206), x ₄ (208), x ₅ (210), x ₆ (212), x ₇ (214), and x ₈ (216) are 4, 3, 3, 3, 2, 2, 2, 2, respectively, and the degrees of check nodes (218, 220, 222, 224) are 6, 5, 5, 5, respectively. Also, the number of non-zero elements in each column of the parity check matrix H ₁ of FIG. 2 corresponding to the variable nodes of FIG. 2 is identical to the degrees of the above-described variable nodes, which are 4, 3, 3, 3, 2, 2, 2, 2, in that order, and the number of non-zero elements in each row of the parity check matrix H ₁ of FIG. 2 corresponding to the check nodes of FIG. 2 is identical to the degrees of the above-described check nodes, which are 6, 5, 5, 5, in that order. For this reason, the degree of each variable node is also called the column degree or column weight, and the degree of a check node is also called the row degree or row weight.

LDPC encoded codeword bits can be decoded based on an iterative decoding algorithm based on a sum-product algorithm on a bipartite graph as listed in Fig. 2. Here, the sum-product algorithm is a type of message passing algorithm, and the message passing algorithm represents an algorithm that exchanges messages through edges on a bipartite graph and calculates and updates an output message from messages input to a variable node or a test node.

Here, the value of the ith coding bit can be determined based on the message of the ith variable node. Both hard decision and soft decision are possible methods for determining the value of the ith coding bit. Therefore, the performance of the ith bit c _i of the LDPC codeword corresponds to the performance of the ith variable node of the Tanner graph, which can be determined by the position and number of 1s in the ith column of the parity check matrix. In other words, the performance of the N _ldpc codeword bits of the codeword can be affected by the position and number of 1s in the parity check matrix, which means that the performance of the LDPC code is greatly affected by the parity check matrix. Therefore, in order to design an LDPC code with excellent performance, a method for designing a good parity check matrix is required.

The parity check matrix used in communication and broadcasting systems is usually a quasi-cyclic LDPC code (or QC-LDPC code, hereinafter referred to as QC-LDPC code) that uses a quasi-cyclic form of the parity check matrix for ease of implementation. Depending on the communication and broadcasting system, there are cases where a parity check matrix that has a structure that is not a complete quasi-cyclic structure but is almost similar to a quasi-cyclic structure is used. Such LDPC codes may not be strictly classified as QC-LDPC codes in terms of algebra, but are sometimes categorized as QC-LDPC codes for convenience.

A typical QC-LDPC code is characterized by having a parity check matrix composed of zero matrices or circulant permutation matrices in the form of small square matrices. In this case, a permutation matrix means a matrix in which each row or column contains only one 1, and all remaining elements are 0. In addition, a circulant permutation matrix means a matrix in which each element of an identity matrix is circulatively shifted to the right or left. In general, the identity matrix itself is also included in a circulant permutation matrix, because each element of the identity matrix is considered to be circulantly shifted 0 times. Therefore, a circulant permutation matrix basically includes an identity matrix, but for the convenience of explanation, an identity matrix and a circulant permutation matrix that is not an identity matrix can be expressed by distinguishing between them.

Below, we describe the QC-LDPC code in detail.

크기의 순환 순열 행렬

을 정의한다. 여기서

는 행렬 상기 행렬 P에서의 i번째 행(row), j번째 열(column)의 원소(entry)를 의미한다.(

)First, as in mathematical formula 2,

Circular permutation matrix of size

is defined here.

means the entry of the i-th row and j-th column in the matrix P above. (

)

[Mathematical expression 2-1]

(0 ≤ i < Z)는

크기의 항등 행렬(identity matrix)의 각 원소들을 i번 만큼 오른쪽 방향으로 순환 이동(circular shift) 시킨 형태의 순환 순열 행렬이다. 순환 순열 행렬은 [수학식 2-2]와 같이 정의될 수도 있는데, 이 경우에는

가

크기의 항등 행렬의 각 원소들을 i번 만큼 왼쪽 방향으로 순환 이동시킨 형태의 순환 순열 행렬이다:For the permutation matrix P defined as above,

(0 ≤ i < Z)

It is a cyclic permutation matrix in the form of a circular shift of each element of the identity matrix of size i to the right. The cyclic permutation matrix can also be defined as in [Mathematical Formula 2-2], in which case

go

It is a cyclic permutation matrix in the form of each element of the identity matrix of size shifted to the left by i times:

[Mathematical expression 2-2]

In the present disclosure, for convenience, various embodiments are described using a cyclic permutation matrix defined based on [Mathematical Formula 2-1]. However, the cyclic permutation matrices defined in [Mathematical Formula 2-1] and [Mathematical Formula 2-2] have the same basic algebraic properties, although their expressions are different. Therefore, a cyclic permutation matrix defined based on Mathematical Formula 2-2 may be used in the embodiments of the present disclosure, or various types of cyclic permutation matrices having the same algebraic properties may be used.

The parity check matrix H of the simplest QC-LDPC code can be expressed in the following mathematical formula 3.

[Mathematical Formula 3]

을

크기의 0-행렬이라 정의할 경우, 상기 수학식 3에서 순환 순열 행렬 또는 0-행렬의 각 지수

는 {-1, 0, 1, 2, ..., Z-1} 값 중에 하나를 갖는다. 항등 행렬은

또는

로 표현될 수 있으며 0-행렬은

또는 로 표현될 수 있다. 또한 상기 수학식 3의 패리티 검사 행렬 H는 열 블록(column block)이

개, 행 블록 (row block)이

개이므로, 상기 패리티 검사 행렬 H의 크기는

이다.For convenience

second

When defined as a 0-matrix of size , each index of the cyclic permutation matrix or 0-matrix in the above mathematical expression 3

has one of the values {-1, 0, 1, 2, ..., Z-1}. The identity matrix is

or

can be expressed as , and the 0-matrix is

or can be expressed as. In addition, the parity check matrix H of the above mathematical expression 3 is a column block.

Dog, row block

Since it is a dog, the size of the above parity check matrix H is

am.

이다. 편의상 정보어 비트에 대응되는

개의 열 블록을 정보어 열 블록이라 부르고 정보어 비트 수는

, 나머지 패리티 비트에 대응되는

개의 열 블록을 패리티 열 블록이라 부를 수 있다. 이 때, 패리티 비트 수는

이다. 참고로 상기 수학식 3의 패리티 검사 행렬이 최대 랭크를 갖지 않을 경우에는 상기 정보어 비트는

보다 크며, 정보어 비트 수는

보다 큰 값을, 패리티 비트 수는

보다 작은 값을 갖는다.If the parity check matrix of the above mathematical expression 3 has the maximum rank (full rank, or complete coefficient), the length of the information word bit of the QC-LDPC code corresponding to the parity check matrix is

For convenience, it corresponds to the information word bit.

The ten blocks of a dog are called information word ten blocks and the number of information word bits is

, corresponding to the remaining parity bits.

The ten blocks of the dog can be called parity ten blocks. In this case, the number of parity bits is

For reference, if the parity check matrix of the above mathematical expression 3 does not have the maximum rank, the above information bits

is larger, and the number of information bits is

The larger the value, the more parity bits

has a smaller value.

크기의 이진(binary) 행렬을 패리티 검사 행렬 H의 모행렬(mother matrix) 또는 기본 행렬 (base matrix) 또는 기본 그래프 (base graph)라 하고 M(H) 또는

라 표현한다. 또한 각 순환 순열 행렬 또는 0-행렬의 지수를 선택하여 수학식 4와 같이 얻은

크기의 정수 행렬을 패리티 검사 행렬 H의 지수 행렬 (exponent matrix)

라 한다.Typically, each cyclic permutation matrix and 0-matrix in the parity check matrix of the above mathematical expression 3 are replaced with 1 and 0, respectively.

A binary matrix of size H is called the mother matrix or base matrix or base graph of the parity check matrix H, and M(H) or

It is expressed as . Also, by selecting the index of each cyclic permutation matrix or 0-matrix, it is obtained as in mathematical formula 4.

An integer matrix of size H is the exponent matrix of the parity check matrix H.

It is said.

[Mathematical Formula 4]

를 다른 명칭으로 부를 수 있다. 예를 들어, 각 순환 순열 행렬의 지수는 [수학식 2-1] 또는 [수학식 2-2]와 같이 항등 행렬을 순환 이동시키는 값에 대응되므로, 각 지수를 순환 이동 값 (shift value or circular shift value))라 하고,

를 순환 이동 값 행렬 (circular shift value matrix) 또는 이동 값 행렬(shift value matrix)이라 부를 수도 있다. 일반적으로 지수 행렬 또는 이동 값 행렬과 순환 순열 행렬 또는 0-행렬의 크기에 대응되는

값이 주어져 있을 경우에 패리티 검사 행렬이 결정 (determine) 또는 확인(identify)될 수 있다. 이러한 이유로 수학적 정의에 따르면 패리티 검사 행렬은 수학식 1의 조건을 만족하는 이진 행렬 H를 의미하지만, 경우에 따라서는 편의상 지수 행렬 또는 이동 값 행렬을 패리티 검사 행렬이라 명명할 수도 있다.Of course, the names of these matrices are just examples and are exponential matrices.

can be called by different names. For example, since the indices of each cyclic permutation matrix correspond to values that circularly shift the identity matrix, as in [Mathematical Formula 2-1] or [Mathematical Formula 2-2], each indices is called a circular shift value (or circular shift value).

It can also be called a circular shift value matrix or shift value matrix. It is generally a matrix of exponents or shift value matrix and a circular permutation matrix or 0-matrix corresponding in size to the

Given a value, a parity check matrix can be determined or identified. For this reason, according to the mathematical definition, a parity check matrix means a binary matrix H that satisfies the condition of Equation 1, but in some cases, an exponential matrix or a shift value matrix can be conveniently named a parity check matrix.

Since one integer included in an exponential matrix or a shift value matrix corresponds to a cyclic permutation matrix in a parity check matrix, the exponential matrix may be conveniently expressed as a sequence of integers. In general, a parity check matrix can be expressed not only as an exponential matrix but also as various sequences that can express algebraically identical characteristics. In the present disclosure, for convenience, the parity check matrix is expressed as a sequence indicating the position of 1 in an exponential matrix or a parity check matrix, but since there are various sequence notations that can distinguish the positions of 1 or 0 included in a parity check matrix, it is not limited to the method expressed in this specification and can be expressed in the form of various sequences or matrices that exhibit the algebraically identical effect. The sequence may be called in various ways, such as an LDPC sequence, an LDPC code sequence, an LDPC sequence, a parity check matrix sequence, or a (cyclic) shift value sequence, in order to distinguish it from other sequences.

Also, a transceiver may perform LDPC encoding and decoding by directly generating a parity check matrix, but depending on the implementation characteristics, LDPC encoding and decoding may also be performed based on an exponential matrix, a shift value matrix, or a sequence that has the same effect algebraically as the parity check matrix. Therefore, although encoding and decoding using a parity check matrix is described for convenience in this disclosure, an actual transceiver may implement encoding and decoding through various methods that can obtain the same effect as the parity check matrix.

For reference, the algebraically identical effect means that two or more different representations can be explained or converted as being completely identical to each other logically or mathematically. In particular, in the case of codes that can be defined by matrices such as LDPC codes, it can mean that algebraic values that can be defined by matrices, such as minimum distance, rank, and cycle characteristics on Tanner graphs, are identical, and it can also mean that the basic structure or operation in the encoding/decoding process is identical. For example, if the same matrix is obtained through appropriate column permutation and row permutation, the two matrices can be viewed as algebraically identical matrices from a code perspective. In addition, various transpose transformations that do not change the characteristics of the actual code can also provide algebraically identical effects.

As a concrete example, given a matrix A such as the following, examples of various transformations that provide algebraically identical effects are given in A1 through A8.

는

와 서로 소인 정수) , (step,

Is

and coprime integers)

은

의 두번째 열블록과 세번째 열블록을 치환한 블록 단위 순열의 예시이다.

은

에 추가로 첫번째 행블록과 세번째 행블록을 치환한 블록 단위 순열의 예시이다.

은

의 첫번째 열블록과 세번째 열블록에 대해서만 각각 순환 순열을 적용한 예시이다.

는

에 추가로 두번째 행블록과 네번째 행블록에 대해서만 각각 순환 순열을 적용한 예시이다.

는

에 대해 전치 변환(transpose)을 적용한 예시이다.

은

에 대해 블록 단위의 전치 변환을 적용한 예시이다.

은

에 대해 각 지수(또는 순환 이동 값)들의 부호를 반대로 변환한 예시이다 (단, 편의상

크기의 0-행렬을

로 표현하는 경우에 음수의 지수(또는 이동 값) 사용은 혼동을 줄 수 있으므로,

는

와 같이 양수 값으로 표현될 수도 있다).

은

에 대해 상수항이 0인 아핀(affine) 변환을 적용한 예시이다 (일반적으로 상수항이 0이 아닌 경우도 적용 가능하다). 참고로 위의 예들은 편의상

가

크기의 0-행렬인 원소가 없는 경우에 대해 설명하였지만, 0-행렬이 포함되었을 경우에, 0-행렬에 대응되는 부분은 변환과 상관없이 항상 0-행렬이다. 예를 들어,

에서

가 0-행렬이라면,

,

및

에서도

는 0-행렬이며,

및

에서 각각

및

는 0-행렬이며,

및

에서

는 0-행렬이며,

에서

은 0-행렬이다.

silver

This is an example of a block-by-block permutation that permutes the second and third row blocks.

silver

In addition, here is an example of a block-by-block permutation where the first and third row blocks are permuted.

silver

This is an example where cyclic permutation is applied only to the first and third column blocks.

Is

In addition, here is an example where the cyclic permutation is applied only to the second and fourth row blocks.

Is

This is an example of applying transpose to .

silver

This is an example of applying block-wise transposition transformation.

silver

Here is an example of reversing the signs of each index (or cyclic shift value) (for convenience only)

A 0-matrix of size

When expressing as , using negative exponents (or shift values) can be confusing, so

Is

) can also be expressed as a positive value, such as .

silver

This is an example of applying an affine transformation with a constant term of 0 (it can also be applied to cases where the constant term is not 0 in general). For reference, the above examples are for convenience.

go

Although we have described the case where there are no elements that are 0-matrix of size 0, when a 0-matrix is included, the part corresponding to the 0-matrix is always a 0-matrix regardless of the transformation. For example,

at

If is a 0-matrix,

,

and

In , too

is a 0-matrix,

and

In each

and

is a 0-matrix,

and

at

is a 0-matrix,

at

is a 0-matrix.

Each of the above transformations is only an example, and various other transformations may exist. In addition, each transformation can be applied independently, but can also be applied in an appropriate overlapping and combined manner. Here, the characteristic of each transformation or combination of transformations can be converted into the original matrix through an appropriate invertible transform process.

The above various transformations or combinations of transformations are essentially reversible transformations in which the arrangement of bits (or variable nodes) or check nodes on the Tanner graph is simply changed, or symmetric transformations or specific structures are maintained, so that in terms of the performance of the code, the instantaneous performance may vary depending on the given channel conditions, but the average performance can be provided. In this way, in the present disclosure, all parity check matrices that can be obtained through transformations that can obtain the algebraically identical effect are regarded as the same parity check matrix.

크기의 정사각 블록에 대응되는 순환 순열 행렬이 1 개인 경우만 설명하였으나, 이하 하나의 블록에 복수 개의 순환 순열 행렬이 포함된 경우에도 동일한 발명이 적용될 수 있다. 예를 들어 다음 수학식 5와 같이 하나의 i 번째 행 블록 및 j 번째 열 블록의 위치에 2 개의 순환 순열 행렬 , 가 대응될 때, 간단히 와 같은 합 형태로 표현될 수 있으며, 그 지수 행렬(또는 순환 이동 값 행렬)은 수학식 6과 같이 나타낼 수 있다. 상기 수학식 6을 살펴보면, 상기 복수 개의 순환 순열 행렬 합이 포함된 행 블록 및 열 블록에 대응되는 i번째 행 및 j번째 열에 2개의 정수가 대응되는 행렬임을 알 수 있다.For convenience, one

Although only one cyclic permutation matrix corresponding to a square block of size has been described, the same invention can be applied to a case where multiple cyclic permutation matrices are included in one block. For example, as in the following mathematical expression 5, two cyclic permutation matrices are included in the position of one i-th row block and one j-th column block. , When it corresponds, simply It can be expressed in the form of a sum such as , and its exponential matrix (or cyclic shift value matrix) can be expressed as in mathematical expression 6. Looking at mathematical expression 6, it can be seen that it is a matrix in which two integers correspond to the i-th row and j-th column corresponding to the row block and column block including the sum of the plurality of cyclic permutation matrices.

[Mathematical Formula 5]

[Mathematical Formula 6]

크기의 행렬을 순환 행렬(circulant 또는 circulant matrix 또는 circular matrix)이라 한다. 일반적으로 순환 행렬은 행렬의 각 원소(entry)들이 이진수뿐만 아니라 임의의 수를 원소로 갖지만, 본 개시에서는 편의상 이진 부호에 대해서 설명하기 때문에 상기 순환 행렬은 이진 순환 행렬을 의미한다. 물론 본 개시에서 제안하는 대수적인 구조 및 특징들은 비이진 (non-binary) 부호의 경우에도 유사한 방식으로 확장할 수 있지만, 본 개시에서 상세한 내용은 생략한다.As in the above embodiment, in general, QC-LDPC codes can correspond to one or more cyclic permutation matrices in one row block and one column block in the parity check matrix, and for reference, multiple cyclic permutation matrices are duplicated in one row block and one column block.

A matrix of the size of is called a circulant matrix (or circulant matrix or circular matrix). In general, each element (entry) of a circulant matrix has not only binary numbers but also arbitrary numbers as elements, but in this disclosure, since a binary code is described for convenience, the circulant matrix means a binary circulant matrix. Of course, the algebraic structure and features proposed in this disclosure can be extended in a similar manner to the case of non-binary codes, but details are omitted in this disclosure.

Meanwhile, the basic matrix (or parent matrix or basic graph) for the parity check matrix and the index matrix (or cyclic shift value matrix) of the above mathematical expressions 5 and 6 means a binary matrix obtained by replacing each cyclic permutation matrix and 0-matrix with 1 and 0, respectively, similar to the definition used in the above mathematical expression 3, and a cyclic matrix included in one block (i.e., a sum of multiple cyclic permutation matrices) can also be replaced with 1.

A simple example of the relationship between a parity check matrix, an exponential matrix (or a cyclic shift matrix), a fundamental matrix, etc. is shown in the following [Mathematical Formula 7].

[Mathematical formula 7]

크기의 0-행렬의 지수를 (또는 이동 값을) -1로 표기한 것은 일례일 뿐이며, 다양한 방식으로 표현 가능하다. 또한 상기 [수학식 7]의 행렬 표현 방식은 다양한 다른 방법을 통해 표기 가능한데, 구체적인 예로서 3GPP 5G 표준 규격인 3GPP TS 38.212에서 정의된 LDPC 부호의 패리티 검사 행렬의 표현 방법을 사용할 수도 있다. 3GPP TS 38.212에서는 BG1 (Base Graph 1) 및 BG2 (Base Graph 2)에 대응되는 LDPC 부호의 패리티 검사 행렬들의 크기가 너무 크기 때문에 표를 이용하여 나타내었는데, 상기 [수학식 7]의 행렬들에 대해 해당 표현 방식을 적용해 보면 다음 [표 1]과 같다.In the above [Mathematical Formula 7]

It is only an example that the index of a 0-matrix of size (or a shift value) is represented as -1, and it can be expressed in various ways. In addition, the matrix representation method of the above [Mathematical Formula 7] can be represented in various other ways, and as a specific example, the representation method of the parity check matrix of the LDPC code defined in 3GPP TS 38.212, which is a 3GPP 5G standard specification, can be used. In 3GPP TS 38.212, the sizes of the parity check matrices of the LDPC code corresponding to BG1 (Base Graph 1) and BG2 (Base Graph 2) are too large, so they are represented using a table. When the corresponding representation method is applied to the matrices of the above [Mathematical Formula 7], the result is as shown in the following [Table 1].

는

크기의 행렬이며,

은

크기의 행렬이다. 다음 표 1에서 표현되지 않은 기본 행렬 (또는 기본 그래프) 및 패리티 검사 행렬들의 원소(entry)들은 0 또는

크기의 0-행렬이 대응된다.

Is

is a matrix of size,

silver

is a matrix of size. The entries of the basic matrix (or basic graph) and parity check matrices not expressed in Table 1 below are 0 or

A 0-matrix of size 0 corresponds.

[Table 1]

If the basic matrix and exponential matrix in the above [Mathematical Formula 7] are expressed using a sequence, they can be expressed in the following manner.

:

:

0 2 3

0 1 3 4

1 2 4 5

0 1 2 5

:

:

159 0 0

117 109 0 0

225 1 0 0

84 211 0 0

를 수열로 표현했을 경우에 편의 상 시프트 수열 (shift sequence) 또는 시프트 값 수열 (shift value sequence), LDPC 수열 등과 같이 다양한 방식으로 명명할 수도 있다. 위의 수열 표현 방식에서

는 원소가 0가 아닌 열의 위치를 각 행 별로 나열한 방식이며,

는 0-행렬이 아닌 각 순환 순열 행렬의 지수 또는 이동 값을 각 행 별로 나열한 방식이다. 위의 수열들로부터 지수 행렬 (또는 이동 값 행렬)이 정확히 정의될 수 있으며, 만일

값에 대한 정보를 획득한다면, 패리티 검사 행렬 또한 정확히 정의될 수 있다.Exponential matrix as above

When expressed as a sequence, it can be conveniently named in various ways, such as shift sequence, shift value sequence, LDPC sequence, etc. In the above sequence expression method,

is a method of listing the positions of columns where the elements are not 0 for each row.

is a method of listing the indices or shift values of each cyclic permutation matrix, not a 0-matrix, for each row. From the above sequences, the index matrix (or shift value matrix) can be defined exactly, and if

If we obtain information about the values, the parity check matrix can also be defined exactly.

크기 블록에 2개 이상의 순환 순열 행렬이 대응되는 순환 행렬을 포함하는 경우를 도시한다.Another simple example of the relationship between the parity check matrix and the exponential matrix (or cyclic shift matrix), the fundamental matrix, etc. is given in the following [Mathematical Equation 8]. In the example of [Mathematical Equation 8], at least one

It illustrates a case where a block of size contains a circulant matrix corresponding to two or more circulant permutation matrices.

[Mathematical formula 8]

는 기본 행렬 또는 지수 행렬 또는 패리티 검사 행렬에 대한 무게 행렬(Weight Matrix)이며, 기본 행렬 및 지수 행렬에서 i번째 행, j번째 열, 또는 패리티 검사 행렬에서 i번째 행 블록, j번째 열 블록에 몇 개의 순환 순열 행렬이 대응되는지를 표현하는 행렬이다. 예를 들어,

는 패리티 검사 행렬에서 i번째 행 블록, j번째 열 블록에 대응되는

크기의 순환 행렬을 구성하는 순환 순열 행렬의 개수를 i번째 행, j번째 열의 원소로 나타낸 행렬을 의미한다. 즉,

는 0-행렬이 대응될 경우에는 0을, w개의 순환 순열 행렬이 대응되는 경우에 w를 각각 원소로 표현하는 행렬이다. (참고로, 0-행렬은 넓은 의미에서 순환 행렬로 볼 수 있으나, 순환 '순열' 행렬은 아니다.)For reference, in the above [Mathematical Formula 8]

is a weight matrix for the fundamental matrix, exponential matrix, or parity check matrix, and is a matrix expressing how many cyclic permutation matrices correspond to the i-th row, j-th column in the fundamental matrix and exponential matrix, or the i-th row block, j-th column block in the parity check matrix. For example,

corresponds to the i-th row block and the j-th column block in the parity check matrix.

It means a matrix that represents the number of circulant permutation matrices that constitute a circulant matrix of size as an element of the i-th row and j-th column. That is,

is a matrix that represents 0 as an element when 0-matrices correspond, and w as an element when w cyclic permutation matrices correspond. (Note that 0-matrix can be viewed as a cyclic matrix in a broad sense, but it is not a cyclic 'permutation' matrix.)

If the basic matrix or parity check matrix or circular shift value matrix (or exponential matrix) defined in [Mathematical Formula 8] is expressed by applying the method of expressing parity check matrices of LDPC codes in 3GPP TS 38.212 as in [Table 1], it can be expressed as in the following [Table 2].

는

크기의 행렬이며,

은

크기의 행렬이다. 다음 표 2에서 표현되지 않은 기본 행렬 (또는 기본 그래프) 및 패리티 검사 행렬들의 원소들은 0 또는

크기의 0-행렬이 대응된다.

Is

is a matrix of size,

silver

is a matrix of size . The elements of the basic matrix (or basic graph) and parity check matrix not expressed in Table 2 below are 0 or

A 0-matrix of size 0 corresponds.

[Table 2]

If the basic matrix and exponential matrix of the above [Mathematical Formula 8] are expressed using a sequence, they can be expressed in the following manner.

:

:

0 1 2 3

0 1 2 3

:

:

(117, 159) 109 0 0

84 (211, 225) (1, 3) 0

As another way of expressing it, we can use a weight matrix to express it in a form consisting only of a sequence, as follows:

:

:

0 1 2 3

0 1 2 3

:

:

2 1 1 1

1 2 2 1

:

:

117 159 109 0 0

84 211 225 1 3 0

는 원소가 0가 아닌 열의 위치를 각 행 별로 나열한 방식이며,

는 기본 행렬 또는 지수 행렬 또는 패리티 검사 행렬에 대응되는 순환 행렬들을 구성하는 순환 순열 행렬의 개수에 기반하여 정의되는 행렬이며,

는 0-행렬이 아닌 각 순환 행렬의 지수 또는 이동 값들을 각 행 별로 나열한 방식이다. 위의 수열들로부터 지수 행렬이 정확히 정의될 수 있으며, 만일

값에 대한 정보를 획득한다면, 패리티 검사 행렬 또한 정확히 정의될 수 있다.In the above expression

is a method of listing the positions of columns where the elements are not 0 for each row.

is a matrix defined based on the number of circulant permutation matrices that constitute circulant matrices corresponding to the fundamental matrix, the exponential matrix, or the parity check matrix.

is a method of listing the indices or shift values of each circulant matrix, not a 0-matrix, for each row. The exponential matrix can be defined exactly from the above sequences, and if

If we obtain information about the values, the parity check matrix can also be defined exactly.

Since the performance of an LDPC code is determined by the parity check matrix, it is necessary to design a parity check matrix for an LDPC code with excellent performance. In addition, an LDPC encoding or decoding method that can support various input lengths and code rates is required.

Lifting can be used not only for the efficient design of QC-LDPC codes, but can also mean a method for generating parity check matrices of various lengths or generating LDPC codewords using given base matrices and exponent matrices. That is, the lifting can be applied to efficiently design a very large parity check matrix by setting the Z value, which determines the size of a cyclic permutation matrix or a 0-matrix from a given small parent matrix, according to a specific rule, or can mean a method for generating parity check matrices of various lengths or generating LDPC codewords by applying an appropriate Z value to a given exponent matrix or its corresponding sequence.

The characteristics of the existing lifting method and the QC-LDPC code designed through lifting are briefly explained with reference to the following reference [Myung2006].

Reference [Myung2006]

S. Myung, K. Yang, and Y. Kim, “Lifting Methods for Quasi-Cyclic LDPC Codes,” IEEE Communications Letters. vol. 10, pp. 489-491, June 2006.

는

크기의 지수 행렬 을 가지며 각 지수 들은 {-1, 0, 1, 2, ..., Z_k - 1} 값 중에 하나로 선택된다.First, when an LDPC code C ₀ is given, S QC-LDPC codes to be designed by the lifting method are C ₁ , ..., C _S , and the values corresponding to the sizes of the row blocks and column blocks of the parity check matrix of each QC-LDPC code are L _k . Here, C ₀ corresponds to the smallest LDPC code that has the parent matrix of the C ₁ , ..., C _S codes as the parity check matrix, and the value Z ₀ corresponding to the size of the row blocks and column blocks is 1. In addition, for convenience, the parity check matrix of each code C _k

Is

exponential matrix of size and each index are chosen as one of the values {-1, 0, 1, 2, ..., Z _k - 1}.

만 저장하고 있으면 리프팅 방식에 따라 다음 수학식 9 또는 수학식 10을 이용하여 상기 QC-LDPC 부호 C₀, C₁, ..., C_S를 모두 나타낼 수 있다.The existing lifting method consists of steps such as C ₀ -> C ₁ ->...-> C _S and has the characteristic of satisfying the condition such as Z _k+1 = q _k+1 Z _k (q _k+1 is a positive integer, k=0,1,..., S-1). In addition, the parity check matrix of C _s is

If only storing is performed, all of the above QC-LDPC codes C ₀ , C ₁ , ..., C _S can be represented using the following mathematical expressions 9 or 10 depending on the lifting method.

[Mathematical formula 9]

or

[Mathematical Formula 10]

In addition to the method of designing larger QC-LDPC codes C ₁ , ..., C _S from C ₀ , the method of generating smaller codes C _i (i=k-1, k-2, ..., 1, 0) from larger codes C _k using an appropriate method, such as Equation 9 or Equation 10, can also be called lifting. For reference, in 3GPP TS 38.212, LDPC codes of various lengths can be generated using the lifting method of Equation 10.

The lifting method of the above mathematical expression 9 or 10 makes Z _k , which corresponds to the sizes of row blocks or column blocks in the parity check matrix of each QC-LDPC code C _k , have a multiple relationship with each other, and the index matrix is also selected by a specific method. The existing lifting method like this helps to easily design a QC-LDPC code with improved error floor characteristics by improving the algebraic or graph characteristics of each parity check matrix designed through lifting.

Figures 3a and 3b are examples to simply explain that the cycle characteristics can vary significantly depending on the exponential matrix of the QC-LDPC code.

Figure 3a is a diagram for explaining the cycle characteristics of a QC-LDPC code.

The exponential matrix in Fig. 3a is , and in this case, there may be many 4-cycles in the Tanner graph. Codes with many short cycles like this may cause serious degradation in decoding performance.

Figure 3b is a diagram explaining the cycle characteristics of a QC-LDPC code.

The exponential matrix in Fig. 3b is , and in this case, the length of the shortest cycle on the Tanner graph is 12. Since the cycle characteristics on the Tanner graph can change significantly even by changing only one index of the cyclic permutation matrix, the selection of the index matrix plays an important role in improving the performance of the LDPC code. The lifting method can be viewed as one of the design methods that considers these cycle characteristics.

In general, lifting can be thought of as using the exponential matrix of Equation 4 for LDPC encoding and decoding by changing the values of its elements for various Z values. For example, the exponential matrix of Equation 4 and the transformed exponential matrix according to the Z value. In this case, the following conversion formula, such as mathematical formula 11, can be generally applied.

[Mathematical Formula 11]

or

In the above mathematical expression 11 can be defined in various forms, for example, the above [Mathematical Formula 9] It applies to , the above [Mathematical Formula 10] is may correspond to (mod(a,b) means modulo-b operation for a). In addition, can be defined in various ways, as shown in the following mathematical expression (12).

[Mathematical formula 12]

or

or

In the above mathematical expression 12, D means a constant which is a positive integer defined in advance.

크기의 0-행렬을 표기하는 방법에 따라 다르게 설정될 수 있다. 예를 들어

크기의 0-행렬을 음의 정수 -1이 아닌 사전에 결정되어 있는 다른 수 또는 기호 등으로 정의되어 있을 경우에는 변환식 f를 적용하는 기준 값은 다르게 정의될 수 있다. 또한 지수 행렬 또는 LDPC 수열의 표현에 있어서 0-행렬에 대응되는 지수를 처음부터 배제하여 표기하지 않는 방식에 기반하는 경우에는 수학식 11에서 지수가 0 보다 작은 값들에 대한 규칙은 생략될 수 있다. 변환식 f는 0-행렬이 아닌 순환 순열 행렬 또는 순환 행렬에 대해 적용되는 것이므로, 일반적으로

크기의 0-행렬에 대해 변환을 생략하는 방법은 다양하게 표현될 수 있다.For reference, in the conversion formula of the above mathematical expression 11, the reference value (or,) to which the conversion formula (or conversion function) f is applied is and ) to distinguish the application of The reference value) is expressed as 0 for convenience, but the reference value is the lifting size Z value to be supported or

It can be set differently depending on how the 0-matrix of size is expressed. For example,

If the 0-matrix of size is defined as a number or symbol other than a negative integer -1 that is determined in advance, the reference value for applying the conversion formula f can be defined differently. Also, if the expression of the index matrix or LDPC sequence is based on a method of not expressing the index corresponding to the 0-matrix by excluding it from the beginning, the rule for values whose index is less than 0 in mathematical expression 11 can be omitted. Since the conversion formula f is applied to a circulant permutation matrix or a circulant matrix, not a 0-matrix, in general,

There are various ways to omit transformations for zero-matrix sizes.

As an embodiment of the present disclosure, a case is described in which LDPC encoding and decoding are applied based on a plurality of exponential matrices or LDPC sequences based on a determined basic matrix. That is, the basic matrix is fixed to one, and an exponential matrix or (cyclic) shift value matrix or LDPC sequence of an LDPC code defined based on the basic matrix can be determined, and variable-length LDPC encoding and decoding is performed by applying lifting according to a lifting size included in each lifting size group from the matrix or sequence. This method has a characteristic that elements or numbers constituting the exponential matrix or LDPC sequence of an LDPC code can have different values, but the positions of the corresponding elements or numbers exactly match on the basic matrix.

이 정의되고 각 기본 행렬 별로 8개의 지수 행렬 (또는 순환 이동 값 행렬) ()가 정의되어 LDPC 부호화에 사용될 수 있다. 즉, 표준 규격에 따르면 총 2개의 기본 행렬과 16개의 지수 행렬, 적절한 리프팅 크기

에 기반하여 다양한 LDPC 부호의 패리티 검사 행렬이 결정될 수 있다. 단, TS 38.212 규격에서는

에 해당하는 행렬을 패리티 검사 행렬이라 명명하였으며, 통상적인 패리티 검사 행렬에 대응되는 행렬은 행렬-

라 명명하였다.

는 정수로 이루어진 행렬로서 리프팅 크기

가 주어져야 엄격한 의미의 패리티 검사 행렬을 구성할 수 있으나, 앞서 설명한 것처럼 편의상

를 패리티 검사 행렬이라고 부를 수도 있다.The LDPC code defined in TS 38.212, the 3GPP 5G standard, is also a code designed in the same way, with two basic matrices.

This is defined and 8 exponent matrices (or circular shift value matrices) for each fundamental matrix. ( ) is defined and can be used for LDPC encoding. That is, according to the standard, a total of two basic matrices and 16 exponent matrices, and an appropriate lifting size

Based on this, the parity check matrix of various LDPC codes can be determined. However, in the TS 38.212 standard,

The matrix corresponding to is called the parity check matrix, and the matrix corresponding to the normal parity check matrix is matrix-

It was named La.

is a matrix of integers with lifting size

A parity check matrix in the strict sense can be constructed if given, but for convenience as explained above,

may also be called a parity check matrix.

를 결정하기 위해서 지원하고자 하는 리프팅 크기(Z)를 다음 [표 3]에 나타내었다. (이하 각 리프팅 크기 집합에 대한 집합 인덱스 i _LS 는 예시일 뿐이며 다른 순서로 뒤바뀔 수 있다.)In the following, for the convenience of explanation, the LDPC code and its representation method defined in the 3GPP 5G standard specification TS 38.212 are used as much as possible, but in some cases, it can be expressed in a conventional mathematical expression or in another way. First, the parity check matrix or matrix- of the LDPC code

The lifting sizes (Z) to be supported in order to determine the lifting size are shown in [Table 3] below. (The set index i _LS for each lifting size set below is only an example and can be changed in a different order.)

[Table 3]

In the present disclosure, lifting sizes or block sizes are basically expressed in the manner as in [Table 3] above, but they can also be expressed in the manner as in [Table 4] below, and various other expression methods are also possible.

[Table 4]

In 3GPP 5G, lifting sizes or block sizes Z can be divided into multiple sets (or groups) as shown in [Table 3] or [Table 4]. (Hereinafter, for convenience, they are called lifting size sets (or groups) or block size sets (or groups))

를 결정한다. 이는 및 라 할 때, 각각의 i, j에 대해서 임을 의미한다. (참고로 3GPP 5G 표준 규격 TS 38.212에는 를 간단히

로 표현하였다.)In the 3GPP 5G standard, an exponential matrix can be obtained using the lifting method of [Mathematical Formula 10]. Parity check matrix or matrix-based on

It decides. This is and When , for each i and j, It means that (for reference, the 3GPP 5G standard specification TS 38.212 states that To make it simple

) was expressed as

크기의 0-행렬에 대응되는 부분에 대해서는 특별한 변환을 적용하지 않음에 유의한다. 즉, 에서도 특별한 설명이 없을 경우에 0-행렬에 대응되는 부분은 특별한 변환은 수행하지 않으며,

값에 따라 0-행렬의 크기만 달라질 수 있다. 구체적인 예로서 [표 1] 및 [표 2]처럼 3GPP 5G 표준 규격에서 사용하는 표현 방식에서는

크기의 0-행렬에 대응되는 부분은 처음부터 표기되지 않기 때문에, [표 1] 또는 [표 2]에 포함된

에 대해서만 적절히 모듈로와 같은 사전에 정해진 변환을 수행하면, 0-행렬에 대응되는 부분은 자연스럽게 변환을 수행하지 않으므로써 크기만 달라진 0-행렬을 정의하는 것과 동일하다. 위와 같은 표현 방식은 설명의 편의를 위한 일례일 뿐 다양한 다른 표현 방식이 존재할 수 있다.As explained above in [Mathematical Formula 11], in the present disclosure, from the basic matrix and the exponential matrix

Note that no special transformation is applied to the part corresponding to the 0-matrix of size, i.e., In the absence of special explanation, no special transformation is performed on the part corresponding to the 0-matrix.

Depending on the value, only the size of the 0-matrix can change. As a specific example, in the expression method used in the 3GPP 5G standard specification, as in [Table 1] and [Table 2],

Since the part corresponding to the 0-matrix of size is not indicated from the beginning, it is included in [Table 1] or [Table 2].

If we perform a predefined transformation such as modulo appropriately only for , the part corresponding to the 0-matrix naturally does not perform the transformation, which is equivalent to defining a 0-matrix with a different size. The above expression is only an example for the convenience of explanation, and various other expressions may exist.

는 상기 [표 3]에서 정의된 리프팅 크기만큼 다양하게 변환될 수 있기 때문에, 시스템에 따라서 필요한 리프팅 크기 집합은 다르게 정의될 수 있다. 즉, 상기 [표 3] 및 [표 4]는 일례일 뿐이며, 상기 [표 3] 및 [표 4] 리프팅 크기 (또는 블록 크기) 그룹(또는 집합)에 포함된 모든 리프팅 크기(Z) 값을 사용할 수도 있으며, 시스템에서 요구되는 상황에 따라 적절한 리프팅 크기의 일부를 선택하여 사용할 수도 있으며, 필요에 따라 더 다양한 리프팅 크기 값이 추가될 수도 있다.Parity check matrix or matrix- for a given exponential matrix (or circular shift value matrix).

Since the lifting sizes defined in the above [Table 3] can be variously converted, the set of lifting sizes required for the system can be defined differently. That is, the above [Table 3] and [Table 4] are only examples, and all lifting size (Z) values included in the lifting size (or block size) group (or set) of the above [Table 3] and [Table 4] can be used, and some of the appropriate lifting sizes can be selected and used depending on the situation required by the system, and more diverse lifting size values can be added as needed.

For example, if the minimum size of a transport block (TBS) is 24, Z = 2, 3, 4, 5, 6, 9, and 13 are not actually used in the system. In this case, some Z values can be defined by excluding them, as shown in [Table 5] below.

[Table 5]

In a communication system based on LDPC codes that applies [Table 5] as the lifting size, since the minimum lifting size is 7, each column block that constitutes the parity check matrix of the LDPC code used for LDPC encoding and decoding can be composed of at least 7 columns.

If the minimum value of TBS is greater than 8 for future scalability and additional values such as 8 or 16 are used, the lifting size set (or block size group) may be changed as shown in [Table 6] below.

[Table 6]

The above [Table 6] excludes only the cases in [Table 3] or [Table 4] where Z = 2 or 3, because the minimum Z value that can be determined when TBS is 8 or greater is 4 or greater.

,

,

, ...,

로 분류할 경우에는 기본적으로 다음과 같은 방식으로 분류할 수 있다. ()As an example of setting another lifting size set, let us call the lifting size set A set

,

,

, ...,

When classified, it can be classified basically in the following way. ( )

For example, the cases where A = 4 and A = 8 can be represented as in the following [Table 7-1] and [Table 7-2]. ( )

[Table 7-1]

[Table 7-2]

When the lifting size sets are defined in the manner shown in the above [Table 7-1] and [Table 7-2], there is an advantage in that the distribution of Z values can be set relatively uniformly. The lifting size sets defined in the above [Table 7-1] and [Table 7-2] all include the same number of Z values, but appropriate Z values can be further added or subtracted for each set as needed. For example, it is possible to define the lifting size sets of the above [Tables 3] to [Tables 6] based on the lifting size sets of the above [Table 7-2].

값의 범위를 적절히 설정하여, 시스템에 적합한 Z 값들을 설정할 수도 있다. 예를 들어,

값을 으로 설정하면 각 집합에서 서로 다른 Z 값의 개수가 7개인 리프팅 크기 집합이 얻어지고,

값을 으로 설정하면 각 집합에서 서로 다른 Z 값의 개수가 4개인 리프팅 크기 집합이 얻어진다. 다만, 상기

값은 일 실시예이며, 상기

값의 일 예가 본 개시의 권리 범위를 한정하는 것은 아니다. 또한, 경우에 따라 상기 리프팅 크기 집합들에서 적당한 Z 값의 추가 또는 일부 제외 또한 가능하다. 예를 들어, 만일 시스템에서 설정된 Z의 최댓값이 Zmax이라면 Zmax 보다 큰 값들은 모두 제거될 수 있다 (예: Zmax = 768). 또한, 기존 3GPP 5G 표준에서 지원 가능한 Z 값을 모두 포함할 경우에는 2, 3, 4, 5, 6, 7 등의 값들 중 적어도 일부는 더 포함될 수도 있다. 물론 5G 또는 6G 시스템에서 TBS = 8, 16 과 같은 값들을 추가로 지원하더라도 Z = 2, 3과 같은 값들은 사용되지 않으므로, 4, 6, 7 또는 4, 5, 6, 7 등의 값들만 더 포함될 수도 있으며, 실질적으로 5G에서 사용되지 않는 값들은 제외될 수도 있다. 다음 [표 8]에 리프팅 크기 집합의 구체적인 예를 나타내었다. (표 8에서 ()안의 숫자들은 리프팅 크기로 사용될 수도 있으며 사용되지 않을 수도 있는 값들을 의미한다.)Also, in [Table 7-1] and [Table 7-2]

By setting the range of values appropriately, you can also set Z values suitable for the system. For example,

The value Setting this to , we obtain a set of lifting sizes with 7 different Z values in each set,

The value If set to , a set of lifting sizes is obtained where the number of different Z values in each set is 4. However, the above

The value is an example and the above

An example of a value does not limit the scope of the present disclosure. In addition, it is also possible to add or exclude some appropriate Z values from the lifting size sets, depending on the case. For example, if the maximum value of Z set in the system is Zmax, all values greater than Zmax can be removed (e.g., Zmax = 768). In addition, if all Z values that can be supported by the existing 3GPP 5G standard are included, at least some of the values such as 2, 3, 4, 5, 6, 7, etc. may be further included. Of course, even if values such as TBS = 8, 16 are additionally supported in a 5G or 6G system, since values such as Z = 2, 3 are not used, only values such as 4, 6, 7 or 4, 5, 6, 7 may be further included, and values that are not actually used in 5G may be excluded. The following [Table 8] shows specific examples of lifting size sets. (In Table 8, the numbers in () indicate values that may or may not be used as lifting sizes.)

[Table 8]

() 배수들로 구성되어 있으나 일반적으로는

()와 같이 비연속적인 배수들로 구성되는 것도 가능할 뿐만 아니라, 2의 배수 외에 다른 정수의 배수도 포함될 수 있다.The lifting size sets can be defined in various ways other than those in [Table 3] to [Table 8], but the common characteristics are that each of the multiple lifting size sets must not have overlapping lifting sizes, and the lifting sizes included in each lifting size set must be multiples or divisors of each other. The above [Table 3] to [Table 8] define a continuous lifting size for the smallest lifting size in each lifting size set.

( ) is composed of multiples, but is generally

( ) can be composed of non-consecutive multiples, and can also include multiples of other integers in addition to multiples of 2.

In a new communication system including a 6G system, in order to support backward compatibility with existing systems (e.g., 5G systems), the existing lifting size set may be maintained as is (e.g., [Table 3] or [Table 4]), and a new lifting size set may be added (e.g., [Table 5] to [Table 8]). Or, if the lifting size set is defined as one, but the range of TBS used is determined differently in advance depending on the system settings such as the application scenario or target BLER, the range of Z values used also varies. For example, if the first minimum TBS and the first maximum TBS values are set for a service applying the first target BLER, and the second minimum TBS and/or the second maximum TBS values are defined for a service applying the second target BLER, the first minimum TBS and the second minimum TBS values may be different, or the first maximum TBS and the second maximum TBS values may be different (both the minimum value and the maximum value may be different).

In addition, the applicable service scenario or target BLER, etc. may be determined based on upper layer signaling information. For example, the CQI table or MCS table may be determined by considering target service scenarios or BLERs, for example. (For example, the first target service or BLER may be determined by considering the first CQI table and/or the first MCS table, the second target service or BLER may be determined by considering the second CQI table and/or the second MCS table, the third target service or BLER may be determined by considering the third CQI table and/or the third MCS table, etc.)

As a result, it means that the range of lifting sizes to be used or the set of lifting sizes to be used can be determined from the upper layer signaling information, and the intermediate operations can exist in various ways depending on the system. In addition, the set of lifting sizes to be used can be indicated through the physical layer signaling or the upper layer signaling. The parity check matrix can be determined based on the indicated lifting size set and the determined lifting size Z value.

FIG. 4 is a transport block structure diagram according to one embodiment of the present disclosure.

Referring to Fig. 4, a transport block composed of A bits is added with L bits of CRC bits (TB-CRC bits), and one transport block can become one code block. In addition, if the value B = A + L is greater than a specific threshold value, it can be divided into multiple code blocks through an appropriate segmentation process. At this time, the sizes of the code blocks K are all the same, and for this purpose, specific bits called null bits or filler bits can be added to each code block. The null bits or filler bits usually correspond to a value of 0, but they are not necessarily limited to this, and can be composed of any specific bits determined in advance. The operation of adding predetermined bits such as null bits or fillers in this way is usually called shortening because the size of actual pure information word bits is reduced, and if the values are 0, it can be called zero-padding.

After the size of the transport block to be transmitted (TBS) is determined, one of the basic matrices of two different LDPC codes used for LDPC encoding or decoding can be determined based on the code rate indicated by the TBS size and MCS through a method such as the [basic matrix determination method] below.

[How to determine the basic matrix]

The LDPC basic matrix for LDPC encoding and decoding of a transport block with TBS = A can be determined based on the code rate indicated by the TBS size and MCS as follows:

- When A ≤ 292 (or 288), or A ≤ 3824 and R ≤ 0.67, or R ≤ 0.25, LDPC encoding can be performed using LDPC basic matrix 2.

및 기본 행렬 2

는 다음과 같다.- In addition, LDPC encoding can be performed using LDPC basic matrix 1. For reference, basic matrix 1 defined in the 3GPP 5G standard

and basic matrix 2

is as follows.

:

:

0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23

0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24

0 1 2 4 5 6 7 8 9 10 13 14 15 17 18 19 20 24 25

0 1 3 4 6 7 8 10 11 12 13 14 16 17 18 20 21 22 25

0 1 26

0 1 3 12 16 21 22 27

0 6 10 11 13 17 18 20 28

0 1 4 7 8 14 29

0 1 3 12 16 19 21 22 24 30

0 1 10 11 13 17 18 20 31

1 2 4 7 8 14 32

0 1 12 16 21 22 23 33

0 1 10 11 13 18 34

0 3 7 20 23 35

0 12 15 16 17 21 36

0 1 10 13 18 25 37

1 3 11 20 22 38

0 14 16 17 21 39

1 12 13 18 19 40

0 1 7 8 10 41

0 3 9 11 22 42

1 5 16 20 21 43

0 12 13 17 44

1 2 10 18 45

0 3 4 11 22 46

1 6 7 14 47

0 2 4 15 48

1 6 8 49

0 4 19 21 50

1 14 18 25 51

0 10 13 24 52

1 7 22 25 53

0 12 14 24 54

1 2 11 21 55

0 7 15 17 56

1 6 12 22 57

0 14 15 18 58

1 13 23 59

0 9 10 12 60

1 3 7 19 61

0 8 17 62

1 3 9 18 63

0 4 24 64

1 16 18 25 65

0 7 9 22 66

1 6 10 67

:

:

0 1 2 3 6 9 10 11

0 3 4 5 6 7 8 9 11 12

0 1 3 4 8 10 12 13

1 2 4 5 6 7 8 9 10 13

0 1 11 14

0 1 5 7 11 15

0 5 7 9 11 16

1 5 7 11 13 17

0 1 12 18

1 8 10 11 19

0 1 6 7 20

0 7 9 13 21

1 3 11 22

0 1 8 13 23

1 6 11 13 24

0 10 11 25

1 9 11 12 26

1 5 11 12 27

0 6 7 28

0 1 10 29

1 4 11 30

0 8 13 31

1 2 32

0 3 5 33

1 2 9 34

0 5 35

2 7 12 13 36

0 6 37

1 2 5 38

0 4 39

2 5 7 9 40

1 13 41

0 5 12 42

2 7 10 43

0 12 13 44

1 5 11 45

0 2 7 46

10 13 47

1 5 11 48

0 7 12 49

2 10 13 50

1 5 11 51

및 기본 행렬 2

의 크기는 각각 46×68, 42×52이며, 상기 기본 행렬로부터 결정되는 패리티 검사 행렬의 크기는 46Z×68Z, 42Z×52Z이다.The above basic matrix 1

and basic matrix 2

The sizes of are 46×68 and 42×52, respectively, and the sizes of the parity check matrices determined from the basic matrices are 46Z×68Z and 42Z×52Z.

Additionally, the number of CRC bits (L _TB ) to be added to the transport block can be determined as follows based on the above-determined TBS.

[Method for determining transport block CRC bit count]

The CRC bit size L _TB value for a transport block with TBS = A can be set differently depending on the TBS value as follows:

For A > 3824, L _TB = 24, otherwise L _TB = 16.

According to the TBS size (A) determined in this way or the total number of bits B = A + L added to the CRC in the transport block, an appropriate code block is determined from the transport block, and LDPC encoding and decoding can be performed for each code block. The process of determining the code block length (code block size, CBS) at this time is described in more detail as follows:

[How CBS decides]

The input bit sequence for code block segmentation can be represented as b ₀ , b ₁ , ..., b _B-1 (B > 0). If B is larger than the maximum code block size K _cb , segmentation of the input bit sequence is performed, and a CRC of L = 24 bits is additionally appended to each code block. For LDPC elementary matrix 1, the maximum code block size is K _cb = 8448, and for LDPC elementary matrix 2, the maximum code block size is K _cb = 3840.

The specific steps are explained below.

가 결정될 수 있다.Step 1: Number of code blocks

can be decided.

이면,

이고

이며,

.- If

On the other hand,

And

And,

.

, 이며,

.- Otherwise,

, And,

.

Step 2: When the bit output from the code block segmentation is c _r0 , c _r1 ,..., cr _{(Kr - 1)} , r denotes the code block number (0 ≤ r < C), and Kr (= K) can denote the number of bits of the code block for the code block number r. Here, the number of bits included in each code block, K, can be calculated as follows:

;-

;

.- In the case of LDPC basic matrix 1,

.

- For LDPC basic matrix 2,

이면,

;

On the other hand,

;

이면,

;

On the other hand,

;

이면,

;

On the other hand,

;

이면,

.

On the other hand,

.

값 중에서

를 만족하는 최소값

가 결정될 수 있다. LDPC 기본 행렬 1에 대해

이며, LDPC 기본 행렬 2에 대해

로 설정한다.Step 3: Table 3

Among the values

The minimum value that satisfies

can be determined. For LDPC basic matrix 1,

, and for LDPC basic matrix 2

Set to .

값은 LDPC 부호의 기본 행렬 (또는 기본 그래프) 또는 패리티 검사 행렬에서 LDPC 정보어 비트(information bit)에 대응되는 열 또는 열 블록(column block)에 각각 대응되는 값으로서, 단축 또는 제로 패딩이 없는 LDPC 정보어 비트의 최대 값(

)에 대응될 수 있다. 예를 들어 LDPC 기본 행렬 2 또는 기본 행렬 2에 대응되는 패리티 검사 행렬에서 정보어 비트에 대응되는 열 (또는 열 블록)의 개수가 10개라 하여도, 만일

으로 설정된 경우에는, 실질적으로는(substantially) 최대

비트의 정보어 비트에 대해 LDPC 부호화/복호화가 수행되며, 패리티 검사 행렬에서 최소한

개의 열에 대응되는 정보어 비트는 단축 또는 제로패딩 됨을 의미한다. 여기서 단축 또는 제로 패딩은 0과 같이 송신기 및 수신기가 약속된 비트 값을 할당하는 것을 의미할 수도 있고, 패리티 검사 행렬에서 해당 부분을 사용하지 않는 것을 의미할 수도 있다.In step 2 of the above [CBS Decision Method]

The value corresponds to a column or column block corresponding to an LDPC information bit in the basic matrix (or basic graph) or parity check matrix of the LDPC code, and is the maximum value of the LDPC information bit without shortening or zero padding.

) can be corresponded to. For example, even if the number of columns (or column blocks) corresponding to information word bits in the LDPC basic matrix 2 or the parity check matrix corresponding to the basic matrix 2 is 10, if

When set to , substantially, the maximum

LDPC encoding/decoding is performed on the information bits of the bits, and at least

The information bits corresponding to the columns of the dog are shortened or zero-padded. Here, shortening or zero-padding can mean that the transmitter and receiver assign a promised bit value, such as 0, or it can mean that the corresponding part is not used in the parity check matrix.

The lifting size Z value for LDPC encoding and decoding can be determined based on the lifting size sets shown in [Table 3] to [Table 8] or the lifting size sets to which specific lifting size values have been added and removed. Each Z value is included in a specific set determined in advance according to the index i _LS . When the Z value is determined in step 3 of the [CBS determination method], the set corresponding to the corresponding Z value or the index i _LS value of the set is determined, and the parity check matrix of the LDPC code corresponding to each index or the sequence corresponding thereto can also be determined. The parity check matrix of the LDPC code determined in this manner or the sequence corresponding thereto is converted by applying a modulo operation based on the lifting size Z to support encoding and decoding of LDPC codes of various lengths. In the 3GPP 5G standard, each number included in the parity check matrix or sequence of the LDPC code means a value corresponding to a cyclic permutation matrix.

A flowchart of an embodiment of an LDPC encoding and decoding process based on a designed base matrix or exponential matrix is shown in FIGS. 5 and 6.

Figure 5 is a diagram illustrating an embodiment of an LDPC encoding process.

First, the transmitter determines the transport block size TBS to be transmitted, as in step (510) of Fig. 5. In step (520), the transmitter determines whether the TBS is greater than, less than, or equal to max CBS.

If TBS is greater than max CBS, the transmitter can segment the transport block to determine CBS in step (530). If TBS is less than or equal to max CBS, the transmitter skips the segmentation operation and determines the TBS as CBS.

In step (540), the transmitter determines the lifting size (Z) value to be applied to LDPC encoding based on the CBS.

And the transmitter determines a parity check matrix or sequence according to the TBS or CBS or lifting size (Z) value at step (550). Alternatively, the transmitter may determine an LDPC index matrix or sequence that has an effect algebraically identical to the parity check matrix.

And the transmitter performs LDPC encoding based on the parity check matrix or sequence in step (560). Alternatively, the transmitter may perform LDPC encoding based on the exponential matrix or sequence in step (560). In addition, the transmitter may perform LDPC encoding based on the lifting size and the exponential matrix or sequence in step (560).

)를 사용할 경우에는 TBS 크기에 따라 기본 행렬에서 실질적으로 사용될 열의 개수 또는 패리티 검사 행렬에서 사용될 열 블록의 개수를 의미하는

값을 결정하는 과정이 포함될 수도 있다. (참고로

개의 기본 행렬의 열에 대응되는 패리티 검사 행렬의 열 블록은 단축이 적용된다.)For reference, the step (550) above may include a process of converting the determined LDPC index matrix or sequence based on the determined lifting size, depending on the case. It is obvious that the LDPC index matrix or sequence or parity check matrix for LDPC encoding may be determined in various ways based on TBS or CBS, depending on the system. For example, the transmitter may first determine the base matrix through TBS, and then determine the LDPC index matrix or sequence parity check matrix based on the determined base matrix and CBS, and various other methods may also be applied. For reference, additional operations may be included between steps (520) and (540) or between steps (530) and (540) depending on the system. For example, in the case of a 3GPP 5G system, the base matrix 2 (

) means the number of columns to be actually used in the base matrix or the number of column blocks to be used in the parity check matrix depending on the TBS size.

The process of determining the value may be included. (For reference,

The column blocks of the parity check matrix corresponding to the columns of the basic matrix of the dog are shortened.)

The LDPC decoding process can be similarly represented as in Fig. 6.

Figure 6 is a diagram illustrating an embodiment of an LDPC decoding process.

If TBS is determined in step (610), the receiver determines in step (620) whether TBS is greater than, less than, or equal to max CBS.

If TBS is greater than max CBS, the receiver determines the size of CBS to which segmentation is applied in step (630). If TBS is determined to be less than or equal to max CBS, TBS is determined to be equal to CBS.

The receiver determines the lifting size (Z) value to be applied for LDPC decoding at step (640).

Then, the receiver determines a parity check matrix or sequence based on the TBS or CBS or lifting size (Z) value at step (650). Alternatively, the transmitter may determine an exponential matrix or sequence having an effect algebraically identical to the parity check matrix.

And the receiver can perform LDPC decoding based on the parity check matrix or sequence in step (660). Alternatively, the receiver can perform LDPC decoding using the index matrix or sequence in step (660). For reference, the step (650) may include a process of converting the determined LDPC index matrix or sequence based on the determined lifting size, as the case may be. It is obvious that the LDPC index matrix or sequence or parity check matrix for LDPC decoding can be determined in various ways based on TBS or CBS depending on the system. For example, the receiver can first determine the base matrix through TBS, and then determine the LDPC index matrix or sequence parity check matrix based on the determined base matrix and CBS, and various other methods can also be applied.

)를 사용할 경우에는 TBS 크기에 따라 기본 행렬에서 실질적으로 사용될 열의 개수 또는 패리티 검사 행렬에서 사용될 열 블록의 개수를 의미하는

값을 결정하는 과정이 포함될 수도 있다. 참고로 수신기는

개의 기본 행렬의 열에 대응되는 패리티 검사 행렬의 열 블록에 대응되는 비트들이 송신기에서 단축이 적용되었음을 알 수 있으므로, 수신기는 LDPC 복호화를 수행하기 전에 단축된 비트들에 적절한 동작을 추가로 수행할 수도 있다.According to the above embodiment, the process of determining the exponent matrix or sequence of the LDPC code in steps (550) and (650) of FIGS. 5 and 6 has been described for the case where the exponent matrix or sequence is determined by one of the TBS or CBS or the lifting size (Z), but various other methods may exist. In addition, additional operations may be included between steps (620) and (640) or between steps (630) and (640) of FIG. 6 depending on the system. For example, in the case of a 3GPP 5G system, the basic matrix 2 (

) means the number of columns to be actually used in the base matrix or the number of column blocks to be used in the parity check matrix depending on the TBS size.

A process for determining the value may be included. Note that the receiver

Since the bits corresponding to the column blocks of the parity check matrix corresponding to the columns of the basic matrix of the dog can be known to have been shortened at the transmitter, the receiver may additionally perform appropriate operations on the shortened bits before performing LDPC decoding.

In an embodiment of an LDPC encoding and decoding process based on the base matrix and exponent matrix (or LDPC sequence) of the LDPC code of the above FIGS. 5 and 6, by appropriately shortening or puncturing some of the information bits of the LDPC code and puncturing and repeating some of the codeword bits, LDPC encoding and decoding of various code rates and lengths can be supported. For example, as in the 3GPP 5G standard technology, by applying shortening to some of the information bits in the LDPC encoding process of the above FIG. 5, puncturing the information bits corresponding to the first two columns of the base matrix, that is, the first 2Z columns of the parity check matrix, and puncturing some of the parities or repeating some of the LDPC codewords, it is possible to support various information lengths (or code block lengths) and various code rates.

, 기본 행렬 2인 경우에는

), 다음 [표 9]와 같이 부호화 과정의 일부가 정의될 수 있다.Given input bits or code block bits and the encoding bits When expressed as (except in the case of the basic matrix 1)

, if the basic matrix is 2

), part of the encoding process can be defined as shown in [Table 9] below.

[Table 9]

According to the above encoding process, the first 2Z bits among the input bits or code block bits is not included in the coded bits. That is, the 2Z bits are punctured at the transmitter and are not transmitted to the receiver. For reference, if a part of the information word bits is punctured, it means that the transmitter does not transmit a part of the information word (102) of Fig. 1, and therefore, the receiver can perform decoding by processing the untransmitted information word bits as erased. In other words, since the punctured bits are regarded as erased and have the same probability of 0 and 1, the receiver can insert a corresponding value to perform decoding.

The information bits that are punched out in the above encoding process may not always be transmitted even in the case of retransmission. In the case where a circular buffer is used for rate matching, if rate matching and retransmission are performed without storing the punched information bits in the circular buffer, the punched information bits may not always be transmitted.

On the other hand, in the case of a first transmission, some of the information bits may be perforated, and in the case of a retransmission, all or some of the perforated information bits may be transmitted. All of the information bits are stored in a circular buffer, but in the case of a first transmission, a redundancy value (RV) may be appropriately set so that some of the information bits are perforated (e.g., the RV0 value is set to exclude the information bits to be perforated). Even if some of the information bits are perforated in the first transmission, since the bit values are stored in the circular buffer, in the case of a retransmission, some or all of the perforated information bits may be transmitted depending on the circular buffer rate matching operation and selection of an appropriate RV value.

[Table 9] For convenience, is called a coding bit, but the definition of a coding bit can be changed for convenience of explanation. For example, in [Table 9] The bit string after punching out some of the information bits can be defined as the encoded bit, but in reality, the parity bit vector is used in the encoding process. Input bits or code block bits to generate Because this is used, it is based on the information bit before perforation.

can also be defined as a coded bit. Also, a bit string with rate matching applied based on the allocated resource amount. This can also be defined as a coded bit, a bit stream with interleaving applied to the rate-matched bit stream. This can be defined as a coding bit. In addition, the coding bit string can be defined in various ways for convenience of explanation, but usually, the bit string related to actual transmission in the system is Ina, related to the encoding process This can be defined by the encoding bits.

In the LDPC decoding process of Fig. 6, decoding can be performed by adding an appropriate operation for the shortened information bits and the punctured bits or repeated bits corresponding to the transmitter operation. Normally, the shortened information bits are 0, so the receiver performs decoding by excluding the column corresponding to the shortened bits from the parity check matrix, or performs decoding by setting a value preset in the system for the shortened bits. (Since it is certain to be 0, the highest value corresponding to 0 preset in the system is usually set.) Since the punctured parity bits are regarded as lost and have the same probability of being 0 and 1, the receiver can perform decoding by inserting a corresponding value, or, depending on the structure of the parity check matrix, decoding can be performed without using at least some of the rows corresponding to the punctured parity bits. In general, when puncturing the parity bit corresponding to a column with degree 1, the LDPC decoder can perform decoding without using part or all of the corresponding part in the parity check matrix, which has the advantage of reducing the decoding complexity.

In addition, when supporting variable information word length or variable code rate by using LDPC code shortening or zero padding, the code performance can be improved depending on the shortening order or shortening method. If the shortening order is set, the encoding performance can be improved by appropriately rearranging the order of some or all of the given basic matrices. In addition, the performance can be improved by appropriately determining the number of column blocks to which the lifting size or shortening is applied for a specific information word length (or code block length CBS). Similarly, there is a method for improving the performance of the LDPC code by adjusting the puncturing order of the parity bits or the transmission order of the generated LDPC codeword. For example, better performance can be supported by appropriately puncturing some of the information word bits and the parity bits than simply puncturing the parity bits to support a variable code rate. In addition, when repeating some of the LDPC codewords to support a lower code rate, the order can be appropriately determined in advance to improve the LDPC encoding performance.

Typically, in the LDPC encoding process, the transmitter first determines the size of the input bits (or code blocks) to which the LDPC encoding is to be applied, and then determines the lifting size (Z) to which the LDPC encoding is to be applied based on the size, determines an appropriate LDPC index matrix or sequence based on the lifting size, and then performs LDPC encoding based on the lifting size (Z) and the determined index matrix or LDPC sequence. At this time, the LDPC index matrix or sequence may be applied to the LDPC encoding without transformation, and in some cases, the LDPC index matrix or sequence may be appropriately transformed according to the lifting size (Z) to perform LDPC encoding.

Similarly, in the LDPC decoding process, the receiver determines the size of the input bits (or code blocks) for the transmitted LDPC codeword, and then determines the lifting size (Z) to apply LDPC decoding based on the size, determines an appropriate LDPC exponent matrix or sequence based on the lifting size, and then performs LDPC decoding based on the lifting size (Z) and the determined exponent matrix or LDPC sequence. At this time, the LDPC exponent matrix or sequence can be applied to LDPC decoding without transformation, and in some cases, the LDPC exponent matrix or sequence can be appropriately transformed according to the lifting size (Z) to perform LDPC decoding.

In a parity check matrix, a submatrix corresponding to a parity bit often has a special structure for efficient encoding. In this case, the encoding method or complexity may change due to lifting. Therefore, in order to maintain the same encoding method or complexity, lifting may not be applied to a part of the index matrix for the submatrix corresponding to the parity in the parity check matrix, or a different lifting method may be applied to the index matrix for the submatrix corresponding to the information bits. In other words, the lifting method applied to the sequence corresponding to the information bits in the index matrix and the lifting method applied to the sequence corresponding to the parity bits may be set differently, and in some cases, lifting may not be applied to a part or all of the sequence corresponding to the parity bits, so that a fixed value may be used without sequence transformation.

FIG. 7 is a block diagram of a transmitter according to an embodiment of the present disclosure.

Specifically, as shown in FIG. 7, the transmitter (700) may include a segmentation unit (710), a zero padding unit (720), an LDPC encoding unit (730), a rate matching unit (740), a modulation unit (750), etc., to process variable length input bits. The rate matching unit (740) may include an interleaver (741) and a puncturing/repetition/zero removal unit (742), etc.

Here, the components illustrated in FIG. 7 are components that perform encoding and modulation for variable-length input bits, and this is only an example, and in some cases, some of the components illustrated in FIG. 7 may be omitted or changed, and other components may be added.

Meanwhile, the transmitter (700) can determine necessary parameters (for example, at least one of input bit length, ModCod (modulation and code rate), parameters for zero padding (or shortening), code rate/code length of LDPC code, parameters for interleaving, parameters for repetition and puncturing, and modulation methods), and encode input bits based on the determined parameters and transmit them to the receiver (800).

Since the number of input bits is variable, when the number of input bits is greater than a preset value, the input bits can be segmented to have a length less than or equal to the preset value. In addition, each segmented block can correspond to one LDPC coded block. However, when the number of input bits is less than or equal to a preset value, the input bits are not segmented and the input bits can correspond to one LDPC coded block.

Meanwhile, the transmitter (700) may store various parameters used for encoding, interleaving, and modulation. Here, the parameter used for encoding may include at least one of information on a code rate of an LDPC code, a codeword length, and a parity check matrix. In addition, the parameter used for interleaving may include information on an interleaving rule, and the parameter used for modulation may include information on a modulation method. In addition, the information on puncturing may include a puncturing length. In addition, the information on repetition may include a repetition length. The information on the parity check matrix may include an exponent value of a circulant matrix or values algebraically identical thereto when the parity matrix presented in the present disclosure is used.

In this case, each component constituting the transmitter device (700) can perform an operation using these parameters.

Meanwhile, although not shown, in some cases, the transmitter (700) may further include a control unit (not shown) for controlling the operation of the transmitter (700).

FIG. 8 is a block diagram of a receiving device according to an embodiment of the present disclosure.

Specifically, as shown in FIG. 8, the receiving device (800) may include a demodulation unit (810), a rate dematching unit (820), an LDPC decoding unit (830), a zero removal unit (840), and a desegmentation unit (850), etc., to process variable length information. The rate dematching unit (820) may include an LLR (log likelihood ratio) insertion unit (822), an LLR combiner (823), a deinterleaver (824), etc.

Here, the components illustrated in FIG. 8 are components that perform functions corresponding to the components illustrated in FIG. 8, but this is only an example, and some may be omitted or changed depending on the case, and other components may be added.

The parity check matrix in the present disclosure may be read using a memory, may be given in advance to the transmitter or receiver, or may be generated directly in the transmitter or receiver. In addition, the transmitter may store or generate a sequence or exponential matrix corresponding to the parity check matrix, or a value algebraically identical thereto, and apply it to encoding. Similarly, the receiver may store or generate a sequence or exponential matrix corresponding to the parity check matrix, or a value algebraically identical thereto, and apply it to decoding.

Below, a detailed description of the receiver operation is provided based on Fig. 8.

The demodulator (810) demodulates a signal received from the transmitter (700).

Specifically, the demodulator (810) is a component corresponding to the modulator (750) of the transmitter (700), and can demodulate a signal received from the transmitter (700) to generate values corresponding to bits transmitted by the transmitter (700).

To this end, the receiving device (800) determines parameters required for demodulation and decoding (for example, at least one of input bit length, ModCod (modulation and code rate), parameters for zero padding (or shortening), code rate/codeword length of an LDPC code, parameters for interleaving, parameters for repetition and puncturing, and modulation methods), and based on the determined parameters, the demodulation unit (810) can perform a decoding process of demodulating a signal received from the transmitting device (700) according to a mode to generate values corresponding to LDPC codeword bits.

Meanwhile, the value corresponding to the bits transmitted from the transmitting device (700) may be a LR (likelihood ratio) value or an LLR (log likelihood ratio) value.

Specifically, the LR value refers to the ratio of the probability that the bit transmitted from the transmitter (700) is 0 and the probability that it is 1, and the LLR value can be expressed as the log value of the ratio of the probability that the bit transmitted from the transmitter (700) is 0 and the probability that it is 1. Alternatively, the LR or LLR value may be determined based on the probability or the ratio of the probability or the Log value for the ratio of the probability and expressed as the bit value itself, or may be expressed as a representative value defined in advance according to the section to which the probability or the ratio of the probability or the Log value for the ratio of the probability belongs. An example of a method for determining a representative value defined in advance according to the section to which the probability or the ratio of the probability or the Log value for the ratio of the probability belongs includes a method that considers quantization. In addition, various other values corresponding to the probability or the ratio of the probability or the Log value for the ratio of the probability may be used.

In the present disclosure, for the purpose of convenience, an operation based on an LLR value is shown to explain the operation of the receiving method and device, but it is not necessary to be limited thereto.

The above-mentioned demodulator (810) includes a function of performing multiplexing (not shown) for LLR values. Specifically, the multiplexer (not shown) is a component corresponding to the bit demuxer (not shown) of the transmitter (700) and can perform an operation corresponding to the bit demuxer (not shown).

To this end, the receiving device (800) may store information on parameters that the transmitting device (700) used for demultiplexing and block interleaving. Accordingly, the multiplexer (not shown) may perform the demultiplexing and block interleaving operation performed in the bit demuxer (not shown) in reverse for the LLR value corresponding to the cell word (information representing the received symbol for the LDPC codeword as a vector value), thereby multiplexing the LLR value corresponding to the cell word on a bit-by-bit basis.

The rate dematching unit (820) can additionally insert LLR values into the LLR values output from the demodulator (810). In this case, the rate dematching unit (820) can insert LLR values agreed upon in advance between the LLR values output from the demodulator (810).

Specifically, the rate dematching unit (820) is a component corresponding to the rate matching unit (740) of the transmitting device (700), and can perform operations corresponding to the interleaver (741), zero removal, and puncturing/repetition/zero removal unit (742).

First, the rate dematching unit (820) performs deinterleaving to correspond to the interleaver (741) of the transmitter. The LLR insertion unit (822) can insert an LLR value corresponding to zero bits into the position where the zero bits were padded in the LDPC codeword in the output values of the deinterleaver (824). In this case, the LLR value corresponding to the padded zero bits, i.e., the shortened zero bits, can be ∞ or -∞. However, ∞ or -∞ is a theoretical value, and in practice, it can be the maximum or minimum value of the LLR value used in the receiving device (800).

To this end, the receiving device (800) may store information about the parameters that the transmitting device (700) used to pad zero bits. Accordingly, the rate dematching unit (820) may determine the position where zero bits were padded in the LDPC codeword and insert an LLR value corresponding to the shortened zero bits at the corresponding position.

In addition, the LLR insertion unit (822) of the rate dematching unit (820) can insert LLR values corresponding to the punctured bits into the positions of the punctured bits in the LDPC codeword. In this case, the LLR values corresponding to the punctured bits can be 0 or another value that is determined in advance. In general, when parity bits with degree 1 are punctured, there is no effect on improving the performance of the LDPC decoding process, so some or all of the corresponding punctured positions may not be used in the LDPC decoding process without LLR insertion. However, in order to increase the efficiency of the LDPC decoding process based on a parallel process, the LLR insertion unit (822) can insert a pre-determined LLR value into positions corresponding to some or all of the punctured bits with degree 1 regardless of the improvement in the decoding performance.

To this end, the receiving device (800) can store information on parameters used for puncturing in the transmitting device (700). Accordingly, the LLR insertion unit (822) can insert an LLR value (e.g., LLR = 0) corresponding to the punctured positions of the LDPC information bits or parity bits. However, this process may be omitted for positions of some punctured parity bits.

The LLR combiner (823) can combine, i.e., add, the LLR values output from the LLR insertion unit (822) and the demodulation unit (810). Specifically, the LLR combiner (823) is a component corresponding to the puncturing/repetition/zero removal unit (742) of the transmitter (700) and can perform an operation corresponding to the repetition unit (742). First, the LLR combiner (823) can combine the LLR values corresponding to the repeated bits with another LLR value. Here, the other LLR value can be an LLR value for the bits that formed the basis for generating the repeated bits in the transmitter (700), i.e., the LDPC information word bits or parity bits that were selected as repetition targets.

That is, as described above, the transmitter (700) selects LDPC encoded bits, repeats them between LDPC information bits and LDPC parity bits, and transmits them to the receiver (800). Accordingly, the LLR value for the LDPC encoded bits may be composed of an LLR value for the repeated LDPC encoded bits and an LLR value for the non-repeated LDPC encoded bits. The LLR combiner (823) may combine the LLR values for the same LDPC encoded bits.

To this end, the receiving device (800) can store information on parameters used for repetition in the transmitting device (700). Accordingly, the LLR combiner (823) can determine an LLR value for the repeated LDPC encoded bits and combine it with an LLR value for the LDPC encoded bits that are the basis of the repetition.

Additionally, the LLR combiner (823) can combine the LLR value corresponding to the retransmitted or IR (increment redundancy) bits with another LLR value. Here, the other LLR value can be an LLR value for some or all of the LDPC codeword bits that are the basis for generating the retransmitted or IR bits in the transmitter (700).

As described above, when a NACK occurs for HARQ, the transmitting device (700) can transmit some or all of the code bits to the receiving device (800).

Accordingly, the LLR combiner (823) can combine the LLR values for bits received via retransmission or IR with the LLR values for LDPC codeword bits received via the previous frame.

To this end, the receiving device (800) can store information about parameters used by the transmitting device (700) to generate retransmission or IR bits. Accordingly, the LLR combiner (823) can determine an LLR value for the number of retransmission or IR bits and combine it with an LLR value for LDPC encoded bits that are the basis for generating the retransmission bits.

The deinterleaver (824) can deinterleave the LLR value output from the LLR combiner (823).

Specifically, the deinterleaver unit (824) is a component corresponding to the interleaver (741) of the transmitting device (700) and can perform an operation corresponding to the interleaver (741).

To this end, the receiving device (800) may store information on parameters that the transmitting device (700) used for interleaving. Accordingly, the deinterleaver (824) may reversely perform the interleaving operation performed by the interleaver (741) on the LLR values corresponding to the transmitted LDPC encoded bits, thereby deinterleaving the LLR values corresponding to the transmitted LDPC encoded bits.

The LDPC decoding unit (830) can perform LDPC decoding based on the LLR value output from the rate dematching unit (820).

Specifically, the LDPC decoding unit (830) is a component corresponding to the LDPC encoding unit (730) of the transmitting device (700) and can perform an operation corresponding to the LDPC encoding unit (730).

To this end, the receiving device (800) may store information on parameters used by the transmitting device (700) to perform LDPC encoding according to the mode. Accordingly, the LDPC decoding unit (830) may perform LDPC decoding based on the LLR value output from the rate dematching unit (820) according to the mode.

For example, the LDPC decoding unit (830) can perform LDPC decoding based on the LLR value output from the rate dematching unit (820) based on an iterative decoding method based on a sum-product algorithm, and output bits whose errors are corrected according to the LDPC decoding. The LDPC decoding unit (830) performs LDPC decoding on the LDPC codeword based on a parity check matrix or an exponent matrix or sequence corresponding thereto. In addition, the LDPC decoding can be performed using a parity check matrix defined differently according to a code rate (i.e., a code rate of the LDPC code). The LDPC decoding unit (830) can perform LDPC decoding by passing the LLR value corresponding to the LDPC codeword bits through an iterative decoding algorithm to generate information bits. Here, the LLR value is a channel value corresponding to the LDPC codeword bits, and can be expressed in various ways.

The zero removal unit (840) can remove zero bits from the bits output from the LDPC decoding unit (830).

Specifically, the zero removal unit (840) is a component corresponding to the zero padding unit (720) of the transmitter (700) and can perform an operation corresponding to the zero padding unit (720).

To this end, the receiving device (800) may store information about the parameters used to pad zero bits in the transmitting device (700). Accordingly, the zero removal unit (840) may remove zero bits that were padded in the zero padding unit (720) from the bits output from the LDPC decoding unit (830).

The desegmentation unit (850) is a component corresponding to the segmentation unit (710) of the transmitting device (700) and can perform an operation corresponding to the segmentation unit (710).

To this end, the receiving device (800) may store information about the parameters that the transmitting device (700) used for segmentation. Accordingly, the desegmentation unit (850) can restore the bits before segmentation by combining the bits output from the zero removal unit (840), i.e., segments for variable-length input bits.

FIG. 9 illustrates a structural diagram of an LDPC decoding unit according to an embodiment of the present disclosure.

Meanwhile, as described above, the LDPC decoding unit (830) can perform LDPC decoding using an iterative decoding algorithm, and in this case, the LDPC decoding unit (830) can be configured with a structure as shown in Fig. 9. However, the detailed configuration illustrated in Fig. 9 is also only an example.

According to FIG. 9, the decryption device (900) includes an input processor (901), a memory (902), a variable node operator (904), a controller (906), a check node operator (908), and an output processor (910).

The input processor (901) stores the input value. Specifically, the input processor (901) can store the LLR value of the received signal received through the channel.

The controller (904) determines the number of values input to the variable node operator (904) and the address values in the memory (902), the number of values input to the check node operator (908) and the address values in the memory (902), etc. based on the size of the block of the received signal received through the channel (i.e., the length of the codeword) and the parity check matrix corresponding to the code rate.

The memory (902) stores input data and output data of the variable node operator (904) and the inspection node operator (908).

The variable node operator (904) receives data from the memory (902) based on the address information of the input data and the number information of the input data received from the controller (906) and performs a variable node operation. Thereafter, the variable node operator (904) stores the variable node operation results in the memory (902) based on the address information of the output data and the number information of the output data received from the controller (906). In addition, the variable node operator (904) inputs the variable node operation results to the output processor (910) based on the data received from the input processor (901) and the memory (902). Here, the variable node operation has been described above based on FIG. 6.

The inspection node operator (908) receives data from the memory (902) and performs inspection node operations based on the address information of the input data and the number information of the input data received from the controller (906). Thereafter, the inspection node operator (908) stores the inspection node operation results in the memory (902) based on the address information of the output data and the number information of the output data received from the controller (906). Here, the inspection node operation has been described above based on FIG. 6.

The output processor (910) makes a rough judgment as to whether the information word bits of the codeword of the transmitting side are 0 or 1 based on the data input from the variable node operator (904), and then outputs the result of the rough judgment, and the output value of the output processor (910) becomes the final decoded value. In this case, the rough judgment can be made based on the sum of all message values input to one variable node in Fig. 6 (the initial message value and all message values input from the check node).

Meanwhile, the memory (902) of the decoding device (900) can store information on the code rate, codeword length, and parity check matrix of the LDPC code, and the LDPC decoding unit (810) can perform LDPC encoding using this information. However, this is only an example, and the corresponding information may be provided from the transmitting side.

For reference, this disclosure is limited to LDPC codes as a forward error correction (FEC) technique for a communication system, but in general, FEC encoding and decoding of a communication system may be subdivided into concatenated codes such as outer codes and inner codes. According to the definition of outer codes and inner codes, a transmitter performs inner encoding after outer encoding, and a receiver performs inner decoding after inner decoding.

In the case of external codes, algebraic codes that enable relatively simple error detection or correction, such as CRC (cyclic redundancy check) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, and Reed-Solomon (RS) codes, are often used, but they are not necessarily limited to these, and multiple codes can also be applied repeatedly.

For inner codes, relatively complex but excellent error correction capability encoding methods such as LDPC codes, Turbo codes, and Polar codes are widely used, but it is not necessarily limited to these. (For example, tail-biting convolutional codes or other algebraic codes can be used, and overlapping application of multiple codes is also possible.) For reference, in the 3GPP 5G system, CRC codes are used for outer codes, LDPC codes are used for inner codes for data channels, and Polar codes are used for inner codes for control channels.

Various broadcasting systems and communication systems use LDPC codes optimized for each system. The present disclosure describes a system using an LDPC code defined based on a parity check matrix having the same structure as the LDPC code used in the 3GPP 5G system, but is not necessarily limited thereto. In addition, a communication system including a 5G or 6G system may apply rate matching at a transmitter and rate dematching at a receiver in order to support various code rates and various code lengths. However, in a system that performs encoding/decoding based on a fixed LDPC code, such as some broadcasting systems, not only rate matching or rate dematching but also all or part of other operations may be omitted.

FIG. 10 shows the general structure of a parity check matrix of an LDPC code, which is an internal code applied to an FEC encoding unit (not shown) and an FEC decoding unit (not shown) to be described in the present disclosure.

The number of columns of the parity check matrix illustrated in the above Fig. 10 is N, and the number of rows is (M ₁ + M ₂ ) (provided that M ₁ , M ₂ ≥ 0 and M ₁ + M ₂ > 0). In general, when the parity check matrix has the full rank, the number of columns corresponding to the information bits in the parity check matrix is equal to the total number of columns minus the total number of rows. That is, if the parity check matrix of the above Fig. 10 has the maximum rank (M ₁ + M ₂ ), it means that the number of information bits K becomes N - (M ₁ + M ₂ ). In the present disclosure, for the sake of convenience, only the case where the parity check matrix of the above Fig. 10 has the maximum rank is described, but it is not necessarily limited thereto.

First, the parity-check matrix of the above Fig. 10 can be divided into a first part of the parity-check matrix composed of submatrices A (1010) and B (1020) and a second part of the parity-check matrix composed of submatrices C (1040), D (1050), and E (1060) (however, if either M ₁ or M ₂ is 0, the first part and the second part may not be divided). The submatrix O (1030) means a 0-matrix of the size (M ₁ × M ₂ ). Since the submatrix O (1030) is a 0-matrix of the size (M ₁ × M ₂ ), even if it is included in the first part of the parity-check matrix, it has no effect on the matrix operation. For this reason, in the present disclosure, for convenience, the first part of the parity check matrix is defined as a matrix composed of submatrices A(1010) and B(1020) excluding the 0-matrix of the size (M ₁ × _M 2 ), but, if necessary, the first part of the parity check matrix may also include the 0-matrix of the size (M ₁ × M ₂ ).

및

,

(

,

)에 대해

의 크기를 갖는 기본 행렬 또는 무게 행렬에 대응될 수 있다. 마찬가지로 부분 행렬 A(1010)와 B(1020)로 구성된 패리티 검사 행렬의 제1 파트는 또는

크기의 기본 행렬 또는 무게 행렬의 부분 행렬에 대응되고, 부분행렬 C(1040), D(1050)와 E(1060)로 구성된 패리티 검사 행렬의 제2 파트는 또는

크기의 기본 행렬 또는 무게 행렬의 부분 행렬에 대응된다.If the parity check matrix of the above Fig. 10 is defined as a QC LDPC code with a lifting size or block size of Z, the parity check matrix of the above Fig. 10 is

and

,

(

,

) about

can correspond to a basic matrix or weight matrix having a size of . Similarly, the first part of the parity check matrix consisting of submatrices A (1010) and B (1020) is or

The second part of the parity check matrix, which corresponds to a submatrix of the basic matrix or weight matrix of size and consists of submatrixes C(1040), D(1050) and E(1060), or

Corresponds to a submatrix of the fundamental matrix or weight matrix of size.

The parity check matrix of the above figure 10 is called H for convenience, and the information word bits (or information word bit vector) corresponding to the submatrix A (1010) or C (1040) are and the first parity bits (or the first parity bit vector) corresponding to the submatrix B(1020) or D(1050) and the second parity bits (or the second parity bit vector) corresponding to the submatrix E(1060) Then, from mathematical expression 1, we can obtain a relationship such as the following mathematical expression 13.

[Mathematical formula 13]

Referring to the above mathematical expression 13, the first parity vector can be obtained (or calculated or determined) based on the information word bit vector i and the first part of the parity check matrix. Also, the parity vector After obtaining the information word bit vector , the above parity vector And the parity vector based on the second part of the parity check matrix can be obtained (or calculated or determined).

In this disclosure, information word bit vector Based on the first parity vector The first part of the parity check matrix consisting of A(1010) and B(1020) required to generate may be conveniently called a core part or matrix, a kernel part or matrix, or a precoding part or matrix. In addition, the information word bit vector and/or the first parity vector Based on the second parity vector The second part of the parity-check matrix, which consists of C (1040), D (1050) and E (1060) required to generate the parity-check matrix, may be called an extension part or a single parity-check extension part.

및 기본 행렬 2

의 코어 행렬 부분을 각각 나타내면 다음과 같다.As a concrete example, the basic matrix 1 defined in the 3GPP 5G standard described above

and basic matrix 2

Each core matrix part is represented as follows.

의 코어 행렬:

Core matrix of:

0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23

0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24

0 1 2 4 5 6 7 8 9 10 13 14 15 17 18 19 20 24 25

0 1 3 4 6 7 8 10 11 12 13 14 16 17 18 20 21 22 25

의 코어 행렬:

Core matrix of:

0 1 2 3 6 9 10 11

0 3 4 5 6 7 8 9 11 12

0 1 3 4 8 10 12 13

1 2 4 5 6 7 8 9 10 13

의 코어 행렬의 크기는 4×26이며,

의 코어 행렬의 크기는 4×14이다. 또한 패리티 검사 행렬의 기준으로 코어 행렬의 크기는 각각 4Z×26Z, 4Z×14Z이다. 구체적인 예로서 3GPP 5G 규격 TS 38.212에서 리프팅 크기 집합 인덱스 i _LS = 0인 경우에 대해 정의된 LDPC 부호의 지수 행렬의 일부를 도 11a 및 도 11b에 나타내었다. 상기 도 11a 및 도 11b에서 기본 행렬 또는 패리티 검사 행렬의 코어 행렬에 대응되는 부분은 다음과 같다.

The size of the core matrix is 4×26,

The size of the core matrix is 4×14. Also, the sizes of the core matrices as a reference for the parity check matrix are 4Z×26Z and 4Z×14Z, respectively. As a specific example, a part of the index matrix of the LDPC code defined in the 3GPP 5G standard TS 38.212 for the case where the lifting size set index i _LS = 0 is shown in FIGS. 11a and 11b. The part corresponding to the core matrix of the basic matrix or the parity check matrix in FIGS. 11a and 11b is as follows.

,

의 코어 행렬:

,

Core matrix of:

250 69 226 159 100 10 59 229 110 191 9 195 23 190 35 239 31 1 0

2 239 117 124 71 222 104 173 220 102 109 132 142 155 255 28 0 0 0

106 111 185 63 117 93 229 177 95 39 142 225 225 245 205 251 117 0 0

121 89 84 20 150 131 243 136 86 246 219 211 240 76 244 144 12 1 0

,

의 코어 행렬:

,

Core matrix of:

9 117 204 26 189 205 0 0

167 166 253 125 226 156 224 252 0 0

81 114 44 52 240 1 0 0

8 58 158 104 209 54 18 128 0 0

Meanwhile, in the present disclosure, a parity check matrix based on the following conditions may be considered for the parity check matrix corresponding to the above-described FIG. 10.

의 크기를 갖는 순환 순열 행렬을 의미할 수 있으며, 예를 들어 수학식 5 또는 수학식 6과 같이 구성될 수 있다. 또한, 본 개시에서 순환 행렬은 순환 순열 행렬들이 중첩된 행렬을 의미할 수 있다.Hereinafter, the submatrix A(1010) and the submatrix B(1020) may be referred to as the first submatrix and the second submatrix, respectively. In addition, the cyclic permutation matrix below is determined based on the lifting size Z.

It may mean a cyclic permutation matrix having a size of , and may be configured as in mathematical expression 5 or mathematical expression 6, for example. In addition, in the present disclosure, a cyclic matrix may mean a matrix in which cyclic permutation matrices are overlapped.

크기의 순환 순열 행렬들이 중첩된 순환 행렬을 포함하지 않는 경우에, 상기 부분 행렬 B(1020)의 모든 열 블록의 무게는 2 이상이며, 무게가 3 이상의 홀수인 열 블록이 상기 부분 행렬 B(1020)에 적어도 하나 이상 포함될 수 있다. 또한, 상기 부분 행렬 B(1020)에 대응되는 기본 행렬

의 모든 열의 무게는 2 이상이며, 무게가 3 이상의 홀수인 열이 상기 기본 행렬

에 적어도 하나 이상 포함될 수 있다. Condition 1(a) : In the parity check matrix for the QC-LDPC code of Fig. 10, the submatrix B(1020) is

In the case where the circulant permutation matrices of the size do not include nested circulant matrices, the weight of all column blocks of the submatrix B(1020) is 2 or more, and at least one column block with an odd weight of 3 or more can be included in the submatrix B(1020). In addition, the basic matrix corresponding to the submatrix B(1020)

All columns of the matrix have a weight of 2 or greater, and the columns with an odd weight of 3 or greater are the basic matrix.

may contain at least one or more of:

크기의 순환 순열 행렬들이 중첩된 순환 행렬을 적어도 하나 이상 포함하는 경우에, 상기 부분 행렬 B(1020)의 모든 열 블록의 무게는 2 이상이며, 무게가 3 이상의 홀수인 열 블록이 적어도 하나 이상 상기 부분 행렬 B(1020)에 포함된다. 또한, 상기 부분 행렬 B(1020)에 대응되는 무게 행렬

에서 모든 열의 원소들의 합은 2 이상이며, 열의 원소들의 합이 3 이상의 홀수인 열이 상기 무게 행렬

에 적어도 하나 이상 포함된다. (상기

크기의 순환 순열 행렬들이 중첩된 순환 행렬이 포함되어 있는 열 블록의 무게가 2일 수도 3 이상일 수도 있다.) Condition 1(b) : In the parity check matrix for the QC-LDPC code of Fig. 10, the submatrix B(1020) is

In the case where the circulant permutation matrices of the size include at least one nested circulant matrix, the weights of all column blocks of the submatrix B(1020) are 2 or greater, and at least one column block whose weight is an odd number of 3 or greater is included in the submatrix B(1020). In addition, the weight matrix corresponding to the submatrix B(1020)

In the weight matrix, the sum of all the elements in the column is 2 or greater, and the column whose sum of the elements in the column is an odd number of 3 or greater is

At least one of the above is included.

The weight of the column block containing the circulant matrix, which is a nested circulant matrix of sizes 2 or 3 or more, may be 2 or 3 or more.)

크기 항등 행렬들로 구분할 수 있다. Condition 2 : All column weights and row weights of the submatrix E(1060) of the above Fig. 10 are 1. In addition, the column weights and row weights of the submatrix of the basic matrix and the weight matrix corresponding to the above submatrix E(1060) are all 1. Therefore, E(1060) and the submatrix of the basic matrix and the weight matrix corresponding to E(1060) are identity matrices or matrices that are converted to identity matrices by applying appropriate column permutation or row permutation, etc. (That is, E(1060) is an identity matrix or a matrix having an equivalent algebraic property.) If the parity check matrix of the above Fig. 10 is defined as a quasi-cyclic parity check matrix, the submatrix E has multiple

They can be distinguished by size identity matrices.

The above FIGS. 11a and 11b are embodiments of parity check matrices that satisfy at least one of Condition 1(a), Condition 1(b), or Condition 2. As briefly described above, FIG. 11a is an example of the case in FIG. 10 where K = 22*Z, M ₁ = 4*Z, M ₂ = 2*Z, and FIG. 11b is an example of the case in FIG. 10 where K = 10*Z, M ₁ = 4*Z, M ₂ = 7*Z. Note that since the code rate of the LDPC code corresponding to the parity check matrices of FIGS. 10, 11a, and 11b is K/N, a codeword with a lower code rate can be generated as M ₂ decreases. In other words, according to the present disclosure, LDPC encoding and decoding can be performed based on a parity check matrix that can support a lower code rate by further extending columns having degree 1 while including the above-described FIGS. 11a and 11b.

If a set of lifting sizes is used for LDPC encoding or decoding for a parity check matrix of a quasi-cyclic LDPC code, the number of columns constituting one column block of the parity check matrix is equal to or greater than the minimum value of the lifting size. For example, if the values of Table 6 are used as the lifting sizes, the number of columns constituting one column block of the parity check matrix can be at least 4 or more. Therefore, in a communication system in which the lifting sizes of Table 6 are practically applied to a parity check matrix of an LDPC code having a structure as in FIGS. 10, 11a, and 11b satisfying at least one of Condition 1(a), Condition 1(b), or Condition 2, this means that the number of columns with degree 3 in the submatrix B(1020) is at least 4 or more.

For reference, in a parity check matrix or a base matrix or a weight matrix, a core matrix may also be defined in a form satisfying at least one of Condition 1(a), Condition 1(b), or Condition 2 by adding one or two more rows as follows. However, in the present disclosure, for convenience, a parity check matrix [A(1010) B(1020)] including a submatrix B that satisfies only Condition 1(a) or Condition 1(b) is regarded as a core matrix (or kernel matrix or precoding matrix).

의 코어 행렬:

Core matrix of:

0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23

0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24

0 1 2 4 5 6 7 8 9 10 13 14 15 17 18 19 20 24 25

0 1 3 4 6 7 8 10 11 12 13 14 16 17 18 20 21 22 25

0 1 26

의 코어 행렬:

Core matrix of:

0 1 2 3 6 9 10 11

0 3 4 5 6 7 8 9 11 12

0 1 3 4 8 10 12 13

1 2 4 5 6 7 8 9 10 13

0 1 11 14

As an embodiment of the present disclosure, a method for improving the performance of an LDPC code according to a weight matrix and a method for improving the decoding convergence speed are described.

의 코어 행렬은 4개의 행으로 이루어져 있는데, 이를 수학식 14와 같은 무게 행렬로도 표현할 수 있다. 기본 행렬 1

또는 기본 행렬 2

에 의해 정의된 LDPC 부호는 하나의

크기 블록에 하나의 순환 순열 행렬이 대응되도록 정의하고 있기 때문에 기본 행렬과 무게 행렬은 기본적으로 같다.First, the basic matrix 2 defined in [How to determine the basic matrix]

The core matrix consists of four rows, which can also be expressed as a weight matrix as in Equation 14. Basic matrix 1

or base matrix 2

LDPC code defined by is one

Since we define a single cyclic permutation matrix to correspond to a size block, the base matrix and the weight matrix are basically the same.

[Mathematical formula 14]

크기 블록에 최대 하나의 순환 순열 행렬이 대응되도록 설계된 LDPC 부호는 복호화 시 하나의 행 블록 단위로 레이어드 복호화(layered decoding)을 수행하는데 적합한 구조이다. 즉, LDPC 부호의 구조는 Z-단위의 병렬 처리 프로세서를 통한 복호화를 수행하는데 적합한 구조임을 의미한다.In this way, one

LDPC codes, which are designed so that at most one cyclic permutation matrix corresponds to a size block, are structured to perform layered decoding in units of one row block during decoding. In other words, the structure of LDPC codes is structured to be suitable for performing decoding using a Z-unit parallel processing processor.

Since this layered decoding method usually performs parallel processing on one row block as a basic unit, it can be determined that one iteration of decoding is completed when decoding is performed the number of total row blocks. This means that if there are enough parallel processing processors, the decoding throughput through layered decoding is inversely proportional to the number of row blocks. However, if the same code length is supported using a parity check matrix with a small number of row blocks, the lifting size Z value increases further, so the amount of parallel processing processors required to simultaneously perform decoding on one row block increases.

은 4개의 행과 14개의 열로 이루어져 있으며, 각 열의 무게가 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3, 2, 2, 2인데, 만일 3개의 행과 13개의 열로 이루어져 있으며

와 무게 분포는 비슷한 무게 행렬

와 2개의 행과 12개의 열로 이루어져 있으며

와 무게 분포는 비슷한 무게 행렬

이 아래와 같이 구성될 수 있다.For example, the above weight matrix

It consists of 4 rows and 14 columns, and the weights of each column are 3, 3, 2, 3, 3, 2, 3, 3, 3, 2, 2, 2. If it consists of 3 rows and 13 columns,

And the weight distribution is similar to the weight matrix

It consists of 2 rows and 12 columns.

and the weight distribution is similar to the weight matrix

It can be structured as follows:

,

,

를 이용하여 동일한 부호 길이를 갖는 LDPC 부호를 생성할 수 있고, 각각의 패리티 검사 행렬에 대응되는 리프팅 크기를

,

,

이라 하면, , 의 관계가 있다. 또한 LDPC 복호기에서 각각의

개의 병렬 처리 프로세서가 허용된다면, 대략적인 복호화 정보 처리량은

는

의 1.5배,

는

의 2배가 될 수 있다.If each weight matrix

,

,

LDPC codes with the same code length can be generated using the same code length, and the lifting size corresponding to each parity check matrix can be

,

,

If so, , There is a relationship between . Also, in the LDPC decoder, each

If the number of parallel processing processors allowed, the approximate decryption information processing volume is

Is

1.5 times of

Is

can be twice as much.

In this way, if sufficient parallel processing processors are allowed, reducing the number of row blocks can increase the decryption information processing amount inversely. Therefore, in the case of a system requiring a very high decryption information processing amount, if more parallel processing processors can be applied, it is advantageous to keep the number of rows of the basic matrix or weight matrix, that is, the number of row blocks of the parity check matrix, small.

Although keeping the number of rows of the base matrix or weight matrix, or in other words the number of row blocks of the parity check matrix, small may be good from the perspective of decoding information processing volume, if the number of row blocks is set too small, serious restrictions may be placed on the algebraic characteristics of the LDPC code, such as the cycle characteristics or minimum distance characteristics, which may result in performance degradation. Therefore, the base matrix or weight matrix should be determined by simultaneously considering the target information processing volume and target error correction capability of the system.

As an embodiment of the present disclosure, a method for improving the performance of a code while having a high decoding information throughput is proposed. In particular, the present disclosure proposes an algebraic property that a core matrix part of a basic matrix or a weight matrix, which is closely related to a maximum decoding throughput or a peak data rate of a system, must satisfy. Of course, if the parity check matrix does not include a second part of the parity check matrix composed of submatrices C (1040), D (1050) and E (1060) of FIG. 10, the core matrix may be identical to the basic matrix or the weight matrix.

이하가 되기 때문에 오류 마루 (error floor) 현상이 쉽게 발생할 가능성이 높다. 따라서 , , , ...와 같이 0이 아닌 원소가 하나 밖에 없는 임의의 두 열에서 0이 아닌 원소들은 반드시 다른 행에 위치해야 한다. 이는 기본 행렬에 대해서도 무게가 1인 열들에 위치한 0이 아닌 원소들은 모두 서로 다른 행에 위치해 있음을 의미한다. 상기의 내용은 하기의 조건 3(a) 및 3(b)과 같이 정의될 수 있다.One of the conditions that the core matrix of the parity check matrix must satisfy is that when two columns are selected from the weight matrix corresponding to the core matrix, there is only one non-zero element. ( ) should not contain non-zero elements in only one row. As a simple example, , , , , ..., etc. The minimum distance of the parity check matrix corresponding to the weight matrix or the core matrix including this structure is

Since it is below, there is a high possibility that the error floor phenomenon will easily occur. Therefore, , , , ..., in any two columns that have only one non-zero element, the non-zero elements must be located in different rows. This also means that for the elementary matrix, all non-zero elements located in columns with weight 1 are located in different rows. The above can be defined as conditions 3(a) and 3(b) below.

Condition 3(a) : All columns of the basic matrix or weight matrix corresponding to the core matrix have weights greater than or equal to 2, or the number of columns with weight 1 is at most 1.

Condition 3(b) : If there are two or more columns with weight 1 among the columns of the basic matrix or weight matrix corresponding to the core matrix, the non-zero elements included in the columns with weight 1 are located in different rows.

크기 순환 순열 행렬 또는 순환 행렬들은 반드시 서로 다른 행 블록에 포함됨을 의미한다. 또한 상기 조건 3(a) 및 조건 (3b)는 심각한 오류 마루 현상을 방지하기 위한 구조인데, 만일 이 보다 더 우수한 오류 마루 특성을 얻기 위해서 다음과 같은 조건4가 더 추가될 수도 있다. 상술한 바와 같이 상기 순환 순열 행렬, 순환 행렬은

크기를 가질 수 있다.The above conditions 3(a) and 3(b) are satisfied when the number of column blocks consisting of only one circulating permutation matrix or circulating matrices included in the core matrix is at most 1, or when the core matrix includes two or more circulating permutation matrices or circulating matrices.

The size of the circular permutation matrix or circular matrix is necessarily included in different row blocks. In addition, the above conditions 3(a) and (3b) are structures for preventing serious error floor phenomenon, but if a better error floor characteristic is to be obtained, the following condition 4 may be additionally added. As described above, the above circular permutation matrix, circular matrix

Can have any size.

Condition 4 : The weight of the column corresponding to the information bit (or input bit or code block) in the parity check matrix corresponding to the core matrix is 3 or greater.

에 대응되는 패리티 검사 행렬처럼 정보 비트에 대응되는 열의 무게가 2인 경우가 없도록하여 부호화 이득은 감소할 수 있으나 오류 마루 현상을 개선하고자 할 때 적용할 수 있다.The above condition 4 is the basic matrix 2 of mathematical expression 14.

It can be applied when trying to improve the error floor phenomenon, but the encoding gain can be reduced by ensuring that the weight of the column corresponding to the information bit is not 2, such as the corresponding parity check matrix.

크기의 순환 순열 행렬들이 중첩된 순환 행렬을 포함하지 않는 경우에, 상기 부분 행렬 A(1010)의 모든 열 블록의 무게는 3 이상이며, 상기 부분 행렬 A(1010)에 대응되는 기본 행렬

의 모든 열의 무게는 3 이상임을 의미한다. 또한 QC-LDPC 부호에 대한 패리티 검사 행렬에서 부분 행렬 A(1010)가

크기의 순환 순열 행렬들이 중첩된 순환 행렬을 적어도 하나 이상 포함하는 경우에, 상기 부분 행렬 A(1010)의 모든 열 블록의 무게는 3 이상이며, 상기 부분 행렬 A(1010)에 대응되는 무게 행렬

의 모든 열의 원소들의 합은 3 이상임을 의미한다.The above condition 4 is that the submatrix A(1010) in the parity check matrix for the QC-LDPC code

If the circulant permutation matrices of the size do not contain nested circulant matrices, the weight of all column blocks of the submatrix A(1010) is 3 or greater, and the fundamental matrix corresponding to the submatrix A(1010)

It means that the weight of all columns is 3 or more. Also, in the parity check matrix for QC-LDPC code, the submatrix A(1010)

If the circulant permutation matrices of the size include at least one nested circulant matrix, the weight of all column blocks of the submatrix A(1010) is 3 or more, and the weight matrix corresponding to the submatrix A(1010)

It means that the sum of all the elements of the column is 3 or more.

크기의 순환 행렬을 구성하는 순환 순열 행렬이 3개 이상 중복(overlap)되어 있을 경우에는

값과 무관하게 사이클의 최대 길이가 6으로 한정된다. 사이클 길이가짧은 경우에는 반복 복호에 의한 성능 개선 효과가 줄어들기 때문에, 3 이상인 값을 원소로 포함하는 무게 행렬 또는 코어 행렬에 대응되는 패리티 검사 행렬은 부호 길이가 짧거나 부호율이 비교적 높은 경우에 사용하는 것이 적합하다. 본 개시에서는 다양한 부호율과 다양한 부호 길이를 지원하는 LDPC 부호의 설계 방법에 대해 다루기 때문에 무게 행렬의 코어 행렬에 3 이상인 원소가 포함되지 않도록 한다. (물론 싱글 패리티 검사 확장 파트에 대응되는 부분에는 포함될 수도 있다.)상기의 내용은하기의 조건 5와 같이 정의될 수 있다Another condition that the core matrix of the parity check matrix must satisfy may be that the weight matrix corresponding to the core matrix does not include an element greater than or equal to 3. In general, if the core matrix of the weight matrix includes an element greater than or equal to 3, it means that three or more cyclic permutation matrices correspond to the corresponding position.

If there are three or more circulant permutation matrices that constitute a circulant matrix of size that overlap,

Regardless of the value, the maximum length of the cycle is limited to 6. When the cycle length is short, the performance improvement effect by iterative decoding is reduced, so it is appropriate to use a parity check matrix corresponding to a weight matrix or core matrix including values of 3 or more as elements when the code length is short or the code rate is relatively high. Since this disclosure deals with a design method of an LDPC code supporting various code rates and various code lengths, the core matrix of the weight matrix does not include elements of 3 or more. (Of course, it may be included in the part corresponding to the single parity check extension part.) The above contents can be defined as the following condition 5.

Condition 5 : The weight matrix corresponding to the core matrix consists of only 0 and 1, or only 0, 1, and 2.

Another condition that the core matrix must satisfy is the first parity vector The submatrix B(1020) of Fig. 10 corresponding to must have the maximum rank to enable efficient encoding, and the following restrictive structure is desirable to prevent serious degradation of cycle characteristics.

Condition 6(a) : If the weight matrix corresponding to the core matrix consists of four rows, then the submatrix corresponding to B(1020) in the weight matrix and the fundamental matrix is one of the following:

Condition 6(b) : If the weight matrix corresponding to the core matrix consists of three rows, the submatrix of the basic matrix corresponding to the submatrix B(1020) is , and the weight matrix is one of:

Condition 6(c) : If the weight matrix corresponding to the core matrix consists of two rows, the submatrix of the basic matrix corresponding to the submatrix B(1020) is , and the weight matrix is one of:

크기의 0-행렬을 의미하며, 1은

크기의 항등 행렬

또는 순환 순열 행렬

(v > 0)을 의미한다. 또한, 2는

크기의 순환 행렬

를 의미한다().For reference, the above condition 6(a) shows the case where the weight matrix and the base matrix are the same, and condition 6(b) shows the case where the weight matrix is has the same form as the fundamental matrix only if 0 is in the fundamental matrix or weight matrix shown in Conditions 6(a), 6(b), and 6(c).

It means a 0-matrix of size 1.

Identity matrix of size

or cyclic permutation matrix

(v > 0). Also, 2 is

Circular matrix of size

It means ( ).

(또는

)이면 많은 수의 4-사이클이 생성되므로 기본적으로 v1, v2는

,

(또는

)를 만족하는 정수로 설정된다. 마찬가지로 인 경우에 v1 = 0인 경우에는 많은 수의 4-cycle이 생성되므로, 기본적으로 v1은

을 만족하는 정수, v2는

을 만족하는 정수로 설정된다. 이상은 4-사이클을 제거하기 위한 방법일 뿐이며, 보다 긴 사이클들을 얻기 위해서 v1, v2 값들은 다양한 방식으로 제한될 수 있다.In general, an upper bound on the cycle length can be predicted from the basic matrix or weight matrix, but the cycle characteristics of the parity check matrix corresponding to the basic matrix or weight matrix are unknown. For example, the submatrix B(1020) or In each case, regardless of the values of v1 and v2, the base matrix or weight matrix is or Although they are identical, their cycle characteristics are very different. If at least one of v1 or v2 is 0,

(or

) will generate a large number of 4-cycles, so basically v1, v2

,

(or

) is set to an integer satisfying . Likewise, In the case where v1 = 0, a large number of 4-cycles are generated, so basically v1 is

An integer satisfying v2 is

is set to an integer satisfying . The above is only a method to remove 4-cycles, and the values of v1 and v2 can be restricted in various ways to obtain longer cycles.

If the communication system applies the perforation of information bits as described in [Table 9], the following conditions that the core matrix must satisfy may be added.

Condition 7 : In an LDPC encoding system where puncturing of information bits is applied, a submatrix of a core matrix composed only of columns corresponding to the punctured information bits has at least one row with a row weight of 1.

Since the bits punctured at the receiver are regarded as bits lost during the reception process, the probability that the punctured bits are 0 and 1 is determined to be the same. This usually means 1 when decoding is performed using LR values, and 0 when decoding is performed using LLR values, but it may be determined in a different form based on the values used in the decoding process. When LDPC decoding is performed based on a parity check matrix that does not satisfy Condition 7, the punctured information bits may not be decoded if the ML (maximum likelihood) decoding or pseudo ML decoding technique is not used. Since the ML or pseudo ML decoding method is not usually used due to its complexity, the parity check matrix may be determined to satisfy Condition 7 in order to ensure a successful decoding.

If the LDPC code is a QC-LDPC code, the parity check matrix can be expressed based on the lifting size Z value and the base matrix and/or the weight matrix and/or the exponent matrix, so it can also be expressed as in the following condition 8.

Condition 8 : In a QC-LDPC encoding system in which puncturing of information bits is applied in units of a lifting size Z or a multiple thereof, a submatrix of a basic matrix composed of only a columns corresponding to a submatrix of a core matrix composed of only a*Z columns corresponding to the punctured a*Z (a: integer greater than or equal to 1) information bits has at least one row whose weight is 1. In addition, a submatrix of a weight matrix composed of only a columns corresponding to the submatrix of the core matrix composed of only a*Z columns has at least one row whose weight is 1 and whose element is 1.

For example, in a QC-LDPC encoding system where puncturing of the information bits of 2Z bits is always applied, condition 8 implies that a = 2.

Meanwhile, in the present disclosure, at least one of the above conditions may be used to construct a parity check matrix. That is, the parity check matrix may be determined to satisfy one of the above conditions or may be determined to satisfy a combination of at least two of the above conditions.

As an embodiment of the present disclosure, a method for improving the error floor performance of an LDPC code is proposed. In general, the error floor phenomenon of an LDPC code is greatly affected by the cycle characteristic of the Tanner graph. However, since the cycle characteristic of a QC LDPC code on the Tanner graph is determined by the relationship between the index or the cyclic shift value of the basic matrix and the cyclic permutation matrix, not only the position of the cyclic permutation matrix constituting the parity check matrix but also the cyclic shift value must be appropriately selected.

In the present disclosure, first parity bits (or first parity bit vector) in the first part of the parity check matrix composed of sub-matrices A (1010) and B (1020) in FIG. 10 We propose an algebraic property that the submatrix B(1020) corresponding to must satisfy.

(또는

)이며, 상기 부분 행렬 B(1020)은

(또는

) 크기의 기본 행렬 또는 무게 행렬에 대응된다. 또한 부분 행렬 B(1020)의 첫번째 열 블록은 3개의 순환 순열 행렬로 구성되어 있다. 이 때, 상기 순환 순열 행렬에는 항등 행렬이 포함될 수 있다. 즉, 본 개시에서 순환 순열 행렬은 항등 행렬의 각 원소들을 i 만큼 순환 이동시킨 형태의 행렬로 정의되며, i 값이 0인 경우 순환 순열 행렬은 항등 행렬이 될 수 있다. 이는 본 개시의 상세한 설명 전반에 적용될 수 있다. 또한 부분 행렬 B(1020)의 나머지 열 블록들은 2개의 순환 순열 행렬 또는 항등 행렬로 구성된다. 본 발명에서는 편의상 나머지 열 블록들은 항등 행렬이 이중 대각 구조로 구성되어 있는 경우만 표현하지만, 일반적으로 그와 같이 제한될 필요는 없다.The size of the above submatrix B(1020) is

(or

), and the submatrix B(1020) is

(or

) corresponds to a basic matrix or a weight matrix of the size of the submatrix B(1020). In addition, the first column block of the submatrix B(1020) is composed of three cyclic permutation matrices. At this time, the cyclic permutation matrix may include an identity matrix. That is, in the present disclosure, the cyclic permutation matrix is defined as a matrix in which each element of the identity matrix is cyclically shifted by i, and when the value of i is 0, the cyclic permutation matrix can be an identity matrix. This can be applied throughout the detailed description of the present disclosure. In addition, the remaining column blocks of the submatrix B(1020) are composed of two cyclic permutation matrices or identity matrices. In the present invention, for convenience, the remaining column blocks are expressed only when the identity matrix is composed of a dual diagonal structure, but in general, it is not necessary to be limited thereto.

A specific example of the partial matrix B(1020) is shown in Mathematical Expression 15. The partial matrix B(1020) can be determined based on at least one of the matrices included in Mathematical Expression 15 below. However, the embodiment of the present disclosure is not limited thereto, and various matrices satisfying the above characteristics (the first column block is composed of three cyclic permutation matrices, and the remaining column blocks are composed of two cyclic permutation matrices or an identity matrix) can be considered.

[Mathematical expression 15]

,

,

,

는 첫번째 열 블록이 세 개의 서로 다른 순환 순열 행렬

,

,

로 구성되어 있다. 또한, 수학식 15에서는 편의상

값이 3, 4, 5인 경우에 대해서만 나타내었지만, 그 이상의 정수에 대해서도 유사하게 부분 행렬 B(1020)이 정의될 수 있다. 또한 적절한 역변환(invertible transform) 과정을 통해 위와 같은 형태의 부분 행렬 B(1020)로 변환 가능한 행렬들은 대수적으로 동일한 행렬로 간주할 수 있다.In the above mathematical expression 15

,

,

,

The first column blocks are three different cyclic permutation matrices.

,

,

It consists of . Also, in mathematical expression 15, for convenience,

Although it is shown only for the cases where the values are 3, 4, and 5, the submatrix B(1020) can be defined similarly for integers greater than that. In addition, matrices that can be transformed into the submatrix B(1020) of the above form through an appropriate invertible transform process can be considered as algebraically identical matrices.

,

,

,

뿐만 아니라 유사한 형태의 더 큰 부분 행렬 B(1020)에 대해서 사이클 특성을 개선하는 방법을 제안하고자 한다. 편의상 QCLDPC 부호의 사이클 특성을 분석하는 방법 및 일부 대수적 특성에 대한 상세한 내용은 본 개시에서는 생략하지만, 참조 문헌 [Myung2005]의 내용을 참조한다.In the present disclosure, the mathematical expression 15 above

,

,

,

In addition, we propose a method to improve the cycle characteristics for a larger submatrix B(1020) of a similar form. For convenience, the detailed description of the method for analyzing the cycle characteristics of the QCLDPC code and some algebraic properties are omitted in this disclosure, but refer to the contents of the reference [Myung2005].

[Myung2005]

S. Myung, K. Yang, and J. Kim, “Quasi-Cyclic LDPC Codes for Fast Encoding,” IEEE Transactions on Information Theory, vol. 51, No. 8, pp. 2894-2901, Aug. 2005.

,

,

중에서 적어도 2개의 값은 같은 값으로 설정되었다.이 경우에 부호화 과정에서 사용되는

크기의

행렬이 항등 행렬

또는 단순한 순환 순열 행렬

가 되는데,

의 역행렬

가 항등 행렬

또는

같이 단순화되어 부호화 과정이 간결해진다. (자세한 QC LDPC 부호의 부호화 과정은 [Myung2005] 참조)구체적인 예로서

로 설정할 경우에

는

가 되며

는

가 되므로 효율적인 부호화를 수행할 수있다. 마찬가지로,

로 설정할 경우에

는

가 되며

는

가 되므로 효율적인 부호화를 수행할 수있다.If the remaining column blocks except the first column block in the submatrix B(1020) as in Equation 15 have a dual diagonal structure composed of identity matrices, the indices (or cyclic shift values) of the cyclic permutation matrix of the first column block were used for encoding convenience.

,

,

At least two values among them were set to the same value. In this case, the values used in the encoding process are

Size of

The matrix is an identity matrix

or a simple cyclic permutation matrix

It becomes,

Inverse matrix of

is the identity matrix

or

It is simplified together, so the encoding process becomes simpler. (For detailed encoding process of QC LDPC code, refer to [Myung2005]) As a specific example,

If set to

Is

Becomes

Is

Therefore, efficient encoding can be performed. Likewise,

If set to

Is

Becomes

Is

Therefore, efficient encoding can be performed.

인 경우에는다음 수학식 16에 나타낸 구조에 의해 태너 그래프 상에서 길이가

인 사이클

개가 항상 존재한다. 다시 말해,만일

의 값이 고정되어 있다면 리프팅 크기

및 지수

값에 상관없이 길이가

인 사이클이 항상 존재한다. (자세한 QC LDPC 부호의 사이클 특성에 대한 내용은 [Myung2005] 참조)however

In this case, the length on the Tanner graph is determined by the structure shown in the following mathematical expression 16.

In cycle

The dog is always present. In other words, if

If the value of is fixed, the lifting size

and index

Length regardless of value

There is always a cycle in the QC LDPC code. (For detailed information on the cycle characteristics of QC LDPC codes, see [Myung2005].)

[Mathematical formula 16]

인 경우에는 다음 수학식 17과 같은 구조로 인해, 리프팅 크기

및 지수

값에 상관없이

보다도 더 짧은 사이클이 항상 존재한다.Not only that

In this case, the lifting size is due to the structure as shown in the following mathematical expression 17.

and index

Regardless of the value

There are always shorter cycles.

[Mathematical formula 17]

값이 적절히 큰 경우에는 수학식 16 및 수학식 17과 같은 구조에 대응되는 태너 그래프의 사이클 특성이 LDPC 부호의 성능에 큰 영향을 주지 않을 수도 있다.하지만,

값이 상대적으로 작은 경우에는 오류 마루 현상으로 인해 BLER이 증가할 가능성이 있으며, 이는 시스템의 타겟 BLER가낮을수록 무시할 수 없는 문제가 된다.should

When the value is suitably large, the cycle characteristics of the Tanner graph corresponding to structures such as Equations 16 and 17 may not have a significant effect on the performance of the LDPC code. However,

When the value is relatively small, the BLER may increase due to the error floor phenomenon, which becomes a non-negligible problem as the target BLER of the system is lower.

,

,

가 특정 대수적인 조건을 만족하도록한정하여 사이클 특성을 개선하는 방법을 제안한다. 또한 상기 방법은 사이클 특성을 개선하면서도 LDPC 부호화 과정에서 필요한

행렬과 관련된 연산 복잡도가 합리적인 수준으로 증가하는 특징이 있음을 설명한다.In order to solve this problem, the present invention uses the indices (or cyclic shift values) of the cyclic permutation matrices that constitute the first column block of the partial matrix B(1020) having the structure of mathematical expression 15.

,

,

We propose a method to improve the cycle characteristics by limiting the satisfies certain algebraic conditions. In addition, the method improves the cycle characteristics while maintaining the required LDPC encoding process.

It explains that the computational complexity associated with matrices has a property of increasing to a reasonable level.

를

, (

는 홀수,

은 0 이상의 정수)라 할 때, 부분 행렬 B(1020)의 첫번째 열 블록을 구성하는 순환 순열 행렬들의 지수들 (또는 순환 이동 값)

,

,

는 서로 다른 정수이며, 다음의 조건들의 적어도 일부 또는 전부를 만족한다:If the lifting size for the parity check matrix of the QC LDPC code

cast

, (

is odd,

When B(1020) is an integer greater than or equal to 0, the indices (or circular shift values) of the cyclic permutation matrices that constitute the first column block of the submatrix B(1020)

,

,

are distinct integers, satisfying at least some or all of the following conditions:

와의 최대 공약수가 1이거나 1보다 큰

의 약수 중 가장 작은 수이다. (즉,

와 서로 소이거나 1 보다 큰

의 최소 약수를 최대 공약수로 갖는다.) Index condition 1a : At least one of the differences between the two indices (circular shift values) is a lifting size.

The greatest common divisor with is 1 or greater than 1

is the smallest number among the divisors of (i.e.,

and are prime or greater than 1

) has its least divisor as its greatest common divisor.

와의 공약수가 1이거나 1보다 큰

의 약수 중 가장 작은 수이다. Index condition 1b : Two of the differences between the two indices are the lifting magnitudes.

The common divisor with is 1 or greater than 1

It is the smallest number among the divisors of .

)이다. Index condition 2a: At least one of the differences between the two indices is(

)am.

가 1이고

인 경우에는 (

)이며,

가 3 이상인 홀수이고

인 경우에는 (

)이다. Index condition 2b: At least one of the differences between the two indices is

is 1

In this case (

) and

is an odd number greater than or equal to 3

In this case (

)am.

,

,

등을 의미한다.For reference, the difference between the exponents used in the above exponent conditions is

,

,

It means back.

와 서로 소인 경우에는 상기 두 지수와 관련된 순환 순열 행렬에 의해 결정되는 사이클의 길이가 최대화된다. 예를 들어,

의 값이

와 서로 소인 경우에 수학식17의 에 의해서 결정되는 태너 그래프 상의 사이클의 길이는

가 된다. 만일

와

의 최대 공약수가

라면 사이클 길이는

가 된다. 결과적으로

값이 증가할수록 사이클의 길이 또한 함께 증가하게 된다.According to the above index condition 1a, the difference between the two indices is

If and are coprime, the length of the cycle determined by the cyclic permutation matrix associated with the two indices is maximized. For example,

The value of

In the case where and are relatively prime, the mathematical expression 17 The length of a cycle on a Tanner graph is determined by

becomes. If

and

The greatest common divisor of

The ramen cycle length is

becomes. As a result

As the value increases, the length of the cycle also increases.

의 값이

와 서로 소인 경우에 수학식16의 구조에 의해 결정되는 사이클 길이는

가 된다. 만일

와

의 최대 공약수가

라면 사이클 길이는

가 된다. 결과적으로 Z값과 무관하게 사이클 길이가 고정되는 것이 아니라 Z 값 증가에 따라 사이클 길이도 증가함을 알 수 있다. 사이클 특성만을 고려하면 지수 사이의 차이가

와 서로 소인 것이 바람직하지만, 상황에 따라 다른 조건에 의해 최대 공약수 D가 작도록 (예를 들어 1보다 큰 Z의 최소 약수가 되도록)지수가 선택될 수 있다. 예를 들어,지수 사이의 차이가 Z와 서로 소인 특징을 만족할 수 없는 경우, 최대 공약수

가 작게되는 지수가 선택되는 것이 바람직하다.As another example,

The value of

In the case where and are coprime, the cycle length determined by the structure of mathematical expression 16 is

becomes. If

and

The greatest common divisor of

The ramen cycle length is

As a result, it can be seen that the cycle length is not fixed regardless of the Z value, but increases as the Z value increases. Considering only the cycle characteristics, the difference between the exponents is

It is desirable that they are coprime to each other, but depending on the situation, the exponents can be chosen so that the greatest common divisor D is small (for example, so that it is the least divisor of Z greater than 1) by other conditions. For example, if the difference between the exponents cannot satisfy the property of being coprime to Z, the greatest common divisor

It is desirable to select an exponent that makes the number smaller.

및

값이

와 서로 소인 경우에 와 같이 지수 a, b와 관련된 사이클 특성이 개성된 뿐만 아니라 와 같이 지수 b, c와 관련된 사이클 특성또한 마찬가지로 개선되는 특성이 있다. (수학식 15 및 수학식 15에 기반하여 확장된 다른 형태의 부분 행렬 B에 대해서도 마찬가지로 성립한다.)The above index condition 1b is a condition for further improving the cycle characteristics by further restricting the index condition than index condition 1a. For example,

and

The value

And in case of mutual primacy Not only is the cycle characteristic related to the indices a and b unique, Likewise, the cycle characteristics related to the indices b and c are also improved. (The same holds true for other forms of submatrix B extended based on Equation 15 and Equation 15.)

,

,

가 모두 다를 때, 부호화 과정에서 필요한

행렬이

와 같이 정의된다. 이러한

행렬은

을 구하기도 쉽지 않지만,

행렬의 무게 밀도 (density of weights) 또한 일반적으로 저밀도 특성이 아닌 고밀도 특성을 갖는 경우가 많다. 즉, 저밀도 특성을 갖는

행렬이

행렬의 저밀도 특성을 보장하지 못하는 특징이 있다. 이러한

행렬의 고밀도 특성은 부호화 복잡도를 증가시키는 원인이기 때문에

행렬의 밀도는 가능한 낮은 것이 바람직하며,

행렬은 간단한 구조를 갖는 것이 바람직하다.Another form of submatrix B based on equation 15 and equation 15 is

,

,

When all are different, the encoding process requires

The matrix

is defined as follows.

The matrix is

It is not easy to find,

The density of weights of a matrix also often has a high density characteristic rather than a low density characteristic. That is, it has a low density characteristic.

The matrix

There is a characteristic that it does not guarantee the low density characteristics of the matrix.

The high density characteristic of the matrix is what increases the encoding complexity.

It is desirable that the density of the matrix be as low as possible.

It is desirable for matrices to have a simple structure.

행렬을 가능한 단순화하기 위한 조건이다. 예를 들어, 상기 지수 조건 2a에서 라 할 경우에The above index conditions 2a and 2b are for efficient LDPC encoding.

It is a condition for simplifying the matrix as much as possible. For example, in the above index condition 2a, In that case

Become This is it. Here silver

는 비교적 간단하게 결정될 수 있으나 값이 증가함에 따라

에 의한 연산 복잡도는 증가함을 알 수 있다. 따라서 시스템에서 허용 가능한 복잡도에 따라

값을 적절히 제한하여 사용할 수 있다. 통상적으로 값은

범위에서 사용하는 것이 바람직하나 시스템의 허용 범위에 따라 더 큰 값이 사용될 수도 있다.since

can be determined relatively simply, but As the value increases

It can be seen that the computational complexity increases. Therefore, depending on the complexity that is acceptable in the system,

The values can be used by appropriately limiting them. Usually, The value is

It is recommended to use a range, but a larger value may be used depending on the system's allowable range.

인 임의의 비트열 에 대해

크기의 순환 순열 행렬

를 곱하는 연산 은 실제 행렬 곱 연산이라기 보다 비트열 에 대해

비트만큼 순환 이동 (circular shift)하는 것과 동일하다. 즉, 실제로는 행렬 곱이라기 보다는 비트 이동 연산으로 구현 가능하기에상기 연산은 복잡도가 매우 낮은 연산 또는 동작을 의미한다. 그뿐만 아니라 를 연산하는 과정에서도 의 각 항들을 전개하여 연산하는 것이 아니라 와 같이 단계적인 계산을 통해 연산 복잡도를 최소화할 수 있다. 간단한 예로서 다음과 같은 방법으로 연산을 수행할 수 있다:For reference, the length is

An arbitrary bit string About

Circular permutation matrix of size

Operation of multiplying is a bit-string operation rather than an actual matrix multiplication operation. About

It is equivalent to doing a circular shift of bits. That is, in reality, it can be implemented as a bit shift operation rather than a matrix multiplication, so the above operation means an operation or operation with very low complexity. In addition, Even in the process of calculating Rather than expanding and calculating each term, The computational complexity can be minimized through step-by-step calculations, as in the following example:

을 결정하여 부호화가수행될 수 있다. 하지만, 모든 두 지수 사이의 차이들이 형태인 경우는 사이클 특성이 나빠질 가능성이 높다. 따라서, 효율적인 부호화와 좋은 사이클 특성을 위해서는 두 지수 사이의 차이들 중 적어도 하나는 (

)인 특성을 만족하고,나머지 지수 차이들은 지수 조건 1a또는 지수 조건 1b를 만족하도록 하는 방법이 고려될 수 있다. 또한,두 지수 사이의 차이가 이고 지수 조건 1a또는지수 조건 1b중 적어도 하나를 만족하는 경우가 있다면 상기 지수들을 선택할 수 있다.In the above index condition 2a me In the same case,

Encoding can be performed by determining the difference between all two indices. However, In the case of the form, the cycle characteristics are likely to be poor. Therefore, for efficient encoding and good cycle characteristics, at least one of the differences between the two indices should be (

) and the remaining exponent differences satisfy the exponent condition 1a or exponent condition 1b. In addition, the difference between the two exponents can be considered. The above indices can be selected if at least one of the index conditions 1a or 1b is satisfied.

와 항상 서로 소가 아님을 알 수 있다. 즉,

와 두 지수의 차이는 1 보다 큰 공약수를 갖는다. 을 만족하는 가 있다는 것은

임을 의미하는데, 이는 지수 조건 2b를 만족해야

조건에 의해

와 두 지수의 차이가 서로 소가 아니며,

를 공약수로 갖는다.Index condition 2b is a condition for further improving cycle characteristics while enabling efficient encoding by restricting the index condition more than index condition 2a. When index condition 2b is satisfied, the encoding complexity increases somewhat compared to the existing 5G LDPC code, but the cycle characteristics are improved. Of course, if there is no case where index condition 2b is satisfied, the indices can be determined by considering index condition 2a. For reference, in index condition 2a, The difference between the two indices is , except that

And you can always see that they are not the same. That is,

And the difference between the two exponents has a common divisor greater than 1. Satisfying That there is

This means that the index condition 2b must be satisfied.

By conditions

And the difference between the two exponents is not small,

has as a common divisor.

As an embodiment of the present disclosure, a more specific example of constructing a submatrix B(1020) of FIG. 10 using the above exponential conditions is described.

First, consider a communication system or broadcasting system in which lifting size sets are defined as shown in Tables 3 to 8, such as 5G, and only lifting sizes included in the lifting size sets can be applied. In addition, a separate parity check matrix or index matrix can be defined for each lifting size set. That is, in the case of Tables 3 to 8, a parity check matrix or index matrix, etc. can be defined for a total of eight set indices.

,

,

를 다음과 같이 결정한다고 하자. 일반적으로

에 () 대응되는 패리티 검사 행렬의 부분 행렬 B에 대한 지수

,

,

값이 모두 다를 수도 있기 때문에 편의상

,

,

로 표현하였다.In Equation 15 and another form of submatrix B extended based on Equation 15,

,

,

Let us decide as follows. In general,

to ( ) index for the submatrix B of the corresponding parity check matrix

,

,

For convenience, since the values may all be different

,

,

It was expressed as .

) Example 1 of selecting an index (

)

는 임의의 정수-

is an arbitrary integer

는

이며, 여기서

는 를 만족하는 정수이며, 즉,부분 행렬 B에 대응되는 지수들 중

,

는 을 만족하는 정수이다. 여기서

는

,

의 최대공약수를 의미하며,

는

에 대응되는 리프팅 크기 집합에 속해 있는 임의의 리프팅 크기를 의미한다.-

Is

and here

Is is an integer satisfying , that is, among the indices corresponding to the submatrix B,

,

Is is an integer satisfying . Here,

Is

,

It means the greatest common divisor of ,

Is

It refers to any lifting size that belongs to the set of lifting sizes corresponding to .

는

이며, 여기서

는

에 대응되는 리프팅 크기 집합에 속해 있는 리프팅 크기 값들 중 가장 큰 리프팅 크기

보다는 작은 리프팅 크기 중 하나이다.-

Is

and here

Is

The largest lifting size among the lifting size values belonging to the corresponding lifting size set.

It is one of the smaller lifting sizes.

에 대해 이므로 지수 조건 1a를 만족하며, 에서

는

값들 중 하나이면서 각각의

값은 서로 배수 관계이므로 (

배수 관계),

의 정의에 따라 이 성립하여 지수 조건 1b도 만족하게 된다. 그런데 이므로 지수 조건 2a 및 지수 조건 2b는 리프팅 크기

에 따라 만족 여부가 달라진다. 예를 들어,

인 경우에는 지수 조건 2a 및 지수 조건 2b를 항상 만족하지만,

인 경우에는 가 성립하여

크기의 순환 순열 행렬

및

는 사실상 같게 되므로 지수 조건 2a 및 지수 조건 2b를 만족하지 않을 수 있다. 다시 말해,

인 경우에는 수학식 16과 같은 구조가 되며 사이클 특성이 개선되지 않음을 의미한다. 결론적으로 다양한 길이의 리프팅 크기에 대해 사이클 특성을 개선하기 위해서는

값은 되도록 작은 값으로 결정되는 것이 바람직하다.If we calculate the difference between each index for the submatrix B determined through the above index selection example 1, we get an arbitrary lifting size

About Therefore, it satisfies the index condition 1a, at

Is

One of the values, each of which

Since the values are multiples of each other (

drainage relationship),

According to the definition of This is established and the index condition 1b is also satisfied. However, Therefore, index condition 2a and index condition 2b are the lifting size

Satisfaction varies depending on the situation. For example,

In this case, the index conditions 2a and 2b are always satisfied, but

In this case is established

Circular permutation matrix of size

and

Since they are virtually the same, they may not satisfy the exponent conditions 2a and 2b. In other words,

In this case, the structure is the same as mathematical expression 16, which means that the cycle characteristics are not improved. In conclusion, in order to improve the cycle characteristics for lifting sizes of various lengths,

It is desirable that the value be determined as small as possible.

값이

값에 비해 상대적으로 클 경우에 (즉, 에서 값이 큰 경우에)

행렬 관련 연산으로 인해 부호화 복잡도가 크게 증가할 가능성이 높다. 따라서

값은 사이클 특성과 부호화 복잡도를 고려하여 선택될 수 있다. 사이클 특성 개선만을 고려할 경우에는

에 대응되는 리프팅 크기 집합에 속해 있는 리프팅 크기 값들 중 가장 작은 리프팅 크기가

로 선택될 수 있다. 또한 제한적인 부호화 복잡도 증가를 고려할 경우에는

에 대응되는 리프팅 크기 집합에 속해 있는 리프팅 크기 값들 중 가장 작은 리프팅 크기 보다 크고, 가장 큰 리프팅 크기 보다 작은 리프팅 크기가

로 선택될 수 있다. 통상적으로 리프팅 크기 집합에 포함된 리프팅 크기가 , , ..., 라 할 때 (

),

값은

(

)로 설정될 수 있다. 일반적으로

,

, ...,

의 값들이 연속적인 정수 값이 아니라면,

값은

,

, ... 가 아닌 정수로 선택될 수도 있다. 상기 실시예 외에도 다른 실시예에 대해서도

는 앞서 설명한 바와 같이 다양한 조건에 기반하여 통해 선택될 수 있으나 설명의 편의를 위해 자세한 설명은 생략할 수도 있다.But the lifting size for LDPC encoding

The value

If it is relatively large compared to the value (i.e., at (if the value is large)

It is likely that the encoding complexity will increase significantly due to matrix-related operations. Therefore,

The value can be selected by considering the cycle characteristics and encoding complexity. If only the cycle characteristics improvement is considered,

The smallest lifting size among the lifting size values belonging to the corresponding lifting size set is

can be selected. Also, when considering the limited increase in encoding complexity,

Among the lifting size values belonging to the corresponding lifting size set, a lifting size that is larger than the smallest lifting size and smaller than the largest lifting size

can be selected. Typically, the lifting sizes included in the lifting size set are , , ..., When I say (

),

The value is

(

) can be set to . Generally,

,

, ...,

If the values are not consecutive integers,

The value is

,

, ... may be selected as an integer other than the above embodiment. In addition to the above embodiment, for other embodiments,

As explained above, it can be selected based on various conditions, but detailed explanation may be omitted for convenience of explanation.

, 즉,

로 설정하였을 때 지수 선택의 예를 다음에 나타내었다.For convenience, as a concrete example of the index selection method,

, in other words,

An example of index selection when set to is shown below.

) Example 2 of selecting an index (

)

-

(

로 설정하면, ,

)-

(

If set to , ,

)

는

(또는

)이며, 여기서

는

에 대응되는 리프팅 크기 집합에 속해 있는 리프팅 크기 값들 중 가장 큰 리프팅 크기

보다는 작은 리프팅 크기 중 하나이다.-

Is

(or

) and here

Is

The largest lifting size among the lifting size values belonging to the corresponding lifting size set.

It is one of the smaller lifting sizes.

이 되어 임의의 리프팅 크기

에 대해 항상 이 성립하고, 이 되어 이 성립하므로 지수 조건 1a 및 지수 조건 1b를 만족할 수 있다. 상기 지수 선택 예 2처럼

인 경우에는

뿐만 아니라 일반적으로 )를 만족하는 임의의

에 대해서도 지수 조건 1a 및 지수 조건 1b를 만족할 수 있다. 즉, 인 정수

에 대해,

,

,

,와 같이 설정된 부분 행렬 B는 지수 조건 1a 및 지수 조건 1b를 만족한다. 또한, 이므로 지수 조건 2a 및 지수 조건 2b는 리프팅 크기

에 따라 만족 여부가 달라진다.

(또는

)는 앞서 설명한 것처럼 사이클 특성 개선 및 부호화 복잡도를 고려하여 다양한 조건에 기반하여 선택될 수 있다.If we calculate the difference between each index for the submatrix B determined through the above index selection example 2,

This is an arbitrary lifting size

Always about This is established, Become this Since this holds, index condition 1a and index condition 1b can be satisfied. Like the index selection example 2 above.

In this case

as well as in general ) satisfying any

It is also possible to satisfy the index condition 1a and the index condition 1b. That is, In the integer

About,

,

,

, the submatrix B set as satisfies the index condition 1a and the index condition 1b. In addition, Therefore, index condition 2a and index condition 2b are the lifting size

Satisfaction varies depending on the situation.

(or

) can be selected based on various conditions, taking into account cycle characteristic improvement and encoding complexity, as explained above.

A specific example related to index selection example 2 is described below.

에 대한 패리티 검사 행렬에서 부분 행렬 B의 예를 나타낸 것이다. (수학식 15의 행렬들의 를 설정한 예시이다.) 부분행렬 B는 하기 수학식 18에 포함된 행렬들 중 적어도 하나에 기반하여 결정될 수 있다. 하지만, 본 개시의 실시예가 이에 한정되는 것은 아니다. 즉, 하기 실시예는 리프팅 크기 중 32가 선택되는 경우를 일 예로 설명한 것이나 상기 표 8에 포함된 리프팅 크기 중 어느 하나가 선택될 수 있다. 따라서, 리프팅 크기에 따라 결정된 c에 기반하여 다양한 행렬들이 고려될 수 있다.Given a set of lifting sizes as in Table 8, a specific example of the submatrix B is given in the following mathematical expression 18. Mathematical expression 18 is

An example of a submatrix B in the parity check matrix for is shown. (Matrix of Equation 15) Here is an example of setting the submatrix B. The submatrix B may be determined based on at least one of the matrices included in the following mathematical expression 18. However, the embodiments of the present disclosure are not limited thereto. That is, the following embodiment describes an example in which 32 of the lifting sizes is selected, but any one of the lifting sizes included in the above Table 8 may be selected. Accordingly, various matrices may be considered based on c determined according to the lifting size.

[Mathematical expression 18]

- (Choose 32 lifting sizes)

값이 8, 16, 32와 같이 32 이하로 선택될 경우에는

로부터

이 되어 사실상

행렬이 항등 행렬

가 되어

또한 항등 행렬

가 되므로 부호화 과정이 간결해지는 반면에 사이클 특성이 개선되지 않는 단점이 있다. 만일 사이클 특성을 개선하면서 제한된 부호화 복잡도 증가를 고려했을 때 상기 수학식 18의 구조를 갖는 부분 행렬에서 에 대응되는 지수 쌍 는 다음과 같은 조합들이 가능할 수 있다.In the case of mathematical expression 18, the lifting size in the 0th lifting size set

If the value is selected as 32 or less, such as 8, 16, or 32,

From

This has become a reality

The matrix is an identity matrix

Become

Also the identity matrix

Since the encoding process becomes simpler, there is a disadvantage that the cycle characteristic is not improved. If the cycle characteristic is improved while considering the limited increase in encoding complexity, in the submatrix having the structure of the above mathematical expression 18, The corresponding exponent pair The following combinations may be possible:

[Table 10]

를 선택하여

로 결정될 수 있다.The above Table 10 is only an example, and is generally one of the lifting size values smaller than Zmax.

By selecting

can be determined by

값은 특정 기준 값 보다 작은 리프팅 크기들 중에서 가장 큰 리프팅 크기에 기반하여 결정될 수도 있다. 구체적으로 설명하면, 만일 기준 값이 96로 설정되었다면, [표 3] 내지 [표 8]과 같은 리프팅 크기 집합을 사용하는 시스템에서 각각의 리프팅 크기 집합에서 96 이하인 수는 순서대로 64, 96, 80, 56, 72, 88, 52, 60이다. 따라서 각각의 리프팅 크기 집합에서 주어진 기준 값에 기반하여각 리프팅 크기 집합 인덱스에 따라 정의되는 패리티 검사 행렬에 대응되는

값이 결정된다면, 상기

값은 각 리프팅 크기 집합 인덱스에 따라 순서대로 65, 97, 81, 57, 73, 89, 53, 61로 정의될 수 있다. 만일 기준 값이 48로 설정되었다면, 마찬가지 방법으로 상기

값은 각 리프팅 크기 집합 인덱스에 따라 순서대로 33, 49, 41, 29, 37, 45, 27, 31로 정의될 수 있다.참고로 [표 3] 또는 [표 8]에서 ()안의 숫자를 제외한 리프팅 크기 집합을 사용하는 경우에, i _LS = 1인 리프팅 크기 집합에 포함된 리프팅 크기 중 i번째로 큰 리프팅 크기를 기준 값으로 결정하면, 각 리프팅 크기 집합 인덱스에 따라 정의되는 패리티 검사 행렬에 대응되는

값은 각 집합에서 i번째로 큰 리프팅 크기에 1을 더한 정수로 결정되는 특징이 있다.As one embodiment of the present disclosure, the above

The value may be determined based on the largest lifting size among lifting sizes smaller than a specific reference value. Specifically, if the reference value is set to 96, in a system using lifting size sets such as [Table 3] to [Table 8], the numbers less than or equal to 96 in each lifting size set are 64, 96, 80, 56, 72, 88, 52, and 60 in that order. Therefore, in each lifting size set, based on the given reference value, the parity check matrix corresponding to the index of each lifting size set is defined.

If the value is determined, the above

The values can be defined as 65, 97, 81, 57, 73, 89, 53, 61 in order according to each lifting size set index. If the reference value is set to 48, the same method can be used.

The values can be defined as 33, 49, 41, 29, 37, 45, 27, 31 in order according to each lifting size set index. For reference, in the case of using a lifting size set excluding the numbers in () in [Table 3] or [Table 8], if the i-th largest lifting size among the lifting sizes included in the lifting size set with i _LS = 1 is determined as the reference value, the parity check matrix corresponding to each lifting size set index is defined.

The value has the characteristic that it is determined as an integer that adds 1 to the ith largest lifting size in each set.

값이 결정된다면 (i=5), 상기

값은 각 리프팅 크기 집합 인덱스에 따라 순서대로 17, 25, 21, 15, 19, 23, 14, 16으로 정의될 수 있다. 마찬가지 방법으로 각각의 리프팅 크기 집합에서 4번째로 큰 수에 기반하여 리프팅 크기 집합 인덱스에 따라 정의되는 패리티 검사 행렬에 대응되는

값이 결정된다면 (i=4),

값은 리프팅 크기 집합 인덱스에 따라 순서대로33, 49, 41, 29, 37, 45, 27, 31로 정의될 수 있다. 마찬가지 방법으로 각각의 리프팅 크기 집합에서 3번째로 큰 수에 기반하여 리프팅 크기 집합 인덱스에 따라 정의되는 패리티 검사 행렬에 대응되는

값이 결정된다면 (i=3),

값은 리프팅 크기 집합 인덱스에 따라 순서대로 65, 97, 81, 57, 73, 89, 53, 61로 정의될 수 있다. 마찬가지 방법으로 각각의 리프팅 크기 집합에서 2번째로 큰 수에 기반하여 리프팅 크기 집합 인덱스에 따라 정의되는 패리티 검사 행렬에 대응되는

값이 결정된다면 (i=2),

값은 리프팅 크기 집합 인덱스에 따라 순서대로 129, 193, 161, 113, 145, 177, 105, 121로 정의될 수 있다.In addition, for the uniformity of the encoding method, the i-th largest lifting size in each lifting size set may be selected (i = 2, 3, 4, ...). For example, in a system using the lifting size sets as in [Table 3], the fifth largest numbers in each lifting size set are 16, 24, 20, 14, 18, 22, 13, and 15. Therefore, based on the fifth largest number in each lifting size set, the parity check matrix corresponding to each lifting size set index is defined.

If the value is determined (i=5), the above

The values can be defined as 17, 25, 21, 15, 19, 23, 14, 16 in order according to each lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the fourth largest number in each lifting size set.

If the value is determined (i=4),

The values can be defined as 33, 49, 41, 29, 37, 45, 27, 31 in order of the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the third largest number in each lifting size set.

If the value is determined (i=3),

The values can be defined as 65, 97, 81, 57, 73, 89, 53, 61 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the second largest number in each lifting size set.

If the value is determined (i=2),

The values can be defined as 129, 193, 161, 113, 145, 177, 105, 121 in order of the lifting size set index.

값이 결정된다면 (i=5), 상기

값은 리프팅 크기 집합 인덱스에 따라 순서대로 33, 49, 41, 29, 37, 45, 27, 31으로 정의될 수 있다. 마찬가지 방법으로 각각의 리프팅 크기 집합에서 4번째로 큰 수를 바탕으로 리프팅 크기 집합 인덱스에 따라 정의되는 패리티 검사 행렬에 대응되는

값이 결정된다면 (i=4),

값은 리프팅 크기 집합 인덱스에 따라 순서대로 65, 97, 81, 57, 73, 89, 53, 61로 정의될 수 있다. 마찬가지 방법으로 각각의 리프팅 크기 집합에서 3번째로 큰 수에 기반하여 리프팅 크기 집합 인덱스에 따라 정의되는 패리티 검사 행렬에 대응되는

값이 결정된다면 (i=3),

값은 리프팅 크기 집합 인덱스에 따라 순서대로 129, 193, 161, 113, 145, 177, 105, 121로 정의될 수 있다. 마찬가지 방법으로 각각의 리프팅 크기 집합에서 2번째로 큰 수를 바탕으로 리프팅 크기 집합 인덱스에 따라 정의되는 패리티 검사 행렬에 대응되는

값이 결정된다면 (i=2),

값은 리프팅 크기 집합 인덱스에 따라 순서대로 257, 385, 321, 225, 289, 353, 209, 241로 정의될 수 있다.In a system that uses the lifting size sets of values excluding the values in () in [Table 8], the fifth largest numbers in each lifting size set are 32, 48, 40, 28, 36, 44, 26, and 30. Therefore, the parity check matrix corresponding to each lifting size set index is defined based on the fifth largest number in each lifting size set.

If the value is determined (i=5), the above

The values can be defined as 33, 49, 41, 29, 37, 45, 27, 31 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the fourth largest number in each lifting size set.

If the value is determined (i=4),

The values can be defined as 65, 97, 81, 57, 73, 89, 53, 61 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the third largest number in each lifting size set.

If the value is determined (i=3),

The values can be defined as 129, 193, 161, 113, 145, 177, 105, 121 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the second largest number in each lifting size set.

If the value is determined (i=2),

The values can be defined as 257, 385, 321, 225, 289, 353, 209, 241 in order of the lifting size set index.

행렬이

이 되는데, 상기 지수 선택 예 2에 따라 리프팅 크기

값이

보다 작거나 같은 경우에는 이 성립하게 되어 결국

이므로 사이클 특성이 개선되지는 않지만,

이 성립함을 이용하여 효율적인 LDPC 부호화가 가능하다. 리프팅 크기

값이

보다 큰 경우에는 를 만족하는 가 존재하여 (

) 이 되고, 따라서 인 성질을 이용하여 부호화 복잡도는 증가하지만 효율적인 LDPC 부호화가 가능하다. 여기서

와

에 의해서 결정되는 사이클 길이는 기존의

에서 로 증가한다.

와

또는

와

에 의해서 결정되는 사이클 길이는 지수 조건 1a, 지수 조건 1b를 만족하기 때문에

값에 비례하여 크게 증가한다.Also, as shown in the mathematical expression 18 and the table 10 and the corresponding examples, According to the pair,

The matrix

This is done, and the lifting size is determined according to the above index selection example 2.

The value

If less than or equal to This was established and eventually

Therefore, the cycle characteristics are not improved,

Using this establishment, efficient LDPC encoding is possible. Lifting size

The value

In larger cases Satisfying exists (

) This becomes, and therefore By using the human nature, efficient LDPC encoding is possible, although the encoding complexity increases. Here,

and

The cycle length determined by the existing

at It increases to .

and

or

and

The cycle length determined by satisfies exponential condition 1a and exponential condition 1b.

It increases significantly in proportion to the value.

, 즉,

로 설정하였을 때 지수 선택의 예를 다음에 나타내었다.For convenience, as a concrete example of the index selection method,

, in other words,

An example of index selection when set to is shown below.

) Example 3 of selecting an index (

)

-

(

로 설정하면, ,

)-

(

If set to , ,

)

는

(또는

)이며, 여기서

는

에 대응되는 리프팅 크기 집합에 속해 있는 리프팅 크기 값들 중 가장 큰 리프팅 크기

보다는 작은 리프팅 크기 중 하나이다.-

Is

(or

) and here

Is

The largest lifting size among the lifting size values belonging to the corresponding lifting size set.

It is one of the smaller lifting sizes.

이 되어 임의의 리프팅 크기

에 대해 항상 이 성립하고,

이 되어 이 성립하므로 지수 조건 1a 및 지수 조건 1b를 만족할 수 있다. 상기 지수 선택 예 3처럼

인 경우에는

뿐만 아니라 일반적으로 )를 만족하는 임의의

에 대해서도 지수 조건 1a 및 지수 조건 1b를 만족할 수 있다.즉, 인 정수

에 대해,

,

,

,와 같이 설정된 부분 행렬 B는 지수 조건 1a 및 지수 조건 1b를 만족한다. 또한, 이므로 지수 조건 2a 및 지수 조건 2b는 리프팅 크기

에 따라 만족 여부가 달라진다.

(또는

)는 앞서 설명한 것처럼 사이클 특성 개선 및 부호화 복잡도를 고려하여 다양한 조건에 기반하여 선택될 수 있다.If we calculate the difference between each index for the submatrix B determined through the above index selection example 3,

This is an arbitrary lifting size

Always about This is established,

Become this Since this holds, index condition 1a and index condition 1b can be satisfied. Like the index selection example 3 above.

In this case

as well as in general ) satisfying any

It is also possible to satisfy the index condition 1a and the index condition 1b. That is, In the integer

About,

,

,

, the submatrix B set as satisfies the index condition 1a and the index condition 1b. In addition, Therefore, index condition 2a and index condition 2b are the lifting size

Satisfaction varies depending on the situation.

(or

) can be selected based on various conditions, taking into account cycle characteristic improvement and encoding complexity, as explained above.

Specific examples related to index selection example 3 are described below.

에 대한 패리티 검사 행렬에서 부분 행렬 B의 예를 나타낸 것이다. (수학식 15의 행렬들의 를 설정한 예시이다.) 부분행렬 B는 하기 수학식 19에 포함된 행렬들 중 적어도 하나에 기반하여 결정될 수 있다. 하지만, 본 개시의 실시예가 이에 한정되는 것은 아니다. 즉, 하기 실시예는 리프팅 크기 중 32가 선택되는 경우를 일 예로 설명한 것이나 상기 표 8에 포함된 리프팅 크기 중 어느 하나가 선택될 수 있다. 따라서, 리프팅 크기에 따라 결정된 c에 기반하여 다양한 행렬들이 고려될 수 있다.Given a set of lifting sizes as in Table 8, a specific example of the submatrix B is given in the following mathematical expression 19. Mathematical expression 19 is

An example of a submatrix B in the parity check matrix for is shown. (Matrix of Equation 15) Here is an example in which c is set.) The submatrix B can be determined based on at least one of the matrices included in the following mathematical expression 19. However, the embodiment of the present disclosure is not limited thereto. That is, the following embodiment describes an example in which 32 is selected among the lifting sizes, but any one of the lifting sizes included in Table 8 may be selected. Accordingly, various matrices can be considered based on c determined according to the lifting size.

[Mathematical formula 19]

- (Choose 32 lifting sizes)

값이 8, 16, 32와 같이 32 이하로 선택될 경우에는 로부터

이 되어 사실상

행렬이순환 순열 행렬

가 되어

는 순환 순열 행렬

가 되므로 부호화 과정이 간결해지는 반면에 사이클 특성이 개선되지 않는 단점이 있다. 만일 사이클 특성을 개선하면서 제한된 부호화 복잡도 증가를 고려했을 때 상기 수학식 18의 구조를 갖는 부분 행렬에서 에 대응되는 지수 쌍 는 다음과 같은 조합들이 가능할 수 있다.In the case of mathematical expression 19, the lifting size in the 0th lifting size set

If the value is selected as 32 or less, such as 8, 16, or 32, From

This has become a reality

Matrix is a cyclic permutation matrix

Become

is a cyclic permutation matrix

Since the encoding process becomes simpler, there is a disadvantage that the cycle characteristic is not improved. If the cycle characteristic is improved while considering the limited increase in encoding complexity, in the submatrix having the structure of the above mathematical expression 18, The corresponding exponent pair The following combinations may be possible:

[Table 11]

를 선택하여

로 결정될 수 있다.The above Table 11 is only an example, and is generally one of the lifting size values smaller than Zmax.

By selecting

can be determined by

값은 특정 기준 값 보다 작은 리프팅 크기들 중에서 가장 큰 리프팅 크기에 기반하여 결정될 수도 있다. 구체적으로 설명하면, 만일 기준 값이 96으로 설정되었다면, [표 3] 내지 [표 8]과 같은 리프팅 크기 집합을 사용하는 시스템에서 각각의 리프팅 크기 집합에서 96 이하인 수는 순서대로 64, 96, 80, 56, 72, 88, 52, 60이다. 따라서 각각의 리프팅 크기 집합에서 주어진 기준 값에 기반하여각 리프팅 크기 집합 인덱스에 따라 정의되는 패리티 검사 행렬에 대응되는

값이 결정된다면, 상기

값은 각 리프팅 크기 집합 인덱스에 따라 순서대로 64, 96, 80, 56, 72, 88, 52, 60으로 정의될 수 있다. 만일 기준 값이 48로 설정되었다면, 마찬가지 방법으로 상기

값은 각 리프팅 크기 집합 인덱스에 따라 순서대로 32, 48, 40, 28, 36, 44, 26, 30으로 정의될 수 있다. [표 3] 또는 [표 8]에서 ()안의 숫자를 제외한 리프팅 크기 집합을 사용하는 경우에, i _LS = 1인 리프팅 크기 집합에 포함된 리프팅 크기 중 i번째로 큰 리프팅 크기를 기준 값으로 결정하면, 각 리프팅 크기 집합 인덱스에 따라 정의되는 패리티 검사 행렬에 대응되는

값은 각 집합에서 i번째로 큰 리프팅 크기로 결정되는 특징이 있다.As one embodiment of the present disclosure, the above

The value may be determined based on the largest lifting size among the lifting sizes smaller than a specific reference value. Specifically, if the reference value is set to 96, in a system using lifting size sets such as [Table 3] to [Table 8], the numbers less than or equal to 96 in each lifting size set are 64, 96, 80, 56, 72, 88, 52, and 60 in that order. Therefore, in each lifting size set, based on the given reference value, the parity check matrix corresponding to the parity check matrix defined according to each lifting size set index is

If the value is determined, the above

The values can be defined as 64, 96, 80, 56, 72, 88, 52, 60 in order according to each lifting size set index. If the reference value is set to 48, the same method is used.

The values can be defined as 32, 48, 40, 28, 36, 44, 26, and 30 in order according to each lifting size set index. In case of using a lifting size set excluding the numbers in () in [Table 3] or [Table 8], if the i-th largest lifting size among the lifting sizes included in the lifting size set where i _LS = 1 is determined as the reference value, the corresponding parity check matrix defined according to each lifting size set index is

The value has the characteristic that it is determined by the ith largest lifting size in each set.

값이 결정된다면 (i=5),

값은 리프팅 크기 집합 인덱스에 따라 순서대로 16, 24, 20, 14, 18, 22, 13, 15로 정의될 수 있다. 마찬가지 방법으로 각각의 리프팅 크기 집합에서 4번째로 큰 수에 기반하여 리프팅 크기 집합 인덱스에 따라 정의되는 패리티 검사 행렬에 대응되는

값이 결정된다면 (i=4),

값은 리프팅 크기 집합 인덱스에 따라 순서대로 32, 48, 40, 28, 36, 44, 26, 30으로 정의될 수 있다. 마찬가지 방법으로 각각의 리프팅 크기 집합에서 3번째로 큰 수에 기반하여 리프팅 크기 집합 인덱스에 따라 정의되는 패리티 검사 행렬에 대응되는

값이 결정된다면 (i=3),

값은 리프팅 크기 집합 인덱스에 따라 순서대로 64, 96, 80, 56, 72, 88, 52, 60으로 정의될 수 있다. 마찬가지 방법으로 각각의 리프팅 크기 집합에서 2번째로 큰 수에 기반하여 리프팅 크기 집합 인덱스에 따라 정의되는 패리티 검사 행렬에 대응되는

값이 결정된다면 (i=2),

값은 리프팅 크기 집합 인덱스에 따라 순서대로 128, 192, 160, 112, 144, 176, 104, 120로 정의될 수 있다.In addition, for the uniformity of the encoding method, the i-th largest lifting size in each lifting size set may be selected (i = 2, 3, 4, 5, 6, ...). For example, in a system using lifting size sets such as [Table 3], the fifth largest numbers in each lifting size set are 16, 24, 20, 14, 18, 22, 13, and 15. Therefore, based on the fifth largest number in each lifting size set, the parity check matrix corresponding to each lifting size set index is defined.

If the value is determined (i=5),

The values can be defined as 16, 24, 20, 14, 18, 22, 13, 15 in order of the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the fourth largest number in each lifting size set.

If the value is determined (i=4),

The values can be defined as 32, 48, 40, 28, 36, 44, 26, 30 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the third largest number in each lifting size set.

If the value is determined (i=3),

The values can be defined as 64, 96, 80, 56, 72, 88, 52, 60 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the second largest number in each lifting size set.

If the value is determined (i=2),

The values can be defined as 128, 192, 160, 112, 144, 176, 104, 120 in order of the lifting size set index.

값이 결정된다면 (i=5), 상기

값은 리프팅 크기 집합 인덱스에 따라 순서대로 32, 48, 40, 28, 36, 44, 26, 30으로 정의될 수 있다. 마찬가지 방법으로 각각의 리프팅 크기 집합에서 4번째로 큰 수에 기반하여 리프팅 크기 집합 인덱스에 따라 정의되는 패리티 검사 행렬에 대응되는

값이 결정된다면 (i=4),

값은 리프팅 크기 집합 인덱스에 따라 순서대로 64, 96, 80, 56, 72, 88, 52, 60으로 정의될 수 있다. 마찬가지 방법으로 각각의 리프팅 크기 집합에서 3번째로 큰 수에 기반하여 리프팅 크기 집합 인덱스에 따라 정의되는 패리티 검사 행렬에 대응되는

값이 결정된다면 (i=3),

값은 리프팅 크기 집합 인덱스에 따라 순서대로 128, 192, 160, 112, 144, 176, 104, 120으로 정의될 수 있다. 마찬가지 방법으로 각각의 리프팅 크기 집합에서 2번째로 큰 수에 기반하여, 리프팅 크기 집합 인덱스에 따라 정의되는 패리티 검사 행렬에 대응되는

값이 결정된다면 (i=2),

값은 리프팅 크기 집합 인덱스에 따라 순서대로 256, 384, 320, 224, 288, 353, 208, 240으로 정의될 수 있다.In a system that uses the lifting size sets of values excluding the values in () in [Table 8], the fifth largest numbers in each lifting size set are 32, 48, 40, 28, 36, 44, 26, and 30. Therefore, the parity check matrix corresponding to each lifting size set index is defined based on the fifth largest number in each lifting size set.

If the value is determined (i=5), the above

The values can be defined as 32, 48, 40, 28, 36, 44, 26, 30 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the fourth largest number in each lifting size set.

If the value is determined (i=4),

The values can be defined as 64, 96, 80, 56, 72, 88, 52, 60 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the third largest number in each lifting size set.

If the value is determined (i=3),

The values can be defined as 128, 192, 160, 112, 144, 176, 104, 120 in order according to the lifting size set index. Similarly, based on the second largest number in each lifting size set, the corresponding parity check matrix defined according to the lifting size set index is

If the value is determined (i=2),

The values can be defined as 256, 384, 320, 224, 288, 353, 208, 240 in order of the lifting size set index.

행렬이

이 되는데, 상기 지수 선택 예 3에 따라 리프팅 크기

값이

보다 작거나 같은 경우에는 이 성립하게 되어 결국

이므로 사이클 특성이 개선되지는 않지만,

,

이 성립함을 이용하여 효율적인 LDPC 부호화가 가능하다. 리프팅 크기

값이

보다 큰 경우에는 를 만족하는 가 존재하여 (

) 이 되고, 따라서 인 성질을 이용하여 부호화 복잡도는 증가하지만 효율적인 LDPC 부호화가 가능하다. 여기서

와

에 의해서 결정되는 사이클 길이는 기존의

에서 로 증가한다.

와

또는

와

에 의해서 결정되는 사이클 길이는 지수 조건 1a, 지수 조건 1b를 만족하기 때문에

값에 비례하여 크게 증가한다.Also, as shown in the mathematical expression 19 and the table 11 and the corresponding examples, According to the pair,

The matrix

This is done, and the lifting size is determined according to the above index selection example 3.

The value

If less than or equal to This was established and eventually

Therefore, the cycle characteristics are not improved,

,

Using this establishment, efficient LDPC encoding is possible. Lifting size

The value

In larger cases Satisfying exists (

) This becomes, and therefore By using the human nature, efficient LDPC encoding is possible, although the encoding complexity increases. Here,

and

The cycle length determined by the existing

at It increases to .

and

or

and

The cycle length determined by satisfies exponential condition 1a and exponential condition 1b.

It increases significantly in proportion to the value.

The above index selection examples 1, 2, and 3 are methods for selecting indices of some cyclic permutation matrices constituting the partial matrix B(1020) in the parity check matrix of Fig. 10, which simultaneously consider improvement of cycle characteristics and coding complexity. The above index selection examples propose a method in which the cycle characteristics are not improved when the lifting size is small and the code length is short, but the coding complexity is very low, and the coding complexity increases somewhat as the lifting size increases, but the cycle characteristics are improved. In general, as the length of an LDPC code is longer, it can be more sensitively affected by the error floor phenomenon due to the cycle characteristics, and the above methods in which the cycle characteristics are further improved as the code length increases along with the lifting size can be said to be methods that can improve the error floor phenomenon according to the length of the LDPC code.

Of course, when the lifting size is small and the sign length is short, the cycle characteristics do not significantly affect the error floor phenomenon, but even when the lifting size is small, a method for improving the cycle characteristics can be applied.

As one embodiment of the present disclosure, a method for improving cycle characteristics when a code length is short is described.

) Example 4 of selecting an index (

)

는 임의의 정수-

is an arbitrary integer

는

이며, 여기서

는 를 만족하는 정수이며, 즉,부분 행렬 B에 대응되는 지수들 중

,

는 을 만족하는 정수이다. 여기서

는

,

의 최대공약수를 의미하며,

는

에 대응되는 리프팅 크기 집합에 속해 있는 임의의 리프팅 크기를 의미한다. (

,

는 홀수,

)-

Is

and here

Is is an integer satisfying , that is, among the indices corresponding to the submatrix B,

,

Is is an integer satisfying . Here,

Is

,

It means the greatest common divisor of ,

Is

It means any lifting size that belongs to the set of lifting sizes corresponding to . (

,

is odd,

)

는 -

Is

or

의 크기가 항상

보다 같거나 큰 경우에는 로 간단히 표현할 수 있다.If the system supports

The size of is always

If it is equal to or greater than It can be simply expressed as .

The above index selection example 4 is a cyclic permutation matrix We describe a method in which each index of is not a fixed value but is variably determined based on at least one lifting size Z. Therefore, the method proposed in the present disclosure can be applied not only to the lifting size sets of [Table 3] to [Table 8] but also to various other lifting size sets defined.

에서

인 경우에는 이 정수가 아니므로 상기 예에서는

가 되도록 설정될 수 있다. 즉, 시스템에서 지원하는

값들과 주어진 J 값에 따라서

값이 가변적으로 결정될 수 있다. 만일 시스템에서 지원하는

값이 보다 크거나 같은 경우에는 가 항상 정수이므로, 와 같이 하나의 방법으로 결정할 수 있다.should

at

In this case Since this is not an integer, in the above example

can be set to be, i.e., supported by the system.

Depending on the values and the given J value

The value can be determined variably. If the system supports it.

The value If greater than or equal to Since is always an integer, It can be decided in one way as follows.

에 따라 지수 조건 2a 및 지수 조건 2의 만족 여부는 달라진다. 예를 들어, 지원하는

값의 범위가 보다 크거나 같은 경우에는 지수 조건 2a 및 지수 조건 2b를 만족하며, 보다 작은 경우에는 만족하지 않는다.The method of the above index selection example 4 satisfies index condition 1a and index condition 1b, and the lifting size

Depending on the index condition 2a and the index condition 2, the satisfaction of the index condition 2 varies. For example, supporting

The range of values If it is greater than or equal to, then it satisfies the exponent condition 2a and the exponent condition 2b. If it is less than that, it is not satisfied.

)인 경우에는

와

에 의해서 결정되는 사이클 길이는 기존의

에서 로 증가하며, (또는

)인 경우에는 로 증가한다. (

인 경우에는 증가하지 않는다.)

와

또는

와

에 의해서 결정되는 사이클 길이는 지수 조건 1a, 지수 조건 1b를 만족하기 때문에

값에 비례하여 크게 증가한다.According to the embodiment of the above index selection example 4, (or

) in this case

and

The cycle length determined by the existing

at increases to , (or

) in this case increases to (

) does not increase in this case.

and

or

and

The cycle length determined by satisfies exponential condition 1a and exponential condition 1b.

It increases significantly in proportion to the value.

)인 경우에는

행렬이also (or

) in this case

The matrix

since,

)인 경우에는

행렬이LDPC encoding is possible using . (or

) in this case

The matrix

since,

Integer satisfying Since , LDPC encoding is possible in a similar way.

The method of the above index selection example 4 has a disadvantage that the maximum value of the cycle length that can be improved depending on the J value is fixed regardless of the lifting size Z, but has an advantage that the cycle characteristics are improved even when the lifting size Z is small. In other words, the cyclic permutation matrix The cycle characteristics can be improved for various lifting sizes by determining at least one of the indices of the cyclic permutation matrix variably based on the lifting size Z instead of all of the indices being fixed integer values.

, 즉, 로 설정하였을 때 지수 선택의 예를 다음에 나타내었다.For convenience, as a specific example of the above index selection example 4,

, in other words, An example of index selection when set to is shown below.

) Example 5 of selecting an index (

)

-

(

)-

(

)

는 -

Is

or

의 크기가 항상 보다 같거나 큰 경우에는 로 간단히 표현할 수 있다.If the system supports

The size of is always If it is equal to or greater than It can be simply expressed as .

인 경우에는

뿐만 아니라 를 만족하는 임의의

에 대해서도 지수 조건 1a 및 지수 조건 1b를 만족한다. 즉, 인 정수

에 대해,

,

, (또는 )와 같이 설정된 부분 행렬 B는 지수 조건 1a 및 지수 조건 1b를 만족한다.As in the above index selection example 5

In this case

yes Any arbitrary

It also satisfies index condition 1a and index condition 1b. That is, In the integer

About,

,

, (or ) The submatrix B set as satisfies the index condition 1a and the index condition 1b.

According to the same method as the above index selection example 5,

Become Efficient encoding is possible using .

, 즉, 로 설정하였을 때 지수 선택의 예를 다음에 나타내었다.For convenience, a more specific example of the above index selection example 4 is given.

, in other words, An example of index selection when set to is shown below.

) Example 6 of selecting an index (

)

-

(

)-

(

)

는 -

Is

or )

의 크기가 항상 보다 같거나 큰 경우에는 로 간단히 표현할 수 있다.If the system supports

The size of is always If it is equal to or greater than It can be simply expressed as .

인 경우에는

뿐만 아니라 를 만족하는 임의의

에 대해서도 지수 조건 1a 및 지수 조건 1b를 만족한다. 즉, 인 정수

에 대해,

,

, (또는 )와 같이 설정된 부분 행렬 B는 지수 조건 1a 및 지수 조건 1b를 만족한다.As in the above index selection example 6

In this case

yes Any arbitrary

It also satisfies index condition 1a and index condition 1b. That is, In the integer

About,

,

, (or ) The submatrix B set as satisfies the index condition 1a and the index condition 1b.

According to the same method as the above index selection example 6,

Efficient encoding is possible based on .

값이 비교적 크다면 J 값이 크지 않아도 충분히 사이클 특성이 개선될 수 있다. 통상적으로 J 값은 시스템에서 주어진 패리티 검사 행렬에서 코어 행렬 부분의 행의 개수를 지시하는 파라미터

값과 타겟 BLER 값들을 고려하여 결정될 수 있다. 예를 들어, 타겟 BLER가 비교적 높거나 코어 행렬의

값이 큰 경우에는 J = 1, 2로 충분할 수 있으나, 타겟 BLER가 비교적 낮거나 코어 행렬의

값이 작은 경우에는 J = 2, 3, 4, ... 등으로 설정하는 것이 바람직하다.The index selection methods of the above index selection examples 4, 5 and 6 are such that the cycle length is at most It can be improved by. If

If the value is relatively large, the cycle characteristics can be sufficiently improved even if the J value is not large. Typically, the J value is a parameter that indicates the number of rows in the core matrix part of the parity check matrix given in the system.

can be determined by considering the values and target BLER values. For example, if the target BLER is relatively high or the core matrix

For large values, J = 1, 2 may be sufficient, but if the target BLER is relatively low or the core matrix is

For small values, it is desirable to set J = 2, 3, 4, ...

값을 작게, 리프팅 크기가 상대적으로 큰 경우에는

값을 크게 설정할 수 있다 (

). 리프팅 크기에 따라 J 값을 다르게 설정하는 경우에는 기준이 되는 리프팅 크기 및 적절한

,

값을 결정해야 한다.In general, since the degree to which the performance of a sign is affected by the cycle characteristics varies depending on the length of the sign, it is also possible to set the J value differently depending on the lifting size. That is, at least one of the indices is determined based on the lifting size, but when the lifting size is relatively small,

If the value is small and the lifting size is relatively large,

You can set the value to a large value (

) When setting the J value differently depending on the lifting size, the standard lifting size and the appropriate

,

The value must be determined.

이고 제2 타겟 BLER가

일 때, 제1 타겟 BLER가 제2 타겟 BLER에 비해 높다고 할 수 있다. 만일 제1 타겟 BLER가

, 제2 타겟 BLER가

이고, 제3 타겟 BLER가

일 (또는

)일 때, 제1 타겟 BLER가 제2 타겟 BLER 및 제3 타겟 BLER에 비해 높다고 결정될 수 있으며, 제1 타겟 BLER 및 제2 타겟 BLER가 제3 타겟 BLER에 비해 높다고 결정될 수도 있다. 이와 같이 시스템에서 적용 가능한 타겟 BLER가 복수 개 존재할 때 특정 BLER 값을 기준으로 BLER의 높고 낮음을 판단한 다음에 이에 기반하여 본 개시에서 제안된 지수 선택 방법이 가변적으로 적용될 수 있다.Various possible index selection methods, including the index selection examples 1 to 6 above, can be variably applied depending on the target BLER and/or lifting size of the system. For example, if the target BLER of the system is high, since the cycle characteristic does not significantly affect the decoding performance of the code, encoding can be performed using an existing method with the highest encoding efficiency even if the cycle characteristic is not improved. However, if the target BLER is low, the index selection methods proposed in the present disclosure can be applied. Here, the high and low of the target BLER can be relatively determined when there are multiple target BLERs applicable in the system. For example, if the first target BLER is

And the second target is BLER

When the first target BLER is higher than the second target BLER, it can be said that the first target BLER is higher than the second target BLER. If the first target BLER is

, the second target BLER

And the third target BLER

work (or

), the first target BLER may be determined to be higher than the second target BLER and the third target BLER, and the first target BLER and the second target BLER may be determined to be higher than the third target BLER. In this way, when there are multiple applicable target BLERs in the system, the high and low of the BLER can be determined based on a specific BLER value, and then the index selection method proposed in the present disclosure can be variably applied based on this.

는 편의상 ",

,

는 홀수"와 같이 표현되었으나, 일반적으로는 [표 7-1] 또는 [표 7-2]처럼 ",

,

는

번째 리프팅 크기 집합에서 가장 작은 리프팅 크기"와 같이

를 홀수로 제한하지 않는 경우에도 마찬가지 방법으로 지수 선택 방법들을 적용할 수 있다.However, this is an embodiment of the present invention, and the index selection method proposed in the present disclosure can be applied when the target BLER is high or regardless of the target BLER, and can be variably applied based on other factors. In addition, since the index selection method described throughout the present disclosure means a method of selecting an index of a cyclic permutation matrix included in a submatrix of a parity check matrix (specifically, a submatrix B), the index selection method of the present disclosure can be described as a method of determining a parity check matrix or a method of determining a submatrix included in a parity check matrix. In addition, since the lifting size is closely related to the code length or TBS, etc., all processes among the embodiments disclosed in the present invention that are determined based on the lifting size can be changed to a method of determining based on the code length or TBS. In addition, in the index selection examples 1 to 6, the lifting size

For convenience, " ,

,

It is expressed as "odd number", but it is generally expressed as "Table 7-1] or [Table 7-2] ,

,

Is

"The smallest lifting size in the set of lifting sizes"

The same methods for selecting exponents can be applied even when the number is not restricted to odd numbers.

으로 작게 설정하고, 시스템 타겟 BLER가 낮다고 판단된 경우에는 J 값을 상대적으로 큰

값으로 설정할 수 있다 (

). 또한 이러한 지수 선택의 방법 또는 J 값에 대한 결정은 리프팅 크기를 함꼐 고려하여 결정할 수도 있다. 일반적으로 기준이 되는 BLER 및/또는 리프팅 크기를 A개로 설정하고, 총 (A+1)개의 서로 다른 J 값으로 구분할 수 있다. 예를 들어, 제1 기준 값, 제2 기준 값, ...등이 있다면, J 값은

,

, ...등과 같이 세분화될 수 있다. 일반적으로 J는 0으로도 설정될 수도 있는데, 이 경우에는

가 되어 사이클 특성이 개선되지 않고 가장 간단한 부호화가 가능한 기존 방식을 의미한다.As a specific example of the application of the J value in Index Selection Example 4 to Index Selection Example 6, if the system target BLER is judged to be high, the J value is

If the system target BLER is judged to be low, the J value is set to relatively large.

can be set to a value (

) Also, the method of selecting these indices or the decision on the J value can be determined by considering the lifting size together. Generally, the BLER and/or lifting size that serve as the reference are set to A, and a total of (A+1) different J values can be distinguished. For example, if there is a first reference value, a second reference value, etc., the J value is

,

, ... can be subdivided into, etc. In general, J can also be set to 0, in which case

It refers to the existing method that enables the simplest encoding without improving the cycle characteristics.

For reference, the method of determining the target BLER at the terminal or base station can be applied in various ways depending on the system. For example, the system target BLER may be directly indicated from upper layer signaling such as configured RRC (radio resource control) information, the target BLER may be indirectly indicated according to the configured CQI table or MCS table, and the target BLER may be indirectly indicated according to the configured service scenario.

Meanwhile, the electronic device according to various embodiments disclosed in this document may be a device of various forms. The electronic device may include, for example, at least one of a portable communication device (e.g., a smart phone), a TV, a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance device. The electronic device according to the embodiment of this document is not limited to the above-described devices. In addition, the operation of transmitting a frame may not only mean that it is transmitted through a wireless channel or the like, but may also mean that various electronic devices include an interface for outputting the frame for transmission. For example, a processor may output a frame to an RF front end for transmission through a bus interface. Similarly, the operation of receiving a frame from another device may mean that various electronic devices have an interface for obtaining a frame received from another device. For example, a processor may mean that a frame can be received or obtained from an RF front end through a bus interface.

It should be understood that the various embodiments and terminology used in this document are not intended to limit the technology described in this document to specific embodiments, but rather to encompass various modifications, equivalents, and/or alternatives of the embodiments.

In connection with the description of the drawings, similar reference numerals may be used for similar components. The singular expression may include the plural expression unless the context clearly indicates otherwise. In this document, expressions such as "A or B", "at least one of A and/or B", "A, B, or C" or "at least one of A, B and/or C" may include all possible combinations of the items listed together. Expressions such as "first", "second", "first" or "second" may modify the corresponding components, regardless of order or importance, and are only used to distinguish one component from another component and do not limit the corresponding components. When one (e.g., a first) component is said to be "(functionally or communicatively) connected" or "connected" to another (e.g., a second) component, the one component may be directly connected to the other component, or may be connected via another component (e.g., a third component).

Also, the word "determining" can have many different meanings, including identifying, calculating or computing, processing, deriving, investigating, estimating, looking up (e.g., from a database or other data structure), and ascertaining, depending on the context.

Meanwhile, the order of description in the drawings explaining the method of the present disclosure does not necessarily correspond to the order of execution, and the order of precedence may be changed or executed in parallel.

Alternatively, the drawings illustrating the method of the present disclosure may omit some components and include only some components without damaging the essence of the present disclosure.

In addition, the method of the present disclosure may be implemented by combining part or all of the contents included in each embodiment within a scope that does not harm the essence of the invention.

Although the present disclosure has been described with preferred embodiments, various changes and modifications may occur to those skilled in the art. Such changes and modifications are intended to be included in the scope of the appended claims. In addition, it is obvious that operations expressed as different blocks in the flowchart of the present disclosure for convenience of explanation may be implemented separately by multiple processors in an actual system, but may also be implemented integrated into a single processor.

Claims (16)

In a method performed by a transmitter in a communication system,
A step of determining the number of input bits;
A step of determining a base matrix based on the number of input bits;
A step of determining a lifting size (Z) based on at least one of the number of input bits or the basic matrix;
A step of determining a parity check matrix based on at least one of the above basic matrix or the above lifting size (Z);
A step of performing encoding based on the above parity check matrix and the input bits,
The above parity check matrix includes a first submatrix corresponding to the input bits and a second submatrix corresponding to the first parity bits,
The first column block of the above second submatrix contains three cyclic permutation matrices,
The greatest common divisor of at least one of the difference values of each index of the above cyclic permutation matrix and the lifting size (Z) is 1 or the smallest number greater than 1 among the divisors of the lifting size (Z).
At least one of the difference values of each index of the above cyclic permutation matrix is ( ) is characterized. In the first paragraph,
The greatest common divisor of two of the differences of each index of the above cyclic permutation matrix and the above lifting size (Z) is 1 or the smallest number greater than 1 among the divisors of the above lifting size (Z).
At least one of the difference values of each index of the above cyclic permutation matrix,

is 1

In this case (

) and

is an odd number greater than or equal to 3

In this case (

) is characterized. In the first paragraph,
The above second sub-matrix is,
or Contains at least one of:
or
A method characterized by comprising: In the first paragraph,
The greatest common divisor of the first value among the differences of each index of the above cyclic permutation matrix and the lifting size (Z) is 1,
A method characterized in that the second value among the difference values of each index of the above cyclic permutation matrix is one of the lifting size values smaller than the largest lifting size value among the lifting size values included in the lifting size set. In a method performed by a receiver in a communication system,
Step of receiving a signal;
A step of determining the number of input bits based on the above signal;
A step of determining a base matrix based on the number of input bits;
A step of determining a lifting size (Z) based on at least one of the input bit number or the basic matrix;
A step of determining a parity check matrix based on at least one of the above basic matrix or the above lifting size (Z);
A step of performing decryption of the signal based on the parity check matrix,
The above parity check matrix includes a first submatrix corresponding to the input bits and a second submatrix corresponding to the first parity bits,
The first column block of the above second submatrix contains three cyclic permutation matrices,
The greatest common divisor of at least one of the difference values of each index of the above cyclic permutation matrix and the lifting size (Z) is 1 or the smallest number greater than 1 among the divisors of the lifting size (Z).
At least one of the difference values of each index of the above cyclic permutation matrix is (

) is characterized. In paragraph 5,
The greatest common divisor of two of the differences of each index of the above cyclic permutation matrix and the above lifting size (Z) is 1 or the smallest number greater than 1 among the divisors of the above lifting size (Z).
At least one of the difference values of each index of the above cyclic permutation matrix,

is 1

In this case (

) and

is an odd number greater than or equal to 3

In this case (

) is characterized. In paragraph 5,
The above second sub-matrix is,
or Contains at least one of:
or
A method characterized by comprising: In paragraph 5,
The greatest common divisor of the first value among the differences of each index of the above cyclic permutation matrix and the lifting size (Z) is 1,
A method characterized in that the second value among the difference values of each index of the above cyclic permutation matrix is one of the lifting size values smaller than the largest lifting size value among the lifting size values included in the lifting size set. In a transmitter in a communication system,
Transmitter and receiver; and
Including a control unit connected to the above transmitter and receiver,
The above control unit,
Determine the number of input bits,
Determine the basic matrix based on the number of input bits above,
Determine the lifting size (Z) based on the number of input bits or at least one of the basic matrices,
Determine a parity check matrix based on at least one of the above basic matrix or the above lifting size (Z),
Encoding is performed based on the above parity check matrix and the input bits,
The above parity check matrix includes a first submatrix corresponding to the input bits and a second submatrix corresponding to the first parity bits,
The first column block of the above second submatrix contains three cyclic permutation matrices,
The greatest common divisor of at least one of the difference values of each index of the above cyclic permutation matrix and the lifting size (Z) is 1 or the smallest number greater than 1 among the divisors of the lifting size (Z).
At least one of the difference values of each index of the above cyclic permutation matrix is (

) is characterized by a transmitter. In Article 9,
The greatest common divisor of two of the differences of each index of the above cyclic permutation matrix and the above lifting size (Z) is 1 or the smallest number greater than 1 among the divisors of the above lifting size (Z).
At least one of the difference values of each index of the above cyclic permutation matrix,

is 1

In this case (

) and

is an odd number greater than or equal to 3

In this case (

) is characterized by a transmitter. In Article 9,
The above second sub-matrix is,
or Contains at least one of:
or
A transmitter comprising: In Article 9,
The greatest common divisor of the first value among the differences of each index of the above cyclic permutation matrix and the lifting size (Z) is 1,
A transmitter, characterized in that the second value among the difference values of each index of the above cyclic permutation matrix is one of the lifting size values smaller than the largest lifting size value among the lifting size values included in the lifting size set. In a receiver in a communication system,
Transmitter and receiver; and
Including a control unit connected to the above transmitter and receiver,
The above control unit,
Receive the signal,
Determine the number of input bits based on the above signal,
Determine the basic matrix based on the number of input bits above,
Determine the lifting size (Z) based on at least one of the input bit number or the basic matrix,
Determine a parity check matrix based on at least one of the above basic matrix or the above lifting size (Z),
Decoding of the signal is performed based on the above parity check matrix,
The above parity check matrix includes a first submatrix corresponding to the input bits and a second submatrix corresponding to the first parity bits,
The first column block of the above second submatrix contains three cyclic permutation matrices,
The greatest common divisor of at least one of the difference values of each index of the above cyclic permutation matrix and the lifting size (Z) is 1 or the smallest number greater than 1 among the divisors of the lifting size (Z).
At least one of the difference values of each index of the above cyclic permutation matrix is (

) is characterized by. In Article 13,
The greatest common divisor of two of the differences of each index of the above cyclic permutation matrix and the above lifting size (Z) is 1 or the smallest number greater than 1 among the divisors of the above lifting size (Z).
At least one of the difference values of each index of the above cyclic permutation matrix,

is 1

In this case (

) and

is an odd number greater than or equal to 3

In this case (

) is characterized by. In Article 13,
The above second sub-matrix is,
or Contains at least one of:
or
A receiver characterized by including a . In Article 13,
The greatest common divisor of the first value among the differences of each index of the above cyclic permutation matrix and the lifting size (Z) is 1,
A receiver characterized in that the second value among the difference values of each index of the above cyclic permutation matrix is one of the lifting size values smaller than the largest lifting size value among the lifting size values included in the lifting size set.