KR20250115278A - Apparatus and method for encoding and decoding of data in communication or broadcasting system - Google Patents

Abstract

The present disclosure relates to a 5G or 6G communication system for supporting higher data transmission rates than a 4G communication system such as LTE.

Description

{APPARATUS AND METHOD FOR ENCODING AND DECODING OF DATA IN COMMUNICATION OR BROADCASTING SYSTEM}

The present disclosure relates to a method and device for encoding and decoding data in a communication or broadcasting system.

Looking back at the evolution of wireless communication over successive generations, technologies have primarily been developed for human-facing services such as voice, multimedia, and data. With the commercialization of the 5G (5th Generation) communication system, an explosive increase in connected devices is expected to be connected to communication networks. Examples of networked objects include vehicles, robots, drones, home appliances, displays, smart sensors installed in various infrastructures, construction equipment, and factory equipment. Mobile devices are also expected to evolve into diverse form factors, such as augmented reality glasses, virtual reality headsets, and holographic devices. In the 6G (6th Generation) era, efforts are being made to develop improved 6G communication systems to connect hundreds of billions of devices and objects and provide diverse services. For this reason, 6G communication systems are often referred to as "beyond 5G."

The 6G communication system, expected to be realized around 2030, will have a maximum transmission speed of terabytes (i.e., 1,000 gigabits) per second (bps) and a wireless latency of 100 microseconds (μsec). In other words, compared to 5G, the transmission speed in a 6G communication system will be 50 times faster and the wireless latency will be reduced to one-tenth.

To achieve these high data rates and ultra-low latency, 6G communication systems are being considered for implementation in the terahertz (THz) band (e.g., from 95 gigahertz (GHz) to 3 terahertz (THz)). Compared to the millimeter wave (mmWave) band introduced in 5G, the terahertz band is expected to have more severe path loss and atmospheric absorption, making it more important to develop technologies that can guarantee signal reach, or coverage. Key technologies to ensure coverage include Radio Frequency (RF) components, antennas, new waveforms that offer better coverage than Orthogonal Frequency Division Multiplexing (OFDM), beamforming, and multiple antenna transmission technologies such as massive Multiple-Input and Multiple-Output (MIMO), Full Dimensional MIMO (FD-MIMO), array antennas, and large-scale antennas. In addition, new technologies such as metamaterial-based lenses and antennas, high-dimensional spatial multiplexing using Orbital Angular Momentum (OAM), and Reconfigurable Intelligent Surface (RIS) are being discussed to improve the coverage of terahertz band signals.

In addition, in order to improve frequency efficiency and system network, 6G communication systems are developing full duplex technology that utilizes the same frequency resources at the same time for uplink and downlink; network technology that integrates satellites and HAPS (High-Altitude Platform Stations); network structure innovation technology that supports mobile base stations and enables optimization and automation of network operation; dynamic spectrum sharing technology through collision avoidance based on spectrum usage prediction; AI-based communication technology that utilizes AI (Artificial Intelligence) from the design stage and internalizes end-to-end AI support functions to realize system optimization; and next-generation distributed computing technology that realizes services with complexity that exceeds the limits of terminal computing capabilities by utilizing ultra-high-performance communication and computing resources (Mobile Edge Computing (MEC), cloud, etc.). In addition, efforts are being made to further strengthen connectivity between devices, further optimize networks, promote softwareization of network entities, and increase the openness of wireless communications through the design of new protocols to be used in 6G communication systems, the implementation of hardware-based security environments, the development of mechanisms for the safe use of data, and the development of technologies for maintaining privacy.

Research and development of these 6G communication systems are expected to enable a new level of hyper-connected experience through the hyper-connectivity of 6G communication systems, which encompass not only connections between things but also connections between people and things. Specifically, 6G communication systems are expected to enable services such as truly immersive eXtended Reality (XR), high-fidelity mobile holograms, and digital replicas. Furthermore, services such as remote surgery, industrial automation, and emergency response, which are provided through 6G communication systems through enhanced security and reliability, will be applied in diverse fields such as industry, medicine, automobiles, and home appliances.

The present disclosure provides algebraic characteristics that a parity check matrix of an LDPC (Low Density Parity Check) code must satisfy in order to reduce decoding latency and lower encoding complexity. In addition, an efficient encoding and decoding method and device using an LDPC code having the above algebraic characteristics are provided.

The present disclosure provides algebraic characteristics that a parity check matrix of an LDPC code must satisfy in order to reduce the Block Error Rate (BLER) or block error probability. In addition, an efficient encoding and decoding method and device using an LDPC code having the algebraic characteristics are provided.

The present disclosure provides algebraic characteristics that a parity check matrix of an LDPC code must satisfy by appropriately combining the aforementioned algebraic characteristics to simultaneously reduce decoding latency, encoding complexity, and BLER. Furthermore, the present disclosure provides an efficient encoding and decoding method and device using an LDPC code having the combined algebraic characteristics.

In a communication system according to one embodiment of the present disclosure, a data transmission method of a base station or a terminal may include a step of LDPC encoding data based on a basic matrix and/or a parity check matrix, a step of applying appropriate rate matching to the encoded data, a step of modulating the rate-matched encoded data, and a step of transmitting the modulated signal through a transmission device, wherein the basic matrix or the parity check matrix or the weight matrix corresponding thereto is characterized in that it satisfies a specific algebraic condition.

In a communication system according to one embodiment of the present disclosure, a method for receiving data by a base station or a terminal may include the steps of receiving a modulated signal through a receiving device, performing demodulation to determine values for decoding based on the received signal, performing LDPC decoding based on the determined values and a base matrix and/or a parity check matrix, appropriately applying rate dematching to the LDPC decoded result, and determining data from the rate dematched result, wherein the base matrix or the parity check matrix or the weight matrix corresponding thereto is characterized in that it satisfies a specific algebraic condition.

In addition, in a method performed by a transmitter in a base station communication system in a communication system according to an embodiment of the present disclosure, the method comprises the steps of: determining a number of input bits; determining a basic matrix based on the number of input bits; determining a lifting size (Z) based on at least one of the number of input bits or the basic matrix; determining a parity check matrix based on at least one of the basic matrix or the lifting size (Z); performing encoding based on the parity check matrix and the input bits; and performing rate matching based on the encoded bits, wherein the parity check matrix is a submatrix corresponding to a parity bit. , and the puncturing starts from the parity bits corresponding to the 4th column block among the 0th, 1st, 2nd, 3rd, and 4th column blocks of the submatrix, and is included in the parity check matrix. Is is the identity matrix of size, Is is a zero-sized matrix, , , , Is It is characterized by being an identity matrix or a cyclic permutation matrix of size.

In addition, in a method performed by a transmitter in a communication system according to an embodiment of the present disclosure, the method comprises the steps of: receiving a signal corresponding to an input bit; demodulating the signal to determine a value for decoding; confirming the number of the input bits based on the signal; determining a basic matrix based on the number of the input bits; determining a lifting size (Z) based on at least one of the number of the input bits or the basic matrix; determining a parity check matrix based on at least one of the basic matrix or the lifting size (Z); and performing decoding based on the parity check matrix and the values, wherein the parity check matrix is a submatrix corresponding to a parity bit. , and the signal includes parity bits punctured from the parity bits corresponding to the 4th column block among the 0th, 1st, 2nd, 3rd, and 4th column blocks of the submatrix, and is included in the parity check matrix. Is is the identity matrix of size, Is is a zero-sized matrix, , , ,Is It is characterized by being an identity matrix or a cyclic permutation matrix of size.

In addition, in a communication system according to an embodiment of the present disclosure, a transmitter includes a transceiver, and a control unit connected to the transceiver, wherein the control unit determines the number of input bits, determines a basic matrix based on the number of input bits, determines a lifting size (Z) based on at least one of the number of input bits or the basic matrix, determines a parity check matrix based on at least one of the basic matrix or the lifting size (Z), performs encoding based on the parity check matrix and the input bits, and performs rate matching based on the encoded bits, wherein the parity check matrix is a submatrix corresponding to a parity bit. , and the puncturing starts from the parity bits corresponding to the 4th column block among the 0th, 1st, 2nd, 3rd, and 4th column blocks of the submatrix, and is included in the parity check matrix. Is is the identity matrix of size, Is is a zero-sized matrix, , , ,Is It is characterized by being an identity matrix or a cyclic permutation matrix of size.

In addition, in a communication system according to one embodiment of the present disclosure, a receiver comprises a transceiver; and a control unit connected to the transceiver, wherein the control unit receives a signal corresponding to an input bit, demodulates the signal to determine a value for decoding, verifies the number of the input bits based on the signal, determines a basic matrix based on the number of the input bits, determines a lifting size (Z) based on at least one of the number of the input bits or the basic matrix, determines a parity check matrix based on at least one of the basic matrix or the lifting size (Z), and performs decoding based on the parity check matrix and the values.

The above parity check matrix is a submatrix corresponding to the parity bits.

Includes,

The above signal includes punctured parity bits starting from the parity bits corresponding to the 4th column block among the 0th, 1st, 2nd, 3rd, and 4th column blocks of the above submatrix,

Included in the above parity check matrix Is is the identity matrix of size, Is is a zero-sized matrix, , , ,Is It is characterized by being an identity matrix or a cyclic permutation matrix of size.

According to the present disclosure, by providing algebraic characteristics of a parity check matrix for reducing latency and BLER, LDPC codes can be effectively supported for variable lengths and variable rates.

Figure 1 is a diagram of a systematic LDPC codeword structure.
Figure 2 is a diagram illustrating a method for representing a graph of an LDPC code.
Figure 3a is an example diagram for explaining the cycle characteristics of a QC-LDPC code.
Figure 3b is an example diagram for explaining the cycle characteristics of a QC-LDPC code.
FIG. 4 is a transmission block structure diagram according to an embodiment of the present disclosure.
FIG. 5 is an exemplary diagram of an LDPC encoding process according to an embodiment of the present disclosure.
FIG. 6 is an exemplary diagram of an LDPC decoding process according to an embodiment of the present disclosure.
Figure 7 is a block diagram of a transmitter device according to an embodiment of the present disclosure.
Figure 8 is a block diagram of a receiving device according to an embodiment of the present disclosure.
FIG. 9 is a structural diagram of an LDPC decoding unit according to an embodiment of the present disclosure.
Figure 10 is an example diagram of the structure of a parity check matrix of an LDPC code.
FIG. 11a is an example diagram of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.
FIG. 11b is an example diagram of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.
FIG. 12a is an exemplary diagram for explaining cycle characteristics in a submatrix of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.
FIG. 12b is an exemplary diagram for explaining cycle characteristics in a submatrix of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.
FIG. 12c is an exemplary diagram for explaining cycle characteristics in a submatrix of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.
FIG. 13 is an example diagram of a parity check matrix of an LDPC code according to one embodiment of the present disclosure.
FIG. 14a is an example diagram of applying a permutation rule according to an embodiment of the present disclosure to a parity check matrix.
FIG. 14b is an example diagram of applying a permutation rule according to an embodiment of the present disclosure to a parity check matrix.

Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, in describing the present disclosure, if a detailed description of a related known function or configuration is deemed to unnecessarily obscure the gist of the present disclosure, such detailed description will be omitted. The terms described below are defined based on the functions of the present disclosure and may vary depending on the intent or custom of the user or operator. Therefore, their definitions should be based on the contents of this specification.

The main gist of this disclosure can be applied to other systems with similar technical backgrounds, with minor modifications, without significantly departing from the scope of this disclosure. This can be accomplished at the discretion of those skilled in the technical field of this disclosure. While the term "communication system" generally encompasses the meaning of a broadcasting system, in this disclosure, a communication system whose primary service is broadcasting may be more clearly termed a broadcasting system.

The advantages and features of the present disclosure, and methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below and may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present disclosure is complete and to fully inform those skilled in the art of the scope of the invention, and the present disclosure is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Low Density Parity Check (LDPC) codes, first introduced by Gallager in the 1960s, were long forgotten due to their complexity, which was difficult to implement with the technology of the time. However, in 1993, the turbo code proposed by Berrou, Glavieux, and Thitimajshima showed performance approaching the Shannon channel capacity, which led to many analyses of the performance and characteristics of turbo codes, and much research on iterative decoding and graph-based channel coding was conducted. This led to a restudy of LDPC codes in the late 1990s, and it was discovered that when decoding is performed using iterative decoding based on the sum-product algorithm on the Tanner graph corresponding to the LDPC code, the LDPC code also achieves performance approaching the Shannon channel capacity.

LDPC codes are generally defined as a parity-check matrix and can be represented using a bipartite graph, commonly referred to as a Tanner graph. LDPC codes are generally a type of parity-check code, and are called "low-density" parity-check codes because they have the characteristic that the ratio of the number of 1s (i.e., density) in the parity-check matrix for very long codes is very low. Therefore, the techniques proposed in this disclosure based on LDPC codes for convenience can be easily extended to general parity-check matrix codes.

Figure 1 is a diagram illustrating a systematic LDPC codeword structure.

According to Fig. 1, a device that performs LDPC encoding receives an information word (102) composed of K _ldpc bits or symbols and performs encoding to generate a codeword (100) composed of N _ldpc bits or symbols. For the convenience of the following description, it is assumed that an information word (102) including K _ldpc bits is input and a codeword (100) composed of N _ldpc bits is generated. That is, an information word having K _ldpc input bits When (102) is encoded, the codeword (100) is generated. That is, the information word and the code word are bit strings composed of multiple bits, and the information word bit and the code word bit mean each bit that constitutes the information word and the code word. Typically, the LDPC coded bit

If it contains information words such as , it is called a systematic code. Here, is a parity bit (104), and the number of parity bits N _parity can be expressed as N _parity = N _ldpc - K _ldpc .

LDPC code is a type of linear block code and includes a process of determining a codeword that satisfies the conditions in mathematical expression 1 below.

[Mathematical Formula 1]

Here, am.

In mathematical expression 1, H is a parity check matrix, c is a codeword, c _i is the i-th bit of the codeword, and N _ldpc is the LDPC codeword length. means the i-th column of the parity check matrix (H).

The parity check matrix H consists of N _ldpc columns, which is equal to the number of bits of the LDPC codeword. Mathematical expression 1 shows the i-th column of the parity check matrix ( ) and the i-th code word bit c _i means that the sum of the products is '0', so the i-th column ( ) means that it is related to the i-th code word bit c _i .

Figure 2 is a diagram illustrating a method for representing a graph of an LDPC code.

Referring to Fig. 2, a method for representing a graph of an LDPC code will be described.

Fig. 2 is a diagram illustrating an example of a parity check matrix H ₁ of an LDPC code consisting of 4 rows and 8 columns and its representation as a Tanner graph. Referring to Fig. 2, since the parity check matrix H ₁ has 8 columns, a codeword of length 8 is generated, and the code generated through H ₁ means an LDPC code, and each column corresponds to 8 encoded bits.

Referring to Fig. 2, the Tanner graph of an LDPC code that encodes and decodes based on a parity check matrix H ₁ is composed of eight variable nodes, namely x ₁ (202), x ₂ (204), x ₃ (206), x ₄ (208), x ₅ (210), x ₆ (212), x ₇ (214), x ₈ (216), and four check nodes (218, 220, 222, 224). Here, the i-th column and the j-th row of the parity check matrix H ₁ of the LDPC code correspond to the variable node x _i and the j-th check node, respectively. In addition, the meaning of the value of 1, that is, a non-zero value, at the point where the i-th column and the j-th row of the parity check matrix H ₁ of the LDPC code intersect means that there is an edge connecting the variable node x _i and the j-th check node on the Tanner graph, as shown in Fig. 2.

In the Tanner graph of an LDPC code, the degree of a variable node and a check node refers to the number of line segments connected to each node, which is equal to the number of non-zero elements (entries) in the column or row corresponding to the node in the parity check matrix of the LDPC code. For example, in Fig. 2, the degrees of variable nodes x ₁ (202), x ₂ (204), x ₃ (206), x ₄ (208), x ₅ (210), x ₆ (212), x ₇ (214), x ₈ (216) are 4, 3, 3, 2, 2, 2, 2, respectively, and the degrees of check nodes (218, 220, 222, 224) are 6, 5, 5, 5, respectively, in that order. In addition, the number of non-zero elements in each column of the parity check matrix H ₁ of FIG. 2 corresponding to the variable nodes of FIG. 2 is in order consistent with the degrees of the above-described variable nodes, which are 4, 3, 3, 3, 2, 2, 2, 2, and the number of non-zero elements in each row of the parity check matrix H ₁ of FIG. 2 corresponding to the check nodes of FIG. 2 is in order consistent with the degrees of the above-described check nodes, which are 6, 5, 5, 5. For this reason, the degree of each variable node is also called the column degree or column weight, and the degree of the check node is also called the row degree or row weight.

LDPC encoded codeword bits can be decoded based on an iterative decoding algorithm based on a sum-product algorithm on a bipartite graph as shown in Fig. 2. Here, the sum-product algorithm is a type of message passing algorithm, and the message passing algorithm represents an algorithm that exchanges messages through edges on a bipartite graph and calculates and updates an output message from messages input to a variable node or a test node.

Here, the value of the ith coding bit can be determined based on the message of the ith variable node. Both hard decision and soft decision are possible methods for determining the value of the ith coding bit. Therefore, the performance of the ith bit c _i of the LDPC codeword corresponds to the performance of the ith variable node of the Tanner graph, which can be determined by the position and number of 1s in the ith column of the parity check matrix. In other words, the performance of the N _ldpc codeword bits of the codeword can be affected by the position and number of 1s in the parity check matrix, which means that the performance of the LDPC code is greatly affected by the parity check matrix. Therefore, in order to design an LDPC code with excellent performance, a method for designing a good parity check matrix is required.

The parity check matrix used in communication and broadcasting systems is usually a quasi-cyclic LDPC code (or QC-LDPC code, hereinafter referred to as QC-LDPC code), which uses a quasi-cyclic parity check matrix for ease of implementation. Depending on the communication and broadcasting system, there are cases where a parity check matrix that has a structure that is not a complete quasi-cyclic structure but is almost similar to a quasi-cyclic structure is used. Such LDPC codes may not be strictly classified as QC-LDPC codes algebraically, but they are sometimes categorized as QC-LDPC codes for convenience.

A typical QC-LDPC code is characterized by having a parity check matrix composed of zero matrices or circulant permutation matrices (or circular permutation matrices) in the form of small square matrices. Here, a permutation matrix refers to a matrix in which each row or column contains only one 1, and all remaining elements are 0. In addition, a circulant permutation matrix refers to a matrix in which each element of the identity matrix is cyclically shifted to the right or left. Generally, the identity matrix itself is also included in the circulant permutation matrix, because each element of the identity matrix is regarded as having been cyclically shifted 0 times. Therefore, a circulant permutation matrix basically includes the identity matrix, but for the convenience of explanation, an identity matrix and a circulant permutation matrix that is not an identity matrix can be expressed separately.

Below, the QC-LDPC code is described in detail.

First, as in mathematical equation 2 Circular permutation matrix of size is defined here means the entry of the i-th row and j-th column in the matrix P above. ( )

[Equation 2-1]

For the permutation matrix P defined as above, (0 ≤ i < Z) is It is a cyclic permutation matrix in the form of a circular shift of each element of the identity matrix of size i to the right. The cyclic permutation matrix can also be defined as in [Mathematical Formula 2-2], in which case go It is a cyclic permutation matrix in the form of each element of the identity matrix of size shifted to the left by i times:

[Equation 2-2]

In the present disclosure, for convenience, various embodiments are described using a cyclic permutation matrix defined based on [Mathematical Formula 2-1]. However, the cyclic permutation matrices defined in [Mathematical Formula 2-1] and [Mathematical Formula 2-2] have the same basic algebraic properties, although their expressions are different. Therefore, a cyclic permutation matrix defined based on Mathematical Formula 2-2 can be used in the embodiments of the present disclosure, or various types of cyclic permutation matrices having the same algebraic properties can be used.

The parity check matrix H of the simplest QC-LDPC code can be expressed in the following mathematical expression 3.

[Equation 3]

For convenience second When defined as a 0-matrix of size , each index of the cyclic permutation matrix or 0-matrix in the above mathematical expression 3 has one of the values {-1, 0, 1, 2, ..., Z-1}. The identity matrix is or can be expressed as , and the 0-matrix is or can be expressed as . In addition, the parity check matrix H of the above mathematical expression 3 is a column block. Dog, row block Since it is a dog, the size of the above parity check matrix H is am.

If the parity check matrix of the above mathematical expression 3 has the maximum rank (full rank, or complete coefficient), the length of the information word bit of the QC-LDPC code corresponding to the parity check matrix is For convenience, the information bits correspond to The ten blocks of the dog are called information word ten blocks and the number of information word bits is , corresponding to the remaining parity bits. The ten blocks of the dog can be called parity ten blocks. In this case, the number of parity bits is . For reference, if the parity check matrix of the above mathematical expression 3 does not have the maximum rank, the above information word bits is larger, and the number of information bits is The larger the value, the more parity bits has a smaller value.

Typically, in the parity check matrix of the above mathematical expression 3, each cyclic permutation matrix and 0-matrix are replaced with 1 and 0, respectively. A binary matrix of size H is called the mother matrix or base matrix or base graph of the parity check matrix H, and M(H) or It is expressed as follows. Also, by selecting the index of each cyclic permutation matrix or 0-matrix, it is obtained as in mathematical formula 4. An integer matrix of size H is the exponent matrix of the parity check matrix H. It is said.

[Equation 4]

Of course, the names of these matrices are just examples and are exponential matrices. can be called by different names. For example, since the indices of each cyclic permutation matrix correspond to values that circularly shift the identity matrix, as in [Mathematical Formula 2-1] or [Mathematical Formula 2-2], each indices is called a circular shift value (or circular shift value). It can also be called a circular shift value matrix or shift value matrix. It is generally equivalent to the size of the exponential matrix or shift value matrix and the circular permutation matrix or 0-matrix. Given a value, a parity check matrix can be determined or identified. For this reason, according to the mathematical definition, a parity check matrix means a binary matrix H that satisfies the condition of Equation 1, but in some cases, for convenience, an exponential matrix or a shift value matrix can also be called a parity check matrix.

Since one integer included in the exponential matrix or the shift value matrix corresponds to a cyclic permutation matrix in the parity check matrix, the exponential matrix may be conveniently expressed as a sequence of integers. In general, the parity check matrix can be expressed not only as an exponential matrix but also as various sequences that can express algebraically identical characteristics. In the present disclosure, the parity check matrix is conveniently expressed as a sequence indicating the position of 1 in the exponential matrix or the parity check matrix, but there are various sequence notations that can distinguish the positions of 1 or 0 included in the parity check matrix, and thus the present disclosure is not limited to the method expressed in the present specification and may be expressed in the form of various sequences or matrices that exhibit the algebraically identical effect. The sequence may be called in various ways, such as an LDPC sequence, an LDPC code sequence, an LDPC sequence, a parity check matrix sequence, or a (cyclic) shift value sequence, in order to distinguish it from other sequences.

In addition, a transceiver may directly generate a parity check matrix to perform LDPC encoding and decoding, but depending on implementation characteristics, LDPC encoding and decoding may also be performed based on an exponential matrix, a shift value matrix, or a sequence that has the same effect algebraically as the parity check matrix. Therefore, although encoding and decoding using a parity check matrix is described for convenience in this disclosure, in an actual transceiver, encoding and decoding can be implemented through various methods that can obtain the same effect as the parity check matrix.

For reference, the algebraically equivalent effect means that two or more different representations can be described or transformed as being completely equivalent to each other logically or mathematically. In particular, in the case of codes that can be defined by matrices, such as LDPC codes, it can mean that algebraic values that can be defined by matrices, such as minimum distance, rank, and cycle characteristics in the Tanner graph, are identical. It can also mean that the basic structure or operation during the encoding/decoding process is identical. For example, if the same matrix is obtained through appropriate column permutations and row permutations, the two matrices can be considered algebraically equivalent from a code perspective. Furthermore, various transpose transformations that do not change the actual properties of the code can also provide algebraically equivalent effects.

As a concrete example, given the following matrix A, examples of various transformations that provide algebraically identical effects are shown in A1 through A8.

, (step, Is and coprime integers)

silver This is an example of a block-by-block permutation that permutes the second and third row blocks. silver In addition, here is an example of a block-by-block permutation in which the first and third row blocks are permuted. silver This is an example of applying cyclic permutation only to the first and third column blocks. Is In addition, this is an example in which the cyclic permutation is applied only to the second and fourth row blocks. Is This is an example of applying transpose to . silver This is an example of applying block-wise transposition transformation. silver Here is an example of reversing the signs of each index (or cyclic shift value) (for convenience only) A 0-matrix of size When expressing as , using negative exponents (or shift values) can be confusing, so Is ) can also be expressed as a positive value. silver This is an example of applying an affine transformation with a constant term of 0 (it can also be applied to cases where the constant term is not 0 in general). For reference, the above examples are for convenience. go Although we have described the case where there are no elements that are 0-matrix of size 0, when a 0-matrix is included, the part corresponding to the 0-matrix is always a 0-matrix regardless of the transformation. For example, at If is a 0-matrix, , and In , too is a 0-matrix, and In each and is a 0-matrix, and at is a 0-matrix, at is a 0-matrix.

The above transformations are merely examples, and various other transformations may exist. Furthermore, while each transformation can be applied independently, they can also be applied in combination and overlapping. The characteristic of each transformation or combination of transformations is that they can be converted back to the original matrix through an appropriate invertible transform process.

The above-described various transformations or combinations of transformations are essentially reversible transformations in which the arrangement of bits (or variable nodes) or check nodes on the Tanner graph is simply changed, or symmetrical transformations or specific structures are maintained. Therefore, in terms of code performance, instantaneous performance may vary depending on the given channel conditions, but on average, the same performance can be provided. In this way, in the present disclosure, all parity check matrices that can be obtained through transformations that can achieve the same algebraic effect are considered to be the same parity check matrix.

For convenience, one so far Although only one cyclic permutation matrix corresponding to a square block of size has been described, the same invention can be applied to a case where a single block includes multiple cyclic permutation matrices. For example, as in the following mathematical expression 5, two cyclic permutation matrices are located at the positions of one i-th row block and one j-th column block. , When it corresponds, simply It can be expressed in the form of a sum such as , and the exponential matrix (or cyclic shift value matrix) can be expressed as in mathematical expression 6. Looking at mathematical expression 6, it can be seen that it is a matrix in which two integers correspond to the i-th row and j-th column corresponding to the row block and column block including the sum of the plurality of cyclic permutation matrices.

[Equation 5]

[Equation 6]

As in the above embodiment, in general, a QC-LDPC code can have one or more cyclic permutation matrices corresponding to one row block and one column block in a parity check matrix, and for reference, multiple cyclic permutation matrices are duplicated in one row block and one column block. A matrix of size is called a circulant matrix (or circulant matrix or circular matrix). In general, each element (entry) of a circulant matrix has not only binary numbers but also arbitrary numbers as elements. However, in this disclosure, for convenience, a binary code is described, so the circulant matrix means a binary circulant matrix. Of course, the algebraic structure and features proposed in this disclosure can be extended in a similar manner to the case of non-binary codes, but details are omitted in this disclosure.

Meanwhile, the basic matrix (or parent matrix or basic graph) for the parity check matrix and the index matrix (or cyclic shift value matrix) of the above mathematical expressions 5 and 6 means a binary matrix obtained by replacing each cyclic permutation matrix and 0-matrix with 1 and 0, respectively, similar to the definition used in the above mathematical expression 3, and the cyclic matrix included in one block (i.e., the sum of multiple cyclic permutation matrices) can also be replaced with 1.

A simple example of the relationship between the parity check matrix, the exponential matrix (or the cyclic shift matrix), and the fundamental matrix is shown in the following [Mathematical Formula 7].

[Equation 7]

In the above [Equation 7] The notation of the index (or shift value) of a 0-matrix of size -1 is just an example, and can be expressed in various ways. In addition, the matrix representation method of the above [Mathematical Formula 7] can be expressed in various other ways, and as a specific example, the representation method of the parity check matrix of the LDPC code defined in 3GPP TS 38.212, which is a 3GPP 5G standard specification, can be used. In 3GPP TS 38.212, the sizes of the parity check matrices of the LDPC code corresponding to BG1 (Base Graph 1) and BG2 (Base Graph 2) are too large, so they are represented using a table. When the corresponding representation method is applied to the matrices of the above [Mathematical Formula 7], the result is as follows [Table 1].

Is is a matrix of size, silver is a matrix of size. The entries of the basic matrix (or basic graph) and parity check matrices not expressed in Table 1 below are 0 or A 0-matrix of size 0 corresponds.

[Table 1]

If the basic matrix and exponential matrix in the above [Mathematical Formula 7] are expressed using a sequence, they can be expressed in the following manner.

:

0 2 3

0 1 3 4

1 2 4 5

0 1 2 5

:

159 0 0

117 109 0 0

225 1 0 0

84 211 0 0

Exponential matrix as above When expressed as a sequence, it can be conveniently named in various ways, such as shift sequence, shift value sequence, LDPC sequence, etc. In the sequence expression method above, is a method of listing the positions of columns where the elements are not 0 for each row, is a method of listing the indices or shift values of each cyclic permutation matrix, not a 0-matrix, for each row. From the above sequences, the exponent matrix (or shift value matrix) can be defined exactly, and if If we obtain information about the values, the parity check matrix can also be defined exactly.

Another simple example of the relationship between the parity check matrix and the exponential matrix (or cyclic shift matrix), the fundamental matrix, etc. is shown in the following [Equation 8]. In the example of [Equation 8], at least one It illustrates a case where a block of size contains a circulant matrix corresponding to two or more circulant permutation matrices.

[Equation 8]

For reference, in the above [Equation 8] is a weight matrix for the fundamental matrix, exponential matrix, or parity check matrix, and is a matrix that expresses how many cyclic permutation matrices correspond to the ith row, the jth column in the fundamental matrix and exponential matrix, or the ith row block, the jth column block in the parity check matrix. For example, corresponds to the i-th row block and j-th column block in the parity check matrix. It refers to a matrix that represents the number of circulant permutation matrices that constitute a circulant matrix of size as an element of the i-th row and j-th column. That is, is a matrix that represents 0 as an element when a 0-matrix corresponds, and w as an element when w cyclic permutation matrices correspond. (Note that a 0-matrix can be viewed as a cyclic matrix in a broad sense, but it is not a cyclic 'permutation' matrix.)

If the basic matrix or parity check matrix or circular shift value matrix (or exponential matrix) defined in [Mathematical Formula 8] is expressed by applying the method of expressing parity check matrices of LDPC codes in 3GPP TS 38.212 as in [Table 1], it can be expressed as in [Table 2] below.

Is is a matrix of size, silver is a matrix of size . The elements of the basic matrix (or basic graph) and parity check matrix not expressed in Table 2 below are 0 or A 0-matrix of size 0 corresponds.

[Table 2]

If the basic matrix and exponential matrix of the above [Mathematical Formula 8] are expressed using a sequence, they can be expressed in the following manner.

:

0 1 2 3

0 1 2 3

s:

(117, 159) 109 0 0

84 (211, 225) (1, 3) 0

As another way of expressing it, we can use a weight matrix to express it in a form consisting only of a sequence, as follows:

:

0 1 2 3

0 1 2 3

:

2 1 1 1

1 2 2 1

:

117 159 109 0 0

84 211 225 1 3 0

In the above expression is a method of listing the positions of columns where the elements are not 0 for each row, is a matrix defined based on the number of circulant permutation matrices that constitute the circulant matrices corresponding to the fundamental matrix, the exponential matrix, or the parity check matrix. is a method of listing the indices or shift values of each non-zero circulant matrix by row. The exponential matrix can be defined exactly from the above sequences, and if If we obtain information about the values, the parity check matrix can also be defined exactly.

Since the performance of an LDPC code is determined by its parity check matrix, designing a parity check matrix is essential for achieving high-performance LDPC codes. Furthermore, an LDPC encoding or decoding method capable of supporting various input lengths and code rates is required.

Lifting can be used not only for the efficient design of QC-LDPC codes, but can also mean a method for generating parity check matrices of various lengths or generating LDPC codewords using given base matrices and exponent matrices. That is, the lifting can be applied to efficiently design a very large parity check matrix by setting the Z value, which determines the size of a cyclic permutation matrix or a 0-matrix from a given small parent matrix, according to a specific rule, or can mean a method for generating parity check matrices of various lengths or generating LDPC codewords by applying an appropriate Z value to a given exponent matrix or its corresponding sequence.

The characteristics of the existing lifting method and the QC-LDPC code designed through lifting are briefly explained with reference to the following reference [Myung2006].

Reference [Myung2006]

S. Myung, K. Yang, and Y. Kim, “Lifting Methods for Quasi-Cyclic LDPC Codes,” IEEE Communications Letters. vol. 10, pp. 489-491, June 2006.

First, when an LDPC code C ₀ is given, S QC-LDPC codes to be designed through the lifting method are C ₁ , ..., C _S , and the values corresponding to the sizes of the row blocks and column blocks of the parity check matrix of each QC-LDPC code are L _k . Here, C ₀ corresponds to the smallest LDPC code that has the parent matrix of the C ₁ , ..., C _S codes as the parity check matrix, and the value Z ₀ corresponding to the size of the row blocks and column blocks is 1. In addition, for convenience, the parity check matrix of each code C _k Is exponential matrix of size and each index are chosen as one of the values {-1, 0, 1, 2, ..., Z _k - 1}.

The existing lifting method consists of steps such as C ₀ -> C ₁ ->...-> C _S and has the characteristic of satisfying the condition such as Z _k+1 = q _k+1 Z _k (q _k+1 is a positive integer, k=0,1,..., S-1). In addition, due to the characteristics of the lifting process, the parity check matrix of C _s If only storing is performed, all of the QC-LDPC codes C ₀ , C ₁ , ..., C _S can be expressed using the following mathematical expressions 9 or 10 depending on the lifting method.

[Equation 9]

or

[Equation 10]

In addition to the method of designing larger QC-LDPC codes C ₁ , ..., C _S from C ₀ , the method of generating smaller codes C _i (i=k-1, k-2, ... 1, 0) from larger codes C _k using an appropriate method such as Equation 9 or Equation 10 can also be called lifting. For reference, in 3GPP TS 38.212, LDPC codes of various lengths can be generated using the lifting method of Equation 10.

The lifting method of the above mathematical expression 9 or 10 makes Z _k , which corresponds to the size of the row block or column block in the parity check matrix of each QC-LDPC code C _k , have a multiple relationship with each other, and the exponent matrix is also selected by a specific method. The existing lifting method like this helps to easily design a QC-LDPC code with improved error floor characteristics by improving the algebraic or graph characteristics of each parity check matrix designed through lifting.

Figures 3a and 3b are examples to simply explain that the cycle characteristics of a QC-LDPC code can vary significantly depending on the exponential matrix.

Figure 3a is a diagram for explaining the cycle characteristics of a QC-LDPC code.

The exponential matrix in Fig. 3a is , and in this case, there may be many 4-cycles in the Tanner graph. Codes with many short cycles like this may cause serious degradation in decoding performance.

Figure 3b is a diagram for explaining the cycle characteristics of a QC-LDPC code.

The exponential matrix in Fig. 3b is , and in this case, the length of the shortest cycle on the Tanner graph is 12. Since the cycle characteristics on the Tanner graph can change significantly just by changing a single index of the cyclic permutation matrix, the selection of the index matrix plays an important role in improving the performance of the LDPC code. The lifting method can be viewed as one of the design methods that takes these cycle characteristics into account.

In general, lifting can be thought of as using the exponential matrix of Equation 4 for LDPC encoding and decoding by changing the values of its elements for various Z values. For example, the exponential matrix of Equation 4 above and the transformed exponential matrix according to the Z value In this case, the following conversion formula, such as mathematical formula 11, can be generally applied.

[Equation 11]

In the above mathematical formula 11 can be defined in various forms, for example, the above [Mathematical Formula 9] It corresponds to ( ), the above [Mathematical Formula 10] is may correspond to (mod(a,b) means modulo-b operation for a). In addition, can be defined in various ways, as shown in the following mathematical expression 12.

[Equation 12]

or

or

In the above mathematical expression 12, D means a constant that is a positive integer defined in advance.

For reference, in the conversion formula of the above mathematical expression 11, the reference value (or, and To distinguish the application of The reference value) is represented as 0 for convenience, but the reference value is the lifting size Z value to be supported or It can be set differently depending on how the 0-matrix of size is expressed. For example, If the 0-matrix of size is defined as a number or symbol other than the negative integer -1 and is not determined in advance, the reference value for applying the conversion formula f can be defined differently. In addition, if the expression of the exponent matrix or LDPC sequence is based on a method of not expressing the exponent corresponding to the 0-matrix by excluding it from the beginning, the rule for values whose exponent is less than 0 in mathematical expression 11 can be omitted. Since the conversion formula f is applied to a circulant permutation matrix or a circulant matrix other than a 0-matrix, in general There are various ways to omit transformations for a 0-matrix of size.

As an embodiment of the present disclosure, a case of applying LDPC encoding and decoding based on a plurality of exponential matrices or LDPC sequences based on a single determined base matrix is described. That is, the base matrix is fixed to one, and an exponential matrix or (cyclic) shift value matrix or LDPC sequence of an LDPC code defined based on the base matrix can be determined, and variable-length LDPC encoding and decoding is performed by applying lifting according to a lifting size included in each lifting size group from the matrix or sequence. This method has a characteristic that elements or numbers constituting the exponential matrix or LDPC sequence of an LDPC code can have different values, but the positions of the corresponding elements or numbers are exactly the same on the base matrix.

The LDPC code defined in TS 38.212, the 3GPP 5G standard, is also a code designed in the same way, with two basic matrices. This is defined and 8 exponent matrices (or circular shift value matrices) for each base matrix ( ) is defined and can be used for LDPC encoding. That is, according to the standard, a total of two base matrices and 16 exponent matrices, and an appropriate lifting size Based on this, the parity check matrix of various LDPC codes can be determined. However, in the TS 38.212 standard, The matrix corresponding to is called the parity check matrix, and the matrix corresponding to the normal parity check matrix is matrix- It was named as. is a matrix of integers with lifting size A parity check matrix in the strict sense can be constructed if given, but for convenience as explained above, can also be called a parity check matrix.

In the following, for the convenience of explanation, the LDPC code and its representation method defined in the 3GPP 5G standard specification TS 38.212 are used as much as possible, but in some cases, it can be expressed in a conventional mathematical expression or in another way. First, the parity check matrix or matrix- of the LDPC code The lifting sizes (Z) to be supported to determine the lifting size are shown in [Table 3] below. (The set index i LS for each lifting size set below is only an example and can be changed to a different order.)

[Table 3]

In the present disclosure, lifting sizes or block sizes are basically expressed in the same manner as in [Table 3] above, but they can also be expressed in the same manner as in [Table 4] below, and various other expression methods are also possible.

[Table 4]

In 3GPP 5G, lifting sizes or block sizes Z can be divided into multiple sets (or groups) as shown in [Table 3] or [Table 4]. (Hereinafter, for convenience, they are referred to as lifting size sets (or groups) or block size sets (or groups))

In the 3GPP 5G standard, an exponential matrix can be obtained using the lifting method of [Mathematical Formula 10]. Parity check matrix or matrix-based It decides. This is and When , for each i and j This means that (for reference, the 3GPP 5G standard specification TS 38.212 states that Simply put ) was expressed as

As explained previously in [Mathematical Formula 11], in the present disclosure, from the basic matrix and the exponential matrix Note that no special transformation is applied to the part corresponding to the 0-matrix of size. That is, In cases where there is no special explanation, no special transformation is performed on the part corresponding to the 0-matrix. Depending on the value, only the size of the 0-matrix can change. As a specific example, in the expression method used in the 3GPP 5G standard specifications, as in [Table 1] and [Table 2], Since the part corresponding to the 0-matrix of size is not indicated from the beginning, it is included in [Table 1] or [Table 2]. If we perform a predefined transformation such as modulo appropriately only for , the part corresponding to the 0-matrix is naturally not transformed, which is equivalent to defining a 0-matrix with a different size. The above expression is an example for the convenience of explanation, and various other expression methods may exist.

For a given exponential matrix (or circularly shifted value matrix), a parity check matrix or matrix- Since the lifting sizes defined in [Table 3] above can be transformed in various ways, the set of lifting sizes required for a system can be defined differently. That is, the above [Table 3] and [Table 4] are only examples, and all lifting size (Z) values included in the lifting size (or block size) group (or set) of [Table 3] and [Table 4] above can be used, and some of the appropriate lifting sizes can be selected and used depending on the situation required by the system, and more diverse lifting size values can be added as needed.

For example, if the minimum transport block size (TBS) is 24, Z = 2, 3, 4, 5, 6, 9, and 13 are virtually never used in the system. In this case, some Z values can be defined by excluding them, as shown in [Table 5].

[Table 5]

In a communication system based on LDPC codes that applies [Table 5] as the lifting size, the minimum lifting size is 7, so each column block that constitutes the parity check matrix of the LDPC code used for LDPC encoding and decoding can be composed of at least 7 columns.

If the minimum value of TBS is greater than 8 for future scalability, and additional values such as 8 or 16 are used, the lifting size set (or block size group) may be changed as shown in [Table 6].

[Table 6]

The above [Table 6] excludes only the cases in [Table 3] or [Table 4] where Z = 2 or 3, because the minimum value of Z that can be determined when TBS is 8 or greater is 4 or greater.

As an example of setting another lifting size set, let us call the lifting size set A sets , , , … , When classified, it can be classified in the following way: ( )

...

...

For example, the case where A = 4 and A = 8 can be represented as in the following [Table 7-1] and [Table 7-2]. ( )

[Table 7-1]

[Table 7-2]

When the lifting size sets are defined in the manner shown in [Table 7-1] and [Table 7-2] above, there is an advantage in that the distribution of Z values can be set relatively uniformly. The lifting size sets defined in [Table 7-1] and [Table 7-2] above all contain the same number of Z values, but appropriate Z values can be added or subtracted for each set as needed. For example, it is possible to define the lifting size sets of [Table 3] to [Table 6] above based on the lifting size sets of [Table 7-2] above.

Also, in [Table 7-1] and [Table 7-2] By appropriately setting the range of values, you can also set Z values suitable for your system. For example, The value Setting this to , we obtain a set of lifting sizes with 7 different Z values in each set, The value If set to , a lifting size set with four different Z values is obtained in each set. However, the above The value is an example and the above An example of a value does not limit the scope of the present disclosure. In addition, in some cases, it is also possible to add or exclude some appropriate Z values from the lifting size sets. For example, if the maximum value of Z set in the system is Zmax, all values greater than Zmax can be removed (e.g., Zmax = 768). In addition, if all Z values that can be supported by the existing 3GPP 5G standard are included, at least some of the values such as 2, 3, 4, 5, 6, 7, etc. may be additionally included. Of course, even if values such as TBS = 8, 16 are additionally supported in a 5G or 6G system, values such as Z = 2, 3 are not used, so only values such as 4, 6, 7 or 4, 5, 6, 7 may be additionally included, and values that are not actually used in 5G may be excluded. The following [Table 8] shows specific examples of lifting size sets. (The numbers in () in Table 8 represent values that may or may not be used as lifting sizes.)

[Table 8]

The lifting size sets can be defined in various ways other than [Table 3] to [Table 8], but the common characteristics are that each of the multiple lifting size sets must not have overlapping lifting sizes, and the lifting sizes included in each lifting size set must be multiples or divisors of each other. [Table 3] to [Table 8] above define a continuous lifting size for the smallest lifting size in each lifting size set. ( ) are composed of multiples, but are generally ( ) can be composed of non-consecutive multiples, and can also include multiples of integers other than multiples of 2.

In new communication systems, including 6G systems, in order to support backward compatibility with existing systems (e.g., 5G systems), the existing lifting size set may be maintained as is (e.g., [Table 3] or [Table 4]), and a new lifting size set may be added (e.g., [Table 5] to [Table 8]). Alternatively, if only one lifting size set is defined, but the range of TBS used is determined differently in advance depending on the application scenario or system settings such as the target BLER, the range of Z values used also varies. For example, if the first minimum TBS and the first maximum TBS values are set for a service applying the first target BLER, and the second minimum TBS and/or the second maximum TBS values are defined for a service applying the second target BLER, the first minimum TBS and the second minimum TBS values may be different, or the first maximum TBS and the second maximum TBS values may be different (both the minimum value and the maximum value may be different).

Additionally, the applicable service scenario or target BLER, etc. may be determined based on upper layer signaling information. For example, the CQI (channel quality information) table or the MCS (modulation coding scheme) table may typically be determined by considering the target service scenarios or BLERs. (For example, the first target service or BLER may be the first CQI table and/or the first MCS table, the second target service or BLER may be the second CQI table and/or the second MCS table, the third target service or BLER may be the third CQI table and/or the third MCS table, etc.)

This means that the range of lifting sizes to be used or the set of lifting sizes to be used can be determined from higher-layer signaling information, and the intermediate operations can exist in various ways depending on the system. Furthermore, the set of lifting sizes to be used can be indicated through physical layer signaling or higher-layer signaling. Based on the indicated set of lifting sizes and the determined lifting size Z value, the parity check matrix can be determined.

For reference, in the present invention, the target BLER means the minimum BLER to be achieved in the system, and is typically set so that the average BLER of a terminal or base station does not exceed the target BLER.

FIG. 4 is a transport block structure diagram according to an embodiment of the present disclosure.

Referring to FIG. 4, a transport block composed of A bits is added with L bits of CRC bits (TB-CRC bits), and one transport block can become one code block. In addition, if the value B = A + L is greater than a specific threshold value, it may be divided into multiple code blocks through an appropriate segmentation process. At this time, the size K of the code blocks is all the same, and for this purpose, specific bits called null bits or filler bits may be added to each code block. The null bits or filler bits typically correspond to a value of 0, but are not necessarily limited to this, and may be composed of any specific bits determined in advance. This operation of adding predetermined bits such as null bits or fillers is typically called shortening because the size of the actual pure information word bits is reduced, and if the values are 0, it may be called zero-padding.

After the size of the transport block to be transmitted (TBS, transport block size) is determined, one of the basic matrices of two different LDPC codes used for LDPC encoding or decoding can be determined based on the code rate indicated in the TBS size and MCS through a method such as the [basic matrix determination method] below.

[How to determine the basic matrix]

The LDPC basic matrix for LDPC encoding and decoding of a transport block with TBS = A can be determined based on the TBS size and the code rate indicated by the MCS as follows:

- When A ≤ 292 (or 288), or A ≤ 3824 and R ≤ 0.67, or R ≤ 0.25, LDPC encoding can be performed using LDPC basic matrix 2.

- In addition, LDPC encoding can be performed using LDPC basic matrix 1. For reference, basic matrix 1 defined in the 3GPP 5G standard and basic matrix 2 is as follows.

:

0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23

0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24

0 1 2 4 5 6 7 8 9 10 13 14 15 17 18 19 20 24 25

0 1 3 4 6 7 8 10 11 12 13 14 16 17 18 20 21 22 25

0 1 26

0 1 3 12 16 21 22 27

0 6 10 11 13 17 18 20 28

0 1 4 7 8 14 29

0 1 3 12 16 19 21 22 24 30

0 1 10 11 13 17 18 20 31

1 2 4 7 8 14 32

0 1 12 16 21 22 23 33

0 1 10 11 13 18 34

0 3 7 20 23 35

0 12 15 16 17 21 36

0 1 10 13 18 25 37

1 3 11 20 22 38

0 14 16 17 21 39

1 12 13 18 19 40

0 1 7 8 10 41

0 3 9 11 22 42

1 5 16 20 21 43

0 12 13 17 44

1 2 10 18 45

0 3 4 11 22 46

1 6 7 14 47

0 2 4 15 48

1 6 8 49

0 4 19 21 50

1 14 18 25 51

0 10 13 24 52

1 7 22 25 53

0 12 14 24 54

1 2 11 21 55

0 7 15 17 56

1 6 12 22 57

0 14 15 18 58

1 13 23 59

0 9 10 12 60

1 3 7 19 61

0 8 17 62

1 3 9 18 63

0 4 24 64

1 16 18 25 65

0 7 9 22 66

1 6 10 67

:

0 1 2 3 6 9 10 11

0 3 4 5 6 7 8 9 11 12

0 1 3 4 8 10 12 13

1 2 4 5 6 7 8 9 10 13

0 1 11 14

0 1 5 7 11 15

0 5 7 9 11 16

1 5 7 11 13 17

0 1 12 18

1 8 10 11 19

0 1 6 7 20

0 7 9 13 21

1 3 11 22

0 1 8 13 23

1 6 11 13 24

0 10 11 25

1 9 11 12 26

1 5 11 12 27

0 6 7 28

0 1 10 29

1 4 11 30

0 8 13 31

1 2 32

0 3 5 33

1 2 9 34

0 5 35

2 7 12 13 36

0 6 37

1 2 5 38

0 4 39

2 5 7 9 40

1 13 41

0 5 12 42

2 7 10 43

0 12 13 44

1 5 11 45

0 2 7 46

10 13 47

1 5 11 48

0 7 12 49

2 10 13 50

1 5 11 51

The above basic matrix 1 and basic matrix 2 The sizes of the parity check matrices are 46×68 and 42×52, respectively, and the sizes of the parity check matrices determined from the basic matrices are 46Z×68Z and 42Z×52Z.

Additionally, the number of CRC bits (L _TB ) to be added to the transport block can be determined as follows according to the above-determined TBS.

[Method for determining the number of transport block CRC bits]

The CRC bit size L _TB value for a transport block with TBS = A can be set differently depending on the TBS value as follows:

If A > 3824, L _TB = 24, otherwise L _TB = 16.

Based on the TBS size (A) determined in this way or the total number of bits B (A + L) with the CRC appended to the transport block, an appropriate code block is determined from the transport block, and LDPC encoding and decoding can be performed for each code block. The process of determining the code block length (CBS) is described in more detail as follows:

[How CBS decides]

The input bit sequence for code block segmentation can be expressed as b ₀ , b ₁ , … , b _B-1 (B > 0). If B is larger than the maximum code block size K _cb , segmentation of the input bit sequence is performed, and a CRC of L = 24 bits is additionally appended to each code block. For LDPC elementary matrix 1, the maximum code block size is K _cb = 8448, and for LDPC elementary matrix 2, the maximum code block size is K _cb = 3840.

The specific steps are explained below.

Step 1: Number of code blocks can be decided.

- If On the other hand, And and, .

- Otherwise, , and, .

Step 2: Let the bit output from the code block segmentation be c _r0 , c _r1 ,…, cr _{(Kr - 1)} , where r represents the code block number (0 ≤ r < C), and Kr (= K) represents the number of bits in the code block for the code block number r. Here, K, the number of bits included in each code block, can be calculated as follows:

- ;

- In the case of LDPC basic matrix 1 .

- In the case of LDPC basic matrix 2,

On the other hand, ;

On the other hand, ;

On the other hand, ;

On the other hand, .

Step 3: Table 3 Among the values The minimum value that satisfies can be determined. For LDPC basic matrix 1 , and for LDPC basic matrix 2 Set to .

In step 2 of the above [CBS Determination Method] The value corresponds to a column or column block corresponding to an LDPC information bit in the basic matrix (or basic graph) or parity check matrix of the LDPC code, and is the maximum value of the LDPC information bit without shortening or zero padding. ) can correspond to. For example, even if the number of columns (or column blocks) corresponding to information word bits in the LDPC basic matrix 2 or the parity check matrix corresponding to the basic matrix 2 is 10, if If set to , then substantially the maximum LDPC encoding/decoding is performed on the information bits of the bits, and at least The information bits corresponding to the column of the dog are shortened or zero-padded. Shortening or zero-padding here can mean that the transmitter and receiver assign a bit value promised, such as 0, or it can mean that the corresponding part is not used in the parity check matrix.

The lifting size Z value for LDPC encoding and decoding can be determined based on the lifting size sets shown in [Table 3] to [Table 8] or the lifting size sets with specific lifting size values added and removed. Each Z value is included in a specific set determined in advance according to the index i _LS . When the Z value is determined in step 3 of the [CBS determination method], the set corresponding to the Z value or the index i _LS value of the set is determined, and the parity check matrix of the LDPC code corresponding to each index or the corresponding sequence can also be determined. By applying a modulo operation based on the lifting size Z to the parity check matrix of the LDPC code determined in this way or the corresponding sequence, the parity check matrix or the sequence is transformed to support encoding and decoding of LDPC codes of various lengths. In the 3GPP 5G standard, each number included in the parity check matrix or sequence of the LDPC code means a value corresponding to a cyclic permutation matrix.

A flowchart for an embodiment of an LDPC encoding and decoding process based on a designed base matrix or exponential matrix is shown in FIGS. 5 and 6.

Figure 5 is a diagram illustrating an embodiment of an LDPC encoding process.

First, the transmitter determines the transport block size TBS to be transmitted, as in step (510) of Fig. 5. In step (520), the transmitter determines whether the TBS is greater than, less than, or equal to max CBS.

If TBS is greater than max CBS, the transmitter can segment the transport block to determine CBS in step (530). If TBS is less than or equal to max CBS, the transmitter skips the segmentation operation and determines the TBS as CBS.

In step (540), the transmitter determines the lifting size (Z) value to be applied to LDPC encoding based on the CBS.

And the transmitter determines a parity check matrix or sequence based on the TBS or CBS or lifting size (Z) value in step (550). Alternatively, the transmitter may determine an LDPC index matrix or sequence that has an effect algebraically identical to the parity check matrix.

And the transmitter performs LDPC encoding based on the parity check matrix or sequence in step (560). Alternatively, the transmitter may perform LDPC encoding based on the exponential matrix or sequence in step (560). In addition, the transmitter may perform LDPC encoding based on the lifting size and the exponential matrix or sequence in step (560).

For reference, the step (550) above may include a process of converting the determined LDPC index matrix or sequence based on the determined lifting size, depending on the case. It is obvious that the LDPC index matrix or sequence or parity check matrix for LDPC encoding may be determined in various ways based on TBS or CBS, depending on the system. For example, the transmitter may first determine the base matrix through TBS, and then determine the LDPC index matrix or sequence parity check matrix based on the determined base matrix and CBS, and various other methods may also be applied. For reference, additional operations may be included depending on the system between steps (520) and (540) or between steps (530) and (540). For example, in the case of a 3GPP 5G system, the base matrix 2 ( ) means the number of columns to be actually used in the base matrix or the number of column blocks to be used in the parity check matrix depending on the TBS size. The process of determining the value may be included. (For reference, The column blocks of the parity check matrix corresponding to the columns of the basic matrix of the dog are shortened.)

The LDPC decoding process can be similarly represented as in Fig. 6.

Figure 6 is a diagram illustrating an embodiment of an LDPC decoding process.

If TBS is determined in step (610), the receiver determines in step (620) whether TBS is greater than, less than, or equal to max CBS.

If TBS is greater than max CBS, the receiver determines the size of the CBS to which segmentation is applied in step (630). If TBS is determined to be less than or equal to max CBS, TBS is determined to be equal to CBS.

The receiver determines the lifting size (Z) value to be applied to LDPC decoding at step (640).

Then, the receiver determines a parity check matrix or sequence based on the TBS or CBS or lifting size (Z) value at step (650). Alternatively, the transmitter may determine an exponential matrix or sequence that has an effect algebraically identical to the parity check matrix.

And the receiver can perform LDPC decoding based on the parity check matrix or sequence in step (660). Alternatively, the receiver can perform LDPC decoding using the exponent matrix or sequence in step (660). Note that step (650) may include a process of converting the determined LDPC exponent matrix or sequence based on the determined lifting size, as the case may be. It is obvious that the LDPC exponent matrix or sequence or parity check matrix for LDPC decoding can be determined in various ways based on TBS or CBS depending on the system. For example, the receiver can first determine the base matrix through TBS, and then determine the LDPC exponent matrix or sequence parity check matrix based on the determined base matrix and CBS, and various other methods can also be applied.

According to the above embodiment, the process of determining the exponent matrix or sequence of the LDPC code in steps (550) and (650) of FIGS. 5 and 6 has been described for the case where the exponent matrix or sequence is determined by one of the TBS, CBS, or lifting size (Z), but various other methods may exist. In addition, additional operations may be included between steps (620) and (640) or between steps (630) and (640) of FIG. 6 depending on the system. For example, in the case of a 3GPP 5G system, the basic matrix 2 ( ) means the number of columns to be actually used in the base matrix or the number of column blocks to be used in the parity check matrix depending on the TBS size. A process for determining the value may be included. Note that the receiver Since the bits corresponding to the column blocks of the parity check matrix corresponding to the columns of the base matrix can be known to have been shortened at the transmitter, the receiver may additionally perform appropriate operations on the shortened bits before performing LDPC decoding.

In an embodiment of the LDPC encoding and decoding process based on the basic matrix and the exponential matrix (or LDPC sequence) of the LDPC code of the above FIGS. 5 and 6, LDPC encoding and decoding of various code rates and various lengths can be supported by appropriately shortening or puncturing some of the information bits for the LDPC code and puncturing and repeating some of the code bits. For example, as in the 3GPP 5G standard technology, shortening is applied to some of the information bits in the LDPC encoding process of the above FIG. 5, and the first two of the basic matrix, i.e., the first in the parity check matrix By punching the information bits corresponding to the column of the dog, punching a portion of the parity, or repeating a portion of the LDPC codeword, various information word lengths (or code block lengths) and various code rates can be supported.

Given input bits or code block bits and the encoding bits are When expressed as (however, in the case of the basic matrix 1) , if the basic matrix is 2 ), part of the encoding process can be defined as shown in [Table 9] below.

[Table 9]

According to the above encoding process, the first of the input bits or code block bits bits is not included in the encoding bits. That is, the above This means that the bits are punctured at the transmitter and not transmitted to the receiver. For reference, if a portion of the information word bits is punctured, this means that the transmitter does not transmit a portion of the information word (102) of FIG. 1. Accordingly, the receiver can decode the untransmitted information word bits by treating them as erased. In other words, since the punctured bits are regarded as if they were lost and have the same probability of being 0 or 1, the receiver can insert a corresponding value to perform decoding.

The information bits punctured during the above encoding process may not always be transmitted, even in the case of retransmission. In cases where a circular buffer is used for rate matching, if rate matching and retransmission are performed without storing the punctured information bits in the circular buffer, the punctured information bits may not always be transmitted.

On the other hand, in the case of a first transmission, some of the information bits may be punctured, and in the case of a retransmission, all or some of the punctured information bits may be transmitted. All information bits are stored in a circular buffer, but in the case of a first transmission, the RV (redundancy value) value may be appropriately set so that some of the information bits are punctured (e.g., the RV0 value is set to exclude the information bits to be punctured). Even if some of the information bits are punctured in the first transmission, since the bit values are stored in the circular buffer, in the case of a retransmission, some or all of the punctured information bits may be transmitted depending on the circular buffer rate matching operation and selection of an appropriate RV value.

For convenience, in [Table 9] is called a coding bit, but the definition of a coding bit may change for convenience of explanation. For example, in [Table 9] The bit string after punching out some of the information bits can be defined as the encoded bit, but in reality, the parity bit vector in the encoding process Input bits or code block bits to generate Because this is used, it is based on the pre-perforation of the information bits.

can also be defined as a coded bit. Also, a bit string with rate matching applied based on the allocated resource amount. This can also be defined as a coded bit, and is a bit string with interleaving applied to the rate-matched bit string. This can also be defined as a coded bit. In addition, the coded bit string can be defined in various ways for convenience of explanation, but usually, the bit string related to actual transmission in the system is Ina, related to the encoding process This can be defined by the encoding bits.

In the LDPC decoding process of FIG. 6, decoding can be performed by adding appropriate operations to the shortened information bits and the punctured bits or repeated bits in response to the transmitter operation. Typically, the shortened information bits are 0, so the receiver performs decoding by excluding the column corresponding to the shortened bits from the parity check matrix, or by setting a value preset in the system for the shortened bits to perform decoding. (Since it is certain to be 0, the highest value corresponding to 0 preset in the system is typically set.) Since the punctured parity bits are regarded as lost and have the same probability of being 0 and 1, the receiver can perform decoding by inserting a corresponding value, or, depending on the structure of the parity check matrix, decoding can be performed without using at least some of the rows corresponding to the punctured parity bits. In general, when puncturing the parity bit corresponding to a column with degree 1, the LDPC decoder can perform decoding without using part or all of the corresponding part in the parity check matrix, which has the advantage of reducing decoding complexity.

In addition, when supporting variable information word length or variable code rate by using LDPC code shortening or zero padding, the code performance can be improved depending on the shortening order or shortening method. If a shortening order is set, the encoding performance can be improved by appropriately rearranging the order of some or all of the given basic matrix. In addition, the performance can be improved by appropriately determining the number of column blocks to which the lifting size or shortening is applied for a specific information word length (or code block length CBS). Similarly, there are methods to improve the performance of LDPC codes by adjusting the puncturing order of the parity bits or the transmission order of the generated LDPC codeword. For example, better performance can be supported by appropriately puncturing some of the information word bits and the parity bits than by simply puncturing the parity bits to support a variable code rate. In addition, when repeating some of the LDPC codewords to support a lower code rate, the LDPC encoding performance can be improved by appropriately determining the order in advance.

Typically, in the LDPC encoding process, the transmitter first determines the size of the input bits (or code blocks) to which the LDPC encoding is to be applied, and then determines the lifting size (Z) to which the LDPC encoding is to be applied based on the size, determines an appropriate LDPC index matrix or sequence based on the lifting size, and then performs LDPC encoding based on the lifting size (Z) and the determined index matrix or LDPC sequence. At this time, the LDPC index matrix or sequence may be applied to LDPC encoding without transformation, or in some cases, the LDPC index matrix or sequence may be appropriately transformed based on the lifting size (Z) to perform LDPC encoding.

Similarly, in the LDPC decoding process, the receiver determines the size of the input bits (or code blocks) for the transmitted LDPC codeword, and then determines the lifting size (Z) to apply LDPC decoding based on the size, determines an appropriate LDPC exponent matrix or sequence based on the lifting size, and then performs LDPC decoding based on the lifting size (Z) and the determined exponent matrix or LDPC sequence. At this time, the LDPC exponent matrix or sequence may be applied to LDPC decoding without transformation, and in some cases, the LDPC exponent matrix or sequence may be appropriately transformed based on the lifting size (Z) to perform LDPC decoding.

In a parity check matrix, the submatrix corresponding to the parity bits often has a special structure for efficient encoding. In this case, lifting may change the encoding method or complexity. Therefore, in order to maintain the same encoding method or complexity, lifting may not be applied to some of the exponent matrices for the submatrix corresponding to the parity in the parity check matrix, or a different lifting method may be applied to the exponent matrix for the submatrix corresponding to the information word bits. In other words, the lifting method applied to the sequence corresponding to the information word bits within the exponent matrix may be set differently from the lifting method applied to the sequence corresponding to the parity bits, and in some cases, lifting may not be applied to some or all of the sequence corresponding to the parity bits, so that a fixed value may be used without sequence transformation.

Figure 7 is a block diagram of a transmitter device according to an embodiment of the present disclosure.

Specifically, as shown in FIG. 7, the transmitting device (700) may include a segmentation unit (710), a zero padding unit (720), an LDPC encoding unit (730), a rate matching unit (740), a modulation unit (750), etc., to process variable-length input bits. The rate matching unit (740) may include an interleaver (741) and a puncturing/repetition/zero removal unit (742), etc.

Here, the components illustrated in FIG. 7 are components that perform encoding and modulation for variable-length input bits, and this is only an example, and in some cases, some of the components illustrated in FIG. 7 may be omitted or changed, and other components may be added.

Meanwhile, the transmitting device (700) can determine necessary parameters (e.g., input bit length, ModCod (modulation and code rate), parameters for zero padding (or shortening), code rate/code length of LDPC code, parameters for interleaving, parameters for repetition and puncturing, and at least one of modulation methods), and encode the input bits based on the determined parameters and transmit them to the receiving device (800).

Since the number of input bits is variable, when the number of input bits is greater than a preset value, the input bits can be segmented to have a length less than or equal to the preset value. In addition, each segmented block can correspond to one LDPC coded block. However, when the number of input bits is less than or equal to a preset value, the input bits are not segmented and the input bits can correspond to one LDPC coded block.

Meanwhile, the transmitting device (700) may store various parameters used for encoding, interleaving, and modulation. Here, the parameter used for encoding may include at least one of information on a code rate, a codeword length, and a parity check matrix of an LDPC code. In addition, the parameter used for interleaving may include information on an interleaving rule, and the parameter used for modulation may include information on a modulation method. In addition, information on puncturing may include a puncturing length. In addition, information on repetition may include a repetition length. The information on the parity check matrix may include an exponent value of a circulant matrix or values algebraically identical thereto when using the parity matrix presented in the present disclosure.

In this case, each component constituting the transmitting device (700) can perform an operation using these parameters.

Meanwhile, although not shown, in some cases, the transmitter (700) may further include a control unit (not shown) for controlling the operation of the transmitter (700).

Figure 8 is a block diagram of a receiving device according to an embodiment of the present disclosure.

Specifically, as shown in FIG. 8, the receiving device (800) may include a demodulation unit (810), a rate dematching unit (820), an LDPC decoding unit (830), a zero removal unit (840), and a desegmentation unit (850) to process variable length information. The rate dematching unit (820) may include an LLR (log likelihood ratio) insertion unit (822), an LLR combiner (823), a deinterleaver (824), and the like.

Here, the components illustrated in FIG. 8 are components that perform functions corresponding to the components illustrated in FIG. 8, and this is only an example, and some of them may be omitted or changed depending on the case, and other components may be added.

The parity check matrix in the present disclosure may be read using memory, may be provided in advance to a transmitting device or a receiving device, or may be directly generated by the transmitting device or the receiving device. In addition, the transmitting device may store or generate a sequence or an exponential matrix corresponding to the parity check matrix, or a value algebraically identical thereto, and apply the same to encoding. Similarly, the receiving device may store or generate a sequence or an exponential matrix corresponding to the parity check matrix, or a value algebraically identical thereto, and apply the same to decoding.

Below, a detailed description of the receiver operation is provided based on Fig. 8.

The demodulator (810) demodulates the signal received from the transmitter (700).

Specifically, the demodulator (810) is a component corresponding to the modulation unit (750) of the transmitter (700), and can demodulate a signal received from the transmitter (700) to generate values corresponding to bits transmitted from the transmitter (700).

To this end, the receiving device (800) determines parameters necessary for demodulation and decoding (e.g., at least one of input bit length, ModCod (modulation and code rate), parameters for zero padding (or shortening), code rate/codeword length of LDPC code, parameters for interleaving, parameters for repetition and puncturing, and modulation methods), and based on the determined parameters, the demodulation unit (810) can perform a decoding process of demodulating a signal received from the transmitting device (700) according to a mode to generate values corresponding to LDPC codeword bits.

Meanwhile, the value corresponding to the bits transmitted from the transmitting device (700) may be an LR (likelihood ratio) value or an LLR (log likelihood ratio) value.

Specifically, the LR value refers to the ratio of the probability that the bit transmitted from the transmitting device (700) is 0 and the probability that it is 1, and the LLR value can be expressed as the logarithm of the ratio of the probability that the bit transmitted from the transmitting device (700) is 0 and the probability that it is 1. Alternatively, the LR or LLR value can be expressed as the bit value itself by being determined based on the probability or the ratio of the probability or the Log value for the ratio of the probability, or can be expressed as a representative value defined in advance according to the section to which the probability or the ratio of the probability or the Log value for the ratio of the probability belongs. An example of a method for determining a representative value defined in advance according to the section to which the probability or the ratio of the probability or the Log value for the ratio of the probability belongs includes a method that considers quantization. In addition, various other values corresponding to the probability or the ratio of the probability or the Log value for the ratio of the probability may be used.

In the present disclosure, for convenience, an operation based on an LLR value is shown to explain the operation of the receiving method and device, but it is not necessary to be limited thereto.

The above-mentioned demodulator (810) includes a function for performing multiplexing (not shown) on LLR values. Specifically, the multiplexer (not shown) is a component corresponding to the bit demuxer (not shown) of the transmitter (700) and can perform an operation corresponding to the bit demuxer (not shown).

To this end, the receiving device (800) may store information about parameters that the transmitting device (700) used for demultiplexing and block interleaving. Accordingly, the multiplexer (not shown) may perform the demultiplexing and block interleaving operations performed in the bit demuxer (not shown) in reverse order for the LLR values corresponding to the cell words (information representing the received symbols for the LDPC codeword as vector values), thereby multiplexing the LLR values corresponding to the cell words on a bit-by-bit basis.

The rate dematching unit (820) can additionally insert LLR values into the LLR values output from the demodulation unit (810). In this case, the rate dematching unit (820) can insert pre-arranged LLR values between the LLR values output from the demodulation unit (810).

Specifically, the rate dematching unit (820) is a component corresponding to the rate matching unit (740) of the transmitting device (700), and can perform operations corresponding to the interleaver (741), zero removal, and puncturing/repetition/zero removal unit (742).

First, the rate dematching unit (820) performs deinterleaving to correspond to the interleaver (741) of the transmitter. The LLR insertion unit (822) can insert LLR values corresponding to zero bits into positions where zero bits were padded in the LDPC codeword in the output values of the deinterleaver (824). In this case, the LLR value corresponding to the padded zero bits, i.e., the shortened zero bits, can be ∞ or -∞. However, ∞ or -∞ is a theoretical value, and in practice, it can be the maximum or minimum value of the LLR value used in the receiving device (800).

To this end, the receiving device (800) may store information about the parameters that the transmitting device (700) used to pad zero bits. Accordingly, the rate dematching unit (820) may determine the position where zero bits were padded in the LDPC codeword and insert an LLR value corresponding to the shortened zero bits at that position.

In addition, the LLR insertion unit (822) of the rate dematching unit (820) can insert LLR values corresponding to the punctured bits into the positions of the punctured bits in the LDPC codeword. In this case, the LLR values corresponding to the punctured bits can be 0 or another predetermined value. In general, when parity bits with degree 1 are punctured, there is no effect on improving the performance of the LDPC decoding process, so they may not be used in the LDPC decoding process without inserting LLRs into some or all of the corresponding punctured positions. However, in order to increase the efficiency of the LDPC decoding process based on a parallel process, the LLR insertion unit (822) can insert a predetermined LLR value into positions corresponding to some or all of the punctured bits with degree 1, regardless of the improvement in decoding performance.

To this end, the receiving device (800) can store information on parameters used for puncturing in the transmitting device (700). Accordingly, the LLR insertion unit (822) can insert an LLR value (e.g., LLR = 0) corresponding to the punctured positions of the LDPC information word bits or parity bits. However, this process may be omitted for positions of some punctured parity bits.

The LLR combiner (823) can combine, i.e., add up, the LLR values output from the LLR insertion unit (822) and the demodulation unit (810). Specifically, the LLR combiner (823) is a component corresponding to the puncturing/repetition/zero removal unit (742) of the transmitter (700) and can perform an operation corresponding to the repetition unit (742). First, the LLR combiner (823) can combine the LLR values corresponding to the repeated bits with another LLR value. Here, the another LLR value may be an LLR value for the bits that formed the basis for generating the repeated bits in the transmitter (700), i.e., the LDPC information word bits or parity bits that were selected as repetition targets.

That is, as described above, the transmitting device (700) selects LDPC encoded bits, repeats them between LDPC information bits and LDPC parity bits, and transmits them to the receiving device (800). Accordingly, the LLR value for the LDPC encoded bits can be composed of an LLR value for the repeated LDPC encoded bits and an LLR value for the non-repeated LDPC encoded bits. The LLR combiner (823) can combine the LLR values for the same LDPC encoded bits.

To this end, the receiving device (800) can store information about parameters used for repetition in the transmitting device (700). Accordingly, the LLR combiner (823) can determine the LLR value for the repeated LDPC encoded bits and combine it with the LLR value for the LDPC encoded bits that formed the basis of the repetition.

Additionally, the LLR combiner (823) can combine the LLR value corresponding to the retransmitted or IR (increment redundancy) bits with another LLR value. Here, the other LLR value can be an LLR value for some or all of the LDPC codeword bits that formed the basis for generating the retransmitted or IR bits in the transmitting device (700).

As described above, when a NACK occurs for HARQ, the transmitting device (700) can transmit some or all of the codeword bits to the receiving device (800).

Accordingly, the LLR combiner (823) can combine the LLR values for bits received through retransmission or IR with the LLR values for LDPC codeword bits received through the previous frame.

To this end, the receiving device (800) can store information on parameters used by the transmitting device (700) to generate retransmission or IR bits. Accordingly, the LLR combiner (823) can determine an LLR value for the number of retransmission or IR bits and combine it with an LLR value for LDPC encoded bits that serve as the basis for generating retransmission bits.

The deinterleaver (824) can deinterleave the LLR value output from the LLR combiner (823).

Specifically, the deinterleaver unit (824) is a component corresponding to the interleaver (741) of the transmitting device (700) and can perform an operation corresponding to the interleaver (741).

To this end, the receiving device (800) may store information about the parameters that the transmitting device (700) used for interleaving. Accordingly, the deinterleaver (824) may reversely perform the interleaving operation performed by the interleaver (741) on the LLR values corresponding to the transmitted LDPC coded bits, thereby deinterleaving the LLR values corresponding to the transmitted LDPC coded bits.

The LDPC decoding unit (830) can perform LDPC decoding based on the LLR value output from the rate dematching unit (820).

Specifically, the LDPC decoding unit (830) is a component corresponding to the LDPC encoding unit (730) of the transmitting device (700) and can perform an operation corresponding to the LDPC encoding unit (730).

To this end, the receiving device (800) may store information about parameters used by the transmitting device (700) to perform LDPC encoding according to the mode. Accordingly, the LDPC decoding unit (830) may perform LDPC decoding based on the LLR value output from the rate dematching unit (820) according to the mode.

For example, the LDPC decoding unit (830) can perform LDPC decoding based on the LLR value output from the rate dematching unit (820) based on an iterative decoding method based on a sum-product algorithm, and output bits whose errors are corrected according to the LDPC decoding. The LDPC decoding unit (830) performs LDPC decoding on the LDPC codeword based on a parity check matrix or an exponential matrix or sequence corresponding thereto. In addition, LDPC decoding can be performed using a parity check matrix defined differently according to a code rate (i.e., a code rate of the LDPC code). The LDPC decoding unit (830) can generate information word bits by performing LDPC decoding by passing the LLR value corresponding to the LDPC codeword bits through an iterative decoding algorithm. Here, the LLR value is a channel value corresponding to the LDPC codeword bits, and can be expressed in various ways.

The zero removal unit (840) can remove zero bits from the bits output from the LDPC decoding unit (830).

Specifically, the zero removal unit (840) is a component corresponding to the zero padding unit (720) of the transmitting device (700) and can perform an operation corresponding to the zero padding unit (720).

To this end, the receiving device (800) may store information about the parameters used to pad zero bits in the transmitting device (700). Accordingly, the zero removal unit (840) may remove zero bits that were padded in the zero padding unit (720) from the bits output from the LDPC decoding unit (830).

The desegmentation unit (850) is a component corresponding to the segmentation unit (710) of the transmitting device (700) and can perform an operation corresponding to the segmentation unit (710).

To this end, the receiving device (800) may store information about the parameters that the transmitting device (700) used for segmentation. Accordingly, the desegmentation unit (850) can restore the bits before segmentation by combining the bits output from the zero removal unit (840), i.e., segments for variable-length input bits.

FIG. 9 shows a structural diagram of an LDPC decoding unit according to an embodiment of the present disclosure.

Meanwhile, as described above, the LDPC decoding unit (830) can perform LDPC decoding using an iterative decoding algorithm, and in this case, the LDPC decoding unit (830) can be configured with a structure as shown in FIG. 9. However, the detailed configuration illustrated in FIG. 9 is also just an example.

According to FIG. 9, the decryption device (900) includes an input processor (901), a memory (902), a variable node operator (904), a controller (906), a check node operator (908), and an output processor (910).

The input processor (901) stores the input value. Specifically, the input processor (901) can store the LLR value of the received signal received through the channel.

The controller (906) determines the number of values input to the variable node operator (904) and the address value in the memory (902), the number of values input to the check node operator (908) and the address value in the memory (902), etc. based on the block size (i.e., the length of the codeword) of the received signal received through the channel and the parity check matrix corresponding to the code rate.

The memory (902) stores input data and output data of the variable node operator (904) and the inspection node operator (908).

The variable node operator (904) receives data from the memory (902) based on the address information of the input data and the number information of the input data received from the controller (906) and performs a variable node operation. Thereafter, the variable node operator (904) stores the variable node operation results in the memory (902) based on the address information of the output data and the number information of the output data received from the controller (906). In addition, the variable node operator (904) inputs the variable node operation results to the output processor (910) based on the data received from the input processor (901) and the memory (902). Here, the variable node operation has been described above based on FIG. 6.

The inspection node operator (908) receives data from the memory (902) and performs inspection node operations based on the address information of the input data and the number information of the input data received from the controller (906). Thereafter, the inspection node operator (908) stores the inspection node operation results in the memory (902) based on the address information of the output data and the number information of the output data received from the controller (906). Here, the inspection node operation has been described above based on FIG. 6.

The output processor (910) makes a hard decision on whether the information word bits of the codeword of the transmitting side are 0 or 1 based on the data input from the variable node operator (904), and then outputs the hard decision result, and the output value of the output processor (910) becomes the final decrypted value. In this case, the hard decision can be made based on the sum of all message values input to one variable node in FIG. 6 (the initial message value and all message values input from the check node).

Meanwhile, the memory (902) of the decoding device (900) can store information on the code rate, codeword length, and parity check matrix of the LDPC code, and the LDPC decoding unit (830) can perform LDPC decoding using this information. However, this is only an example, and the relevant information may be provided from the transmitting side.

For reference, in this disclosure, the FEC (forward error correction) technique of a communication system is explained only with respect to LDPC codes, but in general, FEC encoding and decoding of a communication system can be subdivided into concatenated codes such as outer codes and inner codes. According to the definition of outer codes and inner codes, the transmitter performs inner encoding after outer encoding, and the receiver performs inner decoding after inner decoding.

In the case of external codes, algebraic codes that enable relatively simple error detection or correction, such as CRC (cyclic redundancy check) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, and Reed-Solomon (RS) codes, are often used, but they are not necessarily limited to these, and multiple codes can also be applied overlappingly.

For inner codes, relatively complex but excellent error correction capabilities encoding methods such as LDPC codes, Turbo codes, and Polar codes are widely used, but it is not necessarily limited to these. (For example, tail-biting convolutional codes or other algebraic codes can be used, and overlapping application of multiple codes is also possible.) For reference, in the 3GPP 5G system, CRC codes are used for outer codes, LDPC codes are used for inner codes for data channels, and Polar codes are used for inner codes for control channels.

Various broadcasting and communication systems use LDPC codes optimized for each system. In this disclosure, a system using an LDPC code defined based on a parity check matrix having the same structure as the LDPC code used in the 3GPP 5G system is described, but is not necessarily limited thereto. In addition, a communication system including a 5G or 6G system may apply rate matching at the transmitter and rate dematching at the receiver to support various code rates and various code lengths. However, in a system that performs encoding/decoding based on a fixed LDPC code, such as some broadcasting systems, not only rate matching or rate dematching but also all or part of other operations may be omitted.

FIG. 10 shows the general structure of a parity check matrix of an LDPC code, which is an internal code applied to an FEC encoding unit (not shown) and an FEC decoding unit (not shown) to be described in the present disclosure.

The number of columns of the parity check matrix illustrated in FIG. 10 is N, and the number of rows is (M ₁ + M ₂ ) (provided that M ₁ , M ₂ ≥ 0, M ₁ + M ₂ > 0). In general, when the parity check matrix has the full rank, the number of columns corresponding to the information word bits in the parity check matrix is equal to the total number of columns minus the total number of rows. That is, if the parity check matrix of FIG. 10 has the full rank (M ₁ + M ₂ ), the number of information word bits K becomes N - (M ₁ + M ₂ ). In the present disclosure, for convenience, only the case where the parity check matrix of FIG. 10 has the full rank is described, but the present invention is not necessarily limited thereto.

First, the parity-check matrix of FIG. 10 can be divided into a first part of the parity-check matrix composed of submatrices A (1010) and B (1020) and a second part of the parity-check matrix composed of submatrices C (1040), D (1050), and E (1060) (however, if either M ₁ or M ₂ is 0, the first part and the second part may not be divided). Submatrix O (1030) means a 0-matrix of the size (M ₁ × M ₂ ). Since the submatrix O (1030) is a 0-matrix of the size (M ₁ × M ₂ ), even if it is included in the first part of the parity-check matrix, it has no effect on the matrix operation. For this reason, in the present disclosure, for convenience, the first part of the parity check matrix is defined as a matrix composed of submatrices A(1010) and B(1020) excluding the 0-matrix of size (M ₁ × M ₂ ), but if necessary, the first part of the parity check matrix may also include the 0-matrix of size (M ₁ × M ₂ ).

If the parity check matrix of the above Fig. 10 is defined as a QC LDPC code with a lifting size or block size of Z, the parity check matrix of the above Fig. 10 and , ( , ) about can correspond to a basic matrix or weight matrix having a size of . Similarly, the first part of the parity check matrix consisting of submatrices A(1010) and B(1020) is or The second part of the parity check matrix, which corresponds to a submatrix of the fundamental matrix or weight matrix of size and consists of submatrixes C(1040), D(1050) and E(1060), or It corresponds to a submatrix of the fundamental matrix or weight matrix of size.

For convenience, the parity check matrix of the above figure 10 is called H, and the information word bits (or information word bit vector) corresponding to the submatrix A (1010) or C (1040) are and the first parity bits (or first parity bit vector) corresponding to the submatrix B(1020) or D(1050) and the second parity bits (or second parity bit vector) corresponding to the submatrix E(1060) Then, from mathematical expression 1, we can obtain a relationship such as mathematical expression 13.

[Equation 13]

Referring to the above mathematical expression 13, the first parity vector can be obtained (or calculated or determined) based on the information word bit vector i and the first part of the parity check matrix. Also, the parity vector After obtaining the information word bit vector , the above parity vector And the parity vector based on the second part of the parity check matrix can be obtained (or calculated or determined).

In this disclosure, information word bit vector Based on the first parity vector The first part of the parity check matrix consisting of A(1010) and B(1020) required to generate may be conveniently called a core part or matrix, a kernel part or matrix, or a precoding part or matrix. In addition, the information word bit vector and/or the first parity vector Based on the second parity vector The second part of the parity check matrix consisting of C(1040), D(1050) and E(1060) required to generate may be called an extension part or a single parity-check extension part.

As a concrete example, the basic matrix 1 defined in the 3GPP 5G standard described above and basic matrix 2 Each core matrix part is represented as follows.

Core matrix of:

0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23

0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24

0 1 2 4 5 6 7 8 9 10 13 14 15 17 18 19 20 24 25

0 1 3 4 6 7 8 10 11 12 13 14 16 17 18 20 21 22 25

Core matrix of:

0 1 2 3 6 9 10 11

0 3 4 5 6 7 8 9 11 12

0 1 3 4 8 10 12 13

1 2 4 5 6 7 8 9 10 13

The size of the core matrix is 4×26, The size of the core matrix is 4×14. In addition, the sizes of the core matrices based on the parity check matrix are 4Z×26Z and 4Z×14Z, respectively. As a specific example, a part of the index matrix of the LDPC code defined for the case where the lifting size set index iLS = 0 in the 3GPP 5G standard TS 38.212 is shown in FIGS. 11a and 11b. The part corresponding to the core matrix of the basic matrix or the parity check matrix in FIGS. 11a and 11b is as follows.

, Core matrix of:

250 69 226 159 100 10 59 229 110 191 9 195 23 190 35 239 31 1 0

2 239 117 124 71 222 104 173 220 102 109 132 142 155 255 28 0 0 0

106 111 185 63 117 93 229 177 95 39 142 225 225 245 205 251 117 0 0

121 89 84 20 150 131 243 136 86 246 219 211 240 76 244 144 12 1 0

, Core matrix of:

9 117 204 26 189 205 0 0

167 166 253 125 226 156 224 252 0 0

81 114 44 52 240 1 0 0

8 58 158 104 209 54 18 128 0 0

Meanwhile, in the present disclosure, a parity check matrix based on the following conditions may be considered for the parity check matrix corresponding to the above-described FIG. 10.

Hereinafter, submatrix A(1010) and submatrix B(1020) may be referred to as the first submatrix and the second submatrix, respectively. In addition, the cyclic permutation matrix below is determined based on the lifting size Z. It may mean a cyclic permutation matrix having a size of , and may be configured as in mathematical expression 5 or mathematical expression 6, for example. In addition, in the present disclosure, a cyclic matrix may mean a matrix in which cyclic permutation matrices are overlapped.

Condition 1(a) : In the parity check matrix for the QC-LDPC code of Fig. 10, the submatrix B(1020) is In the case where the circulant permutation matrices of the size do not include nested circulant matrices, the weights of all column blocks of the submatrix B(1020) are 2 or more, and at least one column block with an odd weight of 3 or more can be included in the submatrix B(1020). In addition, the basic matrix corresponding to the submatrix B(1020) All columns of the matrix have a weight of 2 or greater, and the columns with an odd weight of 3 or greater are the basic matrix. may contain at least one or more of:

Condition 1(b) : In the parity check matrix for the QC-LDPC code of Fig. 10, the submatrix B(1020) is If the circulant permutation matrices of the size include at least one nested circulant matrix, the weights of all column blocks of the submatrix B(1020) are 2 or greater, and at least one column block whose weight is an odd number of 3 or greater is included in the submatrix B(1020). In addition, the weight matrix corresponding to the submatrix B(1020) In the weight matrix, the sum of the elements of all columns is 2 or more, and the column whose sum of the elements of the column is an odd number of 3 or more At least one of the above is included. The weight of the column block containing the nested circulant matrices of circulant permutation matrices of size 2 may be 2 or 3 or more.)

Condition 2 : All column weights and row weights of the submatrix E(1060) of the above Fig. 10 are 1. In addition, the column weights and row weights of the submatrix of the basic matrix and the weight matrix corresponding to the above submatrix E(1060) are all 1. Therefore, E(1060) and the submatrix of the basic matrix and the weight matrix corresponding to E(1060) are identity matrices or matrices that are converted to identity matrices when appropriate column permutation or row permutation is applied. (That is, E(1060) is an identity matrix or a matrix having an equivalent algebraic property.) If the parity check matrix of the above Fig. 10 is defined as a quasi-cyclic parity check matrix, the submatrix E has multiple They can be classified into size identity matrices.

The above FIGS. 11a and 11b are examples of parity check matrices that satisfy at least one of Condition 1(a), Condition 1(b), or Condition 2. As briefly described above, FIG. 11a is an example of the case where K = 22*Z, M ₁ = 4*Z, and M ₂ = 2*Z in FIG. 10, and FIG. 11b is an example of the case where K = 10*Z, M ₁ = 4*Z, and M ₂ = 7*Z in FIG. 10. Note that since the code rate of the LDPC code corresponding to the parity check matrices of FIGS. 10, 11a, and 11b is K/N, a codeword with a lower code rate can be generated as M ₂ decreases. In other words, according to the present disclosure, LDPC encoding and decoding can be performed based on a parity check matrix that can support a lower code rate by further expanding columns of degree 1 while including the above-described FIGS. 11a and 11b.

If a set of lifting sizes is used for LDPC encoding or decoding for a parity check matrix of a quasi-cyclic LDPC code, the number of columns constituting one column block of the parity check matrix is greater than or equal to the minimum value of the lifting size. For example, if the values in Table 6 are used as the lifting sizes, the number of columns constituting one column block of the parity check matrix may be at least 4 or more. Therefore, in a communication system in which the lifting sizes in Table 6 are practically applied to a parity check matrix of an LDPC code having a structure as in FIGS. 10, 11a, and 11b that satisfies at least one of Condition 1(a), Condition 1(b), or Condition 2, this means that the number of columns with degree 3 in the submatrix B(1020) is at least 4 or more.

Note that the core matrix in the parity check matrix or base matrix or weight matrix can also be defined in a form that satisfies at least one of Condition 1(a), Condition 1(b), or Condition 2 by adding one or two more rows as follows.

Core matrix of:

0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23

0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24

0 1 2 4 5 6 7 8 9 10 13 14 15 17 18 19 20 24 25

0 1 3 4 6 7 8 10 11 12 13 14 16 17 18 20 21 22 25

0 1 26

Core matrix of:

0 1 2 3 6 9 10 11

0 3 4 5 6 7 8 9 11 12

0 1 3 4 8 10 12 13

1 2 4 5 6 7 8 9 10 13

0 1 11 14

However, in the present disclosure, for convenience, a parity check matrix [A(1010) B(1020)] including a partial matrix B that satisfies only Condition 1(a) or Condition 1(b) is regarded as a core matrix (or kernel matrix or precoding matrix). That is, in the present invention, the first part of the basic matrix or the first part of the parity check matrix or the core matrix/part or the kernel matrix/part, etc. means a partial matrix from which columns corresponding to parity bits of degree 1 and rows directly related to the parity bits of degree 1 are excluded.

As an embodiment of the present disclosure, a method for improving the performance of an LDPC code according to a weight matrix and a method for improving the decoding convergence speed are described.

First, the basic matrix 2 defined in [How to determine the basic matrix] The core matrix consists of four rows, which can also be expressed as a weight matrix as in Equation 14. Basic matrix 1 or base matrix 2 An LDPC code defined by is one Since we define that one cyclic permutation matrix corresponds to a size block, the base matrix and the weight matrix are basically the same.

[Equation 14]

In this way, one An LDPC code, which is designed so that at most one cyclic permutation matrix corresponds to a block of size, is a structure suitable for performing layered decoding in units of one row block during decoding. In other words, the structure of the LDPC code is a structure suitable for performing decoding through a Z-unit parallel processing processor. Layered decoding refers to an operation of sequentially performing decoding for each layer. Therefore, decoding may be performed sequentially in units of one row block, or decoding may be performed layer by layer by configuring multiple row blocks as one layer. Meanwhile, although layered decoding in the present disclosure is defined as an operation of sequentially performing decoding for each layer, performing decoding sequentially only means performing decoding for each layer, and does not mean that decoding must be performed in the order of the layer indexes. In addition, performing decoding sequentially in the present disclosure may mean performing decoding sequentially according to a layered decoding order or pattern (or sequence). Additionally, depending on the structure of a parity check matrix, some layers may be composed of one row block and other layers may be composed of multiple row blocks.

This layered decoding method typically performs parallel processing on a basic unit of a single row block or a layer composed of multiple row blocks, so one iteration of decoding can be considered complete when decoding is performed for the total number of row blocks. This means that if there are enough parallel processing processors, the decoding throughput through layered decoding is inversely proportional to the number of row blocks. However, if the same code length is supported using a parity check matrix with a small number of row blocks, the lifting size Z value increases further, so the amount of parallel processing processors required to simultaneously decode one row block increases.

For example, the above weight matrix It consists of 4 rows and 14 columns, and the weights of each column are 3, 3, 2, 3, 3, 2, 3, 3, 3, 3, 2, 2, 2. If it consists of 3 rows and 13 columns, and the weight distribution is similar to the weight matrix It consists of 2 rows and 12 columns. and the weight distribution is similar to the weight matrix It can be structured as follows:

If each weight matrix , , LDPC codes with the same code length can be generated using , and the lifting size corresponding to each parity check matrix can be , , If so, , There is a relationship between . Also, in the LDPC decoder, each If the number of parallel processing processors allowed, the approximate throughput of decryption information is Is 1.5 times of Is It can be twice as much.

In this way, when sufficient parallel processing processors are available, reducing the number of row blocks can increase the decryption information processing capacity inversely. Therefore, for systems requiring extremely high decryption information processing capacity, if more parallel processing processors are available, it is advantageous to keep the number of rows in the base or weight matrix, or in other words, the number of row blocks in the parity check matrix, small.

While keeping the number of rows in the base matrix or weight matrix, or in other words, the number of row blocks in the parity check matrix, small may be beneficial from the perspective of decoding information processing capacity, setting the number of row blocks too small can severely limit the algebraic properties of the LDPC code, such as its cycle characteristics or minimum distance characteristics, and can result in performance degradation. Therefore, the base matrix or weight matrix must be determined by simultaneously considering the system's target information processing capacity and target error correction capability.

As an embodiment of the present disclosure, a method for improving code performance while achieving high decoding throughput is proposed. In particular, the present disclosure proposes algebraic properties that a core matrix portion of a basic matrix or a weight matrix, which is closely related to the maximum decoding throughput or peak data rate of a system, must satisfy. Of course, if the parity check matrix does not include a second part of the parity check matrix composed of submatrices C (1040), D (1050), and E (1060) of FIG. 10, the core matrix may be identical to the basic matrix or the weight matrix.

One of the conditions that the core matrix of the parity check matrix must satisfy is that when two columns with only one non-zero element are selected from the weight matrix corresponding to the core matrix, ( ) should not contain non-zero elements in only one row. As a simple example, , , , , …, etc. are applicable. The minimum distance of the parity check matrix corresponding to the weight matrix or the core matrix including this structure is Since it is below, there is a high possibility that the error floor phenomenon will easily occur. Therefore, , , , …, in any two columns with only one non-zero element, the non-zero elements must be located in different rows. This means that for the elementary matrix, all non-zero elements located in columns with weight 1 are located in different rows. The above can be defined as conditions 3(a) and 3(b) below.

Condition 3(a) : All columns of the basic matrix or weight matrix corresponding to the core matrix have weights greater than or equal to 2, or the number of columns with weight 1 is at most 1.

Condition 3(b) : If there are two or more columns with weight 1 among the columns of the basic matrix or weight matrix corresponding to the core matrix, the non-zero elements included in the columns with weight 1 are located in different rows.

The above conditions 3(a) and 3(b) are satisfied when the number of column blocks consisting of only one circulating permutation matrix or circulating matrix included in the core matrix is at most 1, or when the core matrix includes two or more circulating permutation matrixes or circulating matrix-only column blocks. It means that the size cyclic permutation matrix or cyclic matrices are necessarily included in different row blocks. In addition, the above conditions 3(a) and (3b) are structures to prevent serious error floor phenomenon, but if an even better error floor characteristic is to be obtained, the following condition 4 may be additionally added. As described above, the above cyclic permutation matrix and cyclic matrix It can have any size.

Condition 4 : The weight of the column corresponding to the information bit (or input bit or code block) in the parity check matrix corresponding to the core matrix is 3 or greater.

The above condition 4 is the basic matrix 2 of mathematical expression 14. The encoding gain may be reduced by ensuring that the weight of the column corresponding to the information bit is not 2, as in the corresponding parity check matrix, but it can be applied when trying to improve the error floor phenomenon.

The above condition 4 is that the submatrix A(1010) in the parity check matrix for the QC-LDPC code If the circulant permutation matrices of the size do not contain nested circulant matrices, the weight of all column blocks of the submatrix A(1010) is 3 or more, and the fundamental matrix corresponding to the submatrix A(1010) It means that the weight of all columns is 3 or more. Also, in the parity check matrix for QC-LDPC code, the submatrix A(1010) If the circulant permutation matrices of the size include at least one nested circulant matrix, the weight of all column blocks of the submatrix A(1010) is 3 or more, and the weight matrix corresponding to the submatrix A(1010) It means that the sum of all the elements of the column is 3 or more.

Another condition that the core matrix of the parity check matrix must satisfy is that the weight matrix corresponding to the core matrix does not contain an element greater than or equal to 3. In general, if the core matrix of the weight matrix contains an element greater than or equal to 3, it means that three or more cyclic permutation matrices correspond to the corresponding position. If there are three or more circulant permutation matrices that constitute a circulant matrix of size that overlap, Regardless of the value, the maximum length of the cycle is limited to 6. Since the performance improvement effect by iterative decoding is reduced when the cycle length is short, it is appropriate to use a parity check matrix corresponding to a weight matrix or core matrix that includes values of 3 or more as elements when the code length is short or the code rate is relatively high. Since this disclosure deals with a design method of an LDPC code that supports various code rates and various code lengths, the core matrix of the weight matrix does not include elements of 3 or more. (Of course, it may be included in the part corresponding to the single parity check extension part.) The above contents can be defined as the following condition 5.

Condition 5 : The weight matrix corresponding to the core matrix consists of only 0 and 1, or only 0, 1, and 2.

Another condition that the core matrix must satisfy is the first parity vector The submatrix B(1020) of Fig. 10 corresponding to must have a maximum rank to enable efficient encoding, and the following restrictive structure is desirable to prevent serious degradation of cycle characteristics.

Condition 6(a) : If the weight matrix corresponding to the core matrix consists of four rows, the submatrix corresponding to B(1020) in the weight matrix and the fundamental matrix is one of the following:

Condition 6(b) : If the weight matrix corresponding to the core matrix consists of three rows, the submatrix of the basic matrix corresponding to the submatrix B(1020) is , and the weight matrix is one of:

Condition 6(c) : If the weight matrix corresponding to the core matrix consists of two rows, the submatrix of the basic matrix corresponding to the submatrix B(1020) is , and the weight matrix is one of: , .

For reference, the above condition 6(a) shows the case where the weight matrix and the base matrix are the same, and condition 6(b) shows the case where the weight matrix is It has the same form as the fundamental matrix only if 0 is in the fundamental matrix or weight matrix shown in Conditions 6(a), 6(b), and 6(c). It means 0-matrix of size 1, identity matrix of size or cyclic permutation matrix (v > 0). Also, 2 is Circular matrix of size It means ( ).

In general, an upper bound on the cycle length can be predicted from the base matrix or weight matrix, but the cycle characteristics of the parity check matrix corresponding to the base matrix or weight matrix are unknown. For example, if the submatrix B(1020) or In each case, regardless of the values of v1 and v2, the base matrix or weight matrix is or Although they are the same, their cycle characteristics are very different. If at least one of v1 or v2 is 0, or (or ) will generate a large number of 4-cycles, so basically v1, v2 , (or ) is set to an integer satisfying . Similarly In the case where v1 = 0, a large number of 4-cycles are generated, so basically v1 is An integer satisfying v2 is is set to an integer satisfying . The above is only a method to remove 4-cycles, and the values of v1 and v2 can be limited in various ways to obtain longer cycles.

If the communication system applies the perforation of the information bits described in [Table 9], the following conditions that the core matrix must satisfy may be added.

Condition 7 : In an LDPC encoding system where puncturing of information word bits is applied, a submatrix of a core matrix composed only of columns corresponding to the punctured information word bits has at least one row with a row weight of 1.

Since the bits punctured at the receiver are regarded as bits lost during the reception process, the probability that the punctured bit is 0 and the probability that the punctured bit is 1 are determined to be the same. This usually means 1 when decoding is performed using the LR value, and 0 when decoding is performed using the LLR value, but it can be determined in another form based on the values used in the decoding process. When LDPC decoding is performed based on a parity check matrix that does not satisfy Condition 7, the punctured information bits may not be decoded unless ML (maximum likelihood) decoding or pseudo ML decoding is used. Since ML or pseudo ML decoding is not commonly used due to its complexity, the parity check matrix can be determined to satisfy Condition 7 to ensure decoding success.

If the LDPC code is a QC-LDPC code, the parity check matrix can be expressed based on the lifting size Z value and the basic matrix and/or weight matrix and/or exponent matrix, etc., and thus can be expressed as in the following condition 8.

Condition 8 : In a QC-LDPC encoding system in which puncturing of information bits is applied in units of a lifting size Z or its multiples, a submatrix of a basic matrix composed of only a columns corresponding to a submatrix of a core matrix composed of only a*Z columns corresponding to the punctured a*Z (a: integer greater than or equal to 1) information bits has at least one row with weight 1. In addition, a submatrix of a weight matrix composed of only a columns corresponding to a submatrix of a core matrix composed of only a*Z columns has at least one row with weight 1 and an element 1.

For example, in a QC-LDPC encoding system where puncturing of the information bits of 2Z bits is always applied, condition 8 implies that a = 2.

Meanwhile, in the present disclosure, at least one of the above conditions may be used to construct a parity check matrix. That is, the parity check matrix may be determined to satisfy one of the above conditions or a combination of at least two of the above conditions.

As an embodiment of the present disclosure, a method for improving the error floor performance of an LDPC code is proposed. In general, the error floor phenomenon of an LDPC code is greatly affected by the cycle characteristics of the Tanner graph. However, since the cycle characteristics of a QC LDPC code on the Tanner graph are determined by the relationship between the base matrix and the indices or cyclic shift values of the cyclic permutation matrix, not only the positions of the cyclic permutation matrix constituting the parity check matrix but also the cyclic shift values must be appropriately selected.

In the present disclosure, first parity bits (or first parity bit vector) in the first part of the parity check matrix composed of sub-matrices A (1010) and B (1020) in FIG. 10 We propose an algebraic property that the submatrix B(1020) corresponding to must satisfy.

The size of the above submatrix B(1020) is (or ), and the submatrix B(1020) is (or ) corresponds to the basic matrix or weight matrix of the size. In addition, the first column block of the submatrix B(1020) is composed of three cyclic permutation matrices. At this time, the cyclic permutation matrix may include an identity matrix. That is, in the present disclosure, the cyclic permutation matrix is defined as a matrix in which each element of the identity matrix is cyclically shifted by i, and when the value of i is 0, the cyclic permutation matrix may be an identity matrix. This can be applied throughout the detailed description of the present disclosure. In addition, the remaining column blocks of the submatrix B(1020) are composed of two cyclic permutation matrices or identity matrices. In the present invention, for convenience, the remaining column blocks are expressed only when the identity matrix is composed of a double diagonal structure, but in general, it is not necessary to be limited thereto.

A specific example of the partial matrix B(1020) is shown in Mathematical Expression 15. The partial matrix B(1020) can be determined based on at least one of the matrices included in Mathematical Expression 15 below. However, the embodiment of the present disclosure is not limited thereto, and various matrices satisfying the above characteristics (the first column block is composed of three cyclic permutation matrices, and the remaining column blocks are composed of two cyclic permutation matrices or an identity matrix) can be considered.

[Equation 15]

In the above mathematical formula 15 , , , The first column block contains three different cyclic permutation matrices , , It consists of . Also, in mathematical expression 15, for convenience, Although only the cases where the values are 3, 4, 5, and 6 are shown, a submatrix B(1020) can be similarly defined for integers greater than those. Furthermore, matrices that can be transformed into a submatrix B(1020) of the above form through an appropriate invertible transform process can be considered as algebraically identical matrices.

In the present disclosure, the mathematical expression 15 above , , , In addition, we propose a method for improving the cycle characteristics for a larger submatrix B(1020) of a similar form. For convenience, details on the method for analyzing the cycle characteristics of the QCLDPC code and some of its algebraic properties are omitted in this disclosure, but reference is made to the reference [Myung2005].

[Myung2005]

S. Myung, K. Yang, and J. Kim, “Quasi-Cyclic LDPC Codes for Fast Encoding,” IEEE Transactions on Information Theory, vol. 51, No. 8, pp. 2894-2901, Aug. 2005.

If, as in Equation 15, the submatrix B(1020) has a dual diagonal structure with the size of the remaining column blocks excluding the first column block, which is composed of identity matrices, the indices (or cyclic shift values) of the cyclic permutation matrix of the first column block were used for encoding convenience. , , At least two values among them were set to the same value. In this case, the values used in the encoding process are Size of matrix identity matrix or a simple cyclic permutation matrix It becomes, Inverse matrix of is the identity matrix or It is simplified together, so the encoding process becomes simpler. (For detailed encoding process of QC LDPC code, refer to [Myung2005]) As a specific example, If set to Is and become Is Therefore, efficient encoding can be performed. Similarly, If set to Is and become Is Therefore, efficient encoding can be performed.

however In this case, the length on the Tanner graph is according to the structure shown in the following mathematical expression 16. In cycle The dog is always present. In other words, if If the value of is fixed, the lifting size and index Regardless of the value, the length There is always a cycle in the QC LDPC code. (For detailed information on the cycle characteristics of QC LDPC codes, see [Myung2005].)

[Equation 16]

Not only that In this case, due to the structure as in the following mathematical expression 17, the lifting size and index Regardless of the value There are always shorter cycles than that.

[Equation 17]

should When the value is appropriately large, the cycle characteristics of the Tanner graph corresponding to structures such as Equations 16 and 17 may not have a significant impact on the performance of the LDPC code. However, When the value is relatively small, the BLER may increase due to the error floor phenomenon, which becomes a non-negligible problem as the target BLER of the system is lower.

In order to solve this problem, in the present invention, the indices (or cyclic shift values) of the cyclic permutation matrices constituting the first column block of the submatrix B(1020) having the structure as in mathematical expression 15 , , We propose a method to improve cycle characteristics by limiting the satisfies certain algebraic conditions. In addition, the method improves cycle characteristics while also providing the necessary parameters in the LDPC encoding process. It explains that the computational complexity associated with matrices increases to a reasonable level.

If the lifting size for the parity check matrix of the QC LDPC code cast , ( is odd, When is an integer greater than or equal to 0, the indices (or circular shift values) of the cyclic permutation matrices that constitute the first column block of the submatrix B(1020) , , are distinct integers, satisfying at least some or all of the following conditions:

Index condition 1a : At least one of the differences between two indices (circular shift values) is a lifting magnitude. The greatest common divisor with is 1 or greater than 1 is the smallest number among the divisors of (i.e., and are mutually prime or greater than 1 ) has the least divisor as the greatest common divisor.

Index condition 1b : Two of the differences between the two indices are the lifting magnitudes. The common divisor with is 1 or greater than 1 It is the smallest number among the divisors of .

Index condition 2a : At least one of the differences between the two indices is ( )am.

Index condition 2b : At least one of the differences between the two indices is is 1 In this case ( ) and is an odd number greater than or equal to 3 In this case ( )am.

For reference, the difference between the exponents used in the above exponent conditions is , , It means back.

According to the above index condition 1a, the difference between the two indices is If and are relatively prime, the length of the cycle determined by the cyclic permutation matrix associated with the two indices is maximized. For example, The value of In case of coprime, mathematical expression 17 The length of a cycle on a Tanner graph is determined by becomes. If and The greatest common divisor of The ramen cycle length is becomes. As a result As the value increases, the length of the cycle also increases.

As another example, The value of In the case where and are relatively prime, the cycle length determined by the structure of mathematical expression 16 is becomes. If and The greatest common divisor of The ramen cycle length is As a result, it can be seen that the cycle length is not fixed regardless of the Z value, but rather increases as the Z value increases. Considering only the cycle characteristics, the difference between the exponents is Although it is desirable that they are relatively prime, depending on the situation, the exponents may be chosen so that the greatest common divisor D is small (for example, to be the smallest divisor of Z greater than 1) by other conditions. For example, if the difference between the exponents cannot satisfy the property of being relatively prime to Z, the greatest common divisor It is desirable to select an exponent that makes the value smaller.

The above index condition 1b is a condition for further improving cycle characteristics by restricting the index condition more than index condition 1a. For example, and The value And in case they are mutually prime Not only are the cycle characteristics related to the indices a and b unique, but Likewise, the cycle characteristics related to the indices b and c are also improved. (The same holds true for other forms of submatrix B extended based on Equation 15 and Equation 15.)

Another form of submatrix B based on equation 15 and equation 15 is , , When all are different, the encoding process requires The matrix is defined as follows. The matrix is It is not easy to obtain, The density of weights of a matrix also often has a high density characteristic rather than a low density characteristic. That is, it has a low density characteristic. The matrix It has the characteristic that it does not guarantee the low density characteristic of the matrix. Because the high density nature of the matrix increases the encoding complexity, It is desirable that the density of the matrix be as low as possible, It is desirable for matrices to have a simple structure.

The above index conditions 2a and 2b are for efficient LDPC encoding. It is a condition to simplify the matrix as much as possible. For example, in the above index condition 2a, In that case

Become This is it. Here silver

since can be determined relatively simply, but As the value increases It can be seen that the computational complexity increases. Therefore, depending on the complexity that is acceptable in the system, The values can be used by appropriately limiting them. Typically, The value is It is recommended to use a range, but larger values may be used depending on the system's allowable range.

For reference, the length is An arbitrary bit string About Circular permutation matrix of size Multiplying operation is a bit string operation rather than an actual matrix multiplication operation. About It is equivalent to performing a circular shift by a bit. In other words, the above operation means an operation or action with very low complexity, as it can be implemented as a bit shift operation rather than a matrix multiplication. In addition, Even in the process of calculating Rather than expanding and calculating each term, Computational complexity can be minimized through step-by-step calculations, as in the following example:

In the above index condition 2a me In the same way, if Encoding can be performed by determining the difference between all two indices. However, In the case of the form, the cycle characteristics are likely to be poor. Therefore, for efficient encoding and good cycle characteristics, at least one of the differences between the two indices should be ( ) and the remaining exponent differences can be considered to satisfy the exponent condition 1a or exponent condition 1b. In addition, the difference between the two exponents The above indices can be selected if at least one of the index conditions 1a or 1b is satisfied.

Index condition 2b is a condition for further improving cycle characteristics while enabling efficient encoding by restricting the index condition more than index condition 2a. When index condition 2b is satisfied, encoding complexity increases somewhat compared to the existing 5G LDPC code, but it has the advantage of improving cycle characteristics. Of course, if there is no case where index condition 2b is satisfied, the indices can be determined by considering index condition 2a. For reference, in index condition 2a, The difference between the two indices is , except that And you can always see that they are not the same. That is, And the difference between the two exponents has a common divisor greater than 1. Satisfying That there is This means that the index condition 2b must be satisfied. By condition And the difference between the two exponents is not prime, has as its common divisor.

As an embodiment of the present disclosure, a more specific example of constructing a submatrix B(1020) of FIG. 10 using the above exponential conditions is described.

First, consider a communication system or broadcasting system, such as 5G, where a set of lifting sizes is defined, as shown in Tables 3 through 8, and only lifting sizes included in the set can be applied. Furthermore, a separate parity check matrix or index matrix can be defined for each lifting size set. That is, in the cases of Tables 3 through 8, a parity check matrix or index matrix can be defined for each of the eight set indices.

In Equation 15 and another form of submatrix B extended based on Equation 15, , , Let us decide as follows. In general, to ( ) index for the submatrix B of the corresponding parity check matrix , , For convenience, since the values may all be different , , It was expressed as .

Example 1 of selecting an index ( )

- is an arbitrary integer

- Is and here Is is an integer satisfying , that is, among the indices corresponding to the submatrix B, , Is is an integer satisfying . Here, Is , It means the greatest common divisor of Is It means any lifting size that belongs to the set of lifting sizes corresponding to .

- Is and here Is The largest lifting size among the lifting size values belonging to the corresponding lifting size set It is one of the smaller lifting sizes.

If we calculate the difference between each index for the submatrix B determined through the above index selection example 1, an arbitrary lifting size About Therefore, it satisfies the index condition 1a, at Is One of the values, each of which Since the values are multiples of each other ( drainage relationship), According to the definition of This is established and the index condition 1b is also satisfied. However, Therefore, the index condition 2a and the index condition 2b are the lifting size Satisfaction varies depending on the situation. For example, In this case, the index condition 2a and the index condition 2b are always satisfied, but In this case is established Circular permutation matrix of size and Since they are virtually the same, they may not satisfy the exponent conditions 2a and 2b. In other words, In this case, the structure is as in mathematical expression 16, which means that the cycle characteristics are not improved. In conclusion, in order to improve the cycle characteristics for lifting sizes of various lengths, It is desirable that the value be determined as small as possible.

However, the lifting size for LDPC encoding The value If it is relatively large compared to the value (i.e., at (if the value is large) It is highly likely that the encoding complexity will increase significantly due to matrix-related operations. Therefore, The value can be selected by considering the cycle characteristics and encoding complexity. If only the cycle characteristics improvement is considered, The smallest lifting size among the lifting size values belonging to the corresponding lifting size set can be selected. Also, when considering the limited increase in encoding complexity, Among the lifting size values belonging to the corresponding lifting size set, a lifting size that is greater than the smallest lifting size and smaller than the largest lifting size can be selected. Typically, the lifting sizes included in the lifting size set are , , … , When ( ), The value is ( ) can be set. Generally, , , … , If the values are not consecutive integers, The value is , , … may be selected as an integer other than the above embodiment. In addition to the above embodiment, for other embodiments as well As previously explained, it can be selected based on various conditions, but detailed explanation may be omitted for convenience of explanation.

For convenience, as a concrete example of the index selection method, , in other words, An example of index selection when set to is shown below.

Example 2 of selecting an index ( )

-

- ( If set to , , )

- Is (or ) and here Is The largest lifting size among the lifting size values belonging to the corresponding lifting size set It is one of the smaller lifting sizes.

If we calculate the difference between each index for the submatrix B determined through the above index selection example 2, This is an arbitrary lifting size Always about This is established, Become this Since this holds, index condition 1a and index condition 1b can be satisfied. As in the above index selection example 2. In this case as well as in general ) that satisfies For this, index conditions 1a and 1b can be satisfied. That is, In Jeong-su About, , , , the submatrix B set as satisfies the index condition 1a and the index condition 1b. In addition, Therefore, the index condition 2a and the index condition 2b are the lifting size Satisfaction varies depending on the situation. (or ) can be selected based on various conditions, taking into account cycle characteristic improvement and encoding complexity, as explained above.

A specific example related to index selection example 2 is described below.

Given a set of lifting sizes as in Table 8, a specific example of the submatrix B is given in the following mathematical expression 18. Mathematical expression 18 is An example of a submatrix B in the parity check matrix for is shown. (Matrix of Equation 15) Here is an example of setting the submatrix B. The submatrix B can be determined based on at least one of the matrices included in the following mathematical expression 18. However, the embodiments of the present disclosure are not limited thereto. That is, the following embodiment is an example of a case where 32 is selected among the lifting sizes, but any one of the lifting sizes included in Table 8 above can be selected. Accordingly, various matrices can be considered based on c determined according to the lifting size.

[Equation 18]

- , , (Choose 32 from lifting sizes)

In the case of mathematical expression 18, the lifting size in the 0th lifting size set If the value is selected as 32 or less, such as 8, 16, or 32, From This has become a reality matrix identity matrix Become Also the identity matrix Since the encoding process becomes simpler, there is a disadvantage that the cycle characteristic is not improved. If the cycle characteristic is improved while considering the limited increase in encoding complexity, in the submatrix having the structure of the above mathematical expression 18, The corresponding exponent pair The following combinations may be possible:

[Table 10]

The above Table 10 is only an example, and is generally one of the lifting size values smaller than Zmax. By selecting can be decided by

As one embodiment of the present disclosure, the above The value may be determined based on the largest lifting size among the lifting sizes smaller than a specific reference value. Specifically, if the reference value is set to 96, in a system using lifting size sets such as [Table 3] to [Table 8], the numbers less than or equal to 96 in each lifting size set are 64, 96, 80, 56, 72, 88, 52, and 60 in that order. Therefore, in each lifting size set, based on the given reference value, the parity check matrix corresponding to the index of each lifting size set is defined. If the value is determined, the above The values can be defined as 65, 97, 81, 57, 73, 89, 53, 61 in order according to each lifting size set index. If the reference value is set to 48, the above method can be used in the same way. The values can be defined as 33, 49, 41, 29, 37, 45, 27, 31 in order according to each lifting size set index. For reference, in case of using a lifting size set excluding the numbers in () in [Table 3] or [Table 8], if the i-th largest lifting size among the lifting sizes included in the lifting size set with iLS = 1 is determined as the reference value, the corresponding parity check matrix defined according to each lifting size set index The value has the characteristic that it is determined as an integer that adds 1 to the ith largest lifting size in each set.

In addition, for the uniformity of the encoding method, the ith largest lifting size in each lifting size set may be selected (i = 2, 3, 4, …). For example, in a system using the lifting size sets as in [Table 3], the fifth largest numbers in each lifting size set are 16, 24, 20, 14, 18, 22, 13, 15. Therefore, based on the fifth largest number in each lifting size set, the corresponding parity check matrix defined according to each lifting size set index is If the value is determined (i=5), the above The values can be defined as 17, 25, 21, 15, 19, 23, 14, 16 in order according to each lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the fourth largest number in each lifting size set. If the value is determined (i=4), The values can be defined as 33, 49, 41, 29, 37, 45, 27, 31 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the third largest number in each lifting size set. If the value is determined (i=3), The values can be defined as 65, 97, 81, 57, 73, 89, 53, 61 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the second largest number in each lifting size set. If the value is determined (i=2), The values can be defined as 129, 193, 161, 113, 145, 177, 105, 121 in order of lifting size set index.

In a system that uses the lifting size sets of values excluding the values in () in [Table 8], the fifth largest numbers in each lifting size set are 32, 48, 40, 28, 36, 44, 26, and 30. Therefore, based on the fifth largest number in each lifting size set, the corresponding parity check matrix defined according to each lifting size set index is If the value is determined (i=5), the above The values can be defined as 33, 49, 41, 29, 37, 45, 27, 31 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the fourth largest number in each lifting size set. If the value is determined (i=4), The values can be defined as 65, 97, 81, 57, 73, 89, 53, 61 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the third largest number in each lifting size set. If the value is determined (i=3), The values can be defined as 129, 193, 161, 113, 145, 177, 105, 121 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the second largest number in each lifting size set. If the value is determined (i=2), The values can be defined as 257, 385, 321, 225, 289, 353, 209, 241 in order of the lifting size set index.

Also, as shown in the above mathematical formula 18 and the above table 10 and the corresponding examples, According to the pair, The matrix This is done, and the lifting size is determined according to the above index selection example 2. The value If less than or equal to This was established and eventually Therefore, the cycle characteristics are not improved, This establishment allows efficient LDPC encoding. Lifting size The value In larger cases Satisfying exists ( ) This becomes, and therefore By using the human nature, efficient LDPC encoding is possible, although the encoding complexity increases. Here, and The cycle length determined by the existing at It increases to . and or and The cycle length determined by satisfies exponential condition 1a and exponential condition 1b. It increases significantly in proportion to the value.

For convenience, as a concrete example of the index selection method, , in other words, An example of index selection when set to is shown below.

Example 3 of selecting an index ( )

-

- ( If set to , , )

- Is (or ) and here Is The largest lifting size among the lifting size values belonging to the corresponding lifting size set It is one of the smaller lifting sizes.

If we calculate the difference between each index for the submatrix B determined through the above index selection example 3, This is an arbitrary lifting size Always about This is established, Become this Since this holds, index condition 1a and index condition 1b can be satisfied. As in the above index selection example 3. In this case as well as in general ) that satisfies For this, index conditions 1a and 1b can be satisfied. That is, In Jeong-su About, , , , the submatrix B set as satisfies the index condition 1a and the index condition 1b. In addition, Therefore, the index condition 2a and the index condition 2b are the lifting size Satisfaction varies depending on the situation. (or ) can be selected based on various conditions, taking into account cycle characteristic improvement and encoding complexity, as explained above.

Specific examples related to index selection example 3 are described below.

Given a set of lifting sizes as in Table 8, a specific example of the submatrix B is given in Equation 19 below. Equation 19 is given in Table 8. An example of a submatrix B in the parity check matrix for is shown. (Matrix of Equation 15) Here is an example of setting the submatrix B. The submatrix B can be determined based on at least one of the matrices included in the following mathematical expression 19. However, the embodiments of the present disclosure are not limited thereto. That is, the following embodiment is an example of a case where 32 is selected among the lifting sizes, but any one of the lifting sizes included in Table 8 above can be selected. Accordingly, various matrices can be considered based on c determined according to the lifting size.

[Equation 19]

- , , (Choose 32 from lifting sizes)

In the case of mathematical expression 19, the lifting size in the 0th lifting size set If the value is selected as 32 or less, such as 8, 16, or 32, From This has become a reality The matrix is a cyclic permutation matrix Become is a cyclic permutation matrix Since the encoding process becomes simpler, there is a disadvantage that the cycle characteristic is not improved. If the cycle characteristic is improved while considering the limited increase in encoding complexity, in the submatrix having the structure of the above mathematical expression 18, The corresponding exponent pair The following combinations may be possible:

[Table 11]

The above Table 11 is only an example, and is generally one of the lifting size values smaller than Zmax. By selecting can be decided by

As one embodiment of the present disclosure, the above The value may be determined based on the largest lifting size among the lifting sizes smaller than a specific reference value. Specifically, if the reference value is set to 96, in a system using lifting size sets such as [Table 3] to [Table 8], the numbers less than or equal to 96 in each lifting size set are 64, 96, 80, 56, 72, 88, 52, and 60 in that order. Therefore, in each lifting size set, based on the given reference value, the parity check matrix corresponding to the index of each lifting size set is defined. If the value is determined, the above The values can be defined as 64, 96, 80, 56, 72, 88, 52, 60 in order according to each lifting size set index. If the reference value is set to 48, the above can be defined in the same way. The values can be defined as 32, 48, 40, 28, 36, 44, 26, 30 in order according to each lifting size set index. In case of using a lifting size set excluding the numbers in () in [Table 3] or [Table 8], if the i-th largest lifting size among the lifting sizes included in the lifting size set with iLS = 1 is determined as the reference value, the corresponding parity check matrix defined according to each lifting size set index The value has the characteristic that it is determined by the i-th largest lifting size in each set.

In addition, for the uniformity of the encoding method, the ith largest lifting size in each lifting size set may be selected (i = 2, 3, 4, 5, 6, …). For example, in a system using lifting size sets as in [Table 3], the fifth largest numbers in each lifting size set are 16, 24, 20, 14, 18, 22, 13, 15. Therefore, the parity check matrix corresponding to each lifting size set index is defined based on the fifth largest number in each lifting size set. If the value is determined (i=5), The values can be defined as 16, 24, 20, 14, 18, 22, 13, 15 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the fourth largest number in each lifting size set. If the value is determined (i=4), The values can be defined as 32, 48, 40, 28, 36, 44, 26, 30 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the third largest number in each lifting size set. If the value is determined (i=3), The values can be defined as 64, 96, 80, 56, 72, 88, 52, 60 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the second largest number in each lifting size set. If the value is determined (i=2), The values can be defined as 128, 192, 160, 112, 144, 176, 104, 120 in order of the lifting size set index.

In a system that uses the lifting size sets of values excluding the values in () in [Table 8], the fifth largest numbers in each lifting size set are 32, 48, 40, 28, 36, 44, 26, and 30. Therefore, based on the fifth largest number in each lifting size set, the corresponding parity check matrix defined according to each lifting size set index is If the value is determined (i=5), the above The values can be defined as 32, 48, 40, 28, 36, 44, 26, 30 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the fourth largest number in each lifting size set. If the value is determined (i=4), The values can be defined as 64, 96, 80, 56, 72, 88, 52, 60 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the third largest number in each lifting size set. If the value is determined (i=3), The values can be defined as 128, 192, 160, 112, 144, 176, 104, 120 in order according to the lifting size set index. Similarly, based on the second largest number in each lifting size set, the corresponding parity check matrix defined according to the lifting size set index If the value is determined (i=2), The values can be defined as 256, 384, 320, 224, 288, 353, 208, 240 in order of the lifting size set index.

Also, as shown in the above mathematical formula 19 and the above table 11 and the corresponding examples, According to the pair, The matrix This is done, and the lifting size is determined according to the above index selection example 3. The value If less than or equal to This was established and eventually Therefore, the cycle characteristics are not improved, , This establishment allows efficient LDPC encoding. Lifting size The value In larger cases Satisfying exists ( ) This becomes, and therefore By using the human nature, efficient LDPC encoding is possible, although the encoding complexity increases. Here, and The cycle length determined by the existing at It increases to . and or and The cycle length determined by satisfies exponential condition 1a and exponential condition 1b. It increases significantly in proportion to the value.

The above index selection examples 1, 2, and 3 are index selection methods for some cyclic permutation matrices constituting the submatrix B(1020) in the parity check matrix of FIG. 10, which simultaneously consider improvement of cycle characteristics and coding complexity. The above index selection examples propose a method in which the cycle characteristics are not improved when the code length is short due to a small lifting size, but the coding complexity is very low, and the coding complexity increases somewhat as the lifting size increases, but the cycle characteristics are improved. In general, as the length of an LDPC code is longer, the longer the code, the more sensitively it can be affected by the error floor phenomenon due to the cycle characteristics. Therefore, the above methods, in which the cycle characteristics are further improved as the code length increases along with the lifting size, can be said to be methods that can improve the error floor phenomenon according to the length of the LDPC code.

Of course, when the lifting size is small and the code length is short, the cycle characteristics do not significantly affect the error floor phenomenon, but even when the lifting size is small, a method to improve the cycle characteristics can be applied.

As one embodiment of the present disclosure, a method for improving cycle characteristics when a code length is short is described.

Example 4 of selecting an index ( )

- is an arbitrary integer

- Is and here Is is an integer satisfying , that is, among the indices corresponding to the submatrix B, , Is is an integer satisfying . Here, Is , It means the greatest common divisor of Is It means any lifting size that belongs to the set of lifting sizes corresponding to . ( , is odd, )

- Is

or .

If the system supports The size of is always If it is equal to or greater than It can be simply expressed as .

Example 4 of the above index selection is a cyclic permutation matrix We describe a method in which each index is not a fixed value, but is determined variably based on at least one lifting size Z. Therefore, the method proposed in the present disclosure can be applied not only to the lifting size sets of [Table 3] to [Table 8], but also to various other lifting size sets defined.

should at In this case Since this is not an integer, in the above example can be set to be, i.e., supported by the system. Depending on the values and the given J value The value can be determined variably. If the system supports The value If it is greater than or equal to Since is always an integer, It can be decided in one way as follows.

The method of the above index selection example 4 satisfies index condition 1a and index condition 1b, and the lifting size Depending on the index condition 2a and the index condition 2, the satisfaction of the index condition 2 varies. For example, if the support The range of values If it is greater than or equal to, it satisfies the exponent condition 2a and the exponent condition 2b, If it is less than that, it is not satisfied.

According to the embodiment of the above index selection example 4, (or ) in this case and The cycle length determined by the existing at increases to , (or ) in this case increases to ( ) does not increase in this case. and or and The cycle length determined by satisfies exponential condition 1a and exponential condition 1b. It increases significantly in proportion to the value.

also (or ) in this case The matrix

since,

LDPC encoding is possible using . (or ) in this case The matrix

since,

Integers that satisfy ( ) exists, so LDPC encoding is possible in a similar manner.

The method of the above index selection example 4 has the disadvantage that the maximum value of the cycle length that can be improved depending on the J value is fixed regardless of the lifting size Z, but has the advantage that the cycle characteristics are improved even when the lifting size Z is small. In other words, the cyclic permutation matrix The cycle characteristics can be improved for various lifting sizes by determining at least one of the indices of the cyclic permutation matrix to be variably determined based on the lifting size Z rather than all of the indices being fixed integer values.

For convenience, as a specific example of the above index selection example 4, , in other words, An example of index selection when set to is shown below.

Example 5 of selecting an index ( )

-

- ( )

- Is

or

If the system supports The size of is always If it is equal to or greater than It can be simply expressed as .

As in example 5 of the above index selection In this case yes Any arbitrary It also satisfies index condition 1a and index condition 1b. That is, In Jeong-su About, , , (or ) The submatrix B set as satisfies the index condition 1a and the index condition 1b.

According to the same method as the above index selection example 5,

Become Efficient encoding is possible using .

For convenience, as a more specific example of the above index selection example 4, , in other words, An example of index selection when set to is shown below.

Example 6 of selecting an index ( )

-

- ( )

- Is

or )

If the system supports The size of is always If it is equal to or greater than It can be simply expressed as .

As in example 6 of the above index selection In this case yes Any arbitrary It also satisfies index condition 1a and index condition 1b. That is, In Jeong-su About, , , (or ) The submatrix B set as satisfies the index condition 1a and the index condition 1b.

According to the same method as the above index selection example 6,

Efficient encoding is possible based on .

The index selection methods of the above index selection examples 4, 5 and 6 are such that the cycle length is at most It can be improved by. If If the value is relatively large, the cycle characteristics can be sufficiently improved even if the J value is not large. Typically, the J value is a parameter that indicates the number of rows in the core matrix portion of the parity check matrix given in the system. It can be determined by considering the values and target BLER values. For example, if the target BLER is relatively high or the core matrix For large values, J = 1, 2 may be sufficient, but if the target BLER is relatively low or the core matrix is For small values, it is desirable to set J = 2, 3, 4, …, etc.

In general, since the degree to which the performance of a code is affected by the cycle characteristics varies depending on the length of the code, it is also possible to set the J value differently depending on the lifting size. That is, at least one of the exponents is determined based on the lifting size, but when the lifting size is relatively small, If the value is small and the lifting size is relatively large, You can set the value to a large value ( ). When setting the J value differently depending on the lifting size, the standard lifting size and the appropriate , The value must be determined.

Various possible index selection methods, including the index selection examples 1 to 6, can be variably applied depending on the target BLER and/or lifting size of the system. For example, if the target BLER of the system is high, encoding can be performed using an existing method with the highest encoding efficiency even if the cycle characteristics are not improved because the cycle characteristics do not have a significant impact on the decoding performance of the code. However, if the target BLER is low, the index selection methods proposed in the present disclosure can be applied. Here, the high and low of the target BLER can be relatively determined when there are multiple target BLERs applicable in the system. For example, if the first target BLER is And the second target BLER When the first target BLER is higher than the second target BLER, it can be said that the first target BLER is higher than the second target BLER. If the first target BLER is , the second target BLER And the third target BLER work (or ), the first target BLER may be determined to be higher than the second target BLER and the third target BLER, and the first target BLER and the second target BLER may be determined to be higher than the third target BLER. In this way, when there are multiple target BLERs applicable to the system, the high and low of the BLER can be determined based on a specific BLER value, and then the index selection method proposed in the present disclosure can be variably applied based on this.

However, this is one embodiment of the present invention, and the index selection method proposed in the present disclosure can be applied when the target BLER is high or regardless of the target BLER, and can be applied variably based on other factors. In addition, since the index selection method described throughout the present disclosure refers to a method of selecting an index of a cyclic permutation matrix included in a submatrix of a parity check matrix (specifically, a submatrix B), the index selection method of the present disclosure can be described as a method of determining a parity check matrix or a method of determining a submatrix included in a parity check matrix. In addition, since the lifting size is closely related to the code length or TBS, etc., all processes determined based on the lifting size among the embodiments disclosed in the present invention can be changed to a method determined based on the code length or TBS. In addition, in the index selection examples 1 to 6, the lifting size For convenience, " , , is expressed as "odd number", but is generally expressed as " as in [Table 7-1] or [Table 7-2] , , Is "The smallest lifting size in the set of lifting sizes" The same methods for selecting exponents can be applied even when the number is not restricted to odd numbers.

As a specific example of the application of the J value in Index Selection Example 4 to Index Selection Example 6, if the system target BLER is judged to be high, the J value is If the system target BLER is judged to be low, set the J value to a relatively large value. can be set to a value ( ). Also, the method of selecting these indices or the decision on the J value can be determined by considering the lifting size together. Generally, the reference BLER and/or lifting size is set to A, and a total of (A+1) different J values can be distinguished. For example, if there are the first reference value, the second reference value, etc., the J value is , , … can be subdivided into, etc. In general, J can also be set to 0, in which case It refers to the existing method that enables the simplest encoding without improving cycle characteristics.

Note that the method for determining the target BLER at the terminal or base station can vary depending on the system. For example, the system target BLER may be indicated directly from upper-layer signaling, such as configured RRC (radio resource control) information, indirectly based on configured CQI tables or MCS tables, or indirectly based on configured service scenarios.

As an embodiment of the present disclosure, a method for improving the error floor performance of an LDPC code is proposed. In the present disclosure, an algebraic property that the first part of the parity check matrix, which is composed of sub-matrices A (1010) and B (1020) in FIG. 10, must satisfy when the sub-matrix B (1020) corresponding to the first parity bits in the first part of the parity check matrix is in the form of the following mathematical expression 20 is proposed.

[Equation 20]

The size of the submatrix B(1020) of the above mathematical expression 20 is (or ) and corresponds to the base matrix or weight matrix of size. Also, the first column block of the submatrix B(1020) is 1 A cyclic permutation matrix and two cyclic permutation matrices superimposed It consists of a circular matrix, and the second column block has two It consists of an identity matrix (or a cyclic permutation matrix). For convenience, in this disclosure, the second row blocks are represented only when they consist of an identity matrix, but in general, there is no need to be so restricted. Furthermore, matrices that can be transformed into a submatrix B(1020) of the above form through an appropriate invertible transform process can be considered as algebraically identical matrices.

In the case of the submatrix B(1020) of mathematical expression 20, it is used in the encoding process. Size of The matrix Therefore, efficient encoding is possible depending on the index selection as in the previous examples. However, in order to remove the cycle of length 4 in the structure of the above mathematical expression 20, , (or ) must satisfy the same conditions. It is desirable to remove cycles with a length of 4 because they reduce the decoding performance of the code. In the following, while improving the cycle characteristics for the partial matrix of the above mathematical expression 20, the necessary conditions in the LDPC encoding process are A method for selecting an index that enables efficient encoding by increasing the complexity of operations involving matrices to a reasonable level is described. In the embodiments of the present disclosure, it is assumed that the above condition for removing cycles of length 4 is basically satisfied.

If the lifting size for the parity check matrix of the QC LDPC code cast , ( is odd, When is an integer greater than or equal to 0, the indices (or cyclic shift values) of the cyclic permutation matrices constituting the first column block of the submatrix B(1020) are 0, , are distinct integers, satisfying at least some or all of the following conditions:

Index condition 3 : is the lifting size The greatest common divisor with is 1 or greater than 1 is the smallest number among the divisors of (i.e., Is and are mutually prime or greater than 1 ) has the least divisor as the greatest common divisor.

Index condition 4: In Jeong-su About,

Index Condition 5: In Jeong-su About,

Index condition 6: ( , is an odd number)

According to the above index condition 3, go In the case where they are relatively prime, in the matrix of mathematical expression 20 The length of the cycle on the Tanner graph is determined by A simple example of the cycle characteristics by the exponential condition 3 is shown in Fig. 12a.

FIG. 12a is an exemplary diagram for explaining cycle characteristics in a submatrix of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.

The above figure 12a In case of at An example diagram showing the cycle characteristics induced by a cycle of length 32 is shown. Generally, and The greatest common divisor of The ramen cycle length is It becomes. So As the value increases, the length of the cycle increases. Considering only the cycle characteristics, go Although it is desirable that a and Z are relatively prime, the exponents may be chosen so that the greatest common divisor D is small (so that it is the smallest divisor of Z greater than 1) depending on other conditions. For example, if a cannot satisfy the property of being relatively prime to Z, the greatest common divisor It is desirable to select an exponent that makes the value smaller.

The above index condition 4 is in the matrix of mathematical expression 20. It is a condition for improving the characteristics of the cycle on the Tanner graph determined by . If the index condition 4 is satisfied, the length in the above structure is Since all cycles below are removed, the length is Only ideal cycles exist.

The above index condition 5 is in the matrix of mathematical expression 20. It is a condition for improving the characteristics of the cycle on the Tanner graph determined by . In the above structure, if the index condition 5 is satisfied, In Jeong-su About the length Since all cycles below are removed, the length is Only ideal cycles exist. A simple example of cycle characteristics according to the exponent condition 5 is shown in Figs. 12b and 12c.

FIG. 12b is an exemplary diagram for explaining cycle characteristics in a submatrix of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.

Specifically, Fig. 12b In case of It shows the cycle characteristics induced by . About

but is satisfied with About Because this holds, cycles of length 4 are eliminated, but cycles of length 6 can exist.

FIG. 12c is an exemplary diagram for explaining cycle characteristics in a submatrix of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.

Specifically, Fig. 12c In case of It shows the cycle characteristics induced by . About

but is satisfied with About Because this holds, cycles of length 4 and 6 are eliminated, but cycles of length 8 can exist.

The above index condition 6 is for efficient LDPC encoding. It is a condition for simplifying the matrix as much as possible. In the process of performing LDPC encoding based on the parity check matrix including the submatrix B of mathematical expression 20, The matrix is can be defined as follows. At this time, If set to since Become This becomes. Therefore Relatively efficient encoding is possible using matrices. In the above index condition 6, if the lifting size If is odd Since the values cannot be integers, this embodiment can only be applied when all lifting sizes are even. That is, at is applicable only if the number is an integer greater than or equal to 1. For example, in each set of lifting size sets as in [Table 9], the minimum lifting size must be an even number.

[Table 9]

As an embodiment of the present disclosure, a more specific example of constructing a submatrix B(1020) of FIG. 10 using the above exponential conditions is described.

First, consider a communication system or broadcasting system, such as 5G, where a set of lifting sizes is defined, as shown in Tables 3 through 9, and only lifting sizes included in the set can be applied. Furthermore, a separate parity check matrix or index matrix can be defined for each lifting size set. That is, in the cases of Tables 3 through 9, a parity check matrix or index matrix can be defined for each of the eight set indices.

In the submatrix B based on mathematical expression 20, , Let us decide as follows. For convenience in this disclosure, I will explain only the case where The value of and can be selected from values that are mutually prime or have a smaller greatest common divisor. In general, to ( ) index for the submatrix B of the corresponding parity check matrix Because the values may all be different It was expressed as . Also Is It means any lifting size that belongs to the set of lifting sizes corresponding to , ( is an odd or minimum lifting size, ) can be expressed in the same form.

Example 7 of selecting an index ( )

-

-

(step, , in other words, ) must be satisfied.

In the above index selection example 7, if the system supports The size of all If it is a multiple of (step, ) can be simply expressed as. In this case, the minimum lifting size in each lifting size set as in [Table 9] above is It means that the minimum lifting size is a multiple of 4. For example, when J is set to 2, it means that the minimum lifting size is a multiple of 4, and when J is set to 3, it means that the minimum lifting size is a multiple of 8. In Tables 3 to 9, Like a set of lifting sizes In case of the form To satisfy the condition, the minimum lifting size is For example, when J = 2, 3 are set, the minimum lifting sizes are 8, 16, respectively. In the present disclosure, for convenience of explanation, the minimum lifting size in each lifting size set is This is explained only for cases where the minimum lifting size is a multiple of 2. In general, the minimum lifting size in each set of lifting sizes is a multiple of 2, but Even if the index is not a multiple of , the index selection method described in the present disclosure can be applied.

According to the above index selection example 7, index conditions 3 and 6 are established.

also Therefore, according to the index condition 4, There is no cycle of length 4 induced by . If If it does not have a prime factor of 3 (i.e., (If it is not an odd number that is a multiple of 3) There is no cycle of length 6, since it cannot be an integer. If a has a prime factor of 3, Because it means the form,

is. If J=2, Back side and,

Therefore, there is no cycle of length 6 for all lifting sizes. Also, if J = 2, From Because it satisfies There is no cycle of length 8 induced by . Therefore, if J is chosen as an integer greater than or equal to 2, The length of the cycle induced by is at least 10. As the J value increases, the cycle characteristics can be further improved, but it is desirable to select an appropriate J value according to the requirements of the system because the encoding complexity increases and the constraints on the lifting size increase.

According to Example 7 of selecting an index, is a relatively large integer starting from 0 I am satisfied with it, but and In case of Since it satisfies the index condition 5, as in Fig. 12b and Fig. 12c, Among the cycles induced by , only cycles of length 4 are removed. Therefore, to remove cycles of longer length, J is set to an integer greater than or equal to 2. It is desirable to apply the above index selection method for the lifting size satisfying . For example, J = 2, In this case

- ;

- ;

- ;

- ;

can be established. Therefore, according to index condition 5, as in Fig. 12b and Fig. 12c, It can be seen that all cycles with a length of 12 or less among the cycles that can be induced by are removed.

Considering the features of index conditions 3 to 6 and the index selection example 7 above, a method of selecting an index based on the minimum lifting size of a given set of lifting sizes can also be applied.

Example 8 of selecting an index ( )

-

- A set of lifting sizes corresponding to =

step, and, does not necessarily have to be an odd number.

-

Example 8 of index selection is given a set of lifting sizes, and the minimum lifting size contained in each lifting size set is It means a method of selecting an index based on. According to index selection example 8, It can also be expressed as . As a specific example, in a system that applies lifting size sets excluding the numbers in () in [Table 9], when J = 2 is set, for each set index The values are sequentially 4, 6, 5, 7, 9, 11, 13, 15. If J is set to 3 and the minimum lifting size of each lifting size set is 32, 48, 40, 56, 72, 88, 104, 120, then for each set index The values are sequentially 4, 6, 5, 7, 9, 11, 13, 15.

As one embodiment of the present disclosure, the above The value may also be determined based on lifting sizes greater than a certain reference value. Specifically, assume that J = 2 and the reference value is set to 64. If If the above index selection example 8 is applied only when the value is greater than or equal to the above reference value, then for each set index The values are sequentially 16, 24, 20, 28, 36, 44, 52, 60. As another example, assume that J = 3 and the reference value is set to 64. If If the above index selection example 8 is applied only when the value is greater than or equal to the above reference value, then for each set index The values are sequentially 8, 12, 10, 14, 18, 22, 26, 30.

As an embodiment of the present disclosure, an index selection method for improving the decoding efficiency of LDPC codes is proposed. In the present disclosure, an LDPC encoding and decoding system using a parity check matrix of the form shown in Equation 21 is assumed.

[Equation 21]

The size of the parity check matrix of the above mathematical expression 21 is , and the basic matrix or weight matrix, etc., respectively. The parity check matrix of the above mathematical expression 21 has the size of the submatrix A(1010) in FIG. 10. , and the size of the submatrix B(1020) is It can correspond to the in-core matrix. (In Fig. 10, when M2 = 0, the above mathematical expression 21 corresponds to the entire parity check matrix.)

Also each The th column block is doggy Circular permutation matrix nested It is composed of a circulant matrix. In the present disclosure, for convenience, it is explained as an example that one of the circulant permutation matrices constituting each column block is composed of an identity matrix ( ), it is not generally necessary to be so restricted. Also, matrices that can be transformed into a parity check matrix of the above form through appropriate inverse transformation processes such as circular shift and permutation can be considered as algebraically identical matrices.

In the parity check matrix of the above mathematical expression 21, the front corresponding to the information word doggy The size circulant matrices can be composed of three or more circulant permutation matrices, and are typically composed of four or more circulant permutation matrices to improve the minimum distance property of the code. The last circulant corresponding to the parity bit The th circulant matrix is composed of two or more circulant permutation matrices, but since a circulant matrix composed of two or four circulant permutation matrices does not have full rank, At least one of the columns of the th circulant matrix corresponds to an information word bit. Therefore, it is usually composed of three or more odd circulant permutation matrices to improve the minimum distance characteristic and apply an efficient encoding method known in the past. In addition, it is usually composed of one to remove a cycle of length 4. The differences between the indices (or circular shift values) corresponding to the cyclic permutation matrices that constitute the size cyclic matrix are modulo- It's all different.

An example of the parity check matrix of the above mathematical expression 21 is shown in Fig. 13. The parity check matrix of Fig. 13 is About The size is , and the cyclic permutation matrix constituting the three column blocks is as follows: Equation 22.

[Equation 22]

In general, one parity check matrix like the above mathematical expression 21 and FIG. 13 If three or more cyclic permutation matrices are nested in a cyclic matrix, a cycle of length 6 can always be created. In other words, in the parity check matrix of the above mathematical expression 21, If there is at least one case, the girth (meaning the minimum cycle length on the Tanner graph corresponding to a code) on the Tanner graph is 6. Therefore, the parity check matrix of the above mathematical expression 21 cannot improve the cycle characteristic, so it is preferable to use it in an environment that is not greatly affected by the cycle characteristic. Communication systems that are not sensitive to the cycle characteristic typically have short supported code lengths and/or high supported code rates and/or high target BLER systems.

According to the parity check matrix of the above mathematical expression 21, Once the dog's index is confirmed It has the advantage of high storage efficiency because the parity check matrix can be generated regardless of the size of the terminal or base station. For example, the parity check matrix of FIG. 13 is If we can verify the information of values and [(0, 1, 2, 3,) (0, 5, 10, 15) (0, 2, 3)], we can create or determine the parity check matrix.

In general, QC-LDPC codes are structured to perform parallel processing with one row block as the basic unit through a layered decoding method. However, since the parity check matrix of the above mathematical expression 21 or FIG. 13 has all rows as one row block, - The operation of performing decryption through a parallel processing processor of the unit means processing all rows simultaneously. This decoder structure There is no problem when the value is small, but as the length of the sign increases, the length of the row, i.e., Supporting large code lengths can be burdensome for decoder implementations as the values increase.

In this disclosure, an appropriate index selection method is proposed for a parity check matrix having the structure of the above mathematical expression 21, and when the proposed index selection method is applied, Explains that smaller parallel processing is possible.

first We define rules for applying the following column permutations and row permutations to circulant matrices.

[Permutation Rule]

- , ( : greater than 1 divisor of)

- Each Apply the following permutation rules to the size circulant matrix.

- , About,

(a) Column permutation rules: The second column Go to the second column

(b) Row permutation rules: The second row Move to the th row

A specific example of applying the above [permutation rule] to the parity check matrix of Fig. 13 is shown in Figs. 14a and 14b. In Figs. 14a and 14b, , , The permutation rule was applied based on .

FIG. 14a and FIG. 14b are exemplary diagrams of applying a permutation rule according to an embodiment of the present disclosure to a parity check matrix.

Fig. 14a is an example diagram of applying column permutation to the parity check matrix of Fig. 13, and Fig. 14b is an example diagram of additionally applying row permutation to the parity check matrix of Fig. 14a. Referring to Fig. 14b, The parity check matrix of mathematical formula 22, which is composed of a circulant matrix of size , is rearranged by applying the permutation rule to the columns and rows, as in mathematical formula 23. It can be represented as a parity check matrix consisting of a cyclic permutation matrix of size .

[Equation 23]

In general, simple permutations of rows and columns do not affect the characteristics or performance of the code. In particular, row permutations do not affect the characteristics of the code at all, and column permutations only affect the order of bits and do not affect the characteristics or performance of the code. Therefore, simply rearranging the parity check matrix in this way - It can be converted into a structure that is easy to apply the layered decryption method of the unit.

Applying the above permutation rule to the circulant matrix of size, we get the following mathematical expression 24. divisor of About doggy It can be partitioned into a matrix of cyclic permutations.

[Equation 24]

The above mathematical expression 24 is When a circulant matrix of size is divided, a case is shown where there is no circulant matrix nested in the circulant permutation matrix, but in general, a circulant matrix may exist even after rearrangement, as in the following mathematical expression 25.

[Equation 25]

In this way, various forms of rearrangement are possible depending on the index of the cyclic permutation matrix that constitutes the parity check matrix of mathematical expression 21. However, since a cyclic matrix in which three or more cyclic permutation matrices are overlapped typically significantly increases the decoder implementation complexity, it is advantageous for the decoder implementation to ensure that the cyclic permutation matrices do not overlap, or overlap at most two, if possible.

According to the above mathematical expressions 24 and 26, the column index and row index of each cyclic permutation matrix are the size of the cyclic permutation matrix ( ) divisor The remainder after division can affect the position after rearrangement. That is, the divisor The elements (entries) corresponding to the same column and row for the remainder are the same after reordering. It is included in the circulant matrix of size ( ). As a concrete example, divisors The rows corresponding to the remainder i and the columns corresponding to the remainder j are The elements of the dog correspond to the jth column block of the ith row block. It is included in the circulant matrix of size ( . Therefore, after rearranging the parity check matrix by applying the permutation rule proposed in this disclosure, In order to prevent more than two circulant permutation matrices from being mapped to a circulant matrix of size , one is added to the initially given parity check matrix. Each index (or circular shift value) corresponding to the cyclic permutation matrices that constitute the size cyclic matrix is divisor of It can be set so that there is at most one case where all remainders are different or equal. In other words, the indices (or cyclic shift values) corresponding to the cyclic permutation matrix are modulo- to have all different values or at most one identical value (with no more than one identical case). After reordering, there must be There are no more than two circulant permutation matrices corresponding to a circulant matrix of size . The largest number among the weights of each column block is When you say, If a relationship is established, at least one This means that three circulant permutation matrices are superimposed on a circulant matrix. Therefore, If satisfied, the above rearrangement is possible.

After rearranging the parity check matrix To ensure that a circulant matrix of size has at most one circulant permutation matrix, each of the indices (or circulant shift values) must be divisor of The rest of it must all be different. Also If a relationship is established, at least one Because it means that two circulant permutation matrices are superimposed on a circulant matrix. The above rearrangement is possible only if .

To determine the indices of the circulant permutation matrices that constitute the circulant matrix corresponding to the last column block. In addition to the remainder, efficient encoding should be considered. Since the encoding complexity of the submatrix corresponding to the parity in the parity check matrix is often smaller when it is closer to a lower triangular matrix, it is desirable to select indices close to a lower triangular matrix among the indices satisfying the above conditions. In the present disclosure, Considering the case where the value is 4 or greater, the circulant matrix of the last column block is or This can be applied. Considering the conditions If we consider that is greater than or equal to 4, then the exponent pair (0, 1, 3) or (0, 2, 3) is always Because the remainder is different. Of course, this is just an example, and the index value of the cyclic permutation matrix is the lifting size. and/or the size of the parity check matrix and/or Divisors for rearranging into a form divided by size The index selection method described throughout the present disclosure may be appropriately selected based on at least one of the weight distributions of the circulant matrix constituting the value and/or each column block. Meanwhile, since the index selection method described throughout the present disclosure refers to a method for selecting an index of a circulant permutation matrix included in a submatrix of a parity check matrix, the index selection method of the present disclosure may be described as a method for determining a parity check matrix or a method for determining a submatrix included in a parity check matrix.

As one embodiment of the present disclosure, the parity check matrix is a superposition of two cyclic permutation matrices as in Equation 20 or Equation 21. We present a rate matching method for the case where a matrix contains at least one circulant matrix.

In general, when the weight of the parity check matrix is high, additional parity can be generated through the Row Splitting-Extending (RSE) method that separates and extends the rows of the parity check matrix. The RSE method is briefly explained using the encoding method using the parity check matrix of Equation 26 as follows.

[Equation 26]

First, the above mathematical expression 26 can be expressed by dividing it into three equations as shown in the following mathematical expression 27.

[Equation 27]

A value that acts as an intermediate variable in the above mathematical expression 27 , There is a value and using that value, the equation can be separated and organized as in mathematical expression 28.

[Equation 28]

The above mathematical expression 28 can be expressed as a relational expression based on an extended parity check matrix as in the following mathematical expression 29.

[Equation 28]

Referring to the above mathematical expression 28, the existing codeword The value of the intermediate variable is not changed , This additionally introduces the effect. This process is expressed in Equation 26. By appropriately separating some of the rows of the parity check matrix of size and adding new columns, as in Equation 28, Codeword satisfying for extended parity check matrix of size It is like defining . Also , Since this is equivalent to additionally increasing parity for the existing codeword, it is equivalent to an incremental redundancy (IR) operation. In this disclosure, this IR process is conveniently called the RSE method.

To improve the performance of the IR method using the RSE method, it is important to determine which rows in the parity check matrix to apply the RSE method to. As a simple example, consider the parity check matrix of Equation 29. By applying the RSE method (RSE method 1, RSE method 2) or A matrix such as can be obtained. Meanwhile, below, the matrix obtained (or defined) by applying the RSE method is , and other expressions with the same meaning (e.g., modified parity check matrix, extended parity check matrix, separated parity check matrix, etc.) may be used. Therefore, or Is Each may be referred to as a first modified parity check matrix or a second modified parity check matrix.

[Equation 29]

In the above mathematical expression 29 , and are all It consists of a cyclic permutation matrix or permutation matrices of size , each of which is of size , , am. and The last ten blocks of corresponds to newly generated parity bits as a column block corresponding to the added intermediate variables. The RSE method can be performed row by row as in Equations 26 to 28, but can also be performed row by row block as in Equation 29.

In the above mathematical expression 29 and have the same row and column weights. However, contains a circulant matrix with at most two nested circulant permutation matrices, but contains a circulant matrix in which up to three circulant permutation matrices are nested. As the number of nested circulant permutations constituting the circulant matrix increases, the parity check matrix has the advantage of having a simple form. However, as the number of nested circulant permutations constituting the circulant matrix increases, the parity check matrix has a very limited cycle characteristic, so that the error correction effect may be degraded when performing belief-propagation BP decoding, which is commonly used for decoding LDPC codes. In particular, when the number of nested circulant permutation matrices constituting one circulant matrix is three or more, there is a problem that the maximum cycle length cannot exceed 6. Therefore, except for the case where the parity check matrix is composed of one row block, as in Equation 21 or Equation 29, and In a parity check matrix consisting of two or more row blocks, it is desirable to avoid including a circulant matrix with three or more overlapping circulant permutation matrices.

The general rules of the RSE method considering the cycle characteristics and degree distribution of the parity check matrix can be summarized as follows.

[RSE Rules]

(1) First, a row block containing a circulant matrix in which three or more circulant permutation matrices are overlapped is split and expanded. To ensure that the parity check matrix after splitting and expanding does not contain a circulant matrix in which three or more circulant permutation matrices are overlapped, one row block can be split into two or three or more row blocks and expanded into two or three or more column blocks.

(2) If there is no circulant matrix in which three or more circulant permutation matrices are overlapped, the row block containing the circulant matrix in which two or more circulant permutation matrices are overlapped is first separated and expanded. In order to ensure that the parity check matrix after separation and expansion does not contain a circulant matrix in which two or more circulant permutation matrices are overlapped, one row block can be separated into two or three or more row blocks and expanded into two or three or more column blocks.

(3) If there is no circulant matrix in which two or more circulant permutation matrices overlap, the row block with the highest row degree in the parity check matrix is first separated and expanded. In order to efficiently reduce the row degree in the parity check matrix after separation and expansion, one row block can be separated into two or three or more row blocks and expanded into two or three or more column blocks.

All or at least one of the above rules (1) to (3) for the RSE method can be used to obtain a separated and extended parity check matrix.

The first given parity check matrix , the parity check matrix separated and extended according to the above RSE rule. When you say, Contrast The bits corresponding to the newly generated column or column block can be considered as additional parity bits. In addition, the additional parity bits may be used for services that require separate parity bit transmission to improve reliability, such as retransmission methods such as HARQ. In addition, certain receivers may use the parity check matrix Decryption must be performed using a parity check matrix, and specific receivers must use a parity check matrix. In cases where decoding can be performed using the additional parity, the additional parity can be transmitted separately to perform decoding suited to the characteristics of each receiver. Meanwhile, in the present disclosure, the parity check matrix The first parity check matrix, the parity check matrix is called the second parity check matrix or the parity check matrix The parity check matrix, the parity check matrix It can be called an extended parity check matrix or a modified parity check matrix.

In this way, the receiver physically has a parity check matrix Separation of the parity check matrix from and extended parity check matrix Decide on, LDPC decoding can also be performed using . Alternatively, the receiver can use If no additional parity portion is transmitted while already stored, Contrast extended Parity bits corresponding to a column or block of columns are considered to be punctured and decoding can be performed, and if all or at least part of the additional parity has been transmitted, Contrast extended Decryption may also be performed using all or at least part of a column or block of columns.

In the present invention, in a method and device for transmitting additional parity or performing decoding based on a signal corresponding to the transmitted additional parity bit, a transmitter or a receiver physically transmits a parity check matrix Separation of the parity check matrix from and extended parity check matrix may include a process and device for generating a transmitter or receiver. While saving only Contrast extended Also included are a method and device for performing encoding and decoding through appropriate rate matching for parity bits corresponding to all or at least a portion of a column or column block.

This separation and expansion of the parity check matrix may not actually work in the transmitter or receiver depending on the implementation method, but the parity check matrix Raw and separated and extended parity check matrix The relationship between each and , and the codeword generated for the same input bits or information word bits and Is go There is a relationship that always includes . In other words, for the same input bits or information bits, Add an additional parity bit to can be decided. Also, From the method of creation By appropriately combining some of the rows or row blocks, some of the columns or column blocks are removed. There is a characteristic that it becomes. In the present invention One of the features is that it is actually located at the terminal or base station. and Even if we do not implement it together, Through decide, or Through can be determined. In other words, in the transmitting device or the receiving device. and Even if we only store information about one parity check matrix, and It has the same effect as saving all of them. Not only that, When there is a first communication system based on a parity check matrix There may be other second communication systems based on or other versions of the first communication system.

Additionally, a specific terminal or base station may have a separate and extended parity check matrix. While storing the parity check matrix When communicating with a terminal or base station storing the parity check matrix, a normal rate matching process can be performed. However, the parity check matrix The terminal or base station storing the parity check matrix When communicating with a terminal or base station that only stores LDPC encoding is performed based on the rate matching process. Contrast extended Perforation may always be applied to the parity bits corresponding to all or at least part of a column or column block. In the rate matching process. Contrast extended When performing LDPC decoding at a terminal or base station, if puncturing is always applied to parity bits corresponding to all or at least part of a column or column block, Combine rows or blocks of rows Decryption can also be performed based on the terminal or base station. or Whether or not a system is storing a preamble can typically be determined by distinguishing the system version, or it can be determined through higher layer signaling.

As an embodiment of the present disclosure, when a sub-matrix corresponding to a parity bit in a parity check matrix has a form as in [Mathematical Formula 20], the structure of a sub-matrix corresponding to a parity bit in a separated and extended parity check matrix is proposed as in the following Mathematical Formula 30.

[Equation 30]

Referring to the above mathematical expression 30, if When applying splitting and expansion to only one row block in a parity check matrix including [RSE rule], the row containing the circulant matrix is split into two circulant permutation matrices, and at least the submatrix corresponding to the parity bits In , all of them are made up of cyclic permutation matrices or zero matrices. If When applying splitting and expansion to two row blocks in a parity check matrix including , splitting and expansion are applied to the first row block and the second row block respectively. We can obtain a submatrix corresponding to the parity bits.

As explained above, the terminal or base station may physically separate and expand the parity check matrix, but depending on the implementation, instead of actually separating and expanding, the parity check matrix including the extended parity structure shown in the above mathematical expression 30 may be stored and LDPC encoding and decoding may be performed. As a specific example, If all parity bits corresponding to an extended column or column block are received with the bits punctured, the receiver or Decoding can also be performed based on a parity check matrix with appropriately combined rows, as in If all parity bits corresponding to an extended column or column block are received with the bits punctured, the receiver Decoding can also be performed based on a parity check matrix with appropriately combined rows, such as

As an embodiment of the present disclosure, an example of a process for applying LDPC encoding and rate matching based on a separated and extended parity check matrix is described.

The parity check matrix or the first part of the parity check matrix used when performing LDPC encoding and decoding in the transmitting device and the receiving device Let's say here is a submatrix corresponding to the information word bits, is a submatrix corresponding to a parity bit and may correspond to at least one of the matrices disclosed in mathematical expression 31.

[Equation 31]

The submatrices corresponding to the parity bits of the above mathematical expression 31 are obtained through the reverse process of the RSE process, i.e., by appropriately combining row blocks and deleting column blocks. or It can be decided in the same order. However, at To sequentially represent the process of determining Although it is expressed as determining the sub-matrix in the same order, the decision process according to the above order is not necessarily performed. That is, Based on At least one of them can be determined or Based on At least one of them can be determined, go It can be decided based on. In addition, the above decision process is not necessarily required to be performed. Inland At least one of them may be stored in the transmitter and receiver, and the transmitter and receiver may perform encoding or decoding using the partial matrix. In addition, just as the IR technique can be applied through the RSE process, puncturing can be applied to the additionally generated parity bits used in the IR through the RSE inverse process. In other words, we propose a method of adjusting the code rate by generating sufficient parity and then puncturing, contrary to the IR process. Although this method has a disadvantage of generating parities that may not be transmitted, it is easy to adjust the code rate through a rate matching method that punctures a portion of the parity bits, and has an advantage of efficiently supporting the IR technique by additionally transmitting at least a portion of the punctured parities during retransmission.

Conventional rate matching methods begin with the last parity bit being punctured first, depending on the code rate. However, considering the inverse RSE process, puncturing parity bits in the middle can provide better encoding performance than puncturing parity bits starting from the last bit.

Through the RSE reverse process Considering the process of obtaining , Parity bits for Instead of punching from the last bit, as in mathematical expression 32, The parity bit corresponding to the third column block can be punched (assuming the first column block is the 0th column block). Meanwhile, In (1) is included to indicate that it corresponds to, but (1) above may be omitted. Therefore, the parity bits Is can be expressed as . Also, means the parity bit for the 4th column block from the 0th column block, 0th column block, 1st row block, 2nd row block, 3rd row block, This may mean a parity bit for the 4th column block.

[Equation 32]

In the above mathematical expression 32 Is is the parity bit for the above. That is, is the parity bit for the third column block This may mean that it has been perforated.

In the same way Through the RSE reverse process Considering the process of obtaining , if additional parity bits are punched, Parity bits for Instead of punching from the last bit, as in mathematical expression 33, The first column block of, i.e., The parity bit corresponding to the first column block can be punched.

[Equation 33]

In the above mathematical expression 33 Is is the parity bit for .

In the same way Through the RSE reverse process Considering the process of obtaining , if additional parity bits are punched, Parity bits for As in mathematical formula 34 The second column block of, i.e., The parity bit corresponding to the fourth column block can be punched.

[Equation 34]

In the above mathematical expression 34 Is is the parity bit for .

As a result, the conventional rate matching method applies parity puncturing in the order of parity bits corresponding to the (4, 3, 2, 1, 0)th column block in the submatrix corresponding to the parity, but applying parity puncturing in the order of parity bits corresponding to the (3, 1, 4, 2, 0)th column block by considering RSE or the inverse process of RSE as in this embodiment may provide better encoding performance.

Through the RSE reverse process In the process of obtaining The second column block of, i.e., The same result can be obtained even if the parity bit corresponding to the second column block is punctured. In this case, it is expressed in Equations 33 and 34. and It can be expressed as the following mathematical expression 35, and means that parity puncturing is applied in the order of parity bits corresponding to the (3, 2, 4, 1, 0)th column block.

[Equation 35]

Through the RSE reverse process Considering another process to obtain , It is also possible to puncture from the last bit in the parity bits as in mathematical expression 36.

[Equation 36]

In the above mathematical expression 36 Is is the parity bit for .

In the same way Through the RSE reverse process Considering the process of obtaining , when the parity bit is punctured, Parity bits for Instead of punching from the last bit, as in mathematical expression 37, The first or second row block of the The parity bit corresponding to the first or third column block can be punched.

[Equation 37]

or

In the above mathematical expression 33 Is is the parity bit for .

In the same way Through the RSE reverse process Considering the process of obtaining , when the parity bit is punctured, Parity bits for As in mathematical expression 38 The second column block of, i.e., The parity bit corresponding to the third column block can be punched.

[Equation 38]

In the above mathematical expression 38 Is is the parity bit for .

Consequently, applying parity puncturing in the order of parity bits corresponding to the (4, 1, 3, 2, 0)th column block or in the order of parity bits corresponding to the (4, 2, 3, 1, 0)th column block by considering RSE or the inverse process of RSE may provide better encoding performance.

According to the above results, when puncturing parity bits corresponding to two or more column blocks in the rate matching process, better encoding performance can be obtained when the parity bits are punctured in an appropriate order, such as (3, 1, 4, 2, 0) or (3, 2, 4, 1, 0) or (4, 1, 3, 2, 0) or (4, 2, 3, 1, 0), rather than puncturing them sequentially from the last parity bits in the order of the 3rd column block to the 4th column block. In particular, when the parity bits that are punctured first among the above five column blocks correspond to one of the 1st, 2nd, or 3rd column blocks, or when the parity bits that are punctured first correspond to the 4th column block, and the next corresponding column block is the 1st or 2nd column block, better performance is provided.

RSE or RSE inverse process can be applied not only to the sub-matrices corresponding to the parity bits but also to the combination or division of the sub-matrices corresponding to the information bits. Therefore, even if the sub-matrices corresponding to the parity bits determined through RSE or RSE inverse process have the same form, the sub-matrices corresponding to the information bits may be different from each other, and thus the rate-matched parity bits may be different from each other. In this way, if RSE or RSE inverse process is applied while considering the combination of the sub-matrices corresponding to the information bits, the rate matching order supporting better encoding performance can be determined.

In the above examples, the parity check matrix or the first part of the parity check matrix used when performing LDPC encoding and decoding in the transmitting device and the receiving device As explained in the case of the parity check matrix or the first part of the parity check matrix In this case The puncturing order of the parity bits can be determined by considering the reverse process of the RSE in the same order. For example, The punching order of the parity bits based on the standard can be expressed as the order of the (1, 3, 2, 0)th column block or the order of the (2, 3, 1, 0)th column block.

Meanwhile, in the above examples or In the case defined as , the puncturing order of the parity bits for rate matching can be applied to the rate matching in which the parity bits are punctured in the order of column blocks (1, 3, 4, 2, 0) or (1, 4, 3, 2, 0) or (2, 3, 4, 1, 0) or (2, 4, 3, 1, 0) in the submatrix corresponding to the parity, or in the order of column blocks (2, 3, 1, 0) or (3, 2, 1, 0). In particular, in this case, the puncturing can be applied in the order of (3, 2, 1, 0) in the same manner as the existing rate matching process.

Meanwhile, as described above, the decision-making process according to the above order is not necessarily required. That is, or Based on can be decided Based on can be determined. In addition, in the rate matching process, , or , Or, by punching the parity bits only, , and or , and When puncturing parity bits by considering only the order of the punctured parity bits, the order of the punctured parity bits may be set differently.

For example, in the rate matching process One of the parity bits corresponding to a column block corresponds to When perforation is limited to within a bit, perforation can be applied to the parity bits corresponding to one of the column blocks of the 1st, 2nd, 3rd, or 4th column blocks, excluding the parity bits corresponding to the 0th column block. Here In case of punching the parity bits corresponding to the first or second column block of is equivalent to generating the corresponding parity bits, In case of punching the parity bits corresponding to the 3rd or 4th column block, It is equivalent to generating parity bits corresponding to each column block. If puncturing the parity bits corresponding to any column block does not significantly affect the encoding performance, puncturing can be applied starting from the parity bits corresponding to the last column block, as in the normal rate matching operation.

Also in the rate matching process Two columns of parity bits corresponding to the corresponding block When applying perforation within bits, the parity bits corresponding to three column blocks do not need to be perforated, so they can be expressed only for column blocks corresponding to perforation, such as (3, 1, *, *, *) or (3, 2, *, *, *) or (4, 1, *, *, *) or (4, 2, *, *, *) or (1, 3, *, *, *) or (1, 4, *, *, *) or (2, 3, *, *, *) or (2, 4, *, *, *). (* means that no number is indicated, or if indicated, it is unrelated to perforation.) Similarly, in the rate matching process Two columns of parity bits corresponding to the corresponding block When puncturing is applied within a bit, the parity bits corresponding to three column blocks do not need to be punctured, so they can be expressed only for the column blocks corresponding to the puncturing, such as (3, 1, 4, *, *) or (3, 2, 4, *, *) or (4, 1, 3, *, *) or (4, 2, 3, *, *) or (1, 3, 4, *, *) or (1, 4, 3, *, *) or (2, 3, 4, *, *) or (2, 4, 3, *, *). The method of setting the order of puncturing parity bits differently in the rate matching process can be implemented in various ways. As in the above embodiment, if a pattern for the order of bits to be punctured is stored in a transmitting device or a receiving device, the positions of the punctured parity bits can be identified through rate matching, so LDPC encoding and decoding are possible.

Another way is to appropriately interleave the generated parity bits and then apply the existing rate matching method. For example, the parity bits generated in the order of the (0, 1, 2, 3, 4)th column blocks By performing interleaving in units of column blocks of bits to correspond to the (0, 2, 4, 1, 3) or (0, 1, 4, 2, 3) or (0, 2, 3, 1, 4) or (0, 1, 3, 2, 4) or (0, 2, 4, 3, 1) or (0, 2, 3, 4, 1) or (0, 1, 4, 3, 2)th column block, and then sequentially applying puncturing from the last interleaved parity bits as in the existing rate matching method, the puncturing method of the above embodiment can be supported. The maximum value of the parity bits to be punctured is If it is determined as , the front of the above interleaving pattern The order of the dogs can be reversed.

For example, the parity bits corresponding to the column blocks of the submatrix And, if interleaved in the order of (0, 2, 3, 1, 4)th column block, interleaved parity bits

It can be.

Alternatively, the parity bits corresponding to the column blocks of the submatrix And, if interleaved in the order of (0, 1, 3, 2, 4)th column block, interleaved parity bits

It can be.

Similarly, the parity bits generated in the order of the (0, 1, 2, 3)th column blocks are interleaved in units of column blocks so that the parity bits correspond to the (0, 2, 3, 1) or (0, 1, 3, 2) or (0, 1, 3, 2)th column blocks, and then the puncturing is sequentially applied from the last interleaved parity bits like the existing rate matching method, thereby supporting the puncturing method of the above embodiment. However, if the submatrix corresponding to the parity bit is In this case, interleaving may not be applied.

In this way, in the case where the parity check matrix among the quasi-cyclic LDPC codes has a dual diagonal structure of a sub-matrix corresponding to the parity bits, such as in Equation 15 or Equation 31, it can be seen that an effect similar to that of combining row blocks of the parity check matrix can be obtained through appropriate parity puncturing.

Meanwhile, the electronic devices according to the various embodiments disclosed in this document may be devices of various forms. The electronic devices may include, for example, at least one of a portable communication device (e.g., a smartphone), a TV, a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. The electronic devices according to the embodiments of this document are not limited to the aforementioned devices. Furthermore, the act of transmitting a frame does not only mean that it is transmitted via a wireless channel or the like, but may also mean that various electronic devices include an interface for outputting the frame for transmission. For example, a processor may output a frame to an RF front-end for transmission via a bus interface. Similarly, the act of receiving a frame from another device may mean that various electronic devices have an interface for obtaining a frame received from another device. For example, a processor may receive or obtain a frame from an RF front-end via a bus interface.

It should be understood that the various embodiments and terminology used in this document are not intended to limit the technology described in this document to a specific embodiment, but rather to encompass various modifications, equivalents, and/or alternatives of the embodiments.

In connection with the description of the drawings, similar reference numerals may be used for similar components. The singular expression may include the plural expression unless the context clearly indicates otherwise. In this document, expressions such as "A or B", "at least one of A and/or B", "A, B, or C", or "at least one of A, B, and/or C" may include all possible combinations of the items listed together. Expressions such as "first", "second", "first", or "second" may modify the corresponding components without regard to order or importance, and are only used to distinguish one component from another component and do not limit the corresponding components. When one (e.g., a first) component is said to be "(functionally or communicatively) connected" or "connected" to another (e.g., a second) component, the one component may be directly connected to the other component, or may be connected via another component (e.g., a third component).

Also, the word "determining" can have many different meanings, such as identifying, calculating or computing, processing, deriving, investigating, estimating, looking up (e.g., from a database or other data structure), and ascertaining, depending on the context.

Meanwhile, the order of description in the drawings explaining the method of the present disclosure does not necessarily correspond to the order of execution, and the order of precedence may be changed or executed in parallel.

Alternatively, the drawings illustrating the method of the present disclosure may omit some components and include only some components without detracting from the essence of the present disclosure.

In addition, the method of the present disclosure may be implemented by combining some or all of the contents included in each embodiment within a scope that does not harm the essence of the invention.

While the present disclosure has been described with preferred embodiments in mind, various modifications and variations may occur to those skilled in the art. Such modifications and variations are intended to be encompassed by the appended claims. Furthermore, it should be understood that operations represented by different blocks in the flowchart of the present disclosure for convenience of explanation may be implemented separately across multiple processors in an actual system, but may also be implemented integrated into a single processor.

Claims (16)

In a method performed by a transmitter in a communication system,
A step of determining the number of input bits;
A step of determining a basic matrix based on the number of input bits;
A step of determining a lifting size (Z) based on at least one of the number of input bits or the basic matrix;
determining a parity check matrix based on at least one of the basic matrix or the lifting size (Z); and
A step of performing encoding based on the parity check matrix and the input bits; and
A step of performing rate matching based on the encoded bits,
The above parity check matrix is a submatrix corresponding to the parity bits.

Includes,
Among the 0th, 1st, 2nd, 3rd, and 4th column blocks of the above submatrix, puncturing begins from the parity bits corresponding to the 4th column block.
Included in the above parity check matrix Is is the identity matrix of size, Is is a zero-sized matrix, , , ,Is A method characterized in that the matrix is an identity matrix or a cyclic permutation matrix of size. In the first paragraph,
Among the encoded bits, the parity bits corresponding to the submatrix A method characterized by further comprising the step of performing interleaving on a bit-by-bit basis. In the second paragraph,
Parity bits corresponding to the column blocks of the submatrix based on the above interleaving Is

or

is determined by,
Interleaved parity bits based on the above rate matching A method characterized in that the last bit of the bit is perforated in reverse order. In the first paragraph,
The step of determining the above parity check matrix is:
Further comprising a step of determining a modified parity check matrix based on the above parity check matrix,
A method characterized in that the above modified parity check matrix is defined by combining two or more rows while excluding two or more columns within the parity check matrix. In a method performed by a receiver in a communication system,
A step of receiving a signal corresponding to an input bit;
A step of demodulating the signal to determine a value for decoding;
A step of checking the number of input bits based on the above signal;
A step of determining a basic matrix based on the number of input bits;
A step of determining a lifting size (Z) based on at least one of the number of input bits or the basic matrix;
determining a parity check matrix based on at least one of the basic matrix or the lifting size (Z); and
A step of performing decryption based on the above parity check matrix and the above values,
The above parity check matrix is a submatrix corresponding to the parity bits.

Includes,
The above signal includes punctured parity bits starting from the parity bits corresponding to the 4th column block among the 0th, 1st, 2nd, 3rd, and 4th column blocks of the above submatrix,
Included in the above parity check matrix Is is the identity matrix of size, Is is a zero-sized matrix, , , ,Is A method characterized in that the matrix is an identity matrix or a cyclic permutation matrix of size. In paragraph 5,
The above signal is the parity bits corresponding to the above submatrix. A method characterized by including parity bits interleaved in bit units. In Article 6,
The above interleaved parity bits are parity bits corresponding to the column blocks of the above submatrix. Based on

or

is determined by,
The above interleaved parity bits A method characterized in that the last bit of the bit is perforated in reverse order. In paragraph 5,
The step of determining the above parity check matrix is:
Further comprising a step of determining a modified parity check matrix based on the above parity check matrix,
A method characterized in that the above modified parity check matrix is defined by combining two or more rows while excluding two or more columns within the parity check matrix. In a transmitter in a communication system,
Transmitter and receiver; and
Includes a control unit connected to the above transmitter and receiver,
The above control unit,
Determine the number of input bits,
Determine the basic matrix based on the number of input bits,
Determine the lifting size (Z) based on the number of input bits or at least one of the basic matrices,
Determine a parity check matrix based on at least one of the above basic matrix or the above lifting size (Z),
Encoding is performed based on the above parity check matrix and the above input bits,
Rate matching is performed based on the above encoded bits,
The above parity check matrix is a submatrix corresponding to the parity bits.

Includes,
Among the 0th, 1st, 2nd, 3rd, and 4th column blocks of the above submatrix, puncturing begins from the parity bits corresponding to the 4th column block.
Included in the above parity check matrix Is is the identity matrix of size, Is is a zero-sized matrix, , , , Is A transmitter characterized by being an identity matrix or a cyclic permutation matrix of size . In paragraph 9,
The above control unit selects the parity bits corresponding to the sub-matrix among the encoded bits. A transmitter characterized by performing interleaving on a bit-by-bit basis. In Article 10,
Parity bits corresponding to the column blocks of the submatrix based on the above interleaving Is

or

is determined by,
Interleaved parity bits based on the above rate matching A transmitter characterized in that the last bit of the data is perforated in reverse order. In paragraph 9,
The above control unit,
Determine a modified parity check matrix based on the above parity check matrix,
A transmitter characterized in that the above modified parity check matrix is defined by combining two or more rows excluding two or more columns within the parity check matrix. In a receiver in a communication system,
Transmitter and receiver; and
Includes a control unit connected to the above transmitter and receiver,
The above control unit,
Receive a signal corresponding to the input bit,
Demodulating the signal to determine the value for decoding,
Check the number of input bits based on the above signal,
Determine the basic matrix based on the number of input bits,
Determine the lifting size (Z) based on the number of input bits or at least one of the basic matrices,
Determine a parity check matrix based on at least one of the above basic matrix or the above lifting size (Z),
Decryption is performed based on the above parity check matrix and the above values,
The above parity check matrix is a submatrix corresponding to the parity bits.

Includes,
The above signal includes punctured parity bits starting from the parity bits corresponding to the 4th column block among the 0th, 1st, 2nd, 3rd, and 4th column blocks of the above submatrix,
Included in the above parity check matrix Is is the identity matrix of size, Is is a zero-sized matrix, , , , Is A receiver characterized by being an identity matrix or a cyclic permutation matrix of size. In Article 13,
The above signal is the parity bits corresponding to the above submatrix. A receiver characterized by including parity bits interleaved in bit units. In Article 13,
The above interleaved parity bits are parity bits corresponding to the column blocks of the above submatrix. Based on

or


is determined by,
The above interleaved parity bits A receiver characterized in that the last bit of the signal is perforated in reverse order. In Article 13,
The above control unit,
Determine a modified parity check matrix based on the above parity check matrix,
A receiver characterized in that the above modified parity check matrix is defined by combining two or more rows excluding two or more columns within the parity check matrix.