[go: up one dir, main page]

KR960026951A - Transistors and manufacturing methods thereof - Google Patents

Transistors and manufacturing methods thereof Download PDF

Info

Publication number
KR960026951A
KR960026951A KR1019940036937A KR19940036937A KR960026951A KR 960026951 A KR960026951 A KR 960026951A KR 1019940036937 A KR1019940036937 A KR 1019940036937A KR 19940036937 A KR19940036937 A KR 19940036937A KR 960026951 A KR960026951 A KR 960026951A
Authority
KR
South Korea
Prior art keywords
film
semiconductor substrate
forming
layer
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1019940036937A
Other languages
Korean (ko)
Other versions
KR0143713B1 (en
Inventor
서정원
노광명
황성민
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940036937A priority Critical patent/KR0143713B1/en
Priority to US08/554,891 priority patent/US5693542A/en
Priority to DE19543859A priority patent/DE19543859B4/en
Priority to CN95120590A priority patent/CN1093687C/en
Priority to GB9526141A priority patent/GB2296817B/en
Priority to JP7339626A priority patent/JP2894680B2/en
Publication of KR960026951A publication Critical patent/KR960026951A/en
Application granted granted Critical
Publication of KR0143713B1 publication Critical patent/KR0143713B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0225—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0217—Manufacture or treatment of FETs having insulated gates [IGFET] forming self-aligned punch-through stoppers or threshold implants under gate regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 반도체 기판 상의 게이트 절연층, 상기 게이트 절연층 상의 게이트 전도층, 상기 게이트 전도층 패턴 측 및 타측 하부의 반도체 기판 상에 일정깊이 형성된 소오스 전합층 및 드레인 접합층을 구비하여 상기 게이트 전도층 하부의 소소오스 접합층과 드레인 접합층 사이의 반도체 기판에 채널을 형성하는 트랜지스터에 있어서, 상기 소오스 전합층 및 드레인 접합층 사이의 채널영역 반도체 기판에 형성되어 채널 역할을 하는 전도층과, 상기 전도층 하부의 반도체 기판에 형성되어 숏채널에 의해 발생하는 펀치쓰루(Punchthrough)를 방지하는 절연층을 더 구비하는 것을 특징으로 하는 트랜지스터 및 그 제조 방법에 관한 것으로, SOI 구조 트랜지스터의 장점을 갖으면서, 채널 밑에 절연막이 존재하므로, 깊은 서브마이크론 트랜지스터의 숏 채널에 의해 발생하는 펀치쓰루(Punchtrough)를 방지하여 트랜지스터가 안정된 동작 특성을 갖는 효과가 있다.The present invention provides a gate conductive layer including a gate insulating layer on a semiconductor substrate, a gate conductive layer on the gate insulating layer, a source total layer and a drain junction layer formed on a semiconductor substrate at a lower side of the gate conductive layer pattern side and the lower side of the gate conductive layer. A transistor for forming a channel in a semiconductor substrate between a source junction layer and a drain junction layer in a lower portion, the transistor comprising: a conductive layer formed on a channel region semiconductor substrate between the source junction layer and a drain junction layer to serve as a channel; The present invention relates to a transistor and a method of manufacturing the same, further comprising an insulating layer formed on the semiconductor substrate under the layer to prevent punchthrough generated by the short channel. Since an insulating film exists under the channel, By preventing the punch-through (Punchtrough) caused by the transistor has an effect that has a stable operating characteristics.

Description

트랜지스터 및 그 제조 방법Transistors and manufacturing methods thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1J도는 본 발명의 일실시예에 따른 트랜지스터 제조 공정도.Figure 1J is a transistor manufacturing process according to an embodiment of the present invention.

Claims (15)

반도체 기판 상의 게이트 절연층, 상기 게이트 절연층 상의 게이트 전도층, 상기 게이트 전도층 패턴 측벽일측 및 타측 하부의 반도체 기판 상에 일정깊이 형성된 소오스 전합층 및 드레인 접합층을 구비하여 상기 게이트 전도층 하부의 소오스 접합층과 드레인 접합층을 구비하여 상기 게이트 전도층 하부의 소오스접합층과 드레인 접합층 사이의 반도체 기판에 채널을 형성하는 트랜지스터에 있어서, 상기 소오스 전합층 및 드레인 접합층 사이의 채널영역 반도체 기판에 형성되어 채널 역할을 하는 전도층과, 상기 전도층 하부의 반도체기판에 형성되어 숏채널에 의해 발생하는 펀치쓰루(Punchthrough)를 방지하는 절연층을 더 구비하는 것을 특징으로 하는 트랜지스터.A gate insulating layer on the semiconductor substrate, a gate conducting layer on the gate insulating layer, a source electrolytic layer and a drain junction layer formed on the semiconductor substrate under one side and the other side of the gate conductive layer pattern sidewall, A transistor having a source junction layer and a drain junction layer to form a channel in a semiconductor substrate between a source junction layer and a drain junction layer below the gate conductive layer, wherein the channel region semiconductor substrate is formed between the source junction layer and the drain junction layer. And a conductive layer formed on the semiconductor layer and acting as a channel, and an insulating layer formed on the semiconductor substrate under the conductive layer to prevent punchthrough generated by the short channel. 트랜지스터 제조 방법에 있어서, 트랜지스터의 채널이 형성될 예정된 부위의 반도체 기판을 식각하여 트렌치를 형성하는 단계, 상기 반도체 기판 표면으로 부터 예정된 채널폭 정도의 일정깊이를 제외한 상기 트렌치 내부에 절연막을 형성하는 단계, 상기 반도체 기판 표면으로부터 절연막에 의해 채워지지 않은 트렌치 내부에 전도막을 형성하는단계, 트랜지스터의 패널이 형성될 예정된 부위의 반도체 기판 및 상기 전도막 상에 게이트 절연막과 게이트 전도막을 차례로 형성하는 단계, 및 상기 이온주입을 통해 소오스/드레인 접합을 형성하는 단계를 포함하는 것을 특징으로 하는 트랜지스터 제조 방법.A method of fabricating a transistor, comprising: forming a trench by etching a semiconductor substrate at a portion where a channel of a transistor is to be formed, and forming an insulating layer inside the trench except for a predetermined depth of a predetermined channel width from a surface of the semiconductor substrate Forming a conductive film in the trench which is not filled by the insulating film from the surface of the semiconductor substrate, sequentially forming a gate insulating film and a gate conductive film on the semiconductor substrate at the portion where the panel of the transistor is to be formed, and the conductive film; And forming a source / drain junction through the ion implantation. 제 2 항에 있어서, 상기 반도체 기판 표면으로부터 예정된 채널폭 정도의 일정깊이를 제외한 상기 트렌치 내부에 절연막을 형성하는 단계는, 전체구조 상부에 절연막을 증착하는 단계, 상기 절연막을 예정된 타켓으로 에치백하는 단계를 포함하는 것을 특징으로 하는 트랜지스터의 제조 방법.The method of claim 2, wherein forming an insulating film in the trench except for a predetermined depth of a predetermined channel width from the surface of the semiconductor substrate comprises: depositing an insulating film over an entire structure, and etching back the insulating film to a predetermined target. A method of manufacturing a transistor, comprising the steps of: 제 2 항에 있어서, 상기 반도체 기판 표면으로부터 절연막에 의해 채워지지 않은 트렌치 내부에 폴리실리콘막을 형성하는 단계는, 폴리실리콘막을 전체 구조상부에 증착하는 단계, 예정된 타켓으로 산화 공정을 수행하여 상기반도체 기판 표면 상부의 폴리실리콘막을 산화막으로 형성하는 단계, 상기 반도체 기판 표면의 상부의 산화막을 제거하는단계를 포함하는 것을 특징으로 하는 트랜지스터의 제조 방법.The method of claim 2, wherein the forming of the polysilicon film in the trench not filled by the insulating layer from the surface of the semiconductor substrate comprises depositing the polysilicon film on the entire structure, and performing an oxidation process with a predetermined target. Forming a polysilicon film on the upper surface of the semiconductor film, and removing the oxide film on the upper surface of the semiconductor substrate. 제 4 항에 있어서, 상기 전도막은 실리콘막 또는 폴리실리콘막인 을 특징으로 하는 트랜지스터의 제조 방법.The method of manufacturing a transistor according to claim 4, wherein the conductive film is a silicon film or a polysilicon film. 트랜지스터의 제조 방법에 있어서, 반도체 기판 표면에서부터 일정 깊이에 기판과 다른 타입(Type)의 저농도 불순물을 이온주입하여 저농도 도핑영역을 형성하는 단계, 트랜지스터의 채널이 형성될 예정된 부위의 반도체 기판 표면이 오픈 되도록 제1절연막 패턴을 형성하는 단계, 상기 노출된 반도체 기판을 식각하여 트렌치를 형성하는 단계, 상기 제1절연막과 식각선택비 차이가 큰 제2절연막을 전체구조 상부에 형성하는 단계, 상기 제2절연막을 식각하여 상기 반도체 기판표면으로부터 예정된 채널폭 정도의 일정깊이를 제외한 상기 트렌치 내부에만 제2절연막을 형성하는 단계, 상기 반도체 기판 표면으로부터 제2절연막에 의해 채워지지 않은 트렌치내부에 전도막을 형성하는 단계,상기 제1절연막을 제거하는 단계, 트렌지스터의 채널이 형성될 예정된 부위의반도체 기판 및 상기 전도막 상에 게이트 절연막과 게이트 전도막을 차례로 형성하는 단계, 및 이온주입을 통해 소오스/드레인 접합을 형성하는 단계를 포함하는 것을 특징으로 하는 트랜지스터의 제조 방법.A method for manufacturing a transistor, comprising: implanting a low concentration doping region by ion implantation of a low concentration of impurities different from the substrate at a predetermined depth from a surface of the semiconductor substrate, and opening the surface of the semiconductor substrate at a portion where a channel of the transistor is to be formed; Forming a first insulating layer pattern to form a trench, etching the exposed semiconductor substrate to form a trench, and forming a second insulating layer on the entire structure, the second insulating layer having a large difference in etching selectivity from the first insulating layer; Etching the insulating film to form a second insulating film only in the trench except for a predetermined depth of a predetermined channel width from the surface of the semiconductor substrate; forming a conductive film in the trench not filled by the second insulating film from the semiconductor substrate surface. Step, removing the first insulating layer, the channel of the transistor to be formed Step, and the ion implanting method of manufacturing a transistor comprising the step of forming a a source / drain junction by forming a portion the semiconductor substrate and on said conductive film, of the gate insulating film and the gate conductive film in order. 제 6항에 있어서, 상기 제1절연막은 질화막인 것을 특징으로 하는 트랜지스터의 제조 방법.The method of manufacturing a transistor according to claim 6, wherein the first insulating film is a nitride film. 제 7항에 있어서, 상기 제2절연막은 산화막인 것을 특징으로 하는 트랜지스터의 제조 방법.8. The method of claim 7, wherein the second insulating film is an oxide film. 제 6항에 있어서, 상기 전도막은 실리콘막 또는 폴리실리콘막인 것을 특징으로 하는 트랜지스터의 제조 방법.The method of manufacturing a transistor according to claim 6, wherein the conductive film is a silicon film or a polysilicon film. 제 9 항에 있어서, 상기 반도체 기판 표면으로부터 제2절연막에 의해 채워지지 않은 트렌치 내부에 폴리실리콘막을 형성하는 단계는, 전체구조 상부에 폴리실리콘막을 형성하는 단계, 상기 폴리실리콘막을 에치백하는 단계를포함하는 것을 특징으로 하는 트랜지스터 제조 방법.10. The method of claim 9, wherein the forming of the polysilicon film in the trench not filled by the second insulating film from the surface of the semiconductor substrate comprises: forming a polysilicon film on the entire structure, and etching back the polysilicon film. Transistor manufacturing method comprising a. 트랜지스터 제조 방법에 있어서, 트랜지스터의 채널이 형성될 예정된 부위의 반도체 기판이 오픈되도록제1절연막 및 제2절여막을 차례로 패터닝하는 단계, 상기 노출된 반도체 기판을 식각하여 트렌치를 형성하는 단계, 산화공정을 통해 트렌치에 의해 노출된 반도체 기판을 산화시켜 트렌치 부위에 산화막을 형성하는 단계, 상기 제2절연막을 제거하고 제1절연막 및 산화막을 식각하여 상기 반도체 기판 표면으로부터 예정된 채널폭 정도의 일정깊이를 제외한 상기트렌치 내부에 산화막을 남기고 반도체 기판 표면 상부에 잔류 제1절연막을 형성하는 단계, 상기 반도체 기판 표면으로부터 산화막에 의해 채워지지 않은 트렌치 내부에 전도막을 형성하는 단계, 상기 전도막 상에 게이트 절연막을 형성하고 게이트 전도막을 형성하는 단계, 이온주입을 통해 소오스/드레인 접합을 형성하는 단계를 포함하는 것을 특징하는 트랜지스터의 제조 방법.In the transistor manufacturing method, patterning the first insulating film and the second reducing film in order to open the semiconductor substrate of the region where the channel of the transistor is scheduled to be formed, etching the exposed semiconductor substrate to form a trench, oxidation process Oxidizing the semiconductor substrate exposed by the trench to form an oxide film in the trench, removing the second insulating layer and etching the first insulating layer and the oxide layer to remove the predetermined depth of a predetermined channel width from the surface of the semiconductor substrate. Leaving an oxide film inside the trench and forming a residual first insulating film over the surface of the semiconductor substrate, forming a conductive film in the trench not filled by the oxide film from the semiconductor substrate surface, forming a gate insulating film on the conductive film, Forming a gate conductive film, through ion implantation A method for manufacturing a transistor comprising forming a source / drain junction. 제 11 항에 있어서, 상기 반도체 기판 표면으로부터 산화막에 의해 채워지지 않은 트렌치 내부에 전도막을 형성하는 단계는, 에피텍시(Epitaxy) 공정으로 전도막을 성장시키는 것을 특징으로 하는 트랜지스터의 제조 방법.The method of claim 11, wherein the forming of the conductive film in the trench not filled by the oxide film from the surface of the semiconductor substrate comprises growing the conductive film by an epitaxy process. 제 11항에 있어서, 상기 제1절연막은 산화막인 것을 특징으로 하는 트랜지스터의 제조 방법.12. The method of claim 11, wherein the first insulating film is an oxide film. 제 11항에 있어서, 상기 제2절연막은 질화막인 것을 특징으로 하는 트랜지스터의 제조 방법.12. The method of claim 11, wherein the second insulating film is a nitride film. 제 11항에 있어서, 상기 전도막은 실리콘막 또는 폴리실리콘막인 것을 특징으로 하는 트랜지스터의 제조방법.12. The method of claim 11, wherein the conductive film is a silicon film or a polysilicon film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940036937A 1994-12-26 1994-12-26 Transistors and manufacturing methods thereof Expired - Fee Related KR0143713B1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019940036937A KR0143713B1 (en) 1994-12-26 1994-12-26 Transistors and manufacturing methods thereof
US08/554,891 US5693542A (en) 1994-12-26 1995-11-09 Method for forming a transistor with a trench
DE19543859A DE19543859B4 (en) 1994-12-26 1995-11-24 Transistor and transistor manufacturing process
CN95120590A CN1093687C (en) 1994-12-26 1995-12-08 Transistor and method for forming the same
GB9526141A GB2296817B (en) 1994-12-26 1995-12-21 A transistor and a method of manufacture thereof
JP7339626A JP2894680B2 (en) 1994-12-26 1995-12-26 Transistor and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940036937A KR0143713B1 (en) 1994-12-26 1994-12-26 Transistors and manufacturing methods thereof

Publications (2)

Publication Number Publication Date
KR960026951A true KR960026951A (en) 1996-07-22
KR0143713B1 KR0143713B1 (en) 1998-07-01

Family

ID=19403633

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940036937A Expired - Fee Related KR0143713B1 (en) 1994-12-26 1994-12-26 Transistors and manufacturing methods thereof

Country Status (6)

Country Link
US (1) US5693542A (en)
JP (1) JP2894680B2 (en)
KR (1) KR0143713B1 (en)
CN (1) CN1093687C (en)
DE (1) DE19543859B4 (en)
GB (1) GB2296817B (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3762136B2 (en) 1998-04-24 2006-04-05 株式会社東芝 Semiconductor device
FR2791178B1 (en) * 1999-03-19 2001-11-16 France Telecom NEW SEMICONDUCTOR DEVICE COMBINING THE ADVANTAGES OF MASSIVE AND SELF-ARCHITECTURES, AND MANUFACTURING METHOD
US6683345B1 (en) 1999-12-20 2004-01-27 International Business Machines, Corp. Semiconductor device and method for making the device having an electrically modulated conduction channel
JP2002134634A (en) * 2000-10-25 2002-05-10 Nec Corp Semiconductor device and its manufacturing method
DE10122064A1 (en) * 2001-05-07 2002-11-21 Infineon Technologies Ag Production of a wafer having a surface with recesses partially filled with a protective layer comprises applying the protective layer on the wafer so that the recesses
KR100493018B1 (en) 2002-06-12 2005-06-07 삼성전자주식회사 Method for fabricating a semiconductor device
KR100473476B1 (en) * 2002-07-04 2005-03-10 삼성전자주식회사 Semiconductor device and Method of manufacturing the same
KR100558041B1 (en) * 2003-08-19 2006-03-07 매그나칩 반도체 유한회사 Transistor of semiconductor device and manufacturing method thereof
JP2005257778A (en) * 2004-03-09 2005-09-22 Alps Electric Co Ltd Fine grating manufacturing method
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
CN102479706B (en) * 2010-11-24 2014-04-02 中芯国际集成电路制造(北京)有限公司 Transistor and manufacturing method thereof
CN108417632A (en) * 2017-02-10 2018-08-17 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method of forming the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4132998A (en) * 1977-08-29 1979-01-02 Rca Corp. Insulated gate field effect transistor having a deep channel portion more highly doped than the substrate
JPS59138377A (en) * 1983-01-28 1984-08-08 Agency Of Ind Science & Technol MIS transistor and its manufacturing method
EP0164094A3 (en) * 1984-06-08 1987-02-04 Eaton Corporation Isolated bidirectional power fet
FR2566179B1 (en) * 1984-06-14 1986-08-22 Commissariat Energie Atomique METHOD FOR SELF-POSITIONING OF A LOCALIZED FIELD OXIDE WITH RESPECT TO AN ISOLATION TRENCH
JPS62165364A (en) * 1986-01-17 1987-07-21 Nec Corp Semiconductor device
JPH0779127B2 (en) * 1989-12-27 1995-08-23 株式会社半導体プロセス研究所 Method for manufacturing semiconductor device
JPH04291956A (en) * 1991-03-20 1992-10-16 Fujitsu Ltd Manufacture of semiconductor memory
KR960005553B1 (en) * 1993-03-31 1996-04-26 현대전자산업주식회사 Manufacturing method of field oxide
US5362669A (en) * 1993-06-24 1994-11-08 Northern Telecom Limited Method of making integrated circuits
US5494837A (en) * 1994-09-27 1996-02-27 Purdue Research Foundation Method of forming semiconductor-on-insulator electronic devices by growing monocrystalline semiconducting regions from trench sidewalls

Also Published As

Publication number Publication date
GB2296817A (en) 1996-07-10
GB2296817B (en) 1998-08-19
KR0143713B1 (en) 1998-07-01
CN1131344A (en) 1996-09-18
DE19543859A1 (en) 1996-06-27
JPH0936354A (en) 1997-02-07
US5693542A (en) 1997-12-02
GB9526141D0 (en) 1996-02-21
DE19543859B4 (en) 2005-04-14
CN1093687C (en) 2002-10-30
JP2894680B2 (en) 1999-05-24

Similar Documents

Publication Publication Date Title
US7067365B1 (en) High-voltage metal-oxide-semiconductor devices and method of making the same
KR100246602B1 (en) A mosfet and method for fabricating the same
KR940002400B1 (en) Method of manufacturing semiconductor device having recess gate
KR100440508B1 (en) Integrated cmos circuit arrangement and method for the manufacture thereof"
KR100227621B1 (en) Transistor manufacturing method of semiconductor device
KR960026951A (en) Transistors and manufacturing methods thereof
US5286672A (en) Method for forming field oxide regions
KR970063780A (en) Transistor manufacturing method
KR940016938A (en) MOS transistor and its manufacturing method
KR960015850A (en) Isolation Structure of Semiconductor Device and Manufacturing Method Thereof
KR960012302A (en) SOI type semiconductor device and manufacturing method thereof
JP3049496B2 (en) Method of manufacturing MOSFET
JP3060948B2 (en) Method for manufacturing semiconductor device
KR100305205B1 (en) Manufacturing method of semiconductor device
KR100529618B1 (en) Semiconductor device and manufacturing process thereof
KR100223916B1 (en) Structure and manufacturing method of semiconductor device
KR100575612B1 (en) MOS field effect transistor manufacturing method
KR100196220B1 (en) Semiconductor device manufacturing method
KR0127691B1 (en) Transistors and manufacturing methods thereof
KR950021269A (en) Source / Drain Formation Method of Semiconductor Device
KR19980056994A (en) Method of manufacturing transistor in semiconductor device
KR19990060857A (en) Transistor Formation Method of Semiconductor Device
KR960002793A (en) Transistor and manufacturing method
KR920013700A (en) Soy structure transistor manufacturing method
KR960019611A (en) Semiconductor device manufacturing method

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

R17-X000 Change to representative recorded

St.27 status event code: A-5-5-R10-R17-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 12

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 13

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 14

FPAY Annual fee payment

Payment date: 20120323

Year of fee payment: 15

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 15

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20130411

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20130411

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000